GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) XMEDIA. All rights reserved.
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*/
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#include "drv_sys.h"
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#include "sys_drv.h"
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#include "sys_hal.h"
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xmedia_s32 drv_sys_mod_ctrl(xmedia_chn_info *chn_info, sys_func_id func_id, xmedia_void *io_args)
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{
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xmedia_s32 ret = XMEDIA_FAILURE;
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ret = sys_mod_ctrl(chn_info, func_id, io_args);
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return ret;
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}
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+60
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/*
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* Copyright (c) XMEDIA. All rights reserved.
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*/
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#ifndef DRV_SYS_H
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#define DRV_SYS_H
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#include "drv_vo_comm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif /* End of #ifdef __cplusplus */
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typedef enum {
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SYS_VO_VOU_HD_CKSEL,
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SYS_VO_VOU_PPC_CKSEL,
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SYS_VO_LVDS_POR_SRST,
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SYS_VO_MIPITX_PLL_REF_CKSEL,
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SYS_VO_LVDS_CKSEL,
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SYS_VO_LCD_DIV_CFG,
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SYS_VO_PLL_DIV_CFG,
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SYS_VO_VOU_HD_CKEN,
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SYS_VO_VOU_SRST_REQ,
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SYS_VO_VOU_SRST_GET,
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SYS_VO_LCD_DIV_CKEN,
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SYS_VO_PLL_DIV_CKEN,
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SYS_VO_BT_HD_CKSEL,
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SYS_VO_LCD_HD_CKSEL,
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SYS_VO_MIPITX_HD_CKSEL,
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SYS_VO_LVDSTX_HD_CKSEL,
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SYS_VO_BT_PCTRL,
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SYS_VO_LCD_PCTRL,
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SYS_VO_MIPITX_PCTRL,
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SYS_VO_LVDSTX_PCTRL,
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SYS_VO_BT_CKEN,
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SYS_VO_LCD_CKEN,
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SYS_VO_MIPITX_CKEN,
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SYS_VO_LVDSTX_CKEN,
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SYS_MAX
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} sys_func_id;
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#ifndef xmedia_chn_info
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typedef struct {
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xmedia_mod_id mod_id;
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xmedia_s32 dev_id;
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xmedia_s32 chn_id;
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} xmedia_chn_info;
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#endif
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xmedia_s32 drv_sys_mod_init(xmedia_void);
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xmedia_void drv_sys_mod_exit(xmedia_void);
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xmedia_s32 drv_sys_mod_ctrl(xmedia_chn_info *chn_info, sys_func_id func_id, xmedia_void *io_args);
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#ifdef __cplusplus
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}
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#endif /* End of #ifdef __cplusplus */
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#endif /* DRV_SYS_H */
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+434
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/*
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* Copyright (c) XMEDIA. All rights reserved.
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*/
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#ifndef __DRV_VO_SYS_H__
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#define __DRV_VO_SYS_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef unsigned char xmedia_uchar;
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typedef unsigned char xmedia_u8;
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typedef unsigned short xmedia_u16;
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typedef unsigned int xmedia_u32;
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typedef unsigned long long xmedia_u64;
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typedef unsigned long xmedia_ulong;
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typedef char xmedia_char;
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typedef signed char xmedia_s8;
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typedef short xmedia_s16;
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typedef int xmedia_s32;
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typedef long long xmedia_s64;
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typedef long xmedia_slong;
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typedef float xmedia_float;
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typedef double xmedia_double;
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typedef void xmedia_void;
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typedef xmedia_u32 xmedia_handle;
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typedef xmedia_ulong xmedia_uintptr_t;
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typedef xmedia_slong xmedia_intptr_t;
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typedef enum {
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XMEDIA_FALSE = 0,
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XMEDIA_TRUE = 1,
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} xmedia_bool;
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#define XMEDIA_NULL 0L
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#define XMEDIA_SUCCESS 0
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#define XMEDIA_FAILURE (-1)
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#define XMEDIA_INVALID_HANDLE (0xffffffff)
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#define XMEDIA_UNUSED(x) ((x) = (x))
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#define XMEDIA_ERRCODE_INVALID_PARAM (xmedia_s32)(0x80010001)
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#define XMEDIA_ERRCODE_NULL_PTR (xmedia_s32)(0x80010002)
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#define XMEDIA_ERRCODE_NOT_ENOUGH_MEMORY (xmedia_s32)(0x80010003) // memory allocation fails
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#define XMEDIA_ERRCODE_NOT_INIT (xmedia_s32)(0x80010004)
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#define XMEDIA_ERRCODE_NOT_SUPPORT (xmedia_s32)(0x80010005)
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#define XMEDIA_ERRCODE_TIMEOUT (xmedia_s32)(0x80010006)
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#define XMEDIA_ERRCODE_BAD_ADDRESS (xmedia_s32)(0x80010007)
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#define XMEDIA_ERRCODE_OPEN_FAILED (xmedia_s32)(0x80010008)
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#define XMEDIA_ERRCODE_CLOSE_FAILED (xmedia_s32)(0x80010009)
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#define XMEDIA_ERRCODE_CREATE_FAILED (xmedia_s32)(0x8001000A)
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#define XMEDIA_ERRCODE_DESTROY_FAILED (xmedia_s32)(0x8001000B)
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#define XMEDIA_ERRCODE_BUFFER_EMPTY (xmedia_s32)(0x8001000C)
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#define XMEDIA_ERRCODE_BUFFER_FULL (xmedia_s32)(0x8001000D)
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#define XMEDIA_ERRCODE_NO_BUFFER_FREE (xmedia_s32)(0x8001000E)
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#define XMEDIA_ERRCODE_NOT_PERMITTED (xmedia_s32)(0x8001000F) // Operation not permitted
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#define XMEDIA_ERRCODE_EXIST (xmedia_s32)(0x80010010) // Target exists
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#define XMEDIA_ERRCODE_NOT_EXIST (xmedia_s32)(0x80010011) // Target does not exist
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#define XMEDIA_ERRCODE_NOT_READY (xmedia_s32)(0x80010012) // Target not ready
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#define XMEDIA_ERRCODE_BUSY (xmedia_s32)(0x80010013) // Device or resource busy
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#define XMEDIA_ERRCODE_COPY_DATA_ERROR (xmedia_s32)(0x80010014)
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#define XMEDIA_ERRCODE_TYPE_ERROR (xmedia_s32)(0x80010015)
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#define XMEDIA_ERRCODE_CHN_FULL (xmedia_s32)(0x80010016)
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#define XMEDIA_ERRCODE_INVALID_CHN_ID (xmedia_s32)(0x80010017)
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#define XMEDIA_ERRCODE_INVALID_DEV_ID (xmedia_s32)(0x80010018)
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#define XMEDIA_ERRCODE_INVALID_PIPE_ID (xmedia_s32)(0x80010019)
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#define XMEDIA_ERRCODE_INVALID_GRP_ID (xmedia_s32)(0x8001001A)
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#define XMEDIA_ERRCODE_NOT_CONFIG (xmedia_s32)(0x8001001B)
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#define XMEDIA_ERRCODE_NOT_ENABLE (xmedia_s32)(0x8001001C)
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#define XMEDIA_ERRCODE_NOT_DISABLE (xmedia_s32)(0x8001001D)
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#define XMEDIA_ERRCODE_NOT_BIND (xmedia_s32)(0x8001001E)
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#define XMEDIA_ERRCODE_BINDED (xmedia_s32)(0x8001001F)
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#define MODULE_DBG_EMERG 0
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#define MODULE_DBG_ALERT 1
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#define MODULE_DBG_CRIT 2
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#define MODULE_DBG_ERR 3
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#define MODULE_DBG_WARN 4
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#define MODULE_DBG_NOTICE 5
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#define MODULE_DBG_INFO 6
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#define MODULE_DBG_DEBUG 7
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#define ALIGN_NUM 4
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#define MODULE_USR_DEFAULT_DBG MODULE_DBG_ERR // 用户态日志管理初始化失败时各模块的打印等级
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#define ATTRIBUTE __attribute__((aligned (ALIGN_NUM)))
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typedef enum {
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MOD_ID_VB = 0,
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MOD_ID_SYS = 1,
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MOD_ID_LOG = 2,
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MOD_ID_RGN = 3,
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MOD_ID_CHNL = 4,
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MOD_ID_VI = 5,
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MOD_ID_VO = 6,
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MOD_ID_DIS = 7,
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MOD_ID_AVS = 8,
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MOD_ID_VPSS = 9,
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MOD_ID_ISP = 10,
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MOD_ID_FB = 11,
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MOD_ID_GDC = 12,
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MOD_ID_TDE = 13,
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MOD_ID_VGS = 14,
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MOD_ID_MCF = 15,
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MOD_ID_HDMI = 16,
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MOD_ID_VDEC = 17,
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MOD_ID_VENC = 18,
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MOD_ID_VPU = 19,
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MOD_ID_VALG = 20,
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MOD_ID_RC = 21,
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MOD_ID_JPEGE = 22,
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MOD_ID_JPEGD = 23,
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MOD_ID_H264E = 24,
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MOD_ID_H264D = 25,
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MOD_ID_H265E = 26,
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MOD_ID_AIO = 29,
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MOD_ID_AI = 30,
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MOD_ID_AO = 31,
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MOD_ID_AENC = 32,
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MOD_ID_ADEC = 33,
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MOD_ID_ACOMM = 34,
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MOD_ID_NPU = 35,
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MOD_ID_IVE = 36,
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MOD_ID_USER = 37,
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MOD_ID_PM = 38,
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MOD_ID_GYRODIS = 39,
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MOD_ID_IR = 40,
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MOD_ID_NPU_SVP = 41,
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MOD_ID_DDR_OST_QOS = 42,
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MOD_ID_CIPHER = 43,
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MOD_ID_MAX,
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} xmedia_mod_id;
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typedef struct {
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xmedia_u32 width;
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xmedia_u32 height;
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} xmedia_video_size;
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typedef struct {
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xmedia_s32 x;
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xmedia_s32 y;
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xmedia_u32 width;
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xmedia_u32 height;
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} xmedia_video_rect;
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typedef enum {
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/* Semi-Planner */
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XMEDIA_VIDEO_PIXEL_FMT_YUV_SEMIPLANAR_420 = 0,
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XMEDIA_VIDEO_PIXEL_FMT_YVU_SEMIPLANAR_420,
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XMEDIA_VIDEO_PIXEL_FMT_YUV_SEMIPLANAR_422,
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XMEDIA_VIDEO_PIXEL_FMT_YVU_SEMIPLANAR_422,
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XMEDIA_VIDEO_PIXEL_FMT_YUV_SEMIPLANAR_444,
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XMEDIA_VIDEO_PIXEL_FMT_YVU_SEMIPLANAR_444,
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/* Package */
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XMEDIA_VIDEO_PIXEL_FMT_YUYV_PACKAGE_422 = 0x40,
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XMEDIA_VIDEO_PIXEL_FMT_YVYU_PACKAGE_422,
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XMEDIA_VIDEO_PIXEL_FMT_UYVY_PACKAGE_422,
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XMEDIA_VIDEO_PIXEL_FMT_VYUY_PACKAGE_422,
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XMEDIA_VIDEO_PIXEL_FMT_YYUV_PACKAGE_422,
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XMEDIA_VIDEO_PIXEL_FMT_YYVU_PACKAGE_422,
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XMEDIA_VIDEO_PIXEL_FMT_UVYY_PACKAGE_422,
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XMEDIA_VIDEO_PIXEL_FMT_VUYY_PACKAGE_422,
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XMEDIA_VIDEO_PIXEL_FMT_VY1UY0_PACKAGE_422,
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/*yuv 400 */
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XMEDIA_VIDEO_PIXEL_FMT_YUV_400 = 0x90,
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/*RGB*/
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XMEDIA_VIDEO_PIXEL_FMT_ARGB_1555 = 0xC0,
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XMEDIA_VIDEO_PIXEL_FMT_ARGB_4444,
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XMEDIA_VIDEO_PIXEL_FMT_ARGB_8888,
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XMEDIA_VIDEO_PIXEL_FMT_ABGR_1555,
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XMEDIA_VIDEO_PIXEL_FMT_ABGR_4444,
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XMEDIA_VIDEO_PIXEL_FMT_ABGR_8888,
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XMEDIA_VIDEO_PIXEL_FMT_RGBA_1555,
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XMEDIA_VIDEO_PIXEL_FMT_RGBA_4444,
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XMEDIA_VIDEO_PIXEL_FMT_RGBA_8888,
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XMEDIA_VIDEO_PIXEL_FMT_BGRA_1555,
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XMEDIA_VIDEO_PIXEL_FMT_BGRA_4444,
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XMEDIA_VIDEO_PIXEL_FMT_BGRA_8888,
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XMEDIA_VIDEO_PIXEL_FMT_RGB_565,
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XMEDIA_VIDEO_PIXEL_FMT_RGB_888,
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XMEDIA_VIDEO_PIXEL_FMT_BGR_565,
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XMEDIA_VIDEO_PIXEL_FMT_BGR_888,
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/*CLUT*/
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XMEDIA_VIDEO_PIXEL_FMT_CLUT2 = 0x100,
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XMEDIA_VIDEO_PIXEL_FMT_CLUT4,
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XMEDIA_VIDEO_PIXEL_FMT_CLUT8,
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/*RAW*/
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XMEDIA_VIDEO_PIXEL_FMT_RAW = 0x110,
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XMEDIA_VIDEO_PIXEL_FMT_MAX = 0x120
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} xmedia_video_pixel_format;
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typedef enum {
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XMEDIA_VIDEO_FMT_LINEAR = 0x0,
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XMEDIA_VIDEO_FMT_TILE_16x4,
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XMEDIA_VIDEO_FMT_TILE_32x4,
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XMEDIA_VIDEO_FMT_TILE_64x4,
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XMEDIA_VIDEO_FMT_TILE_64x64,
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XMEDIA_VIDEO_FMT_MAX
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} xmedia_video_format;
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/*维度：
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*yuv、RGB、RAW
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*有损/无损,
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*行、帧、段紧凑、段非紧凑
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*/
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typedef enum {
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XMEDIA_VIDEO_COMPRESS_MODE_NONE = 0x0,
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XMEDIA_VIDEO_COMPRESS_MODE_LINE, // 3DNR 使用行压缩
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XMEDIA_VIDEO_COMPRESS_MODE_FRAME,
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XMEDIA_VIDEO_COMPRESS_MODE_SEG,
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XMEDIA_VIDEO_COMPRESS_MODE_TILE,
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XMEDIA_VIDEO_COMPRESS_MODE_SLICE,
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XMEDIA_VIDEO_COMPRESS_MODE_MAX
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} xmedia_video_compress_mode;
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typedef enum {
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XMEDIA_VIDEO_COLOR_SPACE_YUV = 0x0,
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XMEDIA_VIDEO_COLOR_SPACE_RGB,
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XMEDIA_VIDEO_COLOR_SPACE_MAX
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} xmedia_video_color_space;
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typedef enum {
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XMEDIA_VIDEO_COLOR_GAMUT_BT601 = 0x0,
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XMEDIA_VIDEO_COLOR_GAMUT_BT709,
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XMEDIA_VIDEO_COLOR_GAMUT_BT2020,
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XMEDIA_VIDEO_COLOR_GAMUT_USER,
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XMEDIA_VIDEO_COLOR_GAMUT_MAX
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} xmedia_video_color_gamut;
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typedef enum {
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XMEDIA_VIDEO_COLOR_LIMITED_RANGE = 0x0,
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XMEDIA_VIDEO_COLOR_FULL_RANGE,
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XMEDIA_VIDEO_COLOR_RANGE_MAX
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} xmedia_video_color_quantify_range;
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typedef struct {
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xmedia_video_color_space color_space;
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xmedia_video_color_gamut color_gamut;
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xmedia_video_color_quantify_range quantify_range;
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} xmedia_video_color_descript;
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typedef enum {
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XMEDIA_VIDEO_DYNAMIC_RANGE_SDR = 0x0,
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XMEDIA_VIDEO_DYNAMIC_RANGE_HDR10,
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XMEDIA_VIDEO_DYNAMIC_RANGE_HLG,
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XMEDIA_VIDEO_DYNAMIC_RANGE_MAX
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} xmedia_video_dynamic_range;
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typedef enum {
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XMEDIA_VIDEO_DATA_WIDTH_8 = 0x0,
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XMEDIA_VIDEO_DATA_WIDTH_10,
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XMEDIA_VIDEO_DATA_WIDTH_12,
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XMEDIA_VIDEO_DATA_WIDTH_14,
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XMEDIA_VIDEO_DATA_WIDTH_16,
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XMEDIA_VIDEO_DATA_WIDTH_MAX
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} xmedia_video_data_width;
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typedef struct {
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xmedia_u64 isp_info_phy_addr;
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xmedia_u64 lowdelay_info_phy_addr;
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xmedia_u64 vdec_info_phy_addr;
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xmedia_void *ATTRIBUTE isp_info_vir_addr;
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xmedia_void *ATTRIBUTE lowdelay_info_vir_addr;
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xmedia_void *ATTRIBUTE vdec_info_vir_addr;
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} xmedia_video_private_info;
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typedef struct {
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xmedia_u64 y_head_phy_addr;
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xmedia_u64 c_head_phy_addr;
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xmedia_u64 y_phy_addr;
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xmedia_u64 c_phy_addr;
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// xmedia_u64 y_buf_phy_addr; // luma buffer start phy addr
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// xmedia_u64 c_buf_phy_addr; // chroma buffer start phy addr
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// xmedia_u32 y_size; // luma buffer size
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// xmedia_u32 c_size; // chroma buffer size
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} xmedia_video_frame_address;
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typedef struct {
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xmedia_u32 y_head_stride;
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xmedia_u32 c_head_stride;
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xmedia_u32 y_stride;
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xmedia_u32 c_stride;
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} xmedia_video_frame_stride;
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typedef struct {
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xmedia_u32 index;
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xmedia_u32 width;
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xmedia_u32 height;
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xmedia_video_frame_address addr;
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xmedia_video_frame_stride stride;
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xmedia_video_data_width bit_width;
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||||
xmedia_video_pixel_format pixel_fmt;
|
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xmedia_video_compress_mode compress_mode;
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xmedia_video_format video_fmt;
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||||
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xmedia_video_dynamic_range dynamic_range;
|
||||
xmedia_video_color_descript color_info;
|
||||
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||||
xmedia_u64 pts;
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||||
xmedia_u32 time_ref;
|
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xmedia_u32 frame_flag;
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||||
xmedia_video_private_info priv_info;
|
||||
} xmedia_video_frame;
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||||
|
||||
typedef struct {
|
||||
xmedia_video_frame frame;
|
||||
xmedia_u32 pool_id;
|
||||
xmedia_mod_id mod_id;
|
||||
} xmedia_video_frame_info;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_RAW_8BIT = 0,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_RAW_10BIT,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_RAW_12BIT,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_RAW_14BIT,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_RAW_16BIT,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_RAW_20BIT,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_RAW_24BIT,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_YUV420_8BIT,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_YUV420_LEGACY_8BIT,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_YUV422_8BIT,
|
||||
XMEDIA_INTF_MIPI_CSI_DATA_TYPE_MAX
|
||||
} xmedia_intf_mipi_csi_data_type;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_MIPI_DSI_DATA_TYPE_YUV422_16BIT = 0,
|
||||
XMEDIA_INTF_MIPI_DSI_DATA_TYPE_RGB666_18BIT,
|
||||
XMEDIA_INTF_MIPI_DSI_DATA_TYPE_RGB888_24BIT,
|
||||
XMEDIA_INTF_MIPI_DSI_DATA_TYPE_MAX
|
||||
} xmedia_intf_mipi_dsi_data_type;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_BT_DATA_TYPE_YUV422_8BIT = 0,
|
||||
XMEDIA_INTF_BT_DATA_TYPE_YUV422_10BIT,
|
||||
XMEDIA_INTF_BT_DATA_TYPE_MAX
|
||||
} xmedia_intf_bt_data_type;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_LCD_DATA_TYPE_RGB565_16BIT = 0,
|
||||
XMEDIA_INTF_LCD_DATA_TYPE_RGB666_18BIT,
|
||||
XMEDIA_INTF_LCD_DATA_TYPE_RGB888_24BIT,
|
||||
XMEDIA_INTF_LCD_DATA_TYPE_MAX
|
||||
} xmedia_intf_lcd_data_type;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_LVDS_DATA_TYPE_RGB666_18BIT = 0,
|
||||
XMEDIA_INTF_LVDS_DATA_TYPE_RGB666_36BIT,
|
||||
XMEDIA_INTF_LVDS_DATA_TYPE_RGB888_24BIT,
|
||||
XMEDIA_INTF_LVDS_DATA_TYPE_RGB888_48BIT,
|
||||
XMEDIA_INTF_LVDS_DATA_TYPE_MAX
|
||||
} xmedia_intf_lvds_data_type;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_DC_DATA_TYPE_RAW_8BIT = 0,
|
||||
XMEDIA_INTF_DC_DATA_TYPE_RAW_10BIT,
|
||||
XMEDIA_INTF_DC_DATA_TYPE_RAW_12BIT,
|
||||
XMEDIA_INTF_DC_DATA_TYPE_RAW_14BIT,
|
||||
XMEDIA_INTF_DC_DATA_TYPE_RAW_16BIT,
|
||||
XMEDIA_INTF_DC_DATA_TYPE_MAX
|
||||
} xmedia_intf_dc_data_type;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_TYPE_BT601 = 0,
|
||||
XMEDIA_INTF_TYPE_BT656,
|
||||
XMEDIA_INTF_TYPE_BT1120,
|
||||
XMEDIA_INTF_TYPE_MIPI_CSI,
|
||||
XMEDIA_INTF_TYPE_MIPI_DSI,
|
||||
XMEDIA_INTF_TYPE_LCD,
|
||||
XMEDIA_INTF_TYPE_LVDS,
|
||||
XMEDIA_INTF_TYPE_DC,
|
||||
XMEDIA_INTF_TYPE_MCU,
|
||||
XMEDIA_INTF_TYPE_MAX
|
||||
} xmedia_intf_type;
|
||||
|
||||
/* bt601&bt656 */
|
||||
typedef enum {
|
||||
XMEDIA_INTF_BT601_BT656_DATA_SEQ_UYVY = 0,
|
||||
XMEDIA_INTF_BT601_BT656_DATA_SEQ_VYUY,
|
||||
XMEDIA_INTF_BT601_BT656_DATA_SEQ_YUYV,
|
||||
XMEDIA_INTF_BT601_BT656_DATA_SEQ_YVYU,
|
||||
XMEDIA_INTF_BT601_BT656_DATA_SEQ_MAX
|
||||
} xmedia_intf_bt601_bt656_data_seq;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_BT1120_DATA_SEQ_VUVU = 0,
|
||||
XMEDIA_INTF_BT1120_DATA_SEQ_UVUV,
|
||||
XMEDIA_INTF_BT1120_DATA_SEQ_MAX,
|
||||
} xmedia_intf_bt1120_data_seq;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_LCD_DATA_SEQ_RGB = 0,
|
||||
XMEDIA_INTF_LCD_DATA_SEQ_RBG,
|
||||
XMEDIA_INTF_LCD_DATA_SEQ_GRB,
|
||||
XMEDIA_INTF_LCD_DATA_SEQ_GBR,
|
||||
XMEDIA_INTF_LCD_DATA_SEQ_BRG,
|
||||
XMEDIA_INTF_LCD_DATA_SEQ_BGR,
|
||||
XMEDIA_INTF_LCD_DATA_SEQ_MAX,
|
||||
} xmedia_intf_lcd_data_seq;
|
||||
|
||||
typedef enum {
|
||||
XMEDIA_INTF_LVDS_FORMAT_VESA = 0,
|
||||
XMEDIA_INTF_LVDS_FORMAT_JEIDA,
|
||||
XMEDIA_INTF_LVDS_FORMAT_MAX
|
||||
} xmedia_intf_lvds_format;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,318 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
#ifndef __DRV_VO_COMMON_H__
|
||||
#define __DRV_VO_COMMON_H__
|
||||
#include <net.h>
|
||||
#include <exports.h>
|
||||
#include <serial.h>
|
||||
#include <xyzModem.h>
|
||||
#include "xmedia_vo.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define VO_MIN_CHN_WIDTH 32
|
||||
#define VO_MIN_CHN_HEIGHT 32
|
||||
#define VO_MAX_ZOOM_RATIO 1000
|
||||
#define VO_MAX_DEV_NUM 4
|
||||
#define VO_MAX_LAYER_NUM 4
|
||||
#define VO_MAX_CHN_NUM 4
|
||||
#define VO_MIN_TOLERATE 1
|
||||
#define VO_MAX_TOLERATE 100000
|
||||
|
||||
#define VO_INVALID_CHN_ID VO_MAX_CHN_NUM
|
||||
#define VO_INVALID_NODE_INDEX 0
|
||||
|
||||
#ifdef xmorca
|
||||
#define XMEDIA_VO_REAL_DEV_NUM XMEDIA_VO_DEV_1
|
||||
#define XMEDIA_VO_REAL_LAYER_NUM XMEDIA_VO_LAYER_V1
|
||||
#define XMEDIA_VO_VIRT_DEV_NUM 1
|
||||
#define XMEDIA_VO_VIRT_LAYER_NUM 1
|
||||
#endif
|
||||
|
||||
#ifdef xmfalcon
|
||||
#define XMEDIA_VO_REAL_DEV_NUM XMEDIA_VO_DEV_VIRT_0
|
||||
#define XMEDIA_VO_REAL_LAYER_NUM XMEDIA_VO_LAYER_VIRT_V0
|
||||
#define XMEDIA_VO_VIRT_DEV_NUM 2
|
||||
#define XMEDIA_VO_VIRT_LAYER_NUM 2
|
||||
#endif
|
||||
#define VO_CHECK_VAILD_DEV(dev) ((((dev) >= (XMEDIA_VO_DEV_0)) && ((dev) < (XMEDIA_VO_REAL_DEV_NUM))) || \
|
||||
(((dev) >= (XMEDIA_VO_DEV_VIRT_0)) && ((dev) < ((XMEDIA_VO_DEV_VIRT_0) + (XMEDIA_VO_VIRT_DEV_NUM)))))
|
||||
|
||||
#define VO_CHECK_REAL_DEV(dev) (((dev) >= (XMEDIA_VO_DEV_0)) && ((dev) < (XMEDIA_VO_REAL_DEV_NUM)))
|
||||
|
||||
#define VO_CHECK_VIRT_DEV(dev) (((dev) >= XMEDIA_VO_DEV_VIRT_0) && \
|
||||
((dev) < ((XMEDIA_VO_DEV_VIRT_0) + (XMEDIA_VO_VIRT_DEV_NUM))))
|
||||
|
||||
#define VO_CHECK_VAILD_LAYER(layer) ((((layer) >= (XMEDIA_VO_LAYER_V0)) && ((layer) < (XMEDIA_VO_REAL_LAYER_NUM))) || \
|
||||
(((layer) >= (XMEDIA_VO_LAYER_VIRT_V0)) && ((layer) < ((XMEDIA_VO_LAYER_VIRT_V0) + (XMEDIA_VO_VIRT_LAYER_NUM)))))
|
||||
|
||||
|
||||
#define VO_TRACE(level, fmt, ...) \
|
||||
do { \
|
||||
if (level <= MODULE_DBG_ERR) { \
|
||||
printf("[Func]:%s [Line]:%d [Info]:" fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_VO_PTR_RETURN(pointer) \
|
||||
do { \
|
||||
if ((pointer) == XMEDIA_NULL) { \
|
||||
VO_TRACE(MODULE_DBG_ERR,"vo para is null ptr.\n"); \
|
||||
return XMEDIA_ERRCODE_NULL_PTR; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_VO_DEV_ID_RETURN(dev) \
|
||||
do { \
|
||||
if (dev >= XMEDIA_VO_DEV_MAX) { \
|
||||
VO_TRACE(MODULE_DBG_ERR,"vo dev %d is invalid.\n",dev); \
|
||||
return XMEDIA_ERRCODE_INVALID_DEV_ID; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_VO_DEV_ID(dev) \
|
||||
do { \
|
||||
if (dev >= XMEDIA_VO_DEV_MAX) { \
|
||||
VO_TRACE(MODULE_DBG_ERR,"vo dev %d is invalid.\n",dev); \
|
||||
return; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define CHECK_VO_LAYER_ID_RETURN(layer) \
|
||||
do { \
|
||||
if (layer >= XMEDIA_VO_LAYER_MAX){ \
|
||||
VO_TRACE(MODULE_DBG_ERR,"vo layer %d is invalid.\n",layer); \
|
||||
return XMEDIA_ERRCODE_INVALID_GRP_ID; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_VO_CHN_ID_RETURN(chn) \
|
||||
do { \
|
||||
if ((chn < 0) || (chn >= VO_MAX_CHN_NUM)) { \
|
||||
VO_TRACE(MODULE_DBG_ERR,"vo chn %d is invalid.\n",chn); \
|
||||
return XMEDIA_ERRCODE_INVALID_CHN_ID; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_VO_ZERO_RETURN(value) \
|
||||
do { \
|
||||
if (value == 0) { \
|
||||
VO_TRACE(MODULE_DBG_ERR,"a denominator of 0 is illegal\n"); \
|
||||
return XMEDIA_ERRCODE_NOT_PERMITTED; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define IS_ALIGN(x, bitw) (((x % bitw) == 0) ? XMEDIA_TRUE : XMEDIA_FALSE)
|
||||
|
||||
#define osal_memset(ptr, value, len) memset(ptr, value, len)
|
||||
#define osal_mdelay(msecs) mdelay(msecs)
|
||||
#define osal_memcpy(dst, src, size) memcpy(dst, src, size)
|
||||
#define osal_udelay(usecs) udelay(usecs)
|
||||
#define osal_vmalloc(size) malloc(size)
|
||||
#define osal_vfree(addr) free(addr)
|
||||
|
||||
typedef enum {
|
||||
VO_ISR_INTERRUPT_TYPE = 0,
|
||||
VO_ISR_INTERRUPT_TYPE_DHD0_VTT0 = 0x1,
|
||||
VO_ISR_INTERRUPT_TYPE_DHD0_VTT1 = 0x2,
|
||||
VO_ISR_INTERRUPT_TYPE_DHD0_VTT2 = 0x4,
|
||||
VO_ISR_INTERRUPT_TYPE_DHD0_VTT3 = 0x8,
|
||||
VO_ISR_INTERRUPT_TYPE_DHD0_UFINT = 0x10000, //low band width
|
||||
|
||||
VO_ISR_INTERRUPT_TYPE_DHD1_VTT0 = 0x10,
|
||||
VO_ISR_INTERRUPT_TYPE_DHD1_VTT1 = 0x20,
|
||||
VO_ISR_INTERRUPT_TYPE_DHD1_VTT2 = 0x40,
|
||||
VO_ISR_INTERRUPT_TYPE_DHD1_VTT3 = 0x80,
|
||||
VO_ISR_INTERRUPT_TYPE_DHD1_UFINT = 0x20000,
|
||||
|
||||
VO_ISR_INTERRUPT_TYPE_LOW_DELAY_CERR = 0x100000,
|
||||
VO_ISR_INTERRUPT_TYPE_LOW_DELAY_YERR = 0x200000,
|
||||
|
||||
VO_ISR_INTERRUPT_TYPE_BUSR_ERR = 0x1000000,
|
||||
VO_ISR_INTERRUPT_TYPE_BUSW_ERR = 0x2000000,
|
||||
|
||||
VO_ISR_INTERRUPT_TYPE_ALL = 0xffffffff,
|
||||
} vo_isr_interrupt_type;
|
||||
|
||||
typedef enum {
|
||||
VO_ISR_FIELD_FLAG_FRAME = 0,
|
||||
VO_ISR_FIELD_FLAG_TOP,
|
||||
VO_ISR_FIELD_FLAG_BOTTOM,
|
||||
VO_ISR_FIELD_FLAG_TOP_BOTTOM,
|
||||
VO_ISR_FIELD_FLAG_MAX
|
||||
} vo_isr_field_flag;
|
||||
|
||||
#ifdef xmorca
|
||||
typedef enum {
|
||||
VO_CSC_YUV2RGB_601_LIMIT2FULL = 0,
|
||||
VO_CSC_YUV2RGB_709_LIMIT2FULL,
|
||||
VO_CSC_YUV2RGB_601_FULL2LIMIT,
|
||||
VO_CSC_YUV2RGB_709_FULL2LIMIT,
|
||||
VO_CSC_YUV2RGB_601_FULL2FULL,
|
||||
VO_CSC_YUV2RGB_709_FULL2FULL,
|
||||
VO_CSC_YUV2RGB_601_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2RGB_709_LIMIT2LIMIT,
|
||||
|
||||
VO_CSC_YUV2YUV_601_601_LIMIT2LIMIT = 8,
|
||||
VO_CSC_YUV2YUV_601_709_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_601_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_709_LIMIT2LIMIT,
|
||||
|
||||
VO_CSC_YUV2YUV_601_601_FULL2FULL = 12,
|
||||
VO_CSC_YUV2YUV_601_709_FULL2FULL,
|
||||
VO_CSC_YUV2YUV_709_601_FULL2FULL,
|
||||
VO_CSC_YUV2YUV_709_709_FULL2FULL,
|
||||
|
||||
VO_CSC_YUV2YUV_601_601_LIMIT2FULL = 16,
|
||||
VO_CSC_YUV2YUV_601_709_LIMIT2FULL,
|
||||
VO_CSC_YUV2YUV_709_601_LIMIT2FULL,
|
||||
VO_CSC_YUV2YUV_709_709_LIMIT2FULL,
|
||||
|
||||
VO_CSC_YUV2YUV_601_601_FULL2LIMIT = 20,
|
||||
VO_CSC_YUV2YUV_601_709_FULL2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_601_FULL2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_709_FULL2LIMIT,
|
||||
VO_CSC_MAX
|
||||
} vo_csc_type;
|
||||
#endif
|
||||
|
||||
#ifdef xmfalcon
|
||||
typedef enum {
|
||||
VO_CSC_YUV2RGB_601_LIMIT2FULL = 0,
|
||||
VO_CSC_YUV2RGB_709_LIMIT2FULL,
|
||||
VO_CSC_YUV2RGB_2020_LIMIT2FULL,
|
||||
VO_CSC_YUV2RGB_601_FULL2LIMIT,
|
||||
VO_CSC_YUV2RGB_709_FULL2LIMIT,
|
||||
VO_CSC_YUV2RGB_2020_FULL2LIMIT,
|
||||
VO_CSC_YUV2RGB_601_FULL2FULL,
|
||||
VO_CSC_YUV2RGB_709_FULL2FULL,
|
||||
VO_CSC_YUV2RGB_2020_FULL2FULL,
|
||||
VO_CSC_YUV2RGB_601_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2RGB_709_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2RGB_2020_LIMIT2LIMIT,
|
||||
|
||||
VO_CSC_RGB2YUV_601_LIMIT2FULL = 12,
|
||||
VO_CSC_RGB2YUV_709_LIMIT2FULL,
|
||||
VO_CSC_RGB2YUV_2020_LIMIT2FULL,
|
||||
VO_CSC_RGB2YUV_601_FULL2LIMIT,
|
||||
VO_CSC_RGB2YUV_709_FULL2LIMIT,
|
||||
VO_CSC_RGB2YUV_2020_FULL2LIMIT,
|
||||
VO_CSC_RGB2YUV_601_FULL2FULL,
|
||||
VO_CSC_RGB2YUV_709_FULL2FULL,
|
||||
VO_CSC_RGB2YUV_2020_FULL2FULL,
|
||||
VO_CSC_RGB2YUV_601_LIMIT2LIMIT,
|
||||
VO_CSC_RGB2YUV_709_LIMIT2LIMIT,
|
||||
VO_CSC_RGB2YUV_2020_LIMIT2LIMIT,
|
||||
|
||||
VO_CSC_YUV2YUV_601_601_LIMIT2LIMIT = 24,
|
||||
VO_CSC_YUV2YUV_601_709_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2YUV_601_2020_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_601_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_709_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_2020_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2YUV_2020_601_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2YUV_2020_709_LIMIT2LIMIT,
|
||||
VO_CSC_YUV2YUV_2020_2020_LIMIT2LIMIT,
|
||||
|
||||
VO_CSC_YUV2YUV_601_601_FULL2FULL = 33,
|
||||
VO_CSC_YUV2YUV_601_709_FULL2FULL,
|
||||
VO_CSC_YUV2YUV_601_2020_FULL2FULL,
|
||||
VO_CSC_YUV2YUV_709_601_FULL2FULL,
|
||||
VO_CSC_YUV2YUV_709_709_FULL2FULL,
|
||||
VO_CSC_YUV2YUV_709_2020_FULL2FULL,
|
||||
VO_CSC_YUV2YUV_2020_601_FULL2FULL,
|
||||
VO_CSC_YUV2YUV_2020_709_FULL2FULL,
|
||||
VO_CSC_YUV2YUV_2020_2020_FULL2FULL,
|
||||
|
||||
VO_CSC_YUV2YUV_601_601_LIMIT2FULL = 42,
|
||||
VO_CSC_YUV2YUV_601_709_LIMIT2FULL,
|
||||
VO_CSC_YUV2YUV_601_2020_LIMIT2FULL,
|
||||
VO_CSC_YUV2YUV_709_601_LIMIT2FULL,
|
||||
VO_CSC_YUV2YUV_709_709_LIMIT2FULL,
|
||||
VO_CSC_YUV2YUV_709_2020_LIMIT2FULL,
|
||||
VO_CSC_YUV2YUV_2020_601_LIMIT2FULL,
|
||||
VO_CSC_YUV2YUV_2020_709_LIMIT2FULL,
|
||||
VO_CSC_YUV2YUV_2020_2020_LIMIT2FULL,
|
||||
|
||||
VO_CSC_YUV2YUV_601_601_FULL2LIMIT = 51,
|
||||
VO_CSC_YUV2YUV_601_709_FULL2LIMIT,
|
||||
VO_CSC_YUV2YUV_601_2020_FULL2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_601_FULL2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_709_FULL2LIMIT,
|
||||
VO_CSC_YUV2YUV_709_2020_FULL2LIMIT,
|
||||
VO_CSC_YUV2YUV_2020_601_FULL2LIMIT,
|
||||
VO_CSC_YUV2YUV_2020_709_FULL2LIMIT,
|
||||
VO_CSC_YUV2YUV_2020_2020_FULL2LIMIT,
|
||||
|
||||
VO_CSC_RGB2RGB_LIMIT2LIMIT = 60,
|
||||
VO_CSC_RGB2RGB_FULL2FULL,
|
||||
VO_CSC_RGB2RGB_FULL2LIMIT,
|
||||
VO_CSC_RGB2RGB_LIMIT2FULL,
|
||||
|
||||
VO_CSC_MAX
|
||||
} vo_csc_type;
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
vo_csc_type csc_type;
|
||||
xmedia_u32 luma;
|
||||
xmedia_u32 contrast;
|
||||
xmedia_u32 hue;
|
||||
xmedia_u32 saturation;
|
||||
} vo_pic_info;
|
||||
|
||||
typedef struct {
|
||||
xmedia_u64 lum_addr;
|
||||
xmedia_u64 chm_addr;
|
||||
xmedia_u32 lum_stride;
|
||||
xmedia_u32 chm_stride;
|
||||
} vo_addr;
|
||||
|
||||
typedef struct {
|
||||
xmedia_bool config;
|
||||
xmedia_bool enable;
|
||||
xmedia_u32 chn; //硬件region区域 所对应的软件chn号
|
||||
xmedia_video_rect src_rect;
|
||||
xmedia_video_rect dst_rect;
|
||||
xmedia_video_rect lba_rect;
|
||||
xmedia_u32 lba_color;
|
||||
vo_addr region_addr;
|
||||
} vo_region_info;
|
||||
|
||||
typedef struct {
|
||||
xmedia_bool mute_en;
|
||||
xmedia_video_rect frame_rect; //真实内容 相对于显示窗口的rect
|
||||
xmedia_video_rect video_rect; //层 相对于显示窗口的rect
|
||||
xmedia_video_rect lba_rect;
|
||||
xmedia_u32 lba_color;
|
||||
vo_addr frame_addr;
|
||||
} vo_layer_single_cfg;
|
||||
|
||||
typedef struct {
|
||||
xmedia_video_rect reso_rect;
|
||||
xmedia_video_rect disp_rect;
|
||||
xmedia_u32 region_id;
|
||||
xmedia_bool region_overlap;
|
||||
xmedia_u32 overlap_id;
|
||||
xmedia_u32 region_sort;
|
||||
vo_region_info region[VO_MAX_CHN_NUM]; //硬件region区域配置
|
||||
} vo_layer_multi_cfg;
|
||||
|
||||
typedef struct {
|
||||
xmedia_bool bt656_intf_en;
|
||||
xmedia_bool bt1120_intf_en;
|
||||
xmedia_bool lcd_intf_en;
|
||||
xmedia_bool mipi_intf_en;
|
||||
xmedia_bool lvds_intf_en;
|
||||
xmedia_vo_dev dev;
|
||||
} vo_dev_intf_type_mux;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef DRV_REG_CRG_H
|
||||
#define DRV_REG_CRG_H
|
||||
|
||||
#define CRG_REGS_ADDR 0x12010000
|
||||
#define CRG_REGS_SIZE 0X10000
|
||||
|
||||
#define CRG_PERCTL0_ADDR (CRG_REGS_ADDR + 0x0)
|
||||
#define CRG_PERCTL1_ADDR (CRG_REGS_ADDR + 0x4)
|
||||
#define CRG_PERCTL2_ADDR (CRG_REGS_ADDR + 0x8)
|
||||
|
||||
#define CRG_PERCTL50_ADDR (CRG_REGS_ADDR + 0xc8)
|
||||
#define CRG_PERCTL65_ADDR (CRG_REGS_ADDR + 0x104)
|
||||
#define CRG_PERCTL66_ADDR (CRG_REGS_ADDR + 0x108)
|
||||
#define CRG_PERCTL67_ADDR (CRG_REGS_ADDR + 0x10c)
|
||||
#define CRG_PERCTL121_ADDR (CRG_REGS_ADDR + 0x1e4)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef DRV_REG_SYS_H
|
||||
#define DRV_REG_SYS_H
|
||||
|
||||
#define SYS_REGS_ADDR 0x12020000
|
||||
#define SYS_REGS_SIZE 0x8000
|
||||
|
||||
#define MISC_REGS_ADDR 0x12028000
|
||||
#define MISC_REGS_SIZE 0x8000
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,222 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "common.h"
|
||||
#include "sys_drv.h"
|
||||
#include "sys_hal.h"
|
||||
#include "drv_sys.h"
|
||||
#include "xmedia_vo.h"
|
||||
#include "drv_vo_comm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
#define PHASE 32
|
||||
#define SYS_MULTI_V 1048576
|
||||
#define SYS_MULTI_H 1048576
|
||||
|
||||
|
||||
|
||||
xmedia_s32 sys_mod_init(xmedia_void)
|
||||
{
|
||||
xmedia_s32 ret;
|
||||
ret = sys_hal_init();
|
||||
return ret;
|
||||
}
|
||||
|
||||
xmedia_s32 sys_mod_exit(xmedia_void)
|
||||
{
|
||||
sys_hal_exit();
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
xmedia_s32 sys_mod_ctrl(xmedia_chn_info *chn_info, sys_func_id func_id, xmedia_void *io_args)
|
||||
{
|
||||
xmedia_s32 dev;
|
||||
|
||||
dev = chn_info->dev_id;
|
||||
switch (func_id) {
|
||||
case SYS_VO_VOU_HD_CKSEL:{
|
||||
xmedia_u32 *vou_hd_sel = XMEDIA_NULL;
|
||||
vou_hd_sel = (xmedia_u32 *)io_args;
|
||||
sys_hal_vo_vou_hd_sel(dev, *vou_hd_sel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_VOU_PPC_CKSEL: {
|
||||
xmedia_u32 *vou_ppc_cksel = XMEDIA_NULL;
|
||||
vou_ppc_cksel = (xmedia_u32 *)io_args;
|
||||
sys_hal_vo_vou_ppc_cksel(*vou_ppc_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDS_POR_SRST: {
|
||||
xmedia_bool *lvd_por_srst = XMEDIA_NULL;
|
||||
lvd_por_srst = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvds_por_srst(*lvd_por_srst);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_MIPITX_PLL_REF_CKSEL: {
|
||||
xmedia_bool *mipitx_pll_ref_cksel = XMEDIA_NULL;
|
||||
mipitx_pll_ref_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_mipitx_pll_ref_cksel(*mipitx_pll_ref_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDS_CKSEL:{
|
||||
xmedia_bool *lvds_cksel = XMEDIA_NULL;
|
||||
lvds_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvds_cksel(dev, *lvds_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_DIV_CFG:{
|
||||
xmedia_u32 *lcd_div_cfg = XMEDIA_NULL;
|
||||
lcd_div_cfg = (xmedia_u32 *)io_args;
|
||||
sys_hal_vo_lcd_div_cfg(*lcd_div_cfg);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_PLL_DIV_CFG:{
|
||||
xmedia_u32 *pll_div_cfg = XMEDIA_NULL;
|
||||
pll_div_cfg = (xmedia_u32 *)io_args;
|
||||
if(sys_hal_vo_pll_div_cfg(*pll_div_cfg) != XMEDIA_SUCCESS) {
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_VOU_HD_CKEN:{
|
||||
xmedia_bool *vou_hd_cken = XMEDIA_NULL;
|
||||
vou_hd_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_vou_hd_cken(dev, *vou_hd_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_VOU_SRST_REQ:{
|
||||
xmedia_bool *vou_srst_req = XMEDIA_NULL;
|
||||
vou_srst_req = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_vou_srst_req(*vou_srst_req);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_VOU_SRST_GET:{
|
||||
xmedia_bool *vou_srst = XMEDIA_NULL;
|
||||
vou_srst = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_vou_srst_get(vou_srst);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_DIV_CKEN:{
|
||||
xmedia_bool *lcd_div_cken = XMEDIA_NULL;
|
||||
lcd_div_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lcd_div_cken(*lcd_div_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_PLL_DIV_CKEN:{
|
||||
xmedia_bool *pll_div_cken = XMEDIA_NULL;
|
||||
pll_div_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_pll_div_cken(*pll_div_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_BT_HD_CKSEL:{
|
||||
xmedia_bool *bt_hd_cksel = XMEDIA_NULL;
|
||||
bt_hd_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_bt_hd_cksel(*bt_hd_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_HD_CKSEL:{
|
||||
xmedia_bool *lcd_hd_cksel = XMEDIA_NULL;
|
||||
lcd_hd_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lcd_hd_cksel(*lcd_hd_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_MIPITX_HD_CKSEL:{
|
||||
xmedia_bool *mipitx_hd_cksel = XMEDIA_NULL;
|
||||
mipitx_hd_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_mipitx_hd_cksel(*mipitx_hd_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDSTX_HD_CKSEL:{
|
||||
xmedia_bool *lvdstx_hd_cksel = XMEDIA_NULL;
|
||||
lvdstx_hd_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvdstx_hd_cksel(*lvdstx_hd_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_BT_PCTRL:{
|
||||
xmedia_bool *bt_pctrl = XMEDIA_NULL;
|
||||
bt_pctrl = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_bt_pctrl(*bt_pctrl);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_PCTRL:{
|
||||
xmedia_bool *lcd_pctrl = XMEDIA_NULL;
|
||||
lcd_pctrl = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lcd_pctrl(*lcd_pctrl);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_MIPITX_PCTRL:{
|
||||
xmedia_bool *mipitx_pctrl = XMEDIA_NULL;
|
||||
mipitx_pctrl = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_mipitx_pctrl(*mipitx_pctrl);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDSTX_PCTRL:{
|
||||
xmedia_bool *lvdstx_pctrl = XMEDIA_NULL;
|
||||
lvdstx_pctrl = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvdstx_pctrl(*lvdstx_pctrl);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_BT_CKEN:{
|
||||
xmedia_bool *bt_cken = XMEDIA_NULL;
|
||||
bt_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_bt_cken(*bt_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_CKEN:{
|
||||
xmedia_bool *lcd_cken = XMEDIA_NULL;
|
||||
lcd_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lcd_cken(*lcd_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_MIPITX_CKEN:{
|
||||
xmedia_bool *mipitx_cken = XMEDIA_NULL;
|
||||
mipitx_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_mipitx_cken(*mipitx_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDSTX_CKEN:{
|
||||
xmedia_bool *lvdstx_cken = XMEDIA_NULL;
|
||||
lvdstx_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvdstx_cken(*lvdstx_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
default: {
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
}
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef SYS_DRV_H
|
||||
#define SYS_DRV_H
|
||||
|
||||
#include "drv_sys.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
/*
|
||||
* End : Segment compress parameter data definition.
|
||||
*/
|
||||
xmedia_s32 sys_mod_init(xmedia_void);
|
||||
xmedia_s32 sys_mod_exit(xmedia_void);
|
||||
|
||||
xmedia_s32 sys_mod_ctrl(xmedia_chn_info *chn_info, sys_func_id func_id, xmedia_void *io_args);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
#endif /* End of #ifndef SYS_DRV_H */
|
||||
|
||||
@@ -0,0 +1,452 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "drv_reg_crg.h"
|
||||
#include "drv_reg_sys.h"
|
||||
#include "sys_hal.h"
|
||||
#include "xmedia_vo.h"
|
||||
#include "drv_vo_comm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
|
||||
#define DDRC0_REG_ADDR 0x120d0000 /* base addr of DDRCB */
|
||||
#define DDRC_REGS_SIZE 0x10000
|
||||
|
||||
#define SCT_REGS_ADDR 0x12050000 /* base addr of syscnt */
|
||||
#define SCT_REGS_SIZE 0x100
|
||||
|
||||
#define OTP_REGS_ADDR 0x100A0000
|
||||
#define OTP_REGS_SIZE 0X10000
|
||||
|
||||
#define APLL_VO_VCO_MAX 3700
|
||||
#define APLL_VO_VCO_MIN 1000
|
||||
|
||||
void *g_reg_crg_base_va = (void *)CRG_REGS_ADDR;
|
||||
void *g_reg_sys_base_va = (void *)SYS_REGS_ADDR;
|
||||
void *g_reg_ddr0_base_va = (void *)DDRC0_REG_ADDR;
|
||||
void *g_reg_misc_base_va = (void *)MISC_REGS_ADDR;
|
||||
void *g_reg_otp_base_va = (void *)OTP_REGS_ADDR;
|
||||
void *g_sct_addr = (void *)SCT_REGS_ADDR;
|
||||
|
||||
xmedia_u32 g_sys_efuse_addr = 0;
|
||||
xmedia_u32 g_sys_chip_addr = 0;
|
||||
|
||||
#define IO_CRG_ADDRESS(x) ((uintptr_t)g_reg_crg_base_va + ((x) - (CRG_REGS_ADDR)))
|
||||
#define IO_SYS_ADDRESS(x) ((uintptr_t)g_reg_sys_base_va + ((x) - (SYS_REGS_ADDR)))
|
||||
#define IO_DDR0_ADDRESS(x) ((uintptr_t)g_reg_ddr0_base_va + ((x) - (DDRC0_REG_ADDR)))
|
||||
#define IO_MISC_ADDRESS(x) ((uintptr_t)g_reg_misc_base_va + ((x) - (MISC_REGS_ADDR)))
|
||||
|
||||
static xmedia_u32 hal_vo_sys_reg_read(volatile xmedia_uintptr_t addr)
|
||||
{
|
||||
return *(volatile xmedia_u32 *)(addr);
|
||||
}
|
||||
|
||||
static xmedia_void hal_vo_sys_reg_write(volatile xmedia_uintptr_t addr, xmedia_u32 val)
|
||||
{
|
||||
*(volatile xmedia_u32 *)(addr) = val;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
static inline void sys_reg_set_bit(unsigned long value, unsigned long offset, unsigned long addr)
|
||||
{
|
||||
unsigned long t, mask;
|
||||
|
||||
mask = 1 << offset;
|
||||
t = hal_vo_sys_reg_read((xmedia_uintptr_t)addr);
|
||||
t &= ~mask;
|
||||
t |= (value << offset) & mask;
|
||||
hal_vo_sys_reg_write ( (xmedia_uintptr_t)addr, t);
|
||||
}
|
||||
|
||||
static inline void sys_reg_write_32(unsigned long value, unsigned long mask, unsigned long addr)
|
||||
{
|
||||
unsigned long t;
|
||||
|
||||
t = hal_vo_sys_reg_read((xmedia_uintptr_t)addr);
|
||||
t &= ~mask;
|
||||
t |= value & mask;
|
||||
hal_vo_sys_reg_write((xmedia_uintptr_t)addr, t);
|
||||
}
|
||||
|
||||
static inline void sys_reg_read(unsigned int *pvalue, unsigned long addr)
|
||||
{
|
||||
*pvalue = hal_vo_sys_reg_read((uintptr_t)addr);
|
||||
}
|
||||
|
||||
xmedia_s32 sys_hal_usrdef_slv_enable(xmedia_bool enable)
|
||||
{
|
||||
if (enable == XMEDIA_TRUE) {
|
||||
sys_reg_set_bit(1, 1, IO_CRG_ADDRESS(CRG_PERCTL50_ADDR)); // 打开时钟
|
||||
sys_reg_set_bit(0, 0, IO_CRG_ADDRESS(CRG_PERCTL50_ADDR)); // 撤消复位
|
||||
} else if (enable == XMEDIA_FALSE) {
|
||||
sys_reg_set_bit(0, 1, IO_CRG_ADDRESS(CRG_PERCTL50_ADDR)); // 关闭时钟
|
||||
} else {
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
xmedia_void sys_hal_vo_vou_hd_sel(xmedia_s32 vo_dev, xmedia_u32 vou_hd_sel)
|
||||
{
|
||||
if(vo_dev == 0) {
|
||||
sys_reg_write_32(vou_hd_sel << 1 , 0xf << 1, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else if (vo_dev == 1) {
|
||||
sys_reg_write_32(vou_hd_sel << 13 , 0xf << 13, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_vou_ppc_cksel(xmedia_u32 vou_ppc_cksel)
|
||||
{
|
||||
sys_reg_write_32(vou_ppc_cksel << 24 , 0x3 << 24, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_lvds_por_srst(xmedia_bool lvd_por_srst)
|
||||
{
|
||||
xmedia_u32 tmp = (lvd_por_srst == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 21, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
|
||||
}
|
||||
xmedia_void sys_hal_vo_mipitx_pll_ref_cksel(xmedia_bool mipitx_pll_ref_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (mipitx_pll_ref_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 20, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
|
||||
static inline xmedia_u64 vo_div64_u64(xmedia_u64 dividend, xmedia_u64 divisor)
|
||||
{
|
||||
return dividend / divisor;
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_lcd_div_cfg(xmedia_u32 lcd_div_cfg)
|
||||
{
|
||||
xmedia_u32 lcd_clk_div = (xmedia_u32)vo_div64_u64(vo_div64_u64((xmedia_u64)lcd_div_cfg , 1375) * (1 << 27),
|
||||
1000*1000);
|
||||
sys_reg_set_bit(0, 28, IO_CRG_ADDRESS(CRG_PERCTL65_ADDR));
|
||||
|
||||
sys_reg_write_32(lcd_clk_div, 0x7ffffff, IO_CRG_ADDRESS(CRG_PERCTL65_ADDR));
|
||||
}
|
||||
|
||||
static xmedia_s32 hal_vo_find_fout_div(xmedia_u32 *fout0_div, xmedia_u32 *fout1_div, xmedia_u32 pll_div,
|
||||
xmedia_u32 *pll_vco){
|
||||
xmedia_u32 fout0;
|
||||
xmedia_u32 fout1;
|
||||
xmedia_u32 vco;
|
||||
|
||||
//fout0 fout1 取值范围都是0 - 15
|
||||
for(fout0 = 0;fout0 < 16;fout0++) {
|
||||
for(fout1 = 0;fout1 < 16;fout1++) {
|
||||
vco = pll_div * (fout0 + 1) * (fout1 + 1);
|
||||
//vco的取值范围是950 - 3800，但ic要求不要取临近值，所以这里使用1000 - 3700
|
||||
if((vco > (APLL_VO_VCO_MIN * 1000)) && (vco < (APLL_VO_VCO_MAX * 1000))) {
|
||||
*fout0_div = fout0;
|
||||
*fout1_div = fout1;
|
||||
*pll_vco = vco;
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
}
|
||||
}
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
|
||||
xmedia_s32 sys_hal_vo_pll_div_cfg(xmedia_u32 pll_div_cfg)
|
||||
{
|
||||
xmedia_u32 apll_frac;
|
||||
xmedia_u32 apll_fbdiv;
|
||||
xmedia_u32 fout0_div;
|
||||
xmedia_u32 fout1_div;
|
||||
xmedia_u32 vco;
|
||||
xmedia_u32 pll_div;
|
||||
|
||||
//为避免超出u32范围 对1000取整计算
|
||||
pll_div = pll_div_cfg / 1000;
|
||||
|
||||
//理论不会存在获取不到分频因子的情况
|
||||
if(hal_vo_find_fout_div(&fout0_div, &fout1_div, pll_div, &vco) != XMEDIA_SUCCESS){
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
|
||||
//apll倍频整数部分
|
||||
apll_fbdiv = (vco / 24) / 1000;
|
||||
//apll倍频小数部分
|
||||
apll_frac = (vco / 24) % 1000;
|
||||
apll_frac = (apll_frac * ((1 << 24) / 1000));
|
||||
|
||||
sys_reg_write_32(apll_frac, 0xffffff, IO_CRG_ADDRESS(CRG_PERCTL0_ADDR));
|
||||
|
||||
// apll 小数/整数分频控制 默认为0 小数分频
|
||||
sys_reg_set_bit(0, 23, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
|
||||
//除了fout1 fout0 其他都bypass
|
||||
sys_reg_write_32(0xc << 18, 0xf << 18, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
|
||||
//参考时钟分频系数默认设置为1 apll参考时钟则为24mhz
|
||||
sys_reg_write_32(0x1 << 12, 0x3f << 12, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
|
||||
sys_reg_write_32(apll_fbdiv, 0xfff, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
|
||||
//APLL 配置fout0 fout1 分频因子
|
||||
sys_reg_write_32(fout0_div | (fout1_div << 4), 0xffff, IO_CRG_ADDRESS(CRG_PERCTL2_ADDR));
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_lvds_cksel(xmedia_s32 vo_dev, xmedia_bool lvds_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (lvds_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
if(vo_dev == 0) {
|
||||
sys_reg_set_bit(tmp, 22, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else if (vo_dev == 1){
|
||||
sys_reg_set_bit(tmp, 23, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_vou_hd_cken(xmedia_s32 vo_dev, xmedia_bool vou_hd_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (vou_hd_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
if(vo_dev == 0) {
|
||||
sys_reg_set_bit(tmp, 0, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else if (vo_dev == 1){
|
||||
sys_reg_set_bit(tmp, 12, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else {
|
||||
}
|
||||
}
|
||||
xmedia_void sys_hal_vo_vou_srst_req(xmedia_bool vou_srst_req)
|
||||
{
|
||||
xmedia_u32 tmp = (vou_srst_req == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 28, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
}
|
||||
|
||||
xmedia_s32 sys_hal_vo_vou_srst_get(xmedia_bool* vou_srst)
|
||||
{
|
||||
xmedia_u32 reg;
|
||||
|
||||
if (vou_srst == XMEDIA_NULL) {
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
|
||||
sys_reg_read(®, IO_CRG_ADDRESS(CRG_PERCTL121_ADDR));
|
||||
*vou_srst = (reg & 0x1); // bit[0]: vou reset state
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_lcd_div_cken(xmedia_bool lcd_div_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (lcd_div_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 27, IO_CRG_ADDRESS(CRG_PERCTL65_ADDR));
|
||||
|
||||
}
|
||||
xmedia_void sys_hal_vo_pll_div_cken(xmedia_bool pll_div_cken)
|
||||
{
|
||||
//0表示输出时钟,只使能或去使能fout1 fout0
|
||||
xmedia_u32 apll_foutpostdivpd = ((!pll_div_cken) << 1) | ((!pll_div_cken) << 0);
|
||||
sys_reg_write_32(apll_foutpostdivpd << 24, 0xf << 24, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
//APLL Power Down控制
|
||||
sys_reg_set_bit(!pll_div_cken, 29, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
//APLL VCO输出Power Down控制
|
||||
sys_reg_set_bit(!pll_div_cken, 28, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
//APLL 测试信号控制
|
||||
sys_reg_set_bit(!pll_div_cken, 22, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_bt_hd_cksel(xmedia_bool bt_hd_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (bt_hd_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 17, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lcd_hd_cksel(xmedia_bool lcd_hd_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (lcd_hd_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 16, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_mipitx_hd_cksel(xmedia_bool mipitx_hd_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (mipitx_hd_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 19, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lvdstx_hd_cksel(xmedia_bool lvdstx_hd_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (lvdstx_hd_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 18, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_bt_pctrl(xmedia_bool bt_pctrl)
|
||||
{
|
||||
xmedia_u32 tmp = (bt_pctrl == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 9, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lcd_pctrl(xmedia_bool lcd_pctrl)
|
||||
{
|
||||
xmedia_u32 tmp = (lcd_pctrl == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 8, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_mipitx_pctrl(xmedia_bool mipitx_pctrl)
|
||||
{
|
||||
xmedia_u32 tmp = (mipitx_pctrl == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 11, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lvdstx_pctrl(xmedia_bool lvdstx_pctrl)
|
||||
{
|
||||
xmedia_u32 tmp = (lvdstx_pctrl == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 10, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_bt_cken(xmedia_bool bt_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (bt_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 1, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lcd_cken(xmedia_bool lcd_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (lcd_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 0, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_mipitx_cken(xmedia_bool mipitx_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (mipitx_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 3, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lvdstx_cken(xmedia_bool lvdstx_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (lvdstx_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 2, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
|
||||
|
||||
xmedia_s32 sys_hal_init(xmedia_void)
|
||||
{
|
||||
#ifdef VO_KERNEL
|
||||
if (osal_spin_lock_init(&g_crg_spin_lock) < 0) {
|
||||
osal_printk("spinlock init fail, line: %d. \n", __LINE__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (g_reg_crg_base_va == XMEDIA_NULL) {
|
||||
g_reg_crg_base_va = (void *)osal_ioremap(CRG_REGS_ADDR, (xmedia_u32)CRG_REGS_SIZE);
|
||||
if (g_reg_crg_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap crg reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
if (g_reg_sys_base_va == XMEDIA_NULL) {
|
||||
g_reg_sys_base_va = (void *)osal_ioremap(SYS_REGS_ADDR, (xmedia_u32)SYS_REGS_SIZE);
|
||||
if (g_reg_sys_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap sys reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
if (g_reg_ddr0_base_va == XMEDIA_NULL) {
|
||||
g_reg_ddr0_base_va = (void *)osal_ioremap(DDRC0_REG_ADDR, (xmedia_u32)DDRC_REGS_SIZE);
|
||||
if (g_reg_ddr0_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap ddr0 reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
if (g_reg_misc_base_va == XMEDIA_NULL) {
|
||||
g_reg_misc_base_va = (void *)osal_ioremap(MISC_REGS_ADDR, (xmedia_u32)MISC_REGS_SIZE);
|
||||
if (g_reg_misc_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap MISC reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
/* version_id与性能限制相关，为了避免通过修改osal_ioremap来更改version_id,使用特殊的iomap函数 */
|
||||
if (g_reg_otp_base_va == XMEDIA_NULL) {
|
||||
#ifdef VO_KERNEL
|
||||
g_reg_otp_base_va = (void *)osal_ioremap(OTP_REGS_ADDR, (xmedia_u32)OTP_REGS_SIZE);
|
||||
#else
|
||||
g_reg_otp_base_va = sys_hal_zonediv(OTP_REGS_ADDR, (xmedia_u32)OTP_REGS_SIZE);
|
||||
#endif
|
||||
if (g_reg_otp_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap OTP reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
if (g_sct_addr == XMEDIA_NULL) {
|
||||
g_sct_addr = (void *)osal_ioremap(SCT_REGS_ADDR, (xmedia_u32)SCT_REGS_SIZE);
|
||||
if(g_sct_addr == XMEDIA_NULL) {
|
||||
osal_printk("remap SCT reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
sys_hal_exit();
|
||||
return -1;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_exit(xmedia_void)
|
||||
{
|
||||
#ifdef VO_KERNEL
|
||||
if (g_reg_crg_base_va != XMEDIA_NULL) {
|
||||
osal_iounmap(g_reg_crg_base_va);
|
||||
g_reg_crg_base_va = XMEDIA_NULL;
|
||||
}
|
||||
if (g_reg_sys_base_va != XMEDIA_NULL) {
|
||||
osal_iounmap(g_reg_sys_base_va);
|
||||
g_reg_sys_base_va = XMEDIA_NULL;
|
||||
}
|
||||
if (g_reg_ddr0_base_va != XMEDIA_NULL) {
|
||||
osal_iounmap(g_reg_ddr0_base_va);
|
||||
g_reg_ddr0_base_va = XMEDIA_NULL;
|
||||
}
|
||||
|
||||
if (g_reg_misc_base_va != XMEDIA_NULL) {
|
||||
osal_iounmap(g_reg_misc_base_va);
|
||||
g_reg_misc_base_va = XMEDIA_NULL;
|
||||
}
|
||||
|
||||
if (g_reg_otp_base_va != XMEDIA_NULL) {
|
||||
#ifdef VO_KERNEL
|
||||
osal_iounmap(g_reg_otp_base_va);
|
||||
#else
|
||||
sys_hal_atmos(g_reg_otp_base_va);
|
||||
#endif
|
||||
g_reg_otp_base_va = XMEDIA_NULL;
|
||||
}
|
||||
|
||||
if (g_sct_addr != XMEDIA_NULL) {
|
||||
osal_iounmap(g_sct_addr);
|
||||
g_sct_addr = XMEDIA_NULL;
|
||||
}
|
||||
|
||||
osal_spin_lock_destroy(&g_crg_spin_lock);
|
||||
|
||||
return;
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
#ifndef SYS_HAL_H
|
||||
#define SYS_HAL_H
|
||||
|
||||
#include "drv_vo_comm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
xmedia_s32 sys_hal_init(xmedia_void);
|
||||
xmedia_void sys_hal_exit(xmedia_void);
|
||||
|
||||
xmedia_void sys_hal_vo_vou_hd_sel(xmedia_s32 vo_dev, xmedia_u32 vou_hd_sel);
|
||||
xmedia_void sys_hal_vo_vou_ppc_cksel(xmedia_u32 vou_ppc_cksel);
|
||||
xmedia_void sys_hal_vo_lvds_por_srst(xmedia_bool lvd_por_srst);
|
||||
xmedia_void sys_hal_vo_mipitx_pll_ref_cksel(xmedia_bool mipitx_pll_ref_cksel);
|
||||
xmedia_void sys_hal_vo_lvds_cksel(xmedia_s32 vo_dev, xmedia_bool lvds_cksel);
|
||||
xmedia_void sys_hal_vo_lcd_div_cfg(xmedia_u32 lcd_div_cfg);
|
||||
xmedia_s32 sys_hal_vo_pll_div_cfg(xmedia_u32 pll_div_cfg);
|
||||
xmedia_void sys_hal_vo_vou_hd_cken(xmedia_s32 vo_dev, xmedia_bool vou_hd_cken);
|
||||
xmedia_void sys_hal_vo_vou_srst_req(xmedia_bool vou_srst_req);
|
||||
xmedia_s32 sys_hal_vo_vou_srst_get(xmedia_bool* vou_srst_req);
|
||||
xmedia_void sys_hal_vo_lcd_div_cken(xmedia_bool lcd_div_cken);
|
||||
xmedia_void sys_hal_vo_pll_div_cken(xmedia_bool pll_div_cken);
|
||||
xmedia_void sys_hal_vo_bt_hd_cksel(xmedia_bool bt_hd_cksel);
|
||||
xmedia_void sys_hal_vo_lcd_hd_cksel(xmedia_bool lcd_hd_cksel);
|
||||
xmedia_void sys_hal_vo_mipitx_hd_cksel(xmedia_bool mipitx_hd_cksel);
|
||||
xmedia_void sys_hal_vo_lvdstx_hd_cksel(xmedia_bool lvdstx_hd_cksel);
|
||||
xmedia_void sys_hal_vo_bt_pctrl(xmedia_bool bt_pctrl);
|
||||
xmedia_void sys_hal_vo_lcd_pctrl(xmedia_bool lcd_pctrl);
|
||||
xmedia_void sys_hal_vo_mipitx_pctrl(xmedia_bool mipitx_pctrl);
|
||||
xmedia_void sys_hal_vo_lvdstx_pctrl(xmedia_bool lvdstx_pctrl);
|
||||
xmedia_void sys_hal_vo_bt_cken(xmedia_bool bt_cken);
|
||||
xmedia_void sys_hal_vo_lcd_cken(xmedia_bool lcd_cken);
|
||||
xmedia_void sys_hal_vo_mipitx_cken(xmedia_bool mipitx_cken);
|
||||
xmedia_void sys_hal_vo_lvdstx_cken(xmedia_bool lvdstx_cken);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
#endif /* End of #ifndef SYS_HAL_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef DRV_REG_CRG_H
|
||||
#define DRV_REG_CRG_H
|
||||
|
||||
#define CRG_REGS_ADDR 0x12010000
|
||||
#define CRG_REGS_SIZE 0X10000
|
||||
|
||||
#define CRG_PERCTL0_ADDR (CRG_REGS_ADDR + 0x0)
|
||||
#define CRG_PERCTL1_ADDR (CRG_REGS_ADDR + 0x4)
|
||||
#define CRG_PERCTL2_ADDR (CRG_REGS_ADDR + 0x8)
|
||||
|
||||
#define CRG_PERCTL50_ADDR (CRG_REGS_ADDR + 0xc8)
|
||||
#define CRG_PERCTL65_ADDR (CRG_REGS_ADDR + 0x104)
|
||||
#define CRG_PERCTL66_ADDR (CRG_REGS_ADDR + 0x108)
|
||||
#define CRG_PERCTL67_ADDR (CRG_REGS_ADDR + 0x10c)
|
||||
#define CRG_PERCTL121_ADDR (CRG_REGS_ADDR + 0x1e4)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef DRV_REG_SYS_H
|
||||
#define DRV_REG_SYS_H
|
||||
|
||||
#define SYS_REGS_ADDR 0x12020000
|
||||
#define SYS_REGS_SIZE 0x8000
|
||||
|
||||
#define MISC_REGS_ADDR 0x12028000
|
||||
#define MISC_REGS_SIZE 0x8000
|
||||
|
||||
#endif
|
||||
+222
@@ -0,0 +1,222 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "common.h"
|
||||
#include "sys_drv.h"
|
||||
#include "sys_hal.h"
|
||||
#include "drv_sys.h"
|
||||
#include "xmedia_vo.h"
|
||||
#include "drv_vo_comm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
#define PHASE 32
|
||||
#define SYS_MULTI_V 1048576
|
||||
#define SYS_MULTI_H 1048576
|
||||
|
||||
|
||||
|
||||
xmedia_s32 sys_mod_init(xmedia_void)
|
||||
{
|
||||
xmedia_s32 ret;
|
||||
ret = sys_hal_init();
|
||||
return ret;
|
||||
}
|
||||
|
||||
xmedia_s32 sys_mod_exit(xmedia_void)
|
||||
{
|
||||
sys_hal_exit();
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
xmedia_s32 sys_mod_ctrl(xmedia_chn_info *chn_info, sys_func_id func_id, xmedia_void *io_args)
|
||||
{
|
||||
xmedia_s32 dev;
|
||||
|
||||
dev = chn_info->dev_id;
|
||||
switch (func_id) {
|
||||
case SYS_VO_VOU_HD_CKSEL:{
|
||||
xmedia_u32 *vou_hd_sel = XMEDIA_NULL;
|
||||
vou_hd_sel = (xmedia_u32 *)io_args;
|
||||
sys_hal_vo_vou_hd_sel(dev, *vou_hd_sel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_VOU_PPC_CKSEL: {
|
||||
xmedia_u32 *vou_ppc_cksel = XMEDIA_NULL;
|
||||
vou_ppc_cksel = (xmedia_u32 *)io_args;
|
||||
sys_hal_vo_vou_ppc_cksel(*vou_ppc_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDS_POR_SRST: {
|
||||
xmedia_bool *lvd_por_srst = XMEDIA_NULL;
|
||||
lvd_por_srst = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvds_por_srst(*lvd_por_srst);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_MIPITX_PLL_REF_CKSEL: {
|
||||
xmedia_bool *mipitx_pll_ref_cksel = XMEDIA_NULL;
|
||||
mipitx_pll_ref_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_mipitx_pll_ref_cksel(*mipitx_pll_ref_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDS_CKSEL:{
|
||||
xmedia_bool *lvds_cksel = XMEDIA_NULL;
|
||||
lvds_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvds_cksel(dev, *lvds_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_DIV_CFG:{
|
||||
xmedia_u32 *lcd_div_cfg = XMEDIA_NULL;
|
||||
lcd_div_cfg = (xmedia_u32 *)io_args;
|
||||
sys_hal_vo_lcd_div_cfg(*lcd_div_cfg);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_PLL_DIV_CFG:{
|
||||
xmedia_u32 *pll_div_cfg = XMEDIA_NULL;
|
||||
pll_div_cfg = (xmedia_u32 *)io_args;
|
||||
if(sys_hal_vo_pll_div_cfg(*pll_div_cfg) != XMEDIA_SUCCESS) {
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_VOU_HD_CKEN:{
|
||||
xmedia_bool *vou_hd_cken = XMEDIA_NULL;
|
||||
vou_hd_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_vou_hd_cken(dev, *vou_hd_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_VOU_SRST_REQ:{
|
||||
xmedia_bool *vou_srst_req = XMEDIA_NULL;
|
||||
vou_srst_req = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_vou_srst_req(*vou_srst_req);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_VOU_SRST_GET:{
|
||||
xmedia_bool *vou_srst = XMEDIA_NULL;
|
||||
vou_srst = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_vou_srst_get(vou_srst);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_DIV_CKEN:{
|
||||
xmedia_bool *lcd_div_cken = XMEDIA_NULL;
|
||||
lcd_div_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lcd_div_cken(*lcd_div_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_PLL_DIV_CKEN:{
|
||||
xmedia_bool *pll_div_cken = XMEDIA_NULL;
|
||||
pll_div_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_pll_div_cken(*pll_div_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_BT_HD_CKSEL:{
|
||||
xmedia_bool *bt_hd_cksel = XMEDIA_NULL;
|
||||
bt_hd_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_bt_hd_cksel(*bt_hd_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_HD_CKSEL:{
|
||||
xmedia_bool *lcd_hd_cksel = XMEDIA_NULL;
|
||||
lcd_hd_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lcd_hd_cksel(*lcd_hd_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_MIPITX_HD_CKSEL:{
|
||||
xmedia_bool *mipitx_hd_cksel = XMEDIA_NULL;
|
||||
mipitx_hd_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_mipitx_hd_cksel(*mipitx_hd_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDSTX_HD_CKSEL:{
|
||||
xmedia_bool *lvdstx_hd_cksel = XMEDIA_NULL;
|
||||
lvdstx_hd_cksel = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvdstx_hd_cksel(*lvdstx_hd_cksel);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_BT_PCTRL:{
|
||||
xmedia_bool *bt_pctrl = XMEDIA_NULL;
|
||||
bt_pctrl = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_bt_pctrl(*bt_pctrl);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_PCTRL:{
|
||||
xmedia_bool *lcd_pctrl = XMEDIA_NULL;
|
||||
lcd_pctrl = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lcd_pctrl(*lcd_pctrl);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_MIPITX_PCTRL:{
|
||||
xmedia_bool *mipitx_pctrl = XMEDIA_NULL;
|
||||
mipitx_pctrl = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_mipitx_pctrl(*mipitx_pctrl);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDSTX_PCTRL:{
|
||||
xmedia_bool *lvdstx_pctrl = XMEDIA_NULL;
|
||||
lvdstx_pctrl = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvdstx_pctrl(*lvdstx_pctrl);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_BT_CKEN:{
|
||||
xmedia_bool *bt_cken = XMEDIA_NULL;
|
||||
bt_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_bt_cken(*bt_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LCD_CKEN:{
|
||||
xmedia_bool *lcd_cken = XMEDIA_NULL;
|
||||
lcd_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lcd_cken(*lcd_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_MIPITX_CKEN:{
|
||||
xmedia_bool *mipitx_cken = XMEDIA_NULL;
|
||||
mipitx_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_mipitx_cken(*mipitx_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_VO_LVDSTX_CKEN:{
|
||||
xmedia_bool *lvdstx_cken = XMEDIA_NULL;
|
||||
lvdstx_cken = (xmedia_bool *)io_args;
|
||||
sys_hal_vo_lvdstx_cken(*lvdstx_cken);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
default: {
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
}
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef SYS_DRV_H
|
||||
#define SYS_DRV_H
|
||||
|
||||
#include "drv_sys.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
/*
|
||||
* End : Segment compress parameter data definition.
|
||||
*/
|
||||
xmedia_s32 sys_mod_init(xmedia_void);
|
||||
xmedia_s32 sys_mod_exit(xmedia_void);
|
||||
|
||||
xmedia_s32 sys_mod_ctrl(xmedia_chn_info *chn_info, sys_func_id func_id, xmedia_void *io_args);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
#endif /* End of #ifndef SYS_DRV_H */
|
||||
|
||||
+453
@@ -0,0 +1,453 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "drv_reg_crg.h"
|
||||
#include "drv_reg_sys.h"
|
||||
#include "sys_hal.h"
|
||||
#include "xmedia_vo.h"
|
||||
#include "drv_vo_comm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
|
||||
#define DDRC0_REG_ADDR 0x120d0000 /* base addr of DDRCB */
|
||||
#define DDRC_REGS_SIZE 0x10000
|
||||
|
||||
#define SCT_REGS_ADDR 0x12050000 /* base addr of syscnt */
|
||||
#define SCT_REGS_SIZE 0x100
|
||||
|
||||
#define OTP_REGS_ADDR 0x100A0000
|
||||
#define OTP_REGS_SIZE 0X10000
|
||||
|
||||
#define APLL_VO_VCO_MAX 3700
|
||||
#define APLL_VO_VCO_MIN 1000
|
||||
#define VO_LCD_DIV_SRC 1188
|
||||
|
||||
void *g_reg_crg_base_va = (void *)CRG_REGS_ADDR;
|
||||
void *g_reg_sys_base_va = (void *)SYS_REGS_ADDR;
|
||||
void *g_reg_ddr0_base_va = (void *)DDRC0_REG_ADDR;
|
||||
void *g_reg_misc_base_va = (void *)MISC_REGS_ADDR;
|
||||
void *g_reg_otp_base_va = (void *)OTP_REGS_ADDR;
|
||||
void *g_sct_addr = (void *)SCT_REGS_ADDR;
|
||||
|
||||
xmedia_u32 g_sys_efuse_addr = 0;
|
||||
xmedia_u32 g_sys_chip_addr = 0;
|
||||
|
||||
#define IO_CRG_ADDRESS(x) ((uintptr_t)g_reg_crg_base_va + ((x) - (CRG_REGS_ADDR)))
|
||||
#define IO_SYS_ADDRESS(x) ((uintptr_t)g_reg_sys_base_va + ((x) - (SYS_REGS_ADDR)))
|
||||
#define IO_DDR0_ADDRESS(x) ((uintptr_t)g_reg_ddr0_base_va + ((x) - (DDRC0_REG_ADDR)))
|
||||
#define IO_MISC_ADDRESS(x) ((uintptr_t)g_reg_misc_base_va + ((x) - (MISC_REGS_ADDR)))
|
||||
|
||||
static xmedia_u32 hal_vo_sys_reg_read(volatile xmedia_uintptr_t addr)
|
||||
{
|
||||
return *(volatile xmedia_u32 *)(addr);
|
||||
}
|
||||
|
||||
static xmedia_void hal_vo_sys_reg_write(volatile xmedia_uintptr_t addr, xmedia_u32 val)
|
||||
{
|
||||
*(volatile xmedia_u32 *)(addr) = val;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
static inline void sys_reg_set_bit(unsigned long value, unsigned long offset, unsigned long addr)
|
||||
{
|
||||
unsigned long t, mask;
|
||||
|
||||
mask = 1 << offset;
|
||||
t = hal_vo_sys_reg_read((xmedia_uintptr_t)addr);
|
||||
t &= ~mask;
|
||||
t |= (value << offset) & mask;
|
||||
hal_vo_sys_reg_write ( (xmedia_uintptr_t)addr, t);
|
||||
}
|
||||
|
||||
static inline void sys_reg_write_32(unsigned long value, unsigned long mask, unsigned long addr)
|
||||
{
|
||||
unsigned long t;
|
||||
|
||||
t = hal_vo_sys_reg_read((xmedia_uintptr_t)addr);
|
||||
t &= ~mask;
|
||||
t |= value & mask;
|
||||
hal_vo_sys_reg_write((xmedia_uintptr_t)addr, t);
|
||||
}
|
||||
|
||||
static inline void sys_reg_read(unsigned int *pvalue, unsigned long addr)
|
||||
{
|
||||
*pvalue = hal_vo_sys_reg_read((uintptr_t)addr);
|
||||
}
|
||||
|
||||
xmedia_s32 sys_hal_usrdef_slv_enable(xmedia_bool enable)
|
||||
{
|
||||
if (enable == XMEDIA_TRUE) {
|
||||
sys_reg_set_bit(1, 1, IO_CRG_ADDRESS(CRG_PERCTL50_ADDR)); // 打开时钟
|
||||
sys_reg_set_bit(0, 0, IO_CRG_ADDRESS(CRG_PERCTL50_ADDR)); // 撤消复位
|
||||
} else if (enable == XMEDIA_FALSE) {
|
||||
sys_reg_set_bit(0, 1, IO_CRG_ADDRESS(CRG_PERCTL50_ADDR)); // 关闭时钟
|
||||
} else {
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
xmedia_void sys_hal_vo_vou_hd_sel(xmedia_s32 vo_dev, xmedia_u32 vou_hd_sel)
|
||||
{
|
||||
if(vo_dev == 0) {
|
||||
sys_reg_write_32(vou_hd_sel << 1 , 0xf << 1, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else if (vo_dev == 1) {
|
||||
sys_reg_write_32(vou_hd_sel << 13 , 0xf << 13, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_vou_ppc_cksel(xmedia_u32 vou_ppc_cksel)
|
||||
{
|
||||
sys_reg_write_32(vou_ppc_cksel << 24 , 0x3 << 24, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_lvds_por_srst(xmedia_bool lvd_por_srst)
|
||||
{
|
||||
xmedia_u32 tmp = (lvd_por_srst == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 21, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
|
||||
}
|
||||
xmedia_void sys_hal_vo_mipitx_pll_ref_cksel(xmedia_bool mipitx_pll_ref_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (mipitx_pll_ref_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 20, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
|
||||
static inline xmedia_u64 vo_div64_u64(xmedia_u64 dividend, xmedia_u64 divisor)
|
||||
{
|
||||
return dividend / divisor;
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_lcd_div_cfg(xmedia_u32 lcd_div_cfg)
|
||||
{
|
||||
xmedia_u32 lcd_clk_div = (xmedia_u32)vo_div64_u64(vo_div64_u64((xmedia_u64)lcd_div_cfg , VO_LCD_DIV_SRC) * (1 << 27),
|
||||
1000*1000);
|
||||
sys_reg_set_bit(0, 28, IO_CRG_ADDRESS(CRG_PERCTL65_ADDR));
|
||||
|
||||
sys_reg_write_32(lcd_clk_div, 0x7ffffff, IO_CRG_ADDRESS(CRG_PERCTL65_ADDR));
|
||||
}
|
||||
|
||||
static xmedia_s32 hal_vo_find_fout_div(xmedia_u32 *fout0_div, xmedia_u32 *fout1_div, xmedia_u32 pll_div,
|
||||
xmedia_u32 *pll_vco){
|
||||
xmedia_u32 fout0;
|
||||
xmedia_u32 fout1;
|
||||
xmedia_u32 vco;
|
||||
|
||||
//fout0 fout1 取值范围都是0 - 15
|
||||
for(fout0 = 0;fout0 < 16;fout0++) {
|
||||
for(fout1 = 0;fout1 < 16;fout1++) {
|
||||
vco = pll_div * (fout0 + 1) * (fout1 + 1);
|
||||
//vco的取值范围是950 - 3800，但ic要求不要取临近值，所以这里使用1000 - 3700
|
||||
if((vco > (APLL_VO_VCO_MIN * 1000)) && (vco < (APLL_VO_VCO_MAX * 1000))) {
|
||||
*fout0_div = fout0;
|
||||
*fout1_div = fout1;
|
||||
*pll_vco = vco;
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
}
|
||||
}
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
|
||||
xmedia_s32 sys_hal_vo_pll_div_cfg(xmedia_u32 pll_div_cfg)
|
||||
{
|
||||
xmedia_u32 apll_frac;
|
||||
xmedia_u32 apll_fbdiv;
|
||||
xmedia_u32 fout0_div;
|
||||
xmedia_u32 fout1_div;
|
||||
xmedia_u32 vco;
|
||||
xmedia_u32 pll_div;
|
||||
|
||||
//为避免超出u32范围 对1000取整计算
|
||||
pll_div = pll_div_cfg / 1000;
|
||||
|
||||
//理论不会存在获取不到分频因子的情况
|
||||
if(hal_vo_find_fout_div(&fout0_div, &fout1_div, pll_div, &vco) != XMEDIA_SUCCESS){
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
|
||||
//apll倍频整数部分
|
||||
apll_fbdiv = (vco / 24) / 1000;
|
||||
//apll倍频小数部分
|
||||
apll_frac = (vco / 24) % 1000;
|
||||
apll_frac = (apll_frac * ((1 << 24) / 1000));
|
||||
|
||||
sys_reg_write_32(apll_frac, 0xffffff, IO_CRG_ADDRESS(CRG_PERCTL0_ADDR));
|
||||
|
||||
// apll 小数/整数分频控制 默认为0 小数分频
|
||||
sys_reg_set_bit(0, 23, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
|
||||
//除了fout1 fout0 其他都bypass
|
||||
sys_reg_write_32(0xc << 18, 0xf << 18, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
|
||||
//参考时钟分频系数默认设置为1 apll参考时钟则为24mhz
|
||||
sys_reg_write_32(0x1 << 12, 0x3f << 12, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
|
||||
sys_reg_write_32(apll_fbdiv, 0xfff, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
|
||||
//APLL 配置fout0 fout1 分频因子
|
||||
sys_reg_write_32(fout0_div | (fout1_div << 4), 0xffff, IO_CRG_ADDRESS(CRG_PERCTL2_ADDR));
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_lvds_cksel(xmedia_s32 vo_dev, xmedia_bool lvds_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (lvds_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
if(vo_dev == 0) {
|
||||
sys_reg_set_bit(tmp, 22, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else if (vo_dev == 1){
|
||||
sys_reg_set_bit(tmp, 23, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_vou_hd_cken(xmedia_s32 vo_dev, xmedia_bool vou_hd_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (vou_hd_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
if(vo_dev == 0) {
|
||||
sys_reg_set_bit(tmp, 0, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else if (vo_dev == 1){
|
||||
sys_reg_set_bit(tmp, 12, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
} else {
|
||||
}
|
||||
}
|
||||
xmedia_void sys_hal_vo_vou_srst_req(xmedia_bool vou_srst_req)
|
||||
{
|
||||
xmedia_u32 tmp = (vou_srst_req == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 28, IO_CRG_ADDRESS(CRG_PERCTL67_ADDR));
|
||||
}
|
||||
|
||||
xmedia_s32 sys_hal_vo_vou_srst_get(xmedia_bool* vou_srst)
|
||||
{
|
||||
xmedia_u32 reg;
|
||||
|
||||
if (vou_srst == XMEDIA_NULL) {
|
||||
return XMEDIA_FAILURE;
|
||||
}
|
||||
|
||||
sys_reg_read(®, IO_CRG_ADDRESS(CRG_PERCTL121_ADDR));
|
||||
*vou_srst = (reg & 0x1); // bit[0]: vou reset state
|
||||
return XMEDIA_SUCCESS;
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_vo_lcd_div_cken(xmedia_bool lcd_div_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (lcd_div_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 27, IO_CRG_ADDRESS(CRG_PERCTL65_ADDR));
|
||||
|
||||
}
|
||||
xmedia_void sys_hal_vo_pll_div_cken(xmedia_bool pll_div_cken)
|
||||
{
|
||||
//0表示输出时钟,只使能或去使能fout1 fout0
|
||||
xmedia_u32 apll_foutpostdivpd = ((!pll_div_cken) << 1) | ((!pll_div_cken) << 0);
|
||||
sys_reg_write_32(apll_foutpostdivpd << 24, 0xf << 24, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
//APLL Power Down控制
|
||||
sys_reg_set_bit(!pll_div_cken, 29, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
//APLL VCO输出Power Down控制
|
||||
sys_reg_set_bit(!pll_div_cken, 28, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
//APLL 测试信号控制
|
||||
sys_reg_set_bit(!pll_div_cken, 22, IO_CRG_ADDRESS(CRG_PERCTL1_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_bt_hd_cksel(xmedia_bool bt_hd_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (bt_hd_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 17, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lcd_hd_cksel(xmedia_bool lcd_hd_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (lcd_hd_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 16, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_mipitx_hd_cksel(xmedia_bool mipitx_hd_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (mipitx_hd_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 19, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lvdstx_hd_cksel(xmedia_bool lvdstx_hd_cksel)
|
||||
{
|
||||
xmedia_u32 tmp = (lvdstx_hd_cksel == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 18, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_bt_pctrl(xmedia_bool bt_pctrl)
|
||||
{
|
||||
xmedia_u32 tmp = (bt_pctrl == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 9, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lcd_pctrl(xmedia_bool lcd_pctrl)
|
||||
{
|
||||
xmedia_u32 tmp = (lcd_pctrl == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 8, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_mipitx_pctrl(xmedia_bool mipitx_pctrl)
|
||||
{
|
||||
xmedia_u32 tmp = (mipitx_pctrl == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 11, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lvdstx_pctrl(xmedia_bool lvdstx_pctrl)
|
||||
{
|
||||
xmedia_u32 tmp = (lvdstx_pctrl == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 10, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_bt_cken(xmedia_bool bt_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (bt_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 1, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lcd_cken(xmedia_bool lcd_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (lcd_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 0, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_mipitx_cken(xmedia_bool mipitx_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (mipitx_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 3, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
xmedia_void sys_hal_vo_lvdstx_cken(xmedia_bool lvdstx_cken)
|
||||
{
|
||||
xmedia_u32 tmp = (lvdstx_cken == XMEDIA_TRUE) ? 1 : 0;
|
||||
|
||||
sys_reg_set_bit(tmp, 2, IO_CRG_ADDRESS(CRG_PERCTL66_ADDR));
|
||||
}
|
||||
|
||||
|
||||
xmedia_s32 sys_hal_init(xmedia_void)
|
||||
{
|
||||
#ifdef VO_KERNEL
|
||||
if (osal_spin_lock_init(&g_crg_spin_lock) < 0) {
|
||||
osal_printk("spinlock init fail, line: %d. \n", __LINE__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (g_reg_crg_base_va == XMEDIA_NULL) {
|
||||
g_reg_crg_base_va = (void *)osal_ioremap(CRG_REGS_ADDR, (xmedia_u32)CRG_REGS_SIZE);
|
||||
if (g_reg_crg_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap crg reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
if (g_reg_sys_base_va == XMEDIA_NULL) {
|
||||
g_reg_sys_base_va = (void *)osal_ioremap(SYS_REGS_ADDR, (xmedia_u32)SYS_REGS_SIZE);
|
||||
if (g_reg_sys_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap sys reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
if (g_reg_ddr0_base_va == XMEDIA_NULL) {
|
||||
g_reg_ddr0_base_va = (void *)osal_ioremap(DDRC0_REG_ADDR, (xmedia_u32)DDRC_REGS_SIZE);
|
||||
if (g_reg_ddr0_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap ddr0 reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
if (g_reg_misc_base_va == XMEDIA_NULL) {
|
||||
g_reg_misc_base_va = (void *)osal_ioremap(MISC_REGS_ADDR, (xmedia_u32)MISC_REGS_SIZE);
|
||||
if (g_reg_misc_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap MISC reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
/* version_id与性能限制相关，为了避免通过修改osal_ioremap来更改version_id,使用特殊的iomap函数 */
|
||||
if (g_reg_otp_base_va == XMEDIA_NULL) {
|
||||
#ifdef VO_KERNEL
|
||||
g_reg_otp_base_va = (void *)osal_ioremap(OTP_REGS_ADDR, (xmedia_u32)OTP_REGS_SIZE);
|
||||
#else
|
||||
g_reg_otp_base_va = sys_hal_zonediv(OTP_REGS_ADDR, (xmedia_u32)OTP_REGS_SIZE);
|
||||
#endif
|
||||
if (g_reg_otp_base_va == XMEDIA_NULL) {
|
||||
osal_printk("remap OTP reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
if (g_sct_addr == XMEDIA_NULL) {
|
||||
g_sct_addr = (void *)osal_ioremap(SCT_REGS_ADDR, (xmedia_u32)SCT_REGS_SIZE);
|
||||
if(g_sct_addr == XMEDIA_NULL) {
|
||||
osal_printk("remap SCT reg fail, line: %d. \n", __LINE__);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
sys_hal_exit();
|
||||
return -1;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
xmedia_void sys_hal_exit(xmedia_void)
|
||||
{
|
||||
#ifdef VO_KERNEL
|
||||
if (g_reg_crg_base_va != XMEDIA_NULL) {
|
||||
osal_iounmap(g_reg_crg_base_va);
|
||||
g_reg_crg_base_va = XMEDIA_NULL;
|
||||
}
|
||||
if (g_reg_sys_base_va != XMEDIA_NULL) {
|
||||
osal_iounmap(g_reg_sys_base_va);
|
||||
g_reg_sys_base_va = XMEDIA_NULL;
|
||||
}
|
||||
if (g_reg_ddr0_base_va != XMEDIA_NULL) {
|
||||
osal_iounmap(g_reg_ddr0_base_va);
|
||||
g_reg_ddr0_base_va = XMEDIA_NULL;
|
||||
}
|
||||
|
||||
if (g_reg_misc_base_va != XMEDIA_NULL) {
|
||||
osal_iounmap(g_reg_misc_base_va);
|
||||
g_reg_misc_base_va = XMEDIA_NULL;
|
||||
}
|
||||
|
||||
if (g_reg_otp_base_va != XMEDIA_NULL) {
|
||||
#ifdef VO_KERNEL
|
||||
osal_iounmap(g_reg_otp_base_va);
|
||||
#else
|
||||
sys_hal_atmos(g_reg_otp_base_va);
|
||||
#endif
|
||||
g_reg_otp_base_va = XMEDIA_NULL;
|
||||
}
|
||||
|
||||
if (g_sct_addr != XMEDIA_NULL) {
|
||||
osal_iounmap(g_sct_addr);
|
||||
g_sct_addr = XMEDIA_NULL;
|
||||
}
|
||||
|
||||
osal_spin_lock_destroy(&g_crg_spin_lock);
|
||||
|
||||
return;
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) XMEDIA. All rights reserved.
|
||||
*/
|
||||
#ifndef SYS_HAL_H
|
||||
#define SYS_HAL_H
|
||||
|
||||
#include "drv_vo_comm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
xmedia_s32 sys_hal_init(xmedia_void);
|
||||
xmedia_void sys_hal_exit(xmedia_void);
|
||||
|
||||
xmedia_void sys_hal_vo_vou_hd_sel(xmedia_s32 vo_dev, xmedia_u32 vou_hd_sel);
|
||||
xmedia_void sys_hal_vo_vou_ppc_cksel(xmedia_u32 vou_ppc_cksel);
|
||||
xmedia_void sys_hal_vo_lvds_por_srst(xmedia_bool lvd_por_srst);
|
||||
xmedia_void sys_hal_vo_mipitx_pll_ref_cksel(xmedia_bool mipitx_pll_ref_cksel);
|
||||
xmedia_void sys_hal_vo_lvds_cksel(xmedia_s32 vo_dev, xmedia_bool lvds_cksel);
|
||||
xmedia_void sys_hal_vo_lcd_div_cfg(xmedia_u32 lcd_div_cfg);
|
||||
xmedia_s32 sys_hal_vo_pll_div_cfg(xmedia_u32 pll_div_cfg);
|
||||
xmedia_void sys_hal_vo_vou_hd_cken(xmedia_s32 vo_dev, xmedia_bool vou_hd_cken);
|
||||
xmedia_void sys_hal_vo_vou_srst_req(xmedia_bool vou_srst_req);
|
||||
xmedia_s32 sys_hal_vo_vou_srst_get(xmedia_bool* vou_srst_req);
|
||||
xmedia_void sys_hal_vo_lcd_div_cken(xmedia_bool lcd_div_cken);
|
||||
xmedia_void sys_hal_vo_pll_div_cken(xmedia_bool pll_div_cken);
|
||||
xmedia_void sys_hal_vo_bt_hd_cksel(xmedia_bool bt_hd_cksel);
|
||||
xmedia_void sys_hal_vo_lcd_hd_cksel(xmedia_bool lcd_hd_cksel);
|
||||
xmedia_void sys_hal_vo_mipitx_hd_cksel(xmedia_bool mipitx_hd_cksel);
|
||||
xmedia_void sys_hal_vo_lvdstx_hd_cksel(xmedia_bool lvdstx_hd_cksel);
|
||||
xmedia_void sys_hal_vo_bt_pctrl(xmedia_bool bt_pctrl);
|
||||
xmedia_void sys_hal_vo_lcd_pctrl(xmedia_bool lcd_pctrl);
|
||||
xmedia_void sys_hal_vo_mipitx_pctrl(xmedia_bool mipitx_pctrl);
|
||||
xmedia_void sys_hal_vo_lvdstx_pctrl(xmedia_bool lvdstx_pctrl);
|
||||
xmedia_void sys_hal_vo_bt_cken(xmedia_bool bt_cken);
|
||||
xmedia_void sys_hal_vo_lcd_cken(xmedia_bool lcd_cken);
|
||||
xmedia_void sys_hal_vo_mipitx_cken(xmedia_bool mipitx_cken);
|
||||
xmedia_void sys_hal_vo_lvdstx_cken(xmedia_bool lvdstx_cken);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* End of #ifdef __cplusplus */
|
||||
|
||||
#endif /* End of #ifndef SYS_HAL_H */
|
||||
Reference in New Issue
Block a user