GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/arch/arm/cpu/arm1136/mx31/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= generic.o
+obj-y	+= timer.o
+obj-y	+= devices.o
+obj-y	+= relocate.o

source/bootloader/u-boot-2020.01/arch/arm/cpu/arm1136/mx31/devices.c

@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+void mx31_uart1_hw_init(void)
+{
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+}
+
+void mx31_uart2_hw_init(void)
+{
+	/* setup pins for UART2 */
+	mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
+	mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
+}
+
+#ifdef CONFIG_MXC_SPI
+/*
+ * Note: putting several spi setups here makes no sense as they may differ
+ * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
+ */
+void mx31_spi2_hw_init(void)
+{
+	/* SPI2 */
+	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+	/* start SPI2 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/arm/cpu/arm1136/mx31/generic.c

@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+static u32 mx31_decode_pll(u32 reg, u32 infreq)
+{
+	u32 mfi = GET_PLL_MFI(reg);
+	s32 mfn = GET_PLL_MFN(reg);
+	u32 mfd = GET_PLL_MFD(reg);
+	u32 pd =  GET_PLL_PD(reg);
+
+	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
+	mfd += 1;
+	pd += 1;
+
+	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+		mfd * pd);
+}
+
+static u32 mx31_get_mpl_dpdgck_clk(void)
+{
+	u32 infreq;
+
+	if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+		infreq = MXC_CLK32 * 1024;
+	else
+		infreq = MXC_HCLK;
+
+	return mx31_decode_pll(readl(CCM_MPCTL), infreq);
+}
+
+static u32 mx31_get_mcu_main_clk(void)
+{
+	/* For now we assume mpl_dpdgck_clk == mcu_main_clk
+	 * which should be correct for most boards
+	 */
+	return mx31_get_mpl_dpdgck_clk();
+}
+
+static u32 mx31_get_ipg_clk(void)
+{
+	u32 freq = mx31_get_mcu_main_clk();
+	u32 pdr0 = readl(CCM_PDR0);
+
+	freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
+	freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
+
+	return freq;
+}
+
+/* hsp is the clock for the ipu */
+static u32 mx31_get_hsp_clk(void)
+{
+	u32 freq = mx31_get_mcu_main_clk();
+	u32 pdr0 = readl(CCM_PDR0);
+
+	freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
+
+	return freq;
+}
+
+void mx31_dump_clocks(void)
+{
+	u32 cpufreq = mx31_get_mcu_main_clk();
+	printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
+	printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
+	printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return mx31_get_mcu_main_clk();
+	case MXC_IPG_CLK:
+	case MXC_IPG_PERCLK:
+	case MXC_CSPI_CLK:
+	case MXC_UART_CLK:
+	case MXC_ESDHC_CLK:
+	case MXC_I2C_CLK:
+		return mx31_get_ipg_clk();
+	case MXC_IPU_CLK:
+		return mx31_get_hsp_clk();
+	}
+	return -1;
+}
+
+u32 imx_get_uartclk(void)
+{
+	return mxc_get_clock(MXC_UART_CLK);
+}
+
+void mx31_gpio_mux(unsigned long mode)
+{
+	unsigned long reg, shift, tmp;
+
+	reg = IOMUXC_BASE + (mode & 0x1fc);
+	shift = (~mode & 0x3) * 8;
+
+	tmp = readl(reg);
+	tmp &= ~(0xff << shift);
+	tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
+	writel(tmp, reg);
+}
+
+void mx31_set_pad(enum iomux_pins pin, u32 config)
+{
+	u32 field, l, reg;
+
+	pin &= IOMUX_PADNUM_MASK;
+	reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
+	field = (pin + 2) % 3;
+
+	l = readl(reg);
+	l &= ~(0x1ff << (field * 10));
+	l |= config << (field * 10);
+	writel(l, reg);
+
+}
+
+void mx31_set_gpr(enum iomux_gp_func gp, char en)
+{
+	u32 l;
+	struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
+
+	l = readl(&iomuxc->gpr);
+	if (en)
+		l |= gp;
+	else
+		l &= ~gp;
+
+	writel(l, &iomuxc->gpr);
+}
+
+void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
+{
+	struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
+	struct mx31_weim_cscr *cscr = &weim->cscr[cs];
+
+	writel(weimcs->upper, &cscr->upper);
+	writel(weimcs->lower, &cscr->lower);
+	writel(weimcs->additional, &cscr->additional);
+}
+
+struct mx3_cpu_type mx31_cpu_type[] = {
+	{ .srev = 0x00, .v = 0x10 },
+	{ .srev = 0x10, .v = 0x11 },
+	{ .srev = 0x11, .v = 0x11 },
+	{ .srev = 0x12, .v = 0x1F },
+	{ .srev = 0x13, .v = 0x1F },
+	{ .srev = 0x14, .v = 0x12 },
+	{ .srev = 0x15, .v = 0x12 },
+	{ .srev = 0x28, .v = 0x20 },
+	{ .srev = 0x29, .v = 0x20 },
+};
+
+u32 get_cpu_rev(void)
+{
+	u32 i, srev;
+
+	/* read SREV register from IIM module */
+	struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
+	srev = readl(&iim->iim_srev);
+
+	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+		if (srev == mx31_cpu_type[i].srev)
+			return mx31_cpu_type[i].v | (MXC_CPU_MX31 << 12);
+
+	return srev | 0x8000;
+}
+
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct clock_control_regs *ccm =
+		(struct clock_control_regs *)CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x07;
+
+	switch (cause) {
+	case 0x0000:
+		return "POR";
+	case 0x0001:
+		return "RST";
+	case 0x0002:
+		return "WDOG";
+	case 0x0006:
+		return "JTAG";
+	case 0x0007:
+		return "ARM11P power gating";
+	default:
+		return "unknown reset";
+	}
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 srev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
+			(srev & 0xF0) >> 4, (srev & 0x0F),
+			((srev & 0x8000) ? " unknown" : ""),
+			mx31_get_mcu_main_clk() / 1000000);
+	printf("Reset cause: %s\n", get_reset_cause());
+	return 0;
+}
+#endif

source/bootloader/u-boot-2020.01/arch/arm/cpu/arm1136/mx31/relocate.S

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  relocate - i.MX31-specific vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX31 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	bx	lr
+
+ENDPROC(relocate_vectors)

source/bootloader/u-boot-2020.01/arch/arm/cpu/arm1136/mx31/timer.c

@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+
+#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
+
+/* General purpose timers registers */
+#define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
+#define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
+#define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
+#define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
+#define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
+#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
+#define GPTCR_TEN		1		/* Timer enable		*/
+
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init(void)
+{
+	int i;
+
+	/* setup GP Timer 1 */
+	GPTCR = GPTCR_SWR;
+	for (i = 0; i < 100; i++)
+		GPTCR = 0; /* We have no udelay by now */
+	GPTPR = 0; /* 32Khz */
+	/* Freerun Mode, PERCLK1 input */
+	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+
+	return 0;
+}
+
+unsigned long timer_read_counter(void)
+{
+	return GPTCNT;
+}