GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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obj-y += generic.o timer.o reset.o relocate.o
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009 DENX Software Engineering
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* Author: John Rigby <jrigby@gmail.com>
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*
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* Based on mx27/generic.c:
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* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
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* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
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*/
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#include <common.h>
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#include <div64.h>
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#include <netdev.h>
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#include <vsprintf.h>
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#include <asm/io.h>
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#include <asm/arch-imx/cpu.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#ifdef CONFIG_FSL_ESDHC_IMX
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#include <fsl_esdhc_imx.h>
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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/*
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* get the system pll clock in Hz
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*
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* mfi + mfn / (mfd +1)
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* f = 2 * f_ref * --------------------
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* pd + 1
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*/
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static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
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{
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unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
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& CCM_PLL_MFI_MASK;
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int mfn = (pll >> CCM_PLL_MFN_SHIFT)
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& CCM_PLL_MFN_MASK;
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unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
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& CCM_PLL_MFD_MASK;
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unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
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& CCM_PLL_PD_MASK;
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mfi = mfi <= 5 ? 5 : mfi;
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mfn = mfn >= 512 ? mfn - 1024 : mfn;
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mfd += 1;
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pd += 1;
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return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
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mfd * pd);
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}
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static ulong imx_get_mpllclk(void)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong fref = MXC_HCLK;
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return imx_decode_pll(readl(&ccm->mpctl), fref);
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}
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static ulong imx_get_upllclk(void)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong fref = MXC_HCLK;
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return imx_decode_pll(readl(&ccm->upctl), fref);
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}
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static ulong imx_get_armclk(void)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong cctl = readl(&ccm->cctl);
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ulong fref = imx_get_mpllclk();
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ulong div;
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if (cctl & CCM_CCTL_ARM_SRC)
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fref = lldiv((u64) fref * 3, 4);
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div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
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& CCM_CCTL_ARM_DIV_MASK) + 1;
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return fref / div;
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}
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static ulong imx_get_ahbclk(void)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong cctl = readl(&ccm->cctl);
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ulong fref = imx_get_armclk();
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ulong div;
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div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
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& CCM_CCTL_AHB_DIV_MASK) + 1;
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return fref / div;
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}
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static ulong imx_get_ipgclk(void)
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{
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return imx_get_ahbclk() / 2;
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}
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static ulong imx_get_perclk(int clk)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
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imx_get_ahbclk();
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ulong div;
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div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
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div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
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return fref / div;
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}
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int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
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ulong div = (fref + freq - 1) / freq;
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if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
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return -EINVAL;
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clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
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CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
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div << CCM_PERCLK_SHIFT(clk));
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if (from_upll)
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setbits_le32(&ccm->mcr, 1 << clk);
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else
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clrbits_le32(&ccm->mcr, 1 << clk);
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return 0;
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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if (clk >= MXC_CLK_NUM)
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return -1;
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switch (clk) {
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case MXC_ARM_CLK:
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return imx_get_armclk();
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case MXC_AHB_CLK:
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return imx_get_ahbclk();
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case MXC_IPG_CLK:
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case MXC_CSPI_CLK:
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case MXC_FEC_CLK:
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return imx_get_ipgclk();
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default:
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return imx_get_perclk(clk);
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}
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}
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u32 get_cpu_rev(void)
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{
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u32 srev;
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u32 system_rev = 0x25000;
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/* read SREV register from IIM module */
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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srev = readl(&iim->iim_srev);
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switch (srev) {
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case 0x00:
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system_rev |= CHIP_REV_1_0;
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break;
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case 0x01:
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system_rev |= CHIP_REV_1_1;
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break;
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case 0x02:
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system_rev |= CHIP_REV_1_2;
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break;
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default:
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system_rev |= 0x8000;
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break;
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}
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return system_rev;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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static char *get_reset_cause(void)
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{
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/* read RCSR register from CCM module */
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 cause = readl(&ccm->rcsr) & 0x0f;
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if (cause == 0)
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return "POR";
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else if (cause == 1)
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return "RST";
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else if ((cause & 2) == 2)
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return "WDOG";
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else if ((cause & 4) == 4)
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return "SW RESET";
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else if ((cause & 8) == 8)
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return "JTAG";
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else
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return "unknown reset";
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}
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int print_cpuinfo(void)
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{
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char buf[32];
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u32 cpurev = get_cpu_rev();
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printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
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(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
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((cpurev & 0x8000) ? " unknown" : ""),
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strmhz(buf, imx_get_armclk()));
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printf("Reset cause: %s\n", get_reset_cause());
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return 0;
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}
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#endif
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#if defined(CONFIG_FEC_MXC)
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong val;
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val = readl(&ccm->cgr0);
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val |= (1 << 23);
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writel(val, &ccm->cgr0);
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return fecmxc_initialize(bis);
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}
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#endif
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int get_clocks(void)
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{
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#ifdef CONFIG_FSL_ESDHC_IMX
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#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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#else
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
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#endif
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#endif
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC_IMX
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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#endif
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#ifdef CONFIG_FEC_MXC
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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int i;
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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struct fuse_bank *bank = &iim->bank[0];
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struct fuse_bank0_regs *fuse =
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(struct fuse_bank0_regs *)bank->fuse_regs;
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for (i = 0; i < 6; i++)
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mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
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}
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#endif /* CONFIG_FEC_MXC */
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@@ -0,0 +1,22 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* relocate - i.MX25-specific vector relocation
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*
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* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*/
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#include <linux/linkage.h>
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/*
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* The i.MX25 SoC is very specific with respect to exceptions: it
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* does not provide RAM at the high vectors address (0xFFFF0000),
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* thus only the low address (0x00000000) is useable; but that is
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* in ROM, so let's avoid relocating the vectors.
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*/
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.section .text.relocate_vectors,"ax",%progbits
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ENTRY(relocate_vectors)
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bx lr
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ENDPROC(relocate_vectors)
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@@ -0,0 +1,39 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* (C) Copyright 2009
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* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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/*
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* Reset the cpu by setting up the watchdog timer and let it time out
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*/
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void reset_cpu(ulong ignored)
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{
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struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
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/* Disable watchdog and set Time-Out field to 0 */
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writew(0, ®s->wcr);
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/* Write Service Sequence */
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writew(WSR_UNLOCK1, ®s->wsr);
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writew(WSR_UNLOCK2, ®s->wsr);
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/* Enable watchdog */
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writew(WCR_WDE, ®s->wcr);
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while (1) ;
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}
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@@ -0,0 +1,48 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* (C) Copyright 2009
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* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
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*
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* (C) Copyright 2009 DENX Software Engineering
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* Author: John Rigby <jrigby@gmail.com>
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* Add support for MX25
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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/* nothing really to do with interrupts, just starts up a counter. */
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/* The 32KHz 32-bit timer overruns in 134217 seconds */
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int timer_init(void)
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{
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int i;
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struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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/* setup GP Timer 1 */
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writel(GPT_CTRL_SWR, &gpt->ctrl);
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writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
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for (i = 0; i < 100; i++)
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writel(0, &gpt->ctrl); /* We have no udelay by now */
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writel(0, &gpt->pre); /* prescaler = 1 */
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/* Freerun Mode, 32KHz input */
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writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
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&gpt->ctrl);
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writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
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return 0;
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}
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