GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,19 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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#
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# Based on some other Makefile
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += timer.o
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obj-$(CONFIG_MACH_SUN6I) += tzpc.o
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obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_ARMV7_PSCI) += psci.o
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endif
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ifdef CONFIG_SPL_BUILD
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obj-y += fel_utils.o
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endif
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@@ -0,0 +1,41 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Utility functions for FEL mode.
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*
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* Copyright (c) 2015 Google, Inc
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/system.h>
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#include <linux/linkage.h>
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ENTRY(save_boot_params)
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ldr r0, =fel_stash
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str sp, [r0, #0]
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str lr, [r0, #4]
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mrs lr, cpsr @ Read CPSR
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str lr, [r0, #8]
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mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
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str lr, [r0, #12]
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mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
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str lr, [r0, #16]
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mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
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str lr, [r0, #20]
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b save_boot_params_ret
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ENDPROC(save_boot_params)
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ENTRY(return_to_fel)
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mov sp, r0
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mov lr, r1
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ldr r0, =fel_stash
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ldr r1, [r0, #20]
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mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
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ldr r1, [r0, #16]
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mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
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ldr r1, [r0, #12]
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mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
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ldr r1, [r0, #8]
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msr cpsr, r1 @ Write CPSR
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bx lr
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ENDPROC(return_to_fel)
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@@ -0,0 +1,318 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016
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* Author: Chen-Yu Tsai <wens@csie.org>
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*
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* Based on assembly code by Marc Zyngier <marc.zyngier@arm.com>,
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* which was based on code by Carl van Schaik <carl@ok-labs.com>.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/cpucfg.h>
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#include <asm/arch/prcm.h>
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#include <asm/armv7.h>
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#include <asm/gic.h>
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include <asm/system.h>
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#include <linux/bitops.h>
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#define __irq __attribute__ ((interrupt ("IRQ")))
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#define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
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#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
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/*
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* R40 is different from other single cluster SoCs.
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*
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* The power clamps are located in the unused space after the per-core
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* reset controls for core 3. The secondary core entry address register
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* is in the SRAM controller address range.
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*/
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#define SUN8I_R40_PWROFF (0x110)
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#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
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#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
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static void __secure cp15_write_cntp_tval(u32 tval)
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{
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asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
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}
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static void __secure cp15_write_cntp_ctl(u32 val)
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{
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asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
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}
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static u32 __secure cp15_read_cntp_ctl(void)
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{
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u32 val;
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asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
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return val;
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}
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#define ONE_MS (COUNTER_FREQUENCY / 1000)
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static void __secure __mdelay(u32 ms)
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{
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u32 reg = ONE_MS * ms;
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cp15_write_cntp_tval(reg);
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isb();
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cp15_write_cntp_ctl(3);
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do {
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isb();
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reg = cp15_read_cntp_ctl();
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} while (!(reg & BIT(2)));
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cp15_write_cntp_ctl(0);
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isb();
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}
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static void __secure clamp_release(void __maybe_unused *clamp)
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{
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#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_H3) || \
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defined(CONFIG_MACH_SUN8I_R40)
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u32 tmp = 0x1ff;
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do {
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tmp >>= 1;
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writel(tmp, clamp);
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} while (tmp);
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__mdelay(10);
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#endif
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}
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static void __secure clamp_set(void __maybe_unused *clamp)
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{
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#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_H3) || \
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defined(CONFIG_MACH_SUN8I_R40)
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writel(0xff, clamp);
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#endif
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}
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static void __secure sunxi_power_switch(void *clamp, void *pwroff_ptr, bool on,
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int cpu)
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{
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u32 pwroff;
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memcpy(&pwroff, pwroff_ptr, sizeof(u32));
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if (on) {
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/* Release power clamp */
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clamp_release(clamp);
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/* Clear power gating */
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clrbits_le32(&pwroff, BIT(cpu));
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} else {
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/* Set power gating */
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setbits_le32(&pwroff, BIT(cpu));
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/* Activate power clamp */
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clamp_set(clamp);
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}
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memcpy(pwroff_ptr, &pwroff, sizeof(u32));
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}
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#ifdef CONFIG_MACH_SUN8I_R40
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/* secondary core entry address is programmed differently on R40 */
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static void __secure sunxi_set_entry_address(void *entry)
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{
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writel((u32)entry,
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SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
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}
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#else
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static void __secure sunxi_set_entry_address(void *entry)
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{
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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writel((u32)entry, &cpucfg->priv0);
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}
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#endif
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#ifdef CONFIG_MACH_SUN7I
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/* sun7i (A20) is different from other single cluster SoCs */
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static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
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{
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
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on, 0);
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}
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#elif defined CONFIG_MACH_SUN8I_R40
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static void __secure sunxi_cpu_set_power(int cpu, bool on)
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{
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
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(void *)cpucfg + SUN8I_R40_PWROFF,
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on, 0);
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}
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#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
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static void __secure sunxi_cpu_set_power(int cpu, bool on)
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{
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struct sunxi_prcm_reg *prcm =
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(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
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sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
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on, cpu);
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}
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#endif /* CONFIG_MACH_SUN7I */
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void __secure sunxi_cpu_power_off(u32 cpuid)
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{
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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u32 cpu = cpuid & 0x3;
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/* Wait for the core to enter WFI */
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while (1) {
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if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
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break;
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__mdelay(1);
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}
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/* Assert reset on target CPU */
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writel(0, &cpucfg->cpu[cpu].rst);
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/* Lock CPU (Disable external debug access) */
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clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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/* Power down CPU */
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sunxi_cpu_set_power(cpuid, false);
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/* Unlock CPU (Disable external debug access) */
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setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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}
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static u32 __secure cp15_read_scr(void)
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{
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u32 scr;
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asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr));
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return scr;
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}
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static void __secure cp15_write_scr(u32 scr)
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{
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asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
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isb();
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}
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/*
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* Although this is an FIQ handler, the FIQ is processed in monitor mode,
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* which means there's no FIQ banked registers. This is the same as IRQ
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* mode, so use the IRQ attribute to ask the compiler to handler entry
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* and return.
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*/
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void __secure __irq psci_fiq_enter(void)
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{
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u32 scr, reg, cpu;
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/* Switch to secure mode */
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scr = cp15_read_scr();
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cp15_write_scr(scr & ~BIT(0));
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/* Validate reason based on IAR and acknowledge */
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reg = readl(GICC_BASE + GICC_IAR);
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/* Skip spurious interrupts 1022 and 1023 */
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if (reg == 1023 || reg == 1022)
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goto out;
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/* End of interrupt */
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writel(reg, GICC_BASE + GICC_EOIR);
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dsb();
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/* Get CPU number */
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cpu = (reg >> 10) & 0x7;
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/* Power off the CPU */
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sunxi_cpu_power_off(cpu);
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out:
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/* Restore security level */
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cp15_write_scr(scr);
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}
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int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
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u32 context_id)
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{
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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u32 cpu = (mpidr & 0x3);
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/* store target PC and context id */
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psci_save(cpu, pc, context_id);
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/* Set secondary core power on PC */
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sunxi_set_entry_address(&psci_cpu_entry);
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/* Assert reset on target CPU */
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writel(0, &cpucfg->cpu[cpu].rst);
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/* Invalidate L1 cache */
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clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
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/* Lock CPU (Disable external debug access) */
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clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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/* Power up target CPU */
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sunxi_cpu_set_power(cpu, true);
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/* De-assert reset on target CPU */
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writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
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/* Unlock CPU (Disable external debug access) */
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setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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return ARM_PSCI_RET_SUCCESS;
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}
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s32 __secure psci_cpu_off(void)
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{
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psci_cpu_off_common();
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/* Ask CPU0 via SGI15 to pull the rug... */
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writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
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dsb();
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/* Wait to be turned off */
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while (1)
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wfi();
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}
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void __secure psci_arch_init(void)
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{
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u32 reg;
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/* SGI15 as Group-0 */
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clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15));
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/* Set SGI15 priority to 0 */
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writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15);
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/* Be cool with non-secure */
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writel(0xff, GICC_BASE + GICC_PMR);
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/* Switch FIQEn on */
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setbits_le32(GICC_BASE + GICC_CTLR, BIT(3));
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reg = cp15_read_scr();
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reg |= BIT(2); /* Enable FIQ in monitor mode */
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reg &= ~BIT(0); /* Secure mode */
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cp15_write_scr(reg);
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}
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@@ -0,0 +1 @@
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/* Intentionally empty. Only needed to get FEL SPL link line right */
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@@ -0,0 +1,113 @@
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// SPDX-License-Identifier: GPL-2.0+
|
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/*
|
||||
* (C) Copyright 2007-2011
|
||||
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
|
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* Tom Cubie <tangliang@allwinnertech.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <time.h>
|
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#include <asm/io.h>
|
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#include <asm/arch/timer.h>
|
||||
|
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DECLARE_GLOBAL_DATA_PTR;
|
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|
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#define TIMER_MODE (0x0 << 7) /* continuous mode */
|
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#define TIMER_DIV (0x0 << 4) /* pre scale 1 */
|
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#define TIMER_SRC (0x1 << 2) /* osc24m */
|
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#define TIMER_RELOAD (0x1 << 1) /* reload internal value */
|
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#define TIMER_EN (0x1 << 0) /* enable timer */
|
||||
|
||||
#define TIMER_CLOCK (24 * 1000 * 1000)
|
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#define COUNT_TO_USEC(x) ((x) / 24)
|
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#define USEC_TO_COUNT(x) ((x) * 24)
|
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#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
|
||||
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
|
||||
|
||||
#define TIMER_LOAD_VAL 0xffffffff
|
||||
|
||||
#define TIMER_NUM 0 /* we use timer 0 */
|
||||
|
||||
/* read the 32-bit timer */
|
||||
static ulong read_timer(void)
|
||||
{
|
||||
struct sunxi_timer_reg *timers =
|
||||
(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
|
||||
struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
|
||||
|
||||
/*
|
||||
* The hardware timer counts down, therefore we invert to
|
||||
* produce an incrementing timer.
|
||||
*/
|
||||
return ~readl(&timer->val);
|
||||
}
|
||||
|
||||
/* init timer register */
|
||||
int timer_init(void)
|
||||
{
|
||||
struct sunxi_timer_reg *timers =
|
||||
(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
|
||||
struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
|
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writel(TIMER_LOAD_VAL, &timer->inter);
|
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writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
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&timer->ctl);
|
||||
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||||
return 0;
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||||
}
|
||||
|
||||
/* timer without interrupts */
|
||||
static ulong get_timer_masked(void)
|
||||
{
|
||||
/* current tick value */
|
||||
ulong now = TICKS_TO_HZ(read_timer());
|
||||
|
||||
if (now >= gd->arch.lastinc) /* normal (non rollover) */
|
||||
gd->arch.tbl += (now - gd->arch.lastinc);
|
||||
else {
|
||||
/* rollover */
|
||||
gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
|
||||
- gd->arch.lastinc) + now;
|
||||
}
|
||||
gd->arch.lastinc = now;
|
||||
|
||||
return gd->arch.tbl;
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
/* delay x useconds */
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
long tmo = USEC_TO_COUNT(usec);
|
||||
ulong now, last = read_timer();
|
||||
|
||||
while (tmo > 0) {
|
||||
now = read_timer();
|
||||
if (now > last) /* normal (non rollover) */
|
||||
tmo -= now - last;
|
||||
else /* rollover */
|
||||
tmo -= TIMER_LOAD_VAL - last + now;
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
return CONFIG_SYS_HZ;
|
||||
}
|
||||
@@ -0,0 +1,26 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2015 Chen-Yu Tsai <wens@csie.org>
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/tzpc.h>
|
||||
|
||||
/* Configure Trust Zone Protection Controller */
|
||||
void tzpc_init(void)
|
||||
{
|
||||
struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;
|
||||
|
||||
#ifdef CONFIG_MACH_SUN6I
|
||||
/* Enable non-secure access to the RTC */
|
||||
writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_SUN8I_H3
|
||||
/* Enable non-secure access to all peripherals */
|
||||
writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set);
|
||||
writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set);
|
||||
writel(SUN8I_H3_TZPC_DECPORT2_ALL, &tzpc->decport2_set);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,57 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
|
||||
* Tom Cubie <tangliang@allwinnertech.com>
|
||||
*
|
||||
* Based on omap-common/u-boot-spl.lds:
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*/
|
||||
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
|
||||
LENGTH = IMAGE_MAX_SIZE }
|
||||
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
|
||||
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__start = .;
|
||||
*(.vectors)
|
||||
arch/arm/cpu/armv7/start.o (.text)
|
||||
*(.text*)
|
||||
} > .sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
} > .sram
|
||||
|
||||
. = ALIGN(4);
|
||||
__image_copy_end = .;
|
||||
_end = .;
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} > .sdram
|
||||
}
|
||||
Reference in New Issue
Block a user