GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Grinn
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*/
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#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
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#define __ARCH_ARM_MACH_CHILISOM_SOM_H__
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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void chilisom_enable_pin_mux(void);
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void chilisom_spl_board_init(void);
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#endif
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#endif
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@@ -0,0 +1,42 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* clk-synthesizer.h
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*
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* Clock synthesizer header
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*
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* Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#ifndef __CLK_SYNTHESIZER_H
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#define __CLK_SYNTHESIZER_H
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#include <common.h>
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#define CLK_SYNTHESIZER_ID_REG 0x0
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#define CLK_SYNTHESIZER_XCSEL 0x05
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#define CLK_SYNTHESIZER_MUX_REG 0x14
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#define CLK_SYNTHESIZER_PDIV2_REG 0x16
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#define CLK_SYNTHESIZER_PDIV3_REG 0x17
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#define CLK_SYNTHESIZER_BYTE_MODE 0x80
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/**
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* struct clk_synth: This structure holds data neeed for configuring
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* for clock synthesizer.
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* @id: The id of synthesizer
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* @capacitor: value of the capacitor attached
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* @mux: mux settings.
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* @pdiv2: Div to be applied to second output
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* @pdiv3: Div to be applied to third output
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*/
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struct clk_synth {
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u32 id;
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u32 capacitor;
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u32 mux;
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u32 pdiv2;
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u32 pdiv3;
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};
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int setup_clock_synthesizer(struct clk_synth *data);
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#endif
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@@ -0,0 +1,134 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* clock.h
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*
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* clock header
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*
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* Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef _CLOCKS_H_
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#define _CLOCKS_H_
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#include <asm/arch/clocks_am33xx.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
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#include <asm/arch/clock_ti81xx.h>
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#endif
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#define LDELAY 1000000
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/*CM_<clock_domain>__CLKCTRL */
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#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
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#define CD_CLKCTRL_CLKTRCTRL_MASK 3
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#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
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#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
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#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
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/* CM_<clock_domain>_<module>_CLKCTRL */
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#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
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#define MODULE_CLKCTRL_MODULEMODE_MASK 3
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#define MODULE_CLKCTRL_IDLEST_SHIFT 16
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#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
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#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
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#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
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#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
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#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
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#define MODULE_CLKCTRL_IDLEST_IDLE 2
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#define MODULE_CLKCTRL_IDLEST_DISABLED 3
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/* CM_CLKMODE_DPLL */
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#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12
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#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12)
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#define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13)
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#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
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#define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15)
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#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
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#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
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#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
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#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
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#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
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#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
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#define CM_CLKMODE_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
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#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
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#define DPLL_EN_STOP 1
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#define DPLL_EN_MN_BYPASS 4
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#define DPLL_EN_LOW_POWER_BYPASS 5
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#define DPLL_EN_LOCK 7
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/* CM_IDLEST_DPLL fields */
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#define ST_DPLL_CLK_MASK 1
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/* CM_CLKSEL_DPLL */
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#define CM_CLKSEL_DPLL_M_SHIFT 8
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#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
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#define CM_CLKSEL_DPLL_N_SHIFT 0
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#define CM_CLKSEL_DPLL_N_MASK 0x7F
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struct dpll_params {
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u32 m;
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u32 n;
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s8 m2;
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s8 m3;
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s8 m4;
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s8 m5;
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s8 m6;
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};
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struct dpll_regs {
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u32 cm_clkmode_dpll;
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u32 cm_idlest_dpll;
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u32 cm_autoidle_dpll;
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u32 cm_clksel_dpll;
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u32 cm_div_m2_dpll;
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u32 cm_div_m3_dpll;
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u32 cm_div_m4_dpll;
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u32 cm_div_m5_dpll;
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u32 cm_div_m6_dpll;
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};
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extern const struct dpll_regs dpll_mpu_regs;
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extern const struct dpll_regs dpll_core_regs;
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extern const struct dpll_regs dpll_per_regs;
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extern const struct dpll_regs dpll_ddr_regs;
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extern const struct dpll_regs dpll_disp_regs;
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extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
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extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
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extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
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extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];
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extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];
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extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
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extern struct cm_wkuppll *const cmwkup;
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const struct dpll_params *get_dpll_mpu_params(void);
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const struct dpll_params *get_dpll_core_params(void);
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const struct dpll_params *get_dpll_per_params(void);
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const struct dpll_params *get_dpll_ddr_params(void);
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void scale_vcores(void);
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void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
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void prcm_init(void);
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void enable_basic_clocks(void);
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void rtc_only_update_board_type(u32 btype);
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u32 rtc_only_get_board_type(void);
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void rtc_only_prcm_init(void);
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void rtc_only_enable_basic_clocks(void);
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void do_enable_clocks(u32 *const *, u32 *const *, u8);
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void do_disable_clocks(u32 *const *, u32 *const *, u8);
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void set_mpu_spreadspectrum(int permille);
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#endif
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@@ -0,0 +1,142 @@
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/*
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* ti81xx.h
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*
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Antoine Tenart, <atenart@adeneo-embedded.com>
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*
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* This file is released under the terms of GPL v2 and any later version.
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* See the file COPYING in the root directory of the source tree for details.
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*/
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#ifndef _CLOCK_TI81XX_H_
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#define _CLOCK_TI81XX_H_
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#define PRCM_MOD_EN 0x2
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#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
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#define CM_ALWON_BASE (PRCM_BASE + 0x1400)
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struct cm_def {
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unsigned int resv0[2];
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unsigned int l3fastclkstctrl;
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unsigned int resv1[1];
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unsigned int pciclkstctrl;
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unsigned int resv2[1];
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unsigned int ducaticlkstctrl;
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unsigned int resv3[1];
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unsigned int emif0clkctrl;
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unsigned int emif1clkctrl;
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unsigned int dmmclkctrl;
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unsigned int fwclkctrl;
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unsigned int resv4[10];
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unsigned int usbclkctrl;
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unsigned int resv5[1];
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unsigned int sataclkctrl;
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unsigned int resv6[4];
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unsigned int ducaticlkctrl;
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unsigned int pciclkctrl;
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};
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struct cm_alwon {
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unsigned int l3slowclkstctrl;
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unsigned int ethclkstctrl;
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unsigned int l3medclkstctrl;
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unsigned int mmu_clkstctrl;
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unsigned int mmucfg_clkstctrl;
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unsigned int ocmc0clkstctrl;
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#if defined(CONFIG_TI814X)
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unsigned int vcpclkstctrl;
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#elif defined(CONFIG_TI816X)
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unsigned int ocmc1clkstctrl;
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#endif
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unsigned int mpuclkstctrl;
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unsigned int sysclk4clkstctrl;
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unsigned int sysclk5clkstctrl;
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unsigned int sysclk6clkstctrl;
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unsigned int rtcclkstctrl;
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unsigned int l3fastclkstctrl;
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unsigned int resv0[67];
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unsigned int mcasp0clkctrl;
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unsigned int mcasp1clkctrl;
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unsigned int mcasp2clkctrl;
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unsigned int mcbspclkctrl;
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unsigned int uart0clkctrl;
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unsigned int uart1clkctrl;
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unsigned int uart2clkctrl;
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unsigned int gpio0clkctrl;
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unsigned int gpio1clkctrl;
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unsigned int i2c0clkctrl;
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unsigned int i2c1clkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int mcasp345clkctrl;
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unsigned int atlclkctrl;
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unsigned int mlbclkctrl;
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unsigned int pataclkctrl;
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unsigned int resv1[1];
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unsigned int uart3clkctrl;
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unsigned int uart4clkctrl;
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unsigned int uart5clkctrl;
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#elif defined(CONFIG_TI816X)
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unsigned int resv1[1];
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unsigned int timer1clkctrl;
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unsigned int timer2clkctrl;
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unsigned int timer3clkctrl;
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unsigned int timer4clkctrl;
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unsigned int timer5clkctrl;
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unsigned int timer6clkctrl;
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unsigned int timer7clkctrl;
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#endif
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unsigned int wdtimerclkctrl;
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unsigned int spiclkctrl;
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unsigned int mailboxclkctrl;
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unsigned int spinboxclkctrl;
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unsigned int mmudataclkctrl;
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unsigned int resv2[2];
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unsigned int mmucfgclkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int resv3[2];
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#elif defined(CONFIG_TI816X)
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unsigned int resv3[1];
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unsigned int sdioclkctrl;
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#endif
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unsigned int ocmc0clkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int vcpclkctrl;
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#elif defined(CONFIG_TI816X)
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unsigned int ocmc1clkctrl;
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#endif
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unsigned int resv4[2];
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unsigned int controlclkctrl;
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unsigned int resv5[2];
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unsigned int gpmcclkctrl;
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unsigned int ethernet0clkctrl;
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unsigned int ethernet1clkctrl;
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unsigned int mpuclkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int debugssclkctrl;
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#elif defined(CONFIG_TI816X)
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unsigned int resv6[1];
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#endif
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unsigned int l3clkctrl;
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unsigned int l4hsclkctrl;
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unsigned int l4lsclkctrl;
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unsigned int rtcclkctrl;
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unsigned int tpccclkctrl;
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unsigned int tptc0clkctrl;
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unsigned int tptc1clkctrl;
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unsigned int tptc2clkctrl;
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unsigned int tptc3clkctrl;
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#if defined(CONFIG_TI814X)
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unsigned int resv6[4];
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unsigned int dcan01clkctrl;
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unsigned int mmchs0clkctrl;
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unsigned int mmchs1clkctrl;
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unsigned int mmchs2clkctrl;
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unsigned int custefuseclkctrl;
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#elif defined(CONFIG_TI816X)
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unsigned int sr0clkctrl;
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unsigned int sr1clkctrl;
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#endif
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};
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#endif /* _CLOCK_TI81XX_H_ */
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@@ -0,0 +1,35 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* clocks_am33xx.h
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*
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* AM33xx clock define
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef _CLOCKS_AM33XX_H_
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#define _CLOCKS_AM33XX_H_
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/* MAIN PLL Fdll supported frequencies */
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#define MPUPLL_M_1000 1000
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#define MPUPLL_M_800 800
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#define MPUPLL_M_720 720
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#define MPUPLL_M_600 600
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#define MPUPLL_M_500 500
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#define MPUPLL_M_300 300
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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#define CM_DLL_CTRL_NO_OVERRIDE 0x0
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#define CM_DLL_READYST 0x4
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#define NUM_OPPS 6
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extern void enable_dmm_clocks(void);
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extern void enable_emif_clocks(void);
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extern const struct dpll_params dpll_core_opp100;
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extern struct dpll_params dpll_mpu_opp100;
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#endif /* endif _CLOCKS_AM33XX_H_ */
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@@ -0,0 +1,611 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* cpu.h
|
||||
*
|
||||
* AM33xx specific header file
|
||||
*
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||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*/
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#ifndef _AM33XX_CPU_H
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#define _AM33XX_CPU_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
|
||||
|
||||
#include <asm/arch/hardware.h>
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||||
|
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#define CL_BIT(x) (0 << x)
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||||
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/* Timer register bits */
|
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#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
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#define TCLR_AR BIT(1) /* Auto reload */
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#define TCLR_PRE BIT(5) /* Pre-scaler enable */
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#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
|
||||
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
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||||
#define TCLR_CE BIT(6) /* compare mode enable */
|
||||
#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
|
||||
#define TCLR_TCM BIT(8) /* edge detection of input pin*/
|
||||
#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
|
||||
#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
|
||||
#define TCLR_CAPTMODE BIT(13) /* capture mode */
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||||
#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
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#define TCFG_RESET BIT(0) /* software reset */
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||||
#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
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||||
#define TCFG_IDLEMOD_SHIFT (2) /* power management */
|
||||
|
||||
/* cpu-id for AM43XX AM33XX and TI81XX family */
|
||||
#define AM437X 0xB98C
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#define AM335X 0xB944
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#define TI81XX 0xB81E
|
||||
#define DEVICE_ID (CTRL_BASE + 0x0600)
|
||||
#define DEVICE_ID_MASK 0x1FFF
|
||||
#define PACKAGE_TYPE_SHIFT 16
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||||
#define PACKAGE_TYPE_MASK (3 << 16)
|
||||
|
||||
/* Package Type */
|
||||
#define PACKAGE_TYPE_UNDEFINED 0x0
|
||||
#define PACKAGE_TYPE_ZCZ 0x1
|
||||
#define PACKAGE_TYPE_ZCE 0x2
|
||||
#define PACKAGE_TYPE_RESERVED 0x3
|
||||
|
||||
/* MPU max frequencies */
|
||||
#define AM335X_ZCZ_300 0x1FEF
|
||||
#define AM335X_ZCZ_600 0x1FAF
|
||||
#define AM335X_ZCZ_720 0x1F2F
|
||||
#define AM335X_ZCZ_800 0x1E2F
|
||||
#define AM335X_ZCZ_1000 0x1C2F
|
||||
#define AM335X_ZCE_300 0x1FDF
|
||||
#define AM335X_ZCE_600 0x1F9F
|
||||
|
||||
/* This gives the status of the boot mode pins on the evm */
|
||||
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
|
||||
| BIT(3) | BIT(4))
|
||||
|
||||
#define PRM_RSTCTRL_RESET 0x01
|
||||
#define PRM_RSTST_WARM_RESET_MASK 0x232
|
||||
|
||||
/* EMIF Control register bits */
|
||||
#define EMIF_CTRL_DEVOFF BIT(0)
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/ti-common/omap_wdt.h>
|
||||
|
||||
#ifndef CONFIG_AM43XX
|
||||
/* Encapsulating core pll registers */
|
||||
struct cm_wkuppll {
|
||||
unsigned int wkclkstctrl; /* offset 0x00 */
|
||||
unsigned int wkctrlclkctrl; /* offset 0x04 */
|
||||
unsigned int wkgpio0clkctrl; /* offset 0x08 */
|
||||
unsigned int wkl4wkclkctrl; /* offset 0x0c */
|
||||
unsigned int timer0clkctrl; /* offset 0x10 */
|
||||
unsigned int resv2[3];
|
||||
unsigned int idlestdpllmpu; /* offset 0x20 */
|
||||
unsigned int sscdeltamstepdllmpu; /* off 0x24 */
|
||||
unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
|
||||
unsigned int clkseldpllmpu; /* offset 0x2c */
|
||||
unsigned int resv4[1];
|
||||
unsigned int idlestdpllddr; /* offset 0x34 */
|
||||
unsigned int resv5[2];
|
||||
unsigned int clkseldpllddr; /* offset 0x40 */
|
||||
unsigned int resv6[4];
|
||||
unsigned int clkseldplldisp; /* offset 0x54 */
|
||||
unsigned int resv7[1];
|
||||
unsigned int idlestdpllcore; /* offset 0x5c */
|
||||
unsigned int resv8[2];
|
||||
unsigned int clkseldpllcore; /* offset 0x68 */
|
||||
unsigned int resv9[1];
|
||||
unsigned int idlestdpllper; /* offset 0x70 */
|
||||
unsigned int resv10[2];
|
||||
unsigned int clkdcoldodpllper; /* offset 0x7c */
|
||||
unsigned int divm4dpllcore; /* offset 0x80 */
|
||||
unsigned int divm5dpllcore; /* offset 0x84 */
|
||||
unsigned int clkmoddpllmpu; /* offset 0x88 */
|
||||
unsigned int clkmoddpllper; /* offset 0x8c */
|
||||
unsigned int clkmoddpllcore; /* offset 0x90 */
|
||||
unsigned int clkmoddpllddr; /* offset 0x94 */
|
||||
unsigned int clkmoddplldisp; /* offset 0x98 */
|
||||
unsigned int clkseldpllper; /* offset 0x9c */
|
||||
unsigned int divm2dpllddr; /* offset 0xA0 */
|
||||
unsigned int divm2dplldisp; /* offset 0xA4 */
|
||||
unsigned int divm2dpllmpu; /* offset 0xA8 */
|
||||
unsigned int divm2dpllper; /* offset 0xAC */
|
||||
unsigned int resv11[1];
|
||||
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
|
||||
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
|
||||
unsigned int wkup_adctscctrl; /* offset 0xBC */
|
||||
unsigned int resv12;
|
||||
unsigned int timer1clkctrl; /* offset 0xC4 */
|
||||
unsigned int resv13[4];
|
||||
unsigned int divm6dpllcore; /* offset 0xD8 */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulating peripheral functional clocks
|
||||
* pll registers
|
||||
*/
|
||||
struct cm_perpll {
|
||||
unsigned int l4lsclkstctrl; /* offset 0x00 */
|
||||
unsigned int l3sclkstctrl; /* offset 0x04 */
|
||||
unsigned int l4fwclkstctrl; /* offset 0x08 */
|
||||
unsigned int l3clkstctrl; /* offset 0x0c */
|
||||
unsigned int resv1;
|
||||
unsigned int cpgmac0clkctrl; /* offset 0x14 */
|
||||
unsigned int lcdclkctrl; /* offset 0x18 */
|
||||
unsigned int usb0clkctrl; /* offset 0x1C */
|
||||
unsigned int resv2;
|
||||
unsigned int tptc0clkctrl; /* offset 0x24 */
|
||||
unsigned int emifclkctrl; /* offset 0x28 */
|
||||
unsigned int ocmcramclkctrl; /* offset 0x2c */
|
||||
unsigned int gpmcclkctrl; /* offset 0x30 */
|
||||
unsigned int mcasp0clkctrl; /* offset 0x34 */
|
||||
unsigned int uart5clkctrl; /* offset 0x38 */
|
||||
unsigned int mmc0clkctrl; /* offset 0x3C */
|
||||
unsigned int elmclkctrl; /* offset 0x40 */
|
||||
unsigned int i2c2clkctrl; /* offset 0x44 */
|
||||
unsigned int i2c1clkctrl; /* offset 0x48 */
|
||||
unsigned int spi0clkctrl; /* offset 0x4C */
|
||||
unsigned int spi1clkctrl; /* offset 0x50 */
|
||||
unsigned int resv3[3];
|
||||
unsigned int l4lsclkctrl; /* offset 0x60 */
|
||||
unsigned int l4fwclkctrl; /* offset 0x64 */
|
||||
unsigned int mcasp1clkctrl; /* offset 0x68 */
|
||||
unsigned int uart1clkctrl; /* offset 0x6C */
|
||||
unsigned int uart2clkctrl; /* offset 0x70 */
|
||||
unsigned int uart3clkctrl; /* offset 0x74 */
|
||||
unsigned int uart4clkctrl; /* offset 0x78 */
|
||||
unsigned int timer7clkctrl; /* offset 0x7C */
|
||||
unsigned int timer2clkctrl; /* offset 0x80 */
|
||||
unsigned int timer3clkctrl; /* offset 0x84 */
|
||||
unsigned int timer4clkctrl; /* offset 0x88 */
|
||||
unsigned int resv4[8];
|
||||
unsigned int gpio1clkctrl; /* offset 0xAC */
|
||||
unsigned int gpio2clkctrl; /* offset 0xB0 */
|
||||
unsigned int gpio3clkctrl; /* offset 0xB4 */
|
||||
unsigned int resv5;
|
||||
unsigned int tpccclkctrl; /* offset 0xBC */
|
||||
unsigned int dcan0clkctrl; /* offset 0xC0 */
|
||||
unsigned int dcan1clkctrl; /* offset 0xC4 */
|
||||
unsigned int resv6;
|
||||
unsigned int epwmss1clkctrl; /* offset 0xCC */
|
||||
unsigned int emiffwclkctrl; /* offset 0xD0 */
|
||||
unsigned int epwmss0clkctrl; /* offset 0xD4 */
|
||||
unsigned int epwmss2clkctrl; /* offset 0xD8 */
|
||||
unsigned int l3instrclkctrl; /* offset 0xDC */
|
||||
unsigned int l3clkctrl; /* Offset 0xE0 */
|
||||
unsigned int resv8[2];
|
||||
unsigned int timer5clkctrl; /* offset 0xEC */
|
||||
unsigned int timer6clkctrl; /* offset 0xF0 */
|
||||
unsigned int mmc1clkctrl; /* offset 0xF4 */
|
||||
unsigned int mmc2clkctrl; /* offset 0xF8 */
|
||||
unsigned int resv9[8];
|
||||
unsigned int l4hsclkstctrl; /* offset 0x11C */
|
||||
unsigned int l4hsclkctrl; /* offset 0x120 */
|
||||
unsigned int resv10[8];
|
||||
unsigned int cpswclkstctrl; /* offset 0x144 */
|
||||
unsigned int lcdcclkstctrl; /* offset 0x148 */
|
||||
};
|
||||
|
||||
/* Encapsulating Display pll registers */
|
||||
struct cm_dpll {
|
||||
unsigned int resv1;
|
||||
unsigned int clktimer7clk; /* offset 0x04 */
|
||||
unsigned int clktimer2clk; /* offset 0x08 */
|
||||
unsigned int clktimer3clk; /* offset 0x0C */
|
||||
unsigned int clktimer4clk; /* offset 0x10 */
|
||||
unsigned int resv2;
|
||||
unsigned int clktimer5clk; /* offset 0x18 */
|
||||
unsigned int clktimer6clk; /* offset 0x1C */
|
||||
unsigned int resv3[2];
|
||||
unsigned int clktimer1clk; /* offset 0x28 */
|
||||
unsigned int resv4[2];
|
||||
unsigned int clklcdcpixelclk; /* offset 0x34 */
|
||||
};
|
||||
|
||||
struct prm_device_inst {
|
||||
unsigned int prm_rstctrl;
|
||||
unsigned int prm_rsttime;
|
||||
unsigned int prm_rstst;
|
||||
};
|
||||
#else
|
||||
/* Encapsulating core pll registers */
|
||||
struct cm_wkuppll {
|
||||
unsigned int resv0[136];
|
||||
unsigned int wkl4wkclkctrl; /* offset 0x220 */
|
||||
unsigned int resv1[7];
|
||||
unsigned int usbphy0clkctrl; /* offset 0x240 */
|
||||
unsigned int resv112;
|
||||
unsigned int usbphy1clkctrl; /* offset 0x248 */
|
||||
unsigned int resv113[45];
|
||||
unsigned int wkclkstctrl; /* offset 0x300 */
|
||||
unsigned int resv2[15];
|
||||
unsigned int wkup_i2c0ctrl; /* offset 0x340 */
|
||||
unsigned int resv3;
|
||||
unsigned int wkup_uart0ctrl; /* offset 0x348 */
|
||||
unsigned int resv4[5];
|
||||
unsigned int wkctrlclkctrl; /* offset 0x360 */
|
||||
unsigned int resv5;
|
||||
unsigned int wkgpio0clkctrl; /* offset 0x368 */
|
||||
|
||||
unsigned int resv6[109];
|
||||
unsigned int clkmoddpllcore; /* offset 0x520 */
|
||||
unsigned int idlestdpllcore; /* offset 0x524 */
|
||||
unsigned int resv61;
|
||||
unsigned int clkseldpllcore; /* offset 0x52C */
|
||||
unsigned int resv7[2];
|
||||
unsigned int divm4dpllcore; /* offset 0x538 */
|
||||
unsigned int divm5dpllcore; /* offset 0x53C */
|
||||
unsigned int divm6dpllcore; /* offset 0x540 */
|
||||
|
||||
unsigned int resv8[7];
|
||||
unsigned int clkmoddpllmpu; /* offset 0x560 */
|
||||
unsigned int idlestdpllmpu; /* offset 0x564 */
|
||||
unsigned int resv9;
|
||||
unsigned int clkseldpllmpu; /* offset 0x56c */
|
||||
unsigned int divm2dpllmpu; /* offset 0x570 */
|
||||
|
||||
unsigned int resv10[11];
|
||||
unsigned int clkmoddpllddr; /* offset 0x5A0 */
|
||||
unsigned int idlestdpllddr; /* offset 0x5A4 */
|
||||
unsigned int resv11;
|
||||
unsigned int clkseldpllddr; /* offset 0x5AC */
|
||||
unsigned int divm2dpllddr; /* offset 0x5B0 */
|
||||
|
||||
unsigned int resv12[11];
|
||||
unsigned int clkmoddpllper; /* offset 0x5E0 */
|
||||
unsigned int idlestdpllper; /* offset 0x5E4 */
|
||||
unsigned int resv13;
|
||||
unsigned int clkseldpllper; /* offset 0x5EC */
|
||||
unsigned int divm2dpllper; /* offset 0x5F0 */
|
||||
unsigned int resv14[8];
|
||||
unsigned int clkdcoldodpllper; /* offset 0x614 */
|
||||
|
||||
unsigned int resv15[2];
|
||||
unsigned int clkmoddplldisp; /* offset 0x620 */
|
||||
unsigned int resv16[2];
|
||||
unsigned int clkseldplldisp; /* offset 0x62C */
|
||||
unsigned int divm2dplldisp; /* offset 0x630 */
|
||||
};
|
||||
|
||||
/*
|
||||
* Encapsulating peripheral functional clocks
|
||||
* pll registers
|
||||
*/
|
||||
struct cm_perpll {
|
||||
unsigned int l3clkstctrl; /* offset 0x00 */
|
||||
unsigned int resv0[7];
|
||||
unsigned int l3clkctrl; /* Offset 0x20 */
|
||||
unsigned int resv112[7];
|
||||
unsigned int l3instrclkctrl; /* offset 0x40 */
|
||||
unsigned int resv2[3];
|
||||
unsigned int ocmcramclkctrl; /* offset 0x50 */
|
||||
unsigned int resv3[9];
|
||||
unsigned int tpccclkctrl; /* offset 0x78 */
|
||||
unsigned int resv4;
|
||||
unsigned int tptc0clkctrl; /* offset 0x80 */
|
||||
|
||||
unsigned int resv5[7];
|
||||
unsigned int l4hsclkctrl; /* offset 0x0A0 */
|
||||
unsigned int resv6;
|
||||
unsigned int l4fwclkctrl; /* offset 0x0A8 */
|
||||
unsigned int resv7[85];
|
||||
unsigned int l3sclkstctrl; /* offset 0x200 */
|
||||
unsigned int resv8[7];
|
||||
unsigned int gpmcclkctrl; /* offset 0x220 */
|
||||
unsigned int resv9[5];
|
||||
unsigned int mcasp0clkctrl; /* offset 0x238 */
|
||||
unsigned int resv10;
|
||||
unsigned int mcasp1clkctrl; /* offset 0x240 */
|
||||
unsigned int resv11;
|
||||
unsigned int mmc2clkctrl; /* offset 0x248 */
|
||||
unsigned int resv12[3];
|
||||
unsigned int qspiclkctrl; /* offset 0x258 */
|
||||
unsigned int resv121;
|
||||
unsigned int usb0clkctrl; /* offset 0x260 */
|
||||
unsigned int resv122;
|
||||
unsigned int usb1clkctrl; /* offset 0x268 */
|
||||
unsigned int resv13[101];
|
||||
unsigned int l4lsclkstctrl; /* offset 0x400 */
|
||||
unsigned int resv14[7];
|
||||
unsigned int l4lsclkctrl; /* offset 0x420 */
|
||||
unsigned int resv15;
|
||||
unsigned int dcan0clkctrl; /* offset 0x428 */
|
||||
unsigned int resv16;
|
||||
unsigned int dcan1clkctrl; /* offset 0x430 */
|
||||
unsigned int resv17[13];
|
||||
unsigned int elmclkctrl; /* offset 0x468 */
|
||||
|
||||
unsigned int resv18[3];
|
||||
unsigned int gpio1clkctrl; /* offset 0x478 */
|
||||
unsigned int resv19;
|
||||
unsigned int gpio2clkctrl; /* offset 0x480 */
|
||||
unsigned int resv20;
|
||||
unsigned int gpio3clkctrl; /* offset 0x488 */
|
||||
unsigned int resv41;
|
||||
unsigned int gpio4clkctrl; /* offset 0x490 */
|
||||
unsigned int resv42;
|
||||
unsigned int gpio5clkctrl; /* offset 0x498 */
|
||||
unsigned int resv21[3];
|
||||
|
||||
unsigned int i2c1clkctrl; /* offset 0x4A8 */
|
||||
unsigned int resv22;
|
||||
unsigned int i2c2clkctrl; /* offset 0x4B0 */
|
||||
unsigned int resv23[3];
|
||||
unsigned int mmc0clkctrl; /* offset 0x4C0 */
|
||||
unsigned int resv24;
|
||||
unsigned int mmc1clkctrl; /* offset 0x4C8 */
|
||||
|
||||
unsigned int resv25[13];
|
||||
unsigned int spi0clkctrl; /* offset 0x500 */
|
||||
unsigned int resv26;
|
||||
unsigned int spi1clkctrl; /* offset 0x508 */
|
||||
unsigned int resv27[9];
|
||||
unsigned int timer2clkctrl; /* offset 0x530 */
|
||||
unsigned int resv28;
|
||||
unsigned int timer3clkctrl; /* offset 0x538 */
|
||||
unsigned int resv29;
|
||||
unsigned int timer4clkctrl; /* offset 0x540 */
|
||||
unsigned int resv30[5];
|
||||
unsigned int timer7clkctrl; /* offset 0x558 */
|
||||
|
||||
unsigned int resv31[9];
|
||||
unsigned int uart1clkctrl; /* offset 0x580 */
|
||||
unsigned int resv32;
|
||||
unsigned int uart2clkctrl; /* offset 0x588 */
|
||||
unsigned int resv33;
|
||||
unsigned int uart3clkctrl; /* offset 0x590 */
|
||||
unsigned int resv34;
|
||||
unsigned int uart4clkctrl; /* offset 0x598 */
|
||||
unsigned int resv35;
|
||||
unsigned int uart5clkctrl; /* offset 0x5A0 */
|
||||
unsigned int resv36[5];
|
||||
unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */
|
||||
unsigned int resv361;
|
||||
unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */
|
||||
unsigned int resv3611[79];
|
||||
|
||||
unsigned int emifclkstctrl; /* offset 0x700 */
|
||||
unsigned int resv362[7];
|
||||
unsigned int emifclkctrl; /* offset 0x720 */
|
||||
unsigned int resv37[3];
|
||||
unsigned int emiffwclkctrl; /* offset 0x730 */
|
||||
unsigned int resv371;
|
||||
unsigned int otfaemifclkctrl; /* offset 0x738 */
|
||||
unsigned int resv38[57];
|
||||
unsigned int lcdclkctrl; /* offset 0x820 */
|
||||
unsigned int resv39[183];
|
||||
unsigned int cpswclkstctrl; /* offset 0xB00 */
|
||||
unsigned int resv40[7];
|
||||
unsigned int cpgmac0clkctrl; /* offset 0xB20 */
|
||||
};
|
||||
|
||||
struct cm_device_inst {
|
||||
unsigned int cm_clkout1_ctrl;
|
||||
unsigned int cm_dll_ctrl;
|
||||
};
|
||||
|
||||
struct prm_device_inst {
|
||||
unsigned int rstctrl;
|
||||
unsigned int rstst;
|
||||
unsigned int rsttime;
|
||||
unsigned int sram_count;
|
||||
unsigned int ldo_sram_core_set; /* offset 0x10 */
|
||||
unsigned int ldo_sram_core_ctr;
|
||||
unsigned int ldo_sram_mpu_setu;
|
||||
unsigned int ldo_sram_mpu_ctrl;
|
||||
unsigned int io_count; /* offset 0x20 */
|
||||
unsigned int io_pmctrl;
|
||||
unsigned int vc_val_bypass;
|
||||
unsigned int resv1;
|
||||
unsigned int emif_ctrl; /* offset 0x30 */
|
||||
};
|
||||
|
||||
struct cm_dpll {
|
||||
unsigned int resv1;
|
||||
unsigned int clktimer2clk; /* offset 0x04 */
|
||||
unsigned int resv2[11];
|
||||
unsigned int clkselmacclk; /* offset 0x34 */
|
||||
};
|
||||
#endif /* CONFIG_AM43XX */
|
||||
|
||||
/* Control Module RTC registers */
|
||||
struct cm_rtc {
|
||||
unsigned int rtcclkctrl; /* offset 0x0 */
|
||||
unsigned int clkstctrl; /* offset 0x4 */
|
||||
};
|
||||
|
||||
/* Timer 32 bit registers */
|
||||
struct gptimer {
|
||||
unsigned int tidr; /* offset 0x00 */
|
||||
unsigned char res1[12];
|
||||
unsigned int tiocp_cfg; /* offset 0x10 */
|
||||
unsigned char res2[12];
|
||||
unsigned int tier; /* offset 0x20 */
|
||||
unsigned int tistatr; /* offset 0x24 */
|
||||
unsigned int tistat; /* offset 0x28 */
|
||||
unsigned int tisr; /* offset 0x2c */
|
||||
unsigned int tcicr; /* offset 0x30 */
|
||||
unsigned int twer; /* offset 0x34 */
|
||||
unsigned int tclr; /* offset 0x38 */
|
||||
unsigned int tcrr; /* offset 0x3c */
|
||||
unsigned int tldr; /* offset 0x40 */
|
||||
unsigned int ttgr; /* offset 0x44 */
|
||||
unsigned int twpc; /* offset 0x48 */
|
||||
unsigned int tmar; /* offset 0x4c */
|
||||
unsigned int tcar1; /* offset 0x50 */
|
||||
unsigned int tscir; /* offset 0x54 */
|
||||
unsigned int tcar2; /* offset 0x58 */
|
||||
};
|
||||
|
||||
/* UART Registers */
|
||||
struct uart_sys {
|
||||
unsigned int resv1[21];
|
||||
unsigned int uartsyscfg; /* offset 0x54 */
|
||||
unsigned int uartsyssts; /* offset 0x58 */
|
||||
};
|
||||
|
||||
/* VTP Registers */
|
||||
struct vtp_reg {
|
||||
unsigned int vtp0ctrlreg;
|
||||
};
|
||||
|
||||
/* Control Status Register */
|
||||
struct ctrl_stat {
|
||||
unsigned int resv1[16];
|
||||
unsigned int statusreg; /* ofset 0x40 */
|
||||
unsigned int resv2[51];
|
||||
unsigned int secure_emif_sdram_config; /* offset 0x0110 */
|
||||
unsigned int resv3[319];
|
||||
unsigned int dev_attr;
|
||||
};
|
||||
|
||||
/* AM33XX GPIO registers */
|
||||
#define OMAP_GPIO_REVISION 0x0000
|
||||
#define OMAP_GPIO_SYSCONFIG 0x0010
|
||||
#define OMAP_GPIO_SYSSTATUS 0x0114
|
||||
#define OMAP_GPIO_IRQSTATUS1 0x002c
|
||||
#define OMAP_GPIO_IRQSTATUS2 0x0030
|
||||
#define OMAP_GPIO_IRQSTATUS_SET_0 0x0034
|
||||
#define OMAP_GPIO_IRQSTATUS_SET_1 0x0038
|
||||
#define OMAP_GPIO_CTRL 0x0130
|
||||
#define OMAP_GPIO_OE 0x0134
|
||||
#define OMAP_GPIO_DATAIN 0x0138
|
||||
#define OMAP_GPIO_DATAOUT 0x013c
|
||||
#define OMAP_GPIO_LEVELDETECT0 0x0140
|
||||
#define OMAP_GPIO_LEVELDETECT1 0x0144
|
||||
#define OMAP_GPIO_RISINGDETECT 0x0148
|
||||
#define OMAP_GPIO_FALLINGDETECT 0x014c
|
||||
#define OMAP_GPIO_DEBOUNCE_EN 0x0150
|
||||
#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
|
||||
#define OMAP_GPIO_CLEARDATAOUT 0x0190
|
||||
#define OMAP_GPIO_SETDATAOUT 0x0194
|
||||
|
||||
/* Control Device Register */
|
||||
|
||||
/* Control Device Register */
|
||||
#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
|
||||
#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
|
||||
#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
|
||||
|
||||
struct ctrl_dev {
|
||||
unsigned int deviceid; /* offset 0x00 */
|
||||
unsigned int resv1[7];
|
||||
unsigned int usb_ctrl0; /* offset 0x20 */
|
||||
unsigned int resv2;
|
||||
unsigned int usb_ctrl1; /* offset 0x28 */
|
||||
unsigned int resv3;
|
||||
unsigned int macid0l; /* offset 0x30 */
|
||||
unsigned int macid0h; /* offset 0x34 */
|
||||
unsigned int macid1l; /* offset 0x38 */
|
||||
unsigned int macid1h; /* offset 0x3c */
|
||||
unsigned int resv4[4];
|
||||
unsigned int miisel; /* offset 0x50 */
|
||||
unsigned int resv5[7];
|
||||
unsigned int mreqprio_0; /* offset 0x70 */
|
||||
unsigned int mreqprio_1; /* offset 0x74 */
|
||||
unsigned int resv6[97];
|
||||
unsigned int efuse_sma; /* offset 0x1FC */
|
||||
};
|
||||
|
||||
/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
|
||||
#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
|
||||
#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
|
||||
#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
|
||||
|
||||
struct l3f_cfg_bwlimiter {
|
||||
u32 padding0[2];
|
||||
u32 modena_init0_bw_fractional;
|
||||
u32 modena_init0_bw_integer;
|
||||
u32 modena_init0_watermark_0;
|
||||
};
|
||||
|
||||
/* gmii_sel register defines */
|
||||
#define GMII1_SEL_MII 0x0
|
||||
#define GMII1_SEL_RMII 0x1
|
||||
#define GMII1_SEL_RGMII 0x2
|
||||
#define GMII2_SEL_MII 0x0
|
||||
#define GMII2_SEL_RMII 0x4
|
||||
#define GMII2_SEL_RGMII 0x8
|
||||
#define RGMII1_IDMODE BIT(4)
|
||||
#define RGMII2_IDMODE BIT(5)
|
||||
#define RMII1_IO_CLK_EN BIT(6)
|
||||
#define RMII2_IO_CLK_EN BIT(7)
|
||||
|
||||
#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
|
||||
#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
|
||||
#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
|
||||
#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
|
||||
#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
|
||||
|
||||
/* PWMSS */
|
||||
struct pwmss_regs {
|
||||
unsigned int idver;
|
||||
unsigned int sysconfig;
|
||||
unsigned int clkconfig;
|
||||
unsigned int clkstatus;
|
||||
};
|
||||
#define ECAP_CLK_EN BIT(0)
|
||||
#define ECAP_CLK_STOP_REQ BIT(1)
|
||||
#define EPWM_CLK_EN BIT(8)
|
||||
#define EPWM_CLK_STOP_REQ BIT(9)
|
||||
|
||||
struct pwmss_ecap_regs {
|
||||
unsigned int tsctr;
|
||||
unsigned int ctrphs;
|
||||
unsigned int cap1;
|
||||
unsigned int cap2;
|
||||
unsigned int cap3;
|
||||
unsigned int cap4;
|
||||
unsigned int resv1[4];
|
||||
unsigned short ecctl1;
|
||||
unsigned short ecctl2;
|
||||
};
|
||||
|
||||
struct pwmss_epwm_regs {
|
||||
unsigned short tbctl;
|
||||
unsigned short tbsts;
|
||||
unsigned short tbphshr;
|
||||
unsigned short tbphs;
|
||||
unsigned short tbcnt;
|
||||
unsigned short tbprd;
|
||||
unsigned short res1;
|
||||
unsigned short cmpctl;
|
||||
unsigned short cmpahr;
|
||||
unsigned short cmpa;
|
||||
unsigned short cmpb;
|
||||
unsigned short aqctla;
|
||||
unsigned short aqctlb;
|
||||
unsigned short aqsfrc;
|
||||
unsigned short aqcsfrc;
|
||||
unsigned short dbctl;
|
||||
unsigned short dbred;
|
||||
unsigned short dbfed;
|
||||
unsigned short tzsel;
|
||||
unsigned short tzctl;
|
||||
unsigned short tzflg;
|
||||
unsigned short tzclr;
|
||||
unsigned short tzfrc;
|
||||
unsigned short etsel;
|
||||
unsigned short etps;
|
||||
unsigned short etflg;
|
||||
unsigned short etclr;
|
||||
unsigned short etfrc;
|
||||
unsigned short pcctl;
|
||||
unsigned int res2[66];
|
||||
unsigned short hrcnfg;
|
||||
};
|
||||
|
||||
/* Capture Control register 2 */
|
||||
#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
|
||||
#define ECTRL2_MDSL_ECAP BIT(9)
|
||||
#define ECTRL2_CTRSTP_FREERUN BIT(4)
|
||||
#define ECTRL2_PLSL_LOW BIT(10)
|
||||
#define ECTRL2_SYNC_EN BIT(5)
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#endif /* _AM33XX_CPU_H */
|
||||
@@ -0,0 +1,383 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* ddr_defs.h
|
||||
*
|
||||
* ddr specific header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef _DDR_DEFS_H
|
||||
#define _DDR_DEFS_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/emif.h>
|
||||
|
||||
/* AM335X EMIF Register values */
|
||||
#define VTP_CTRL_READY (0x1 << 5)
|
||||
#define VTP_CTRL_ENABLE (0x1 << 6)
|
||||
#define VTP_CTRL_START_EN (0x1)
|
||||
#ifdef CONFIG_AM43XX
|
||||
#define DDR_CKE_CTRL_NORMAL 0x3
|
||||
#else
|
||||
#define DDR_CKE_CTRL_NORMAL 0x1
|
||||
#endif
|
||||
#define PHY_EN_DYN_PWRDN (0x1 << 20)
|
||||
|
||||
/* Micron MT47H128M16RT-25E */
|
||||
#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
|
||||
#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
|
||||
#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
|
||||
#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
|
||||
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
|
||||
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
|
||||
#define MT47H128M16RT25E_RATIO 0x80
|
||||
#define MT47H128M16RT25E_RD_DQS 0x12
|
||||
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
|
||||
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
|
||||
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41J128M16JT-125 */
|
||||
#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
|
||||
#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
|
||||
#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
|
||||
#define MT41J128MJT125_EMIF_TIM3 0x501F830F
|
||||
#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
|
||||
#define MT41J128MJT125_EMIF_SDREF 0x0000093B
|
||||
#define MT41J128MJT125_ZQ_CFG 0x50074BE4
|
||||
#define MT41J128MJT125_RATIO 0x40
|
||||
#define MT41J128MJT125_INVERT_CLKOUT 0x1
|
||||
#define MT41J128MJT125_RD_DQS 0x3B
|
||||
#define MT41J128MJT125_WR_DQS 0x85
|
||||
#define MT41J128MJT125_PHY_WR_DATA 0xC1
|
||||
#define MT41J128MJT125_PHY_FIFO_WE 0x100
|
||||
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41J128M16JT-125 at 400MHz*/
|
||||
#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
|
||||
#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
|
||||
#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
|
||||
#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
|
||||
#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
|
||||
#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
|
||||
#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
|
||||
#define MT41J128MJT125_RATIO_400MHz 0x80
|
||||
#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
|
||||
#define MT41J128MJT125_RD_DQS_400MHz 0x3A
|
||||
#define MT41J128MJT125_WR_DQS_400MHz 0x3B
|
||||
#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
|
||||
#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
|
||||
|
||||
/* Micron MT41K128M16JT-187E */
|
||||
#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
|
||||
#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
|
||||
#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
|
||||
#define MT41K128MJT187E_EMIF_TIM3 0x501F830F
|
||||
#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
|
||||
#define MT41K128MJT187E_EMIF_SDREF 0x0000093B
|
||||
#define MT41K128MJT187E_ZQ_CFG 0x50074BE4
|
||||
#define MT41K128MJT187E_RATIO 0x40
|
||||
#define MT41K128MJT187E_INVERT_CLKOUT 0x1
|
||||
#define MT41K128MJT187E_RD_DQS 0x3B
|
||||
#define MT41K128MJT187E_WR_DQS 0x85
|
||||
#define MT41K128MJT187E_PHY_WR_DATA 0xC1
|
||||
#define MT41K128MJT187E_PHY_FIFO_WE 0x100
|
||||
#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41K128M16JT-125 IT:K (256 MB) at 400MHz */
|
||||
#define MT41K128M16JT125K_EMIF_READ_LATENCY 0x07
|
||||
#define MT41K128M16JT125K_EMIF_TIM1 0x0AAAD4DB
|
||||
#define MT41K128M16JT125K_EMIF_TIM2 0x2A437FDA
|
||||
#define MT41K128M16JT125K_EMIF_TIM3 0x501F83FF
|
||||
#define MT41K128M16JT125K_EMIF_SDCFG 0x61A052B2
|
||||
#define MT41K128M16JT125K_EMIF_SDREF 0x00000C30
|
||||
#define MT41K128M16JT125K_ZQ_CFG 0x50074BE4
|
||||
#define MT41K128M16JT125K_RATIO 0x80
|
||||
#define MT41K128M16JT125K_INVERT_CLKOUT 0x0
|
||||
#define MT41K128M16JT125K_RD_DQS 0x38
|
||||
#define MT41K128M16JT125K_WR_DQS 0x46
|
||||
#define MT41K128M16JT125K_PHY_WR_DATA 0x7D
|
||||
#define MT41K128M16JT125K_PHY_FIFO_WE 0x9B
|
||||
#define MT41K128M16JT125K_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41J64M16JT-125 */
|
||||
#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
|
||||
|
||||
/* Micron MT41J256M16JT-125 */
|
||||
#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
|
||||
|
||||
/* Micron MT41J256M8HX-15E */
|
||||
#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
|
||||
#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
|
||||
#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
|
||||
#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
|
||||
#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
|
||||
#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
|
||||
#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
|
||||
#define MT41J256M8HX15E_RATIO 0x40
|
||||
#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
|
||||
#define MT41J256M8HX15E_RD_DQS 0x3B
|
||||
#define MT41J256M8HX15E_WR_DQS 0x85
|
||||
#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
|
||||
#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
|
||||
#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41K256M16HA-125E */
|
||||
#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
|
||||
#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
|
||||
#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
|
||||
#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
|
||||
#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
|
||||
#define MT41K256M16HA125E_EMIF_SDREF 0xC30
|
||||
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
|
||||
#define MT41K256M16HA125E_RATIO 0x80
|
||||
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
|
||||
#define MT41K256M16HA125E_RD_DQS 0x38
|
||||
#define MT41K256M16HA125E_WR_DQS 0x44
|
||||
#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
|
||||
#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
|
||||
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Micron MT41J512M8RH-125 on EVM v1.5 */
|
||||
#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
|
||||
#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
|
||||
#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
|
||||
#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
|
||||
#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
|
||||
#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
|
||||
#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
|
||||
#define MT41J512M8RH125_RATIO 0x80
|
||||
#define MT41J512M8RH125_INVERT_CLKOUT 0x0
|
||||
#define MT41J512M8RH125_RD_DQS 0x3B
|
||||
#define MT41J512M8RH125_WR_DQS 0x3C
|
||||
#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
|
||||
#define MT41J512M8RH125_PHY_WR_DATA 0x74
|
||||
#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
|
||||
|
||||
/* Samsung K4B2G1646E-BIH9 */
|
||||
#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
|
||||
#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
|
||||
#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
|
||||
#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
|
||||
#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
|
||||
#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
|
||||
#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
|
||||
#define K4B2G1646EBIH9_RATIO 0x80
|
||||
#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
|
||||
#define K4B2G1646EBIH9_RD_DQS 0x35
|
||||
#define K4B2G1646EBIH9_WR_DQS 0x3A
|
||||
#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
|
||||
#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
|
||||
#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
|
||||
|
||||
#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
|
||||
#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
|
||||
#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
|
||||
#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
|
||||
#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
|
||||
#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
|
||||
#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
|
||||
|
||||
#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
|
||||
#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
|
||||
#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
|
||||
#define DDR3_DATA0_IOCTRL_VALUE 0x84
|
||||
#define DDR3_DATA1_IOCTRL_VALUE 0x84
|
||||
#define DDR3_DATA2_IOCTRL_VALUE 0x84
|
||||
#define DDR3_DATA3_IOCTRL_VALUE 0x84
|
||||
|
||||
/**
|
||||
* Configure DMM
|
||||
*/
|
||||
void config_dmm(const struct dmm_lisa_map_regs *regs);
|
||||
|
||||
/**
|
||||
* Configure SDRAM
|
||||
*/
|
||||
void config_sdram(const struct emif_regs *regs, int nr);
|
||||
void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
|
||||
|
||||
/**
|
||||
* Set SDRAM timings
|
||||
*/
|
||||
void set_sdram_timings(const struct emif_regs *regs, int nr);
|
||||
|
||||
/**
|
||||
* Configure DDR PHY
|
||||
*/
|
||||
void config_ddr_phy(const struct emif_regs *regs, int nr);
|
||||
|
||||
struct ddr_cmd_regs {
|
||||
unsigned int resv0[7];
|
||||
unsigned int cm0csratio; /* offset 0x01C */
|
||||
unsigned int resv1[3];
|
||||
unsigned int cm0iclkout; /* offset 0x02C */
|
||||
unsigned int resv2[8];
|
||||
unsigned int cm1csratio; /* offset 0x050 */
|
||||
unsigned int resv3[3];
|
||||
unsigned int cm1iclkout; /* offset 0x060 */
|
||||
unsigned int resv4[8];
|
||||
unsigned int cm2csratio; /* offset 0x084 */
|
||||
unsigned int resv5[3];
|
||||
unsigned int cm2iclkout; /* offset 0x094 */
|
||||
unsigned int resv6[3];
|
||||
};
|
||||
|
||||
struct ddr_data_regs {
|
||||
unsigned int dt0rdsratio0; /* offset 0x0C8 */
|
||||
unsigned int resv1[4];
|
||||
unsigned int dt0wdsratio0; /* offset 0x0DC */
|
||||
unsigned int resv2[4];
|
||||
unsigned int dt0wiratio0; /* offset 0x0F0 */
|
||||
unsigned int resv3;
|
||||
unsigned int dt0wimode0; /* offset 0x0F8 */
|
||||
unsigned int dt0giratio0; /* offset 0x0FC */
|
||||
unsigned int resv4;
|
||||
unsigned int dt0gimode0; /* offset 0x104 */
|
||||
unsigned int dt0fwsratio0; /* offset 0x108 */
|
||||
unsigned int resv5[4];
|
||||
unsigned int dt0dqoffset; /* offset 0x11C */
|
||||
unsigned int dt0wrsratio0; /* offset 0x120 */
|
||||
unsigned int resv6[4];
|
||||
unsigned int dt0rdelays0; /* offset 0x134 */
|
||||
unsigned int dt0dldiff0; /* offset 0x138 */
|
||||
unsigned int resv7[12];
|
||||
};
|
||||
|
||||
/**
|
||||
* This structure represents the DDR registers on AM33XX devices.
|
||||
* We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
|
||||
* correspond to DATA1 registers defined here.
|
||||
*/
|
||||
struct ddr_regs {
|
||||
unsigned int resv0[3];
|
||||
unsigned int cm0config; /* offset 0x00C */
|
||||
unsigned int cm0configclk; /* offset 0x010 */
|
||||
unsigned int resv1[2];
|
||||
unsigned int cm0csratio; /* offset 0x01C */
|
||||
unsigned int resv2[3];
|
||||
unsigned int cm0iclkout; /* offset 0x02C */
|
||||
unsigned int resv3[4];
|
||||
unsigned int cm1config; /* offset 0x040 */
|
||||
unsigned int cm1configclk; /* offset 0x044 */
|
||||
unsigned int resv4[2];
|
||||
unsigned int cm1csratio; /* offset 0x050 */
|
||||
unsigned int resv5[3];
|
||||
unsigned int cm1iclkout; /* offset 0x060 */
|
||||
unsigned int resv6[4];
|
||||
unsigned int cm2config; /* offset 0x074 */
|
||||
unsigned int cm2configclk; /* offset 0x078 */
|
||||
unsigned int resv7[2];
|
||||
unsigned int cm2csratio; /* offset 0x084 */
|
||||
unsigned int resv8[3];
|
||||
unsigned int cm2iclkout; /* offset 0x094 */
|
||||
unsigned int resv9[12];
|
||||
unsigned int dt0rdsratio0; /* offset 0x0C8 */
|
||||
unsigned int resv10[4];
|
||||
unsigned int dt0wdsratio0; /* offset 0x0DC */
|
||||
unsigned int resv11[4];
|
||||
unsigned int dt0wiratio0; /* offset 0x0F0 */
|
||||
unsigned int resv12;
|
||||
unsigned int dt0wimode0; /* offset 0x0F8 */
|
||||
unsigned int dt0giratio0; /* offset 0x0FC */
|
||||
unsigned int resv13;
|
||||
unsigned int dt0gimode0; /* offset 0x104 */
|
||||
unsigned int dt0fwsratio0; /* offset 0x108 */
|
||||
unsigned int resv14[4];
|
||||
unsigned int dt0dqoffset; /* offset 0x11C */
|
||||
unsigned int dt0wrsratio0; /* offset 0x120 */
|
||||
unsigned int resv15[4];
|
||||
unsigned int dt0rdelays0; /* offset 0x134 */
|
||||
unsigned int dt0dldiff0; /* offset 0x138 */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR CMD control registers.
|
||||
*/
|
||||
struct cmd_control {
|
||||
unsigned long cmd0csratio;
|
||||
unsigned long cmd0csforce;
|
||||
unsigned long cmd0csdelay;
|
||||
unsigned long cmd0iclkout;
|
||||
unsigned long cmd1csratio;
|
||||
unsigned long cmd1csforce;
|
||||
unsigned long cmd1csdelay;
|
||||
unsigned long cmd1iclkout;
|
||||
unsigned long cmd2csratio;
|
||||
unsigned long cmd2csforce;
|
||||
unsigned long cmd2csdelay;
|
||||
unsigned long cmd2iclkout;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR DATA registers.
|
||||
*/
|
||||
struct ddr_data {
|
||||
unsigned long datardsratio0;
|
||||
unsigned long datawdsratio0;
|
||||
unsigned long datawiratio0;
|
||||
unsigned long datagiratio0;
|
||||
unsigned long datafwsratio0;
|
||||
unsigned long datawrsratio0;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure DDR CMD control registers
|
||||
*/
|
||||
void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
|
||||
|
||||
/**
|
||||
* Configure DDR DATA registers
|
||||
*/
|
||||
void config_ddr_data(const struct ddr_data *data, int nr);
|
||||
|
||||
/**
|
||||
* This structure represents the DDR io control on AM33XX devices.
|
||||
*/
|
||||
struct ddr_cmdtctrl {
|
||||
unsigned int cm0ioctl;
|
||||
unsigned int cm1ioctl;
|
||||
unsigned int cm2ioctl;
|
||||
unsigned int resv2[12];
|
||||
unsigned int dt0ioctl;
|
||||
unsigned int dt1ioctl;
|
||||
unsigned int dt2ioctrl;
|
||||
unsigned int dt3ioctrl;
|
||||
unsigned int resv3[4];
|
||||
unsigned int emif_sdram_config_ext;
|
||||
};
|
||||
|
||||
struct ctrl_ioregs {
|
||||
unsigned int cm0ioctl;
|
||||
unsigned int cm1ioctl;
|
||||
unsigned int cm2ioctl;
|
||||
unsigned int dt0ioctl;
|
||||
unsigned int dt1ioctl;
|
||||
unsigned int dt2ioctrl;
|
||||
unsigned int dt3ioctrl;
|
||||
unsigned int emif_sdram_config_ext;
|
||||
};
|
||||
|
||||
/**
|
||||
* Configure DDR io control registers
|
||||
*/
|
||||
void config_io_ctrl(const struct ctrl_ioregs *ioregs);
|
||||
|
||||
struct ddr_ctrl {
|
||||
unsigned int ddrioctrl;
|
||||
unsigned int resv1[325];
|
||||
unsigned int ddrckectrl;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_TI816X
|
||||
void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
|
||||
const struct emif_regs *regs,
|
||||
const struct dmm_lisa_map_regs *lisa_regs, int nrs);
|
||||
#else
|
||||
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
|
||||
const struct ddr_data *data, const struct cmd_control *ctrl,
|
||||
const struct emif_regs *regs, int nr);
|
||||
#endif
|
||||
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
|
||||
|
||||
#endif /* _DDR_DEFS_H */
|
||||
@@ -0,0 +1,37 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2010 Texas Instruments
|
||||
*
|
||||
* Based on:
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* dm644x_emac.h
|
||||
*
|
||||
* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
|
||||
*
|
||||
* Copyright (C) 2005 Texas Instruments.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _EMAC_DEFS_H_
|
||||
#define _EMAC_DEFS_H_
|
||||
|
||||
#ifdef CONFIG_TI816X
|
||||
#define EMAC_BASE_ADDR (0x4A100000)
|
||||
#define EMAC_WRAPPER_BASE_ADDR (0x4A100900)
|
||||
#define EMAC_WRAPPER_RAM_ADDR (0x4A102000)
|
||||
#define EMAC_MDIO_BASE_ADDR (0x4A100800)
|
||||
#define EMAC_MDIO_BUS_FREQ (250000000UL)
|
||||
#define EMAC_MDIO_CLOCK_FREQ (2000000UL)
|
||||
|
||||
typedef volatile unsigned int dv_reg;
|
||||
typedef volatile unsigned int *dv_reg_p;
|
||||
|
||||
#define DAVINCI_EMAC_VERSION2
|
||||
#define DAVINCI_EMAC_GIG_ENABLE
|
||||
#endif
|
||||
|
||||
#endif /* _EMAC_DEFS_H_ */
|
||||
@@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
#ifndef _GPIO_AM33xx_H
|
||||
#define _GPIO_AM33xx_H
|
||||
|
||||
#include <asm/omap_gpio.h>
|
||||
|
||||
#ifdef CONFIG_AM43XX
|
||||
#define OMAP_MAX_GPIO 192
|
||||
#else
|
||||
#define OMAP_MAX_GPIO 128
|
||||
#endif
|
||||
|
||||
#define AM33XX_GPIO0_BASE 0x44E07000
|
||||
#define AM33XX_GPIO1_BASE 0x4804C000
|
||||
#define AM33XX_GPIO2_BASE 0x481AC000
|
||||
#define AM33XX_GPIO3_BASE 0x481AE000
|
||||
#define AM33XX_GPIO4_BASE 0x48320000
|
||||
#define AM33XX_GPIO5_BASE 0x48322000
|
||||
|
||||
/* GPIO CTRL register */
|
||||
#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
|
||||
#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0)
|
||||
#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK
|
||||
|
||||
/* GPIO OUTPUT ENABLE register */
|
||||
#define GPIO_OE_ENABLE(x) (1 << x)
|
||||
|
||||
/* GPIO SETDATAOUT register */
|
||||
#define GPIO_SETDATAOUT(x) (1 << x)
|
||||
#endif /* _GPIO_AM33xx_H */
|
||||
@@ -0,0 +1,89 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* hardware.h
|
||||
*
|
||||
* hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_H
|
||||
#define __AM33XX_HARDWARE_H
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/arch/omap.h>
|
||||
#ifdef CONFIG_AM33XX
|
||||
#include <asm/arch/hardware_am33xx.h>
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#include <asm/arch/hardware_ti816x.h>
|
||||
#elif defined(CONFIG_TI814X)
|
||||
#include <asm/arch/hardware_ti814x.h>
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#include <asm/arch/hardware_am43xx.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Common hardware definitions
|
||||
*/
|
||||
|
||||
/* DM Timer base addresses */
|
||||
#define DM_TIMER0_BASE 0x4802C000
|
||||
#define DM_TIMER1_BASE 0x4802E000
|
||||
#define DM_TIMER2_BASE 0x48040000
|
||||
#define DM_TIMER3_BASE 0x48042000
|
||||
#define DM_TIMER4_BASE 0x48044000
|
||||
#define DM_TIMER5_BASE 0x48046000
|
||||
#define DM_TIMER6_BASE 0x48048000
|
||||
#define DM_TIMER7_BASE 0x4804A000
|
||||
|
||||
/* GPIO Base address */
|
||||
#define GPIO0_BASE 0x48032000
|
||||
#define GPIO1_BASE 0x4804C000
|
||||
|
||||
/* BCH Error Location Module */
|
||||
#define ELM_BASE 0x48080000
|
||||
|
||||
/* EMIF Base address */
|
||||
#define EMIF4_0_CFG_BASE 0x4C000000
|
||||
#define EMIF4_1_CFG_BASE 0x4D000000
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_CTRL_ADDR 0x44E10E04
|
||||
#define DDR_CONTROL_BASE_ADDR 0x44E11404
|
||||
|
||||
/* UART */
|
||||
#if CONFIG_CONS_INDEX == 1
|
||||
# define DEFAULT_UART_BASE UART0_BASE
|
||||
#elif CONFIG_CONS_INDEX == 2
|
||||
# define DEFAULT_UART_BASE UART1_BASE
|
||||
#elif CONFIG_CONS_INDEX == 3
|
||||
# define DEFAULT_UART_BASE UART2_BASE
|
||||
#elif CONFIG_CONS_INDEX == 4
|
||||
# define DEFAULT_UART_BASE UART3_BASE
|
||||
#elif CONFIG_CONS_INDEX == 5
|
||||
# define DEFAULT_UART_BASE UART4_BASE
|
||||
#elif CONFIG_CONS_INDEX == 6
|
||||
# define DEFAULT_UART_BASE UART5_BASE
|
||||
#endif
|
||||
|
||||
/* GPMC Base address */
|
||||
#define GPMC_BASE 0x50000000
|
||||
|
||||
/* CPSW Config space */
|
||||
#define CPSW_BASE 0x4A100000
|
||||
|
||||
/* Control status register */
|
||||
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
|
||||
#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
|
||||
#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
|
||||
#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
|
||||
#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
|
||||
#define CTRL_SYSBOOT_15_14_SHIFT 22
|
||||
|
||||
#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
|
||||
#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
|
||||
|
||||
#define NUM_CRYSTAL_FREQ 0x4
|
||||
|
||||
int clk_get(int clk);
|
||||
#endif /* __AM33XX_HARDWARE_H */
|
||||
@@ -0,0 +1,76 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* hardware_am33xx.h
|
||||
*
|
||||
* AM33xx hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_AM33XX_H
|
||||
#define __AM33XX_HARDWARE_AM33XX_H
|
||||
|
||||
/* Module base addresses */
|
||||
|
||||
/* UART Base Address */
|
||||
#define UART0_BASE 0x44E09000
|
||||
#define UART1_BASE 0x48022000
|
||||
#define UART2_BASE 0x48024000
|
||||
#define UART3_BASE 0x481A6000
|
||||
#define UART4_BASE 0x481A8000
|
||||
#define UART5_BASE 0x481AA000
|
||||
|
||||
/* GPIO Base address */
|
||||
#define GPIO2_BASE 0x481AC000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x44E35000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x44E10000
|
||||
#define CTRL_DEVICE_BASE 0x44E10600
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x44E00000
|
||||
#define CM_PER 0x44E00000
|
||||
#define CM_WKUP 0x44E00400
|
||||
#define CM_DPLL 0x44E00500
|
||||
#define CM_RTC 0x44E00800
|
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
|
||||
#define PRM_RSTST (PRM_RSTCTRL + 8)
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x44E10E0C
|
||||
#define VTP1_CTRL_ADDR 0x48140E10
|
||||
#define PRM_DEVICE_INST 0x44E00F00
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x44E12000
|
||||
#define DDR_PHY_DATA_ADDR 0x44E120C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x47C0C800
|
||||
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
|
||||
#define DDR_DATA_REGS_NR 2
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
|
||||
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
|
||||
|
||||
/* CPSW Config space */
|
||||
#define CPSW_MDIO_BASE 0x4A101000
|
||||
|
||||
/* RTC base address */
|
||||
#define RTC_BASE 0x44E3E000
|
||||
|
||||
/* OTG */
|
||||
#define USB0_OTG_BASE 0x47401000
|
||||
#define USB1_OTG_BASE 0x47401800
|
||||
|
||||
/* LCD Controller */
|
||||
#define LCD_CNTL_BASE 0x4830E000
|
||||
|
||||
/* PWMSS */
|
||||
#define PWMSS0_BASE 0x48300000
|
||||
#define AM33XX_ECAP0_BASE 0x48300100
|
||||
#define AM33XX_EPWM_BASE 0x48300200
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_AM33XX_H */
|
||||
@@ -0,0 +1,90 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* hardware_am43xx.h
|
||||
*
|
||||
* AM43xx hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef __AM43XX_HARDWARE_AM43XX_H
|
||||
#define __AM43XX_HARDWARE_AM43XX_H
|
||||
|
||||
/* Module base addresses */
|
||||
|
||||
/* L3 Fast Configuration Bandwidth Limiter Base Address */
|
||||
#define L3F_CFG_BWLIMITER 0x44005200
|
||||
|
||||
/* UART Base Address */
|
||||
#define UART0_BASE 0x44E09000
|
||||
|
||||
/* GPIO Base address */
|
||||
#define GPIO2_BASE 0x481AC000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x44E35000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x44E10000
|
||||
#define CTRL_DEVICE_BASE 0x44E10600
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x44DF0000
|
||||
#define CM_WKUP 0x44DF2800
|
||||
#define CM_PER 0x44DF8800
|
||||
#define CM_DPLL 0x44DF4200
|
||||
#define CM_RTC 0x44DF8500
|
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x4000)
|
||||
#define PRM_RSTST (PRM_RSTCTRL + 4)
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x44E10E0C
|
||||
#define VTP1_CTRL_ADDR 0x48140E10
|
||||
|
||||
/* USB CTRL Base Address */
|
||||
#define USB1_CTRL 0x44e10628
|
||||
#define USB1_CTRL_CM_PWRDN BIT(0)
|
||||
#define USB1_CTRL_OTG_PWRDN BIT(1)
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x44E12000
|
||||
#define DDR_PHY_DATA_ADDR 0x44E120C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x47C0C800
|
||||
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
|
||||
#define DDR_DATA_REGS_NR 2
|
||||
|
||||
/* CPSW Config space */
|
||||
#define CPSW_MDIO_BASE 0x4A101000
|
||||
|
||||
/* RTC base address */
|
||||
#define RTC_BASE 0x44E3E000
|
||||
|
||||
/* USB OTG */
|
||||
#define USB_OTG_SS1_BASE 0x48390000
|
||||
#define USB_OTG_SS1_GLUE_BASE 0x48380000
|
||||
#define USB2_PHY1_POWER 0x44E10620
|
||||
|
||||
#define USB_OTG_SS2_BASE 0x483D0000
|
||||
#define USB_OTG_SS2_GLUE_BASE 0x483C0000
|
||||
#define USB2_PHY2_POWER 0x44E10628
|
||||
|
||||
/* USB Clock Control */
|
||||
#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
|
||||
#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
|
||||
#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1)
|
||||
#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
|
||||
|
||||
#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
|
||||
#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
|
||||
#define USBPHYOCPSCP_MODULE_EN (1 << 1)
|
||||
#define CM_DEVICE_INST 0x44df4100
|
||||
#define PRM_DEVICE_INST 0x44df4000
|
||||
|
||||
#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
|
||||
#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
|
||||
|
||||
/* EDMA3 Base Address */
|
||||
#define EDMA3_BASE 0x49000000
|
||||
|
||||
#endif /* __AM43XX_HARDWARE_AM43XX_H */
|
||||
@@ -0,0 +1,60 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* hardware_ti814x.h
|
||||
*
|
||||
* TI814x hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_TI814X_H
|
||||
#define __AM33XX_HARDWARE_TI814X_H
|
||||
|
||||
/* Module base addresses */
|
||||
|
||||
/* UART Base Address */
|
||||
#define UART0_BASE 0x48020000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x481C7000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x48140000
|
||||
#define CTRL_DEVICE_BASE 0x48140600
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x48180000
|
||||
#define CM_PER 0x44E00000
|
||||
#define CM_WKUP 0x44E00400
|
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
|
||||
#define PRM_RSTST (PRM_RSTCTRL + 8)
|
||||
|
||||
/* PLL Subsystem Base Address */
|
||||
#define PLL_SUBSYS_BASE 0x481C5000
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x48140E0C
|
||||
#define VTP1_CTRL_ADDR 0x48140E10
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x47C0C400
|
||||
#define DDR_PHY_DATA_ADDR 0x47C0C4C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x47C0C800
|
||||
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
|
||||
#define DDR_DATA_REGS_NR 4
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
|
||||
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
|
||||
|
||||
/* CPSW Config space */
|
||||
#define CPSW_MDIO_BASE 0x4A100800
|
||||
|
||||
/* RTC base address */
|
||||
#define RTC_BASE 0x480C0000
|
||||
|
||||
/* OTG */
|
||||
#define USB0_OTG_BASE 0x47401000
|
||||
#define USB1_OTG_BASE 0x47401800
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_TI814X_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* hardware_ti816x.h
|
||||
*
|
||||
* TI816x hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
||||
* Antoine Tenart, <atenart@adeneo-embedded.com>
|
||||
* Based on TI-PSP-04.00.02.14
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_TI816X_H
|
||||
#define __AM33XX_HARDWARE_TI816X_H
|
||||
|
||||
/* UART */
|
||||
#define UART0_BASE 0x48020000
|
||||
#define UART1_BASE 0x48022000
|
||||
#define UART2_BASE 0x48024000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x480C2000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x48140000
|
||||
#define CTRL_DEVICE_BASE 0x48140600
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x48180000
|
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
|
||||
#define PRM_RSTST (PRM_RSTCTRL + 8)
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x48198358
|
||||
#define VTP1_CTRL_ADDR 0x4819A358
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x48198000
|
||||
#define DDR_PHY_DATA_ADDR 0x481980C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x4819A000
|
||||
#define DDR_PHY_DATA_ADDR2 0x4819A0C8
|
||||
#define DDR_DATA_REGS_NR 4
|
||||
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE 0x48198000
|
||||
#define DDRPHY_1_CONFIG_BASE 0x4819A000
|
||||
#define DDRPHY_CONFIG_BASE ((emif == 0) ? \
|
||||
DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
|
||||
|
||||
/* RTC base address */
|
||||
#define RTC_BASE 0x480C0000
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_TI816X_H */
|
||||
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*/
|
||||
#ifndef _I2C_AM33XX_H_
|
||||
#define _I2C_AM33XX_H_
|
||||
|
||||
#include <asm/omap_i2c.h>
|
||||
|
||||
#define I2C_BASE1 0x44E0B000
|
||||
#define I2C_BASE2 0x4802A000
|
||||
#define I2C_BASE3 0x4819C000
|
||||
|
||||
#define I2C_DEFAULT_BASE I2C_BASE1
|
||||
|
||||
#define I2C_IP_CLK 48000000
|
||||
#define I2C_INTERNAL_SAMPLING_CLK 12000000
|
||||
|
||||
#endif /* _I2C_AM33XX_H_ */
|
||||
@@ -0,0 +1,63 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author
|
||||
* Mansoor Ahamed <mansoor.ahamed@ti.com>
|
||||
*
|
||||
* Initial Code from:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef _MEM_H_
|
||||
#define _MEM_H_
|
||||
|
||||
/*
|
||||
* GPMC settings -
|
||||
* Definitions is as per the following format
|
||||
* #define <PART>_GPMC_CONFIG<x> <value>
|
||||
* Where:
|
||||
* PART is the part name e.g. STNOR - Intel Strata Flash
|
||||
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
|
||||
* Value is corresponding value
|
||||
*
|
||||
* For every valid PRCM configuration there should be only one definition of
|
||||
* the same. if values are independent of the board, this definition will be
|
||||
* present in this file if values are dependent on the board, then this should
|
||||
* go into corresponding mem-boardName.h file
|
||||
*
|
||||
* Currently valid part Names are (PART):
|
||||
* M_NAND - Micron NAND
|
||||
* STNOR - STMicrolelctronics M29W128GL
|
||||
*/
|
||||
#define GPMC_SIZE_256M 0x0
|
||||
#define GPMC_SIZE_128M 0x8
|
||||
#define GPMC_SIZE_64M 0xC
|
||||
#define GPMC_SIZE_32M 0xE
|
||||
#define GPMC_SIZE_16M 0xF
|
||||
|
||||
#define M_NAND_GPMC_CONFIG1 0x00000800
|
||||
#define M_NAND_GPMC_CONFIG2 0x001e1e00
|
||||
#define M_NAND_GPMC_CONFIG3 0x001e1e00
|
||||
#define M_NAND_GPMC_CONFIG4 0x16051807
|
||||
#define M_NAND_GPMC_CONFIG5 0x00151e1e
|
||||
#define M_NAND_GPMC_CONFIG6 0x16000f80
|
||||
#define M_NAND_GPMC_CONFIG7 0x00000008
|
||||
|
||||
#define STNOR_GPMC_CONFIG1 0x00001200
|
||||
#define STNOR_GPMC_CONFIG2 0x00101000
|
||||
#define STNOR_GPMC_CONFIG3 0x00030301
|
||||
#define STNOR_GPMC_CONFIG4 0x10041004
|
||||
#define STNOR_GPMC_CONFIG5 0x000C1010
|
||||
#define STNOR_GPMC_CONFIG6 0x08070280
|
||||
#define STNOR_GPMC_CONFIG7 0x00000F48
|
||||
|
||||
/* max number of GPMC Chip Selects */
|
||||
#define GPMC_MAX_CS 8
|
||||
/* max number of GPMC regs */
|
||||
#define GPMC_MAX_REG 7
|
||||
|
||||
#define DBG_MPDB 6
|
||||
|
||||
#endif /* endif _MEM_H_ */
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* mmc_host_def.h
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MMC_HOST_DEF_H
|
||||
#define MMC_HOST_DEF_H
|
||||
|
||||
#include <asm/omap_mmc.h>
|
||||
|
||||
/*
|
||||
* OMAP HSMMC register definitions
|
||||
*/
|
||||
#define OMAP_HSMMC1_BASE 0x48060000
|
||||
#define OMAP_HSMMC2_BASE 0x481D8000
|
||||
|
||||
#if defined(CONFIG_TI814X)
|
||||
#undef MMC_CLOCK_REFERENCE
|
||||
#define MMC_CLOCK_REFERENCE 192 /* MHz */
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#undef MMC_CLOCK_REFERENCE
|
||||
#define MMC_CLOCK_REFERENCE 48 /* MHz */
|
||||
#endif
|
||||
|
||||
#endif /* MMC_HOST_DEF_H */
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* mux.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MUX_H_
|
||||
#define _MUX_H_
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_AM33XX
|
||||
#include <asm/arch/mux_am33xx.h>
|
||||
#elif defined(CONFIG_TI814X)
|
||||
#include <asm/arch/mux_ti814x.h>
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#include <asm/arch/mux_ti816x.h>
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#include <asm/arch/mux_am43xx.h>
|
||||
#endif
|
||||
|
||||
struct module_pin_mux {
|
||||
short reg_offset;
|
||||
unsigned int val;
|
||||
};
|
||||
|
||||
/* Pad control register offset */
|
||||
#define PAD_CTRL_BASE 0x800
|
||||
#define OFFSET(x) (unsigned int) (&((struct pad_signals *)\
|
||||
(PAD_CTRL_BASE))->x)
|
||||
|
||||
/*
|
||||
* Configure the pin mux for the module
|
||||
*/
|
||||
void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
|
||||
|
||||
#endif /* endif _MUX_H */
|
||||
@@ -0,0 +1,247 @@
|
||||
/*
|
||||
* mux_am33xx.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MUX_AM33XX_H_
|
||||
#define _MUX_AM33XX_H_
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define MUX_CFG(value, offset) \
|
||||
__raw_writel(value, (CTRL_BASE + offset));
|
||||
|
||||
/* PAD Control Fields */
|
||||
#define SLEWCTRL (0x1 << 6)
|
||||
#define RXACTIVE (0x1 << 5)
|
||||
#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
|
||||
#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
|
||||
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
|
||||
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
|
||||
#define MODE(val) val /* used for Readability */
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS
|
||||
* Field names corresponds to the pad signal name
|
||||
*/
|
||||
struct pad_signals {
|
||||
int gpmc_ad0;
|
||||
int gpmc_ad1;
|
||||
int gpmc_ad2;
|
||||
int gpmc_ad3;
|
||||
int gpmc_ad4;
|
||||
int gpmc_ad5;
|
||||
int gpmc_ad6;
|
||||
int gpmc_ad7;
|
||||
int gpmc_ad8;
|
||||
int gpmc_ad9;
|
||||
int gpmc_ad10;
|
||||
int gpmc_ad11;
|
||||
int gpmc_ad12;
|
||||
int gpmc_ad13;
|
||||
int gpmc_ad14;
|
||||
int gpmc_ad15;
|
||||
int gpmc_a0;
|
||||
int gpmc_a1;
|
||||
int gpmc_a2;
|
||||
int gpmc_a3;
|
||||
int gpmc_a4;
|
||||
int gpmc_a5;
|
||||
int gpmc_a6;
|
||||
int gpmc_a7;
|
||||
int gpmc_a8;
|
||||
int gpmc_a9;
|
||||
int gpmc_a10;
|
||||
int gpmc_a11;
|
||||
int gpmc_wait0;
|
||||
int gpmc_wpn;
|
||||
int gpmc_be1n;
|
||||
int gpmc_csn0;
|
||||
int gpmc_csn1;
|
||||
int gpmc_csn2;
|
||||
int gpmc_csn3;
|
||||
int gpmc_clk;
|
||||
int gpmc_advn_ale;
|
||||
int gpmc_oen_ren;
|
||||
int gpmc_wen;
|
||||
int gpmc_be0n_cle;
|
||||
int lcd_data0;
|
||||
int lcd_data1;
|
||||
int lcd_data2;
|
||||
int lcd_data3;
|
||||
int lcd_data4;
|
||||
int lcd_data5;
|
||||
int lcd_data6;
|
||||
int lcd_data7;
|
||||
int lcd_data8;
|
||||
int lcd_data9;
|
||||
int lcd_data10;
|
||||
int lcd_data11;
|
||||
int lcd_data12;
|
||||
int lcd_data13;
|
||||
int lcd_data14;
|
||||
int lcd_data15;
|
||||
int lcd_vsync;
|
||||
int lcd_hsync;
|
||||
int lcd_pclk;
|
||||
int lcd_ac_bias_en;
|
||||
int mmc0_dat3;
|
||||
int mmc0_dat2;
|
||||
int mmc0_dat1;
|
||||
int mmc0_dat0;
|
||||
int mmc0_clk;
|
||||
int mmc0_cmd;
|
||||
int mii1_col;
|
||||
int mii1_crs;
|
||||
int mii1_rxerr;
|
||||
int mii1_txen;
|
||||
int mii1_rxdv;
|
||||
int mii1_txd3;
|
||||
int mii1_txd2;
|
||||
int mii1_txd1;
|
||||
int mii1_txd0;
|
||||
int mii1_txclk;
|
||||
int mii1_rxclk;
|
||||
int mii1_rxd3;
|
||||
int mii1_rxd2;
|
||||
int mii1_rxd1;
|
||||
int mii1_rxd0;
|
||||
int rmii1_refclk;
|
||||
int mdio_data;
|
||||
int mdio_clk;
|
||||
int spi0_sclk;
|
||||
int spi0_d0;
|
||||
int spi0_d1;
|
||||
int spi0_cs0;
|
||||
int spi0_cs1;
|
||||
int ecap0_in_pwm0_out;
|
||||
int uart0_ctsn;
|
||||
int uart0_rtsn;
|
||||
int uart0_rxd;
|
||||
int uart0_txd;
|
||||
int uart1_ctsn;
|
||||
int uart1_rtsn;
|
||||
int uart1_rxd;
|
||||
int uart1_txd;
|
||||
int i2c0_sda;
|
||||
int i2c0_scl;
|
||||
int mcasp0_aclkx;
|
||||
int mcasp0_fsx;
|
||||
int mcasp0_axr0;
|
||||
int mcasp0_ahclkr;
|
||||
int mcasp0_aclkr;
|
||||
int mcasp0_fsr;
|
||||
int mcasp0_axr1;
|
||||
int mcasp0_ahclkx;
|
||||
int xdma_event_intr0;
|
||||
int xdma_event_intr1;
|
||||
int nresetin_out;
|
||||
int porz;
|
||||
int nnmi;
|
||||
int osc0_in;
|
||||
int osc0_out;
|
||||
int rsvd1;
|
||||
int tms;
|
||||
int tdi;
|
||||
int tdo;
|
||||
int tck;
|
||||
int ntrst;
|
||||
int emu0;
|
||||
int emu1;
|
||||
int osc1_in;
|
||||
int osc1_out;
|
||||
int pmic_power_en;
|
||||
int rtc_porz;
|
||||
int rsvd2;
|
||||
int ext_wakeup;
|
||||
int enz_kaldo_1p8v;
|
||||
int usb0_dm;
|
||||
int usb0_dp;
|
||||
int usb0_ce;
|
||||
int usb0_id;
|
||||
int usb0_vbus;
|
||||
int usb0_drvvbus;
|
||||
int usb1_dm;
|
||||
int usb1_dp;
|
||||
int usb1_ce;
|
||||
int usb1_id;
|
||||
int usb1_vbus;
|
||||
int usb1_drvvbus;
|
||||
int ddr_resetn;
|
||||
int ddr_csn0;
|
||||
int ddr_cke;
|
||||
int ddr_ck;
|
||||
int ddr_nck;
|
||||
int ddr_casn;
|
||||
int ddr_rasn;
|
||||
int ddr_wen;
|
||||
int ddr_ba0;
|
||||
int ddr_ba1;
|
||||
int ddr_ba2;
|
||||
int ddr_a0;
|
||||
int ddr_a1;
|
||||
int ddr_a2;
|
||||
int ddr_a3;
|
||||
int ddr_a4;
|
||||
int ddr_a5;
|
||||
int ddr_a6;
|
||||
int ddr_a7;
|
||||
int ddr_a8;
|
||||
int ddr_a9;
|
||||
int ddr_a10;
|
||||
int ddr_a11;
|
||||
int ddr_a12;
|
||||
int ddr_a13;
|
||||
int ddr_a14;
|
||||
int ddr_a15;
|
||||
int ddr_odt;
|
||||
int ddr_d0;
|
||||
int ddr_d1;
|
||||
int ddr_d2;
|
||||
int ddr_d3;
|
||||
int ddr_d4;
|
||||
int ddr_d5;
|
||||
int ddr_d6;
|
||||
int ddr_d7;
|
||||
int ddr_d8;
|
||||
int ddr_d9;
|
||||
int ddr_d10;
|
||||
int ddr_d11;
|
||||
int ddr_d12;
|
||||
int ddr_d13;
|
||||
int ddr_d14;
|
||||
int ddr_d15;
|
||||
int ddr_dqm0;
|
||||
int ddr_dqm1;
|
||||
int ddr_dqs0;
|
||||
int ddr_dqsn0;
|
||||
int ddr_dqs1;
|
||||
int ddr_dqsn1;
|
||||
int ddr_vref;
|
||||
int ddr_vtp;
|
||||
int ddr_strben0;
|
||||
int ddr_strben1;
|
||||
int ain7;
|
||||
int ain6;
|
||||
int ain5;
|
||||
int ain4;
|
||||
int ain3;
|
||||
int ain2;
|
||||
int ain1;
|
||||
int ain0;
|
||||
int vrefp;
|
||||
int vrefn;
|
||||
};
|
||||
|
||||
#endif /* endif _MUX_AM33XX_H_ */
|
||||
@@ -0,0 +1,211 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* mux_am43xx.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef _MUX_AM43XX_H_
|
||||
#define _MUX_AM43XX_H_
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define MUX_CFG(value, offset) \
|
||||
__raw_writel(value, (CTRL_BASE + offset));
|
||||
|
||||
/* PAD Control Fields */
|
||||
#define SLEWCTRL (0x1 << 19)
|
||||
#define RXACTIVE (0x1 << 18)
|
||||
#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */
|
||||
#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */
|
||||
#define PULLUDEN (0x0 << 16) /* Pull up/down enable */
|
||||
#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */
|
||||
#define MODE(val) val /* used for Readability */
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS
|
||||
* Field names corresponds to the pad signal name
|
||||
*/
|
||||
struct pad_signals {
|
||||
int gpmc_ad0;
|
||||
int gpmc_ad1;
|
||||
int gpmc_ad2;
|
||||
int gpmc_ad3;
|
||||
int gpmc_ad4;
|
||||
int gpmc_ad5;
|
||||
int gpmc_ad6;
|
||||
int gpmc_ad7;
|
||||
int gpmc_ad8;
|
||||
int gpmc_ad9;
|
||||
int gpmc_ad10;
|
||||
int gpmc_ad11;
|
||||
int gpmc_ad12;
|
||||
int gpmc_ad13;
|
||||
int gpmc_ad14;
|
||||
int gpmc_ad15;
|
||||
int gpmc_a0;
|
||||
int gpmc_a1;
|
||||
int gpmc_a2;
|
||||
int gpmc_a3;
|
||||
int gpmc_a4;
|
||||
int gpmc_a5;
|
||||
int gpmc_a6;
|
||||
int gpmc_a7;
|
||||
int gpmc_a8;
|
||||
int gpmc_a9;
|
||||
int gpmc_a10;
|
||||
int gpmc_a11;
|
||||
int gpmc_wait0;
|
||||
int gpmc_wpn;
|
||||
int gpmc_be1n;
|
||||
int gpmc_csn0;
|
||||
int gpmc_csn1;
|
||||
int gpmc_csn2;
|
||||
int gpmc_csn3;
|
||||
int gpmc_clk;
|
||||
int gpmc_advn_ale;
|
||||
int gpmc_oen_ren;
|
||||
int gpmc_wen;
|
||||
int gpmc_be0n_cle;
|
||||
int lcd_data0;
|
||||
int lcd_data1;
|
||||
int lcd_data2;
|
||||
int lcd_data3;
|
||||
int lcd_data4;
|
||||
int lcd_data5;
|
||||
int lcd_data6;
|
||||
int lcd_data7;
|
||||
int lcd_data8;
|
||||
int lcd_data9;
|
||||
int lcd_data10;
|
||||
int lcd_data11;
|
||||
int lcd_data12;
|
||||
int lcd_data13;
|
||||
int lcd_data14;
|
||||
int lcd_data15;
|
||||
int lcd_vsync;
|
||||
int lcd_hsync;
|
||||
int lcd_pclk;
|
||||
int lcd_ac_bias_en;
|
||||
int mmc0_dat3;
|
||||
int mmc0_dat2;
|
||||
int mmc0_dat1;
|
||||
int mmc0_dat0;
|
||||
int mmc0_clk;
|
||||
int mmc0_cmd;
|
||||
int mii1_col;
|
||||
int mii1_crs;
|
||||
int mii1_rxerr;
|
||||
int mii1_txen;
|
||||
int mii1_rxdv;
|
||||
int mii1_txd3;
|
||||
int mii1_txd2;
|
||||
int mii1_txd1;
|
||||
int mii1_txd0;
|
||||
int mii1_txclk;
|
||||
int mii1_rxclk;
|
||||
int mii1_rxd3;
|
||||
int mii1_rxd2;
|
||||
int mii1_rxd1;
|
||||
int mii1_rxd0;
|
||||
int rmii1_refclk;
|
||||
int mdio_data;
|
||||
int mdio_clk;
|
||||
int spi0_sclk;
|
||||
int spi0_d0;
|
||||
int spi0_d1;
|
||||
int spi0_cs0;
|
||||
int spi0_cs1;
|
||||
int ecap0_in_pwm0_out;
|
||||
int uart0_ctsn;
|
||||
int uart0_rtsn;
|
||||
int uart0_rxd;
|
||||
int uart0_txd;
|
||||
int uart1_ctsn;
|
||||
int uart1_rtsn;
|
||||
int uart1_rxd;
|
||||
int uart1_txd;
|
||||
int i2c0_sda;
|
||||
int i2c0_scl;
|
||||
int mcasp0_aclkx;
|
||||
int mcasp0_fsx;
|
||||
int mcasp0_axr0;
|
||||
int mcasp0_ahclkr;
|
||||
int mcasp0_aclkr;
|
||||
int mcasp0_fsr;
|
||||
int mcasp0_axr1;
|
||||
int mcasp0_ahclkx;
|
||||
int cam0_hd;
|
||||
int cam0_vd;
|
||||
int cam0_field;
|
||||
int cam0_wen;
|
||||
int cam0_pclk;
|
||||
int cam0_data8;
|
||||
int cam0_data9;
|
||||
int cam1_data9;
|
||||
int cam1_data8;
|
||||
int cam1_hd;
|
||||
int cam1_vd;
|
||||
int cam1_pclk;
|
||||
int cam1_field;
|
||||
int cam1_wen;
|
||||
int cam1_data0;
|
||||
int cam1_data1;
|
||||
int cam1_data2;
|
||||
int cam1_data3;
|
||||
int cam1_data4;
|
||||
int cam1_data5;
|
||||
int cam1_data6;
|
||||
int cam1_data7;
|
||||
int cam0_data0;
|
||||
int cam0_data1;
|
||||
int cam0_data2;
|
||||
int cam0_data3;
|
||||
int cam0_data4;
|
||||
int cam0_data5;
|
||||
int cam0_data6;
|
||||
int cam0_data7;
|
||||
int uart3_rxd;
|
||||
int uart3_txd;
|
||||
int uart3_ctsn;
|
||||
int uart3_rtsn;
|
||||
int gpio5_8;
|
||||
int gpio5_9;
|
||||
int gpio5_10;
|
||||
int gpio5_11;
|
||||
int gpio5_12;
|
||||
int gpio5_13;
|
||||
int spi4_sclk;
|
||||
int spi4_d0;
|
||||
int spi4_d1;
|
||||
int spi4_cs0;
|
||||
int spi2_sclk;
|
||||
int spi2_d0;
|
||||
int spi2_d1;
|
||||
int spi2_cs0;
|
||||
int xdma_evt_intr0;
|
||||
int xdma_evt_intr1;
|
||||
int clkreq;
|
||||
int nresetin_out;
|
||||
int rsvd1;
|
||||
int nnmi;
|
||||
int rsvd2;
|
||||
int rsvd3;
|
||||
int tms;
|
||||
int tdi;
|
||||
int tdo;
|
||||
int tck;
|
||||
int ntrst;
|
||||
int emu0;
|
||||
int emu1;
|
||||
int osc1_in;
|
||||
int osc1_out;
|
||||
int rtc_porz;
|
||||
int ext_wakeup0;
|
||||
int pmic_power_en0;
|
||||
int usb0_drvvbus;
|
||||
int usb1_drvvbus;
|
||||
};
|
||||
|
||||
#endif /* _MUX_AM43XX_H_ */
|
||||
@@ -0,0 +1,311 @@
|
||||
/*
|
||||
* mux_ti814x.h
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MUX_TI814X_H_
|
||||
#define _MUX_TI814X_H_
|
||||
|
||||
/* PAD Control Fields */
|
||||
#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */
|
||||
#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */
|
||||
#define PULLUDEN (0x0 << 16) /* Pull up enabled */
|
||||
#define PULLUDDIS (0x1 << 16) /* Pull up disabled */
|
||||
#define MODE(val) val /* used for Readability */
|
||||
|
||||
#define MUX_CFG(value, offset) \
|
||||
{ \
|
||||
int tmp; \
|
||||
tmp = __raw_readl(CTRL_BASE + offset); \
|
||||
tmp &= PINCNTL_RSV_MSK; \
|
||||
__raw_writel(tmp | value, (CTRL_BASE + offset));\
|
||||
}
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS
|
||||
* Field names corresponds to the pad signal name
|
||||
*/
|
||||
struct pad_signals {
|
||||
int pincntl1;
|
||||
int pincntl2;
|
||||
int pincntl3;
|
||||
int pincntl4;
|
||||
int pincntl5;
|
||||
int pincntl6;
|
||||
int pincntl7;
|
||||
int pincntl8;
|
||||
int pincntl9;
|
||||
int pincntl10;
|
||||
int pincntl11;
|
||||
int pincntl12;
|
||||
int pincntl13;
|
||||
int pincntl14;
|
||||
int pincntl15;
|
||||
int pincntl16;
|
||||
int pincntl17;
|
||||
int pincntl18;
|
||||
int pincntl19;
|
||||
int pincntl20;
|
||||
int pincntl21;
|
||||
int pincntl22;
|
||||
int pincntl23;
|
||||
int pincntl24;
|
||||
int pincntl25;
|
||||
int pincntl26;
|
||||
int pincntl27;
|
||||
int pincntl28;
|
||||
int pincntl29;
|
||||
int pincntl30;
|
||||
int pincntl31;
|
||||
int pincntl32;
|
||||
int pincntl33;
|
||||
int pincntl34;
|
||||
int pincntl35;
|
||||
int pincntl36;
|
||||
int pincntl37;
|
||||
int pincntl38;
|
||||
int pincntl39;
|
||||
int pincntl40;
|
||||
int pincntl41;
|
||||
int pincntl42;
|
||||
int pincntl43;
|
||||
int pincntl44;
|
||||
int pincntl45;
|
||||
int pincntl46;
|
||||
int pincntl47;
|
||||
int pincntl48;
|
||||
int pincntl49;
|
||||
int pincntl50;
|
||||
int pincntl51;
|
||||
int pincntl52;
|
||||
int pincntl53;
|
||||
int pincntl54;
|
||||
int pincntl55;
|
||||
int pincntl56;
|
||||
int pincntl57;
|
||||
int pincntl58;
|
||||
int pincntl59;
|
||||
int pincntl60;
|
||||
int pincntl61;
|
||||
int pincntl62;
|
||||
int pincntl63;
|
||||
int pincntl64;
|
||||
int pincntl65;
|
||||
int pincntl66;
|
||||
int pincntl67;
|
||||
int pincntl68;
|
||||
int pincntl69;
|
||||
int pincntl70;
|
||||
int pincntl71;
|
||||
int pincntl72;
|
||||
int pincntl73;
|
||||
int pincntl74;
|
||||
int pincntl75;
|
||||
int pincntl76;
|
||||
int pincntl77;
|
||||
int pincntl78;
|
||||
int pincntl79;
|
||||
int pincntl80;
|
||||
int pincntl81;
|
||||
int pincntl82;
|
||||
int pincntl83;
|
||||
int pincntl84;
|
||||
int pincntl85;
|
||||
int pincntl86;
|
||||
int pincntl87;
|
||||
int pincntl88;
|
||||
int pincntl89;
|
||||
int pincntl90;
|
||||
int pincntl91;
|
||||
int pincntl92;
|
||||
int pincntl93;
|
||||
int pincntl94;
|
||||
int pincntl95;
|
||||
int pincntl96;
|
||||
int pincntl97;
|
||||
int pincntl98;
|
||||
int pincntl99;
|
||||
int pincntl100;
|
||||
int pincntl101;
|
||||
int pincntl102;
|
||||
int pincntl103;
|
||||
int pincntl104;
|
||||
int pincntl105;
|
||||
int pincntl106;
|
||||
int pincntl107;
|
||||
int pincntl108;
|
||||
int pincntl109;
|
||||
int pincntl110;
|
||||
int pincntl111;
|
||||
int pincntl112;
|
||||
int pincntl113;
|
||||
int pincntl114;
|
||||
int pincntl115;
|
||||
int pincntl116;
|
||||
int pincntl117;
|
||||
int pincntl118;
|
||||
int pincntl119;
|
||||
int pincntl120;
|
||||
int pincntl121;
|
||||
int pincntl122;
|
||||
int pincntl123;
|
||||
int pincntl124;
|
||||
int pincntl125;
|
||||
int pincntl126;
|
||||
int pincntl127;
|
||||
int pincntl128;
|
||||
int pincntl129;
|
||||
int pincntl130;
|
||||
int pincntl131;
|
||||
int pincntl132;
|
||||
int pincntl133;
|
||||
int pincntl134;
|
||||
int pincntl135;
|
||||
int pincntl136;
|
||||
int pincntl137;
|
||||
int pincntl138;
|
||||
int pincntl139;
|
||||
int pincntl140;
|
||||
int pincntl141;
|
||||
int pincntl142;
|
||||
int pincntl143;
|
||||
int pincntl144;
|
||||
int pincntl145;
|
||||
int pincntl146;
|
||||
int pincntl147;
|
||||
int pincntl148;
|
||||
int pincntl149;
|
||||
int pincntl150;
|
||||
int pincntl151;
|
||||
int pincntl152;
|
||||
int pincntl153;
|
||||
int pincntl154;
|
||||
int pincntl155;
|
||||
int pincntl156;
|
||||
int pincntl157;
|
||||
int pincntl158;
|
||||
int pincntl159;
|
||||
int pincntl160;
|
||||
int pincntl161;
|
||||
int pincntl162;
|
||||
int pincntl163;
|
||||
int pincntl164;
|
||||
int pincntl165;
|
||||
int pincntl166;
|
||||
int pincntl167;
|
||||
int pincntl168;
|
||||
int pincntl169;
|
||||
int pincntl170;
|
||||
int pincntl171;
|
||||
int pincntl172;
|
||||
int pincntl173;
|
||||
int pincntl174;
|
||||
int pincntl175;
|
||||
int pincntl176;
|
||||
int pincntl177;
|
||||
int pincntl178;
|
||||
int pincntl179;
|
||||
int pincntl180;
|
||||
int pincntl181;
|
||||
int pincntl182;
|
||||
int pincntl183;
|
||||
int pincntl184;
|
||||
int pincntl185;
|
||||
int pincntl186;
|
||||
int pincntl187;
|
||||
int pincntl188;
|
||||
int pincntl189;
|
||||
int pincntl190;
|
||||
int pincntl191;
|
||||
int pincntl192;
|
||||
int pincntl193;
|
||||
int pincntl194;
|
||||
int pincntl195;
|
||||
int pincntl196;
|
||||
int pincntl197;
|
||||
int pincntl198;
|
||||
int pincntl199;
|
||||
int pincntl200;
|
||||
int pincntl201;
|
||||
int pincntl202;
|
||||
int pincntl203;
|
||||
int pincntl204;
|
||||
int pincntl205;
|
||||
int pincntl206;
|
||||
int pincntl207;
|
||||
int pincntl208;
|
||||
int pincntl209;
|
||||
int pincntl210;
|
||||
int pincntl211;
|
||||
int pincntl212;
|
||||
int pincntl213;
|
||||
int pincntl214;
|
||||
int pincntl215;
|
||||
int pincntl216;
|
||||
int pincntl217;
|
||||
int pincntl218;
|
||||
int pincntl219;
|
||||
int pincntl220;
|
||||
int pincntl221;
|
||||
int pincntl222;
|
||||
int pincntl223;
|
||||
int pincntl224;
|
||||
int pincntl225;
|
||||
int pincntl226;
|
||||
int pincntl227;
|
||||
int pincntl228;
|
||||
int pincntl229;
|
||||
int pincntl230;
|
||||
int pincntl231;
|
||||
int pincntl232;
|
||||
int pincntl233;
|
||||
int pincntl234;
|
||||
int pincntl235;
|
||||
int pincntl236;
|
||||
int pincntl237;
|
||||
int pincntl238;
|
||||
int pincntl239;
|
||||
int pincntl240;
|
||||
int pincntl241;
|
||||
int pincntl242;
|
||||
int pincntl243;
|
||||
int pincntl244;
|
||||
int pincntl245;
|
||||
int pincntl246;
|
||||
int pincntl247;
|
||||
int pincntl248;
|
||||
int pincntl249;
|
||||
int pincntl250;
|
||||
int pincntl251;
|
||||
int pincntl252;
|
||||
int pincntl253;
|
||||
int pincntl254;
|
||||
int pincntl255;
|
||||
int pincntl256;
|
||||
int pincntl257;
|
||||
int pincntl258;
|
||||
int pincntl259;
|
||||
int pincntl260;
|
||||
int pincntl261;
|
||||
int pincntl262;
|
||||
int pincntl263;
|
||||
int pincntl264;
|
||||
int pincntl265;
|
||||
int pincntl266;
|
||||
int pincntl267;
|
||||
int pincntl268;
|
||||
int pincntl269;
|
||||
int pincntl270;
|
||||
};
|
||||
|
||||
#endif /* endif _MUX_TI814X_H_ */
|
||||
@@ -0,0 +1,363 @@
|
||||
/*
|
||||
* mux_ti816x.h
|
||||
*
|
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
||||
* Antoine Tenart, <atenart@adeneo-embedded.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MUX_TI816X_H_
|
||||
#define _MUX_TI816X_H_
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define MUX_CFG(value, offset) \
|
||||
__raw_writel(value, (CTRL_BASE + offset));
|
||||
|
||||
#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
|
||||
#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
|
||||
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
|
||||
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
|
||||
#define MODE(val) (val) /* used for Readability */
|
||||
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS
|
||||
* Field names corresponds to the pad signal name
|
||||
*/
|
||||
struct pad_signals {
|
||||
int pincntl1;
|
||||
int pincntl2;
|
||||
int pincntl3;
|
||||
int pincntl4;
|
||||
int pincntl5;
|
||||
int pincntl6;
|
||||
int pincntl7;
|
||||
int pincntl8;
|
||||
int pincntl9;
|
||||
int pincntl10;
|
||||
int pincntl11;
|
||||
int pincntl12;
|
||||
int pincntl13;
|
||||
int pincntl14;
|
||||
int pincntl15;
|
||||
int pincntl16;
|
||||
int pincntl17;
|
||||
int pincntl18;
|
||||
int pincntl19;
|
||||
int pincntl20;
|
||||
int pincntl21;
|
||||
int pincntl22;
|
||||
int pincntl23;
|
||||
int pincntl24;
|
||||
int pincntl25;
|
||||
int pincntl26;
|
||||
int pincntl27;
|
||||
int pincntl28;
|
||||
int pincntl29;
|
||||
int pincntl30;
|
||||
int pincntl31;
|
||||
int pincntl32;
|
||||
int pincntl33;
|
||||
int pincntl34;
|
||||
int pincntl35;
|
||||
int pincntl36;
|
||||
int pincntl37;
|
||||
int pincntl38;
|
||||
int pincntl39;
|
||||
int pincntl40;
|
||||
int pincntl41;
|
||||
int pincntl42;
|
||||
int pincntl43;
|
||||
int pincntl44;
|
||||
int pincntl45;
|
||||
int pincntl46;
|
||||
int pincntl47;
|
||||
int pincntl48;
|
||||
int pincntl49;
|
||||
int pincntl50;
|
||||
int pincntl51;
|
||||
int pincntl52;
|
||||
int pincntl53;
|
||||
int pincntl54;
|
||||
int pincntl55;
|
||||
int pincntl56;
|
||||
int pincntl57;
|
||||
int pincntl58;
|
||||
int pincntl59;
|
||||
int pincntl60;
|
||||
int pincntl61;
|
||||
int pincntl62;
|
||||
int pincntl63;
|
||||
int pincntl64;
|
||||
int pincntl65;
|
||||
int pincntl66;
|
||||
int pincntl67;
|
||||
int pincntl68;
|
||||
int pincntl69;
|
||||
int pincntl70;
|
||||
int pincntl71;
|
||||
int pincntl72;
|
||||
int pincntl73;
|
||||
int pincntl74;
|
||||
int pincntl75;
|
||||
int pincntl76;
|
||||
int pincntl77;
|
||||
int pincntl78;
|
||||
int pincntl79;
|
||||
int pincntl80;
|
||||
int pincntl81;
|
||||
int pincntl82;
|
||||
int pincntl83;
|
||||
int pincntl84;
|
||||
int pincntl85;
|
||||
int pincntl86;
|
||||
int pincntl87;
|
||||
int pincntl88;
|
||||
int pincntl89;
|
||||
int pincntl90;
|
||||
int pincntl91;
|
||||
int pincntl92;
|
||||
int pincntl93;
|
||||
int pincntl94;
|
||||
int pincntl95;
|
||||
int pincntl96;
|
||||
int pincntl97;
|
||||
int pincntl98;
|
||||
int pincntl99;
|
||||
int pincntl100;
|
||||
int pincntl101;
|
||||
int pincntl102;
|
||||
int pincntl103;
|
||||
int pincntl104;
|
||||
int pincntl105;
|
||||
int pincntl106;
|
||||
int pincntl107;
|
||||
int pincntl108;
|
||||
int pincntl109;
|
||||
int pincntl110;
|
||||
int pincntl111;
|
||||
int pincntl112;
|
||||
int pincntl113;
|
||||
int pincntl114;
|
||||
int pincntl115;
|
||||
int pincntl116;
|
||||
int pincntl117;
|
||||
int pincntl118;
|
||||
int pincntl119;
|
||||
int pincntl120;
|
||||
int pincntl121;
|
||||
int pincntl122;
|
||||
int pincntl123;
|
||||
int pincntl124;
|
||||
int pincntl125;
|
||||
int pincntl126;
|
||||
int pincntl127;
|
||||
int pincntl128;
|
||||
int pincntl129;
|
||||
int pincntl130;
|
||||
int pincntl131;
|
||||
int pincntl132;
|
||||
int pincntl133;
|
||||
int pincntl134;
|
||||
int pincntl135;
|
||||
int pincntl136;
|
||||
int pincntl137;
|
||||
int pincntl138;
|
||||
int pincntl139;
|
||||
int pincntl140;
|
||||
int pincntl141;
|
||||
int pincntl142;
|
||||
int pincntl143;
|
||||
int pincntl144;
|
||||
int pincntl145;
|
||||
int pincntl146;
|
||||
int pincntl147;
|
||||
int pincntl148;
|
||||
int pincntl149;
|
||||
int pincntl150;
|
||||
int pincntl151;
|
||||
int pincntl152;
|
||||
int pincntl153;
|
||||
int pincntl154;
|
||||
int pincntl155;
|
||||
int pincntl156;
|
||||
int pincntl157;
|
||||
int pincntl158;
|
||||
int pincntl159;
|
||||
int pincntl160;
|
||||
int pincntl161;
|
||||
int pincntl162;
|
||||
int pincntl163;
|
||||
int pincntl164;
|
||||
int pincntl165;
|
||||
int pincntl166;
|
||||
int pincntl167;
|
||||
int pincntl168;
|
||||
int pincntl169;
|
||||
int pincntl170;
|
||||
int pincntl171;
|
||||
int pincntl172;
|
||||
int pincntl173;
|
||||
int pincntl174;
|
||||
int pincntl175;
|
||||
int pincntl176;
|
||||
int pincntl177;
|
||||
int pincntl178;
|
||||
int pincntl179;
|
||||
int pincntl180;
|
||||
int pincntl181;
|
||||
int pincntl182;
|
||||
int pincntl183;
|
||||
int pincntl184;
|
||||
int pincntl185;
|
||||
int pincntl186;
|
||||
int pincntl187;
|
||||
int pincntl188;
|
||||
int pincntl189;
|
||||
int pincntl190;
|
||||
int pincntl191;
|
||||
int pincntl192;
|
||||
int pincntl193;
|
||||
int pincntl194;
|
||||
int pincntl195;
|
||||
int pincntl196;
|
||||
int pincntl197;
|
||||
int pincntl198;
|
||||
int pincntl199;
|
||||
int pincntl200;
|
||||
int pincntl201;
|
||||
int pincntl202;
|
||||
int pincntl203;
|
||||
int pincntl204;
|
||||
int pincntl205;
|
||||
int pincntl206;
|
||||
int pincntl207;
|
||||
int pincntl208;
|
||||
int pincntl209;
|
||||
int pincntl210;
|
||||
int pincntl211;
|
||||
int pincntl212;
|
||||
int pincntl213;
|
||||
int pincntl214;
|
||||
int pincntl215;
|
||||
int pincntl216;
|
||||
int pincntl217;
|
||||
int pincntl218;
|
||||
int pincntl219;
|
||||
int pincntl220;
|
||||
int pincntl221;
|
||||
int pincntl222;
|
||||
int pincntl223;
|
||||
int pincntl224;
|
||||
int pincntl225;
|
||||
int pincntl226;
|
||||
int pincntl227;
|
||||
int pincntl228;
|
||||
int pincntl229;
|
||||
int pincntl230;
|
||||
int pincntl231;
|
||||
int pincntl232;
|
||||
int pincntl233;
|
||||
int pincntl234;
|
||||
int pincntl235;
|
||||
int pincntl236;
|
||||
int pincntl237;
|
||||
int pincntl238;
|
||||
int pincntl239;
|
||||
int pincntl240;
|
||||
int pincntl241;
|
||||
int pincntl242;
|
||||
int pincntl243;
|
||||
int pincntl244;
|
||||
int pincntl245;
|
||||
int pincntl246;
|
||||
int pincntl247;
|
||||
int pincntl248;
|
||||
int pincntl249;
|
||||
int pincntl250;
|
||||
int pincntl251;
|
||||
int pincntl252;
|
||||
int pincntl253;
|
||||
int pincntl254;
|
||||
int pincntl255;
|
||||
int pincntl256;
|
||||
int pincntl257;
|
||||
int pincntl258;
|
||||
int pincntl259;
|
||||
int pincntl260;
|
||||
int pincntl261;
|
||||
int pincntl262;
|
||||
int pincntl263;
|
||||
int pincntl264;
|
||||
int pincntl265;
|
||||
int pincntl266;
|
||||
int pincntl267;
|
||||
int pincntl268;
|
||||
int pincntl269;
|
||||
int pincntl270;
|
||||
int pincntl271;
|
||||
int pincntl272;
|
||||
int pincntl273;
|
||||
int pincntl274;
|
||||
int pincntl275;
|
||||
int pincntl276;
|
||||
int pincntl277;
|
||||
int pincntl278;
|
||||
int pincntl279;
|
||||
int pincntl280;
|
||||
int pincntl281;
|
||||
int pincntl282;
|
||||
int pincntl283;
|
||||
int pincntl284;
|
||||
int pincntl285;
|
||||
int pincntl286;
|
||||
int pincntl287;
|
||||
int pincntl288;
|
||||
int pincntl289;
|
||||
int pincntl290;
|
||||
int pincntl291;
|
||||
int pincntl292;
|
||||
int pincntl293;
|
||||
int pincntl294;
|
||||
int pincntl295;
|
||||
int pincntl296;
|
||||
int pincntl297;
|
||||
int pincntl298;
|
||||
int pincntl299;
|
||||
int pincntl300;
|
||||
int pincntl301;
|
||||
int pincntl302;
|
||||
int pincntl303;
|
||||
int pincntl304;
|
||||
int pincntl305;
|
||||
int pincntl306;
|
||||
int pincntl307;
|
||||
int pincntl308;
|
||||
int pincntl309;
|
||||
int pincntl310;
|
||||
int pincntl311;
|
||||
int pincntl312;
|
||||
int pincntl313;
|
||||
int pincntl314;
|
||||
int pincntl315;
|
||||
int pincntl316;
|
||||
int pincntl317;
|
||||
int pincntl318;
|
||||
int pincntl319;
|
||||
int pincntl320;
|
||||
int pincntl321;
|
||||
int pincntl322;
|
||||
int pincntl323;
|
||||
};
|
||||
|
||||
#endif /* endif _MUX_TI816X_H_ */
|
||||
@@ -0,0 +1,48 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* omap.h
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Author:
|
||||
* Chandan Nath <chandan.nath@ti.com>
|
||||
*
|
||||
* Derived from OMAP4 work by
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef _OMAP_H_
|
||||
#define _OMAP_H_
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#ifdef CONFIG_AM33XX
|
||||
#define NON_SECURE_SRAM_START 0x402F0400
|
||||
#define NON_SECURE_SRAM_END 0x40310000
|
||||
#define NON_SECURE_SRAM_IMG_END 0x4030B800
|
||||
#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
|
||||
#define NON_SECURE_SRAM_START 0x40300000
|
||||
#define NON_SECURE_SRAM_END 0x40320000
|
||||
#define NON_SECURE_SRAM_IMG_END 0x4031B800
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#define NON_SECURE_SRAM_START 0x402F0400
|
||||
#define NON_SECURE_SRAM_END 0x40340000
|
||||
#define NON_SECURE_SRAM_IMG_END 0x40337DE0
|
||||
#define QSPI_BASE 0x47900000
|
||||
#endif
|
||||
#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
|
||||
|
||||
/* Boot parameters */
|
||||
#ifndef __ASSEMBLY__
|
||||
struct omap_boot_parameters {
|
||||
unsigned int reserved;
|
||||
unsigned int boot_device_descriptor;
|
||||
unsigned char boot_device;
|
||||
unsigned char reset_reason;
|
||||
};
|
||||
|
||||
#define DEVICE_TYPE_SHIFT 0x8
|
||||
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,72 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_NONE 0x00
|
||||
#define BOOT_DEVICE_MMC2_2 0xFF
|
||||
|
||||
#if defined(CONFIG_TI814X)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x05
|
||||
#define BOOT_DEVICE_NAND_I2C 0x06
|
||||
#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */
|
||||
#define BOOT_DEVICE_MMC1 0x09
|
||||
#define BOOT_DEVICE_SPI 0x15
|
||||
#define BOOT_DEVICE_UART 0x41
|
||||
#define BOOT_DEVICE_USBETH 0x44
|
||||
#define BOOT_DEVICE_CPGMAC 0x46
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x03
|
||||
#define BOOT_DEVICE_ONENAND 0x04
|
||||
#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */
|
||||
#define BOOT_DEVICE_MMC1 0x06
|
||||
#define BOOT_DEVICE_UART 0x43
|
||||
#define BOOT_DEVICE_USB 0x45
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
|
||||
#elif defined(CONFIG_AM33XX)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x05
|
||||
#define BOOT_DEVICE_NAND_I2C 0x06
|
||||
#define BOOT_DEVICE_MMC1 0x08
|
||||
#define BOOT_DEVICE_MMC2 0x09
|
||||
#define BOOT_DEVICE_SPI 0x0B
|
||||
#define BOOT_DEVICE_UART 0x41
|
||||
#define BOOT_DEVICE_USBETH 0x44
|
||||
#define BOOT_DEVICE_CPGMAC 0x46
|
||||
#define BOOT_DEVICE_ONENAND 0xFF /* ROM does not support OneNAND. */
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#define BOOT_DEVICE_NOR 0x01
|
||||
#define BOOT_DEVICE_NAND 0x05
|
||||
#define BOOT_DEVICE_MMC1 0x07
|
||||
#define BOOT_DEVICE_MMC2 0x08
|
||||
#define BOOT_DEVICE_SPI 0x0A
|
||||
#define BOOT_DEVICE_USB 0x0D
|
||||
#define BOOT_DEVICE_UART 0x41
|
||||
#define BOOT_DEVICE_USBETH 0x45
|
||||
#define BOOT_DEVICE_CPGMAC 0x47
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
|
||||
#ifdef CONFIG_SPL_USB_STORAGE
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB
|
||||
#else
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,49 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* sys_proto.h
|
||||
*
|
||||
* System information header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
#include <linux/mtd/omap_gpmc.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
u32 get_cpu_rev(void);
|
||||
u32 get_sysboot_value(void);
|
||||
|
||||
extern struct ctrl_stat *cstat;
|
||||
u32 get_device_type(void);
|
||||
void save_omap_boot_params(void);
|
||||
void setup_early_clocks(void);
|
||||
void setup_clocks_for_console(void);
|
||||
void mpu_pll_config_val(int mpull_m);
|
||||
void ddr_pll_config(unsigned int ddrpll_M);
|
||||
|
||||
void sdelay(unsigned long);
|
||||
|
||||
void gpmc_init(void);
|
||||
void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base,
|
||||
u32 size);
|
||||
int omap_nand_switch_ecc(uint32_t, uint32_t);
|
||||
|
||||
void set_uart_mux_conf(void);
|
||||
void set_mux_conf_regs(void);
|
||||
void sdram_init(void);
|
||||
u32 wait_on_value(u32, u32, void *, u32);
|
||||
#ifdef CONFIG_NOR_BOOT
|
||||
void enable_norboot_pin_mux(void);
|
||||
#endif
|
||||
void am33xx_spl_board_init(void);
|
||||
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
|
||||
int am335x_get_mpu_vdd(int sil_rev, int frequency);
|
||||
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
|
||||
#endif
|
||||
|
||||
void enable_usb_clocks(int index);
|
||||
void disable_usb_clocks(int index);
|
||||
void do_board_detect(void);
|
||||
u32 get_sys_clk_index(void);
|
||||
@@ -0,0 +1,59 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
* Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_ARMADA100_H
|
||||
#define _ASM_ARCH_ARMADA100_H
|
||||
|
||||
#if defined (CONFIG_ARMADA100)
|
||||
|
||||
/* Common APB clock register bit definitions */
|
||||
#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
|
||||
#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
|
||||
#define APBC_RST (1<<2) /* Reset Generation */
|
||||
/* Functional Clock Selection Mask */
|
||||
#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
|
||||
|
||||
/* Fast Ethernet Controller Clock register definition */
|
||||
#define FE_CLK_RST 0x1
|
||||
#define FE_CLK_ENA 0x8
|
||||
|
||||
/* SSP2 Clock Control */
|
||||
#define SSP2_APBCLK 0x01
|
||||
#define SSP2_FNCLK 0x02
|
||||
|
||||
/* USB Clock/reset control bits */
|
||||
#define USB_SPH_AXICLK_EN 0x10
|
||||
#define USB_SPH_AXI_RST 0x02
|
||||
|
||||
/* MPMU Clocks */
|
||||
#define APB2_26M_EN (1 << 20)
|
||||
#define AP_26M (1 << 4)
|
||||
|
||||
/* Register Base Addresses */
|
||||
#define ARMD1_DRAM_BASE 0xB0000000
|
||||
#define ARMD1_FEC_BASE 0xC0800000
|
||||
#define ARMD1_TIMER_BASE 0xD4014000
|
||||
#define ARMD1_APBC1_BASE 0xD4015000
|
||||
#define ARMD1_APBC2_BASE 0xD4015800
|
||||
#define ARMD1_UART1_BASE 0xD4017000
|
||||
#define ARMD1_UART2_BASE 0xD4018000
|
||||
#define ARMD1_GPIO_BASE 0xD4019000
|
||||
#define ARMD1_SSP1_BASE 0xD401B000
|
||||
#define ARMD1_SSP2_BASE 0xD401C000
|
||||
#define ARMD1_MFPR_BASE 0xD401E000
|
||||
#define ARMD1_SSP3_BASE 0xD401F000
|
||||
#define ARMD1_SSP4_BASE 0xD4020000
|
||||
#define ARMD1_SSP5_BASE 0xD4021000
|
||||
#define ARMD1_UART3_BASE 0xD4026000
|
||||
#define ARMD1_MPMU_BASE 0xD4050000
|
||||
#define ARMD1_USB_HOST_BASE 0xD4209000
|
||||
#define ARMD1_APMU_BASE 0xD4282800
|
||||
#define ARMD1_CPU_BASE 0xD4282C00
|
||||
|
||||
#endif /* CONFIG_ARMADA100 */
|
||||
#endif /* _ASM_ARCH_ARMADA100_H */
|
||||
@@ -0,0 +1,27 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Lei Wen <leiwen@marvell.com>
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file should be included in board config header file.
|
||||
*
|
||||
* It supports common definitions for Armada100 platform
|
||||
*/
|
||||
|
||||
#ifndef _ARMD1_CONFIG_H
|
||||
#define _ARMD1_CONFIG_H
|
||||
|
||||
#include <asm/arch/armada100.h>
|
||||
|
||||
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
|
||||
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
|
||||
#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
|
||||
#define MV_MFPR_BASE ARMD1_MFPR_BASE
|
||||
#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
|
||||
#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
|
||||
represents UART Unit Enable */
|
||||
|
||||
#endif /* _ARMD1_CONFIG_H */
|
||||
@@ -0,0 +1,161 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef _ARMADA100CPU_H
|
||||
#define _ARMADA100CPU_H
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
/*
|
||||
* Main Power Management (MPMU) Registers
|
||||
* Refer Datasheet Appendix A.8
|
||||
*/
|
||||
struct armd1mpmu_registers {
|
||||
u8 pad0[0x08 - 0x00];
|
||||
u32 fccr; /*0x0008*/
|
||||
u32 pocr; /*0x000c*/
|
||||
u32 posr; /*0x0010*/
|
||||
u32 succr; /*0x0014*/
|
||||
u8 pad1[0x030 - 0x014 - 4];
|
||||
u32 gpcr; /*0x0030*/
|
||||
u8 pad2[0x200 - 0x030 - 4];
|
||||
u32 wdtpcr; /*0x0200*/
|
||||
u8 pad3[0x1000 - 0x200 - 4];
|
||||
u32 apcr; /*0x1000*/
|
||||
u32 apsr; /*0x1004*/
|
||||
u8 pad4[0x1020 - 0x1004 - 4];
|
||||
u32 aprr; /*0x1020*/
|
||||
u32 acgr; /*0x1024*/
|
||||
u32 arsr; /*0x1028*/
|
||||
};
|
||||
|
||||
/*
|
||||
* Application Subsystem Power Management
|
||||
* Refer Datasheet Appendix A.9
|
||||
*/
|
||||
struct armd1apmu_registers {
|
||||
u32 pcr; /* 0x000 */
|
||||
u32 ccr; /* 0x004 */
|
||||
u32 pad1;
|
||||
u32 ccsr; /* 0x00C */
|
||||
u32 fc_timer; /* 0x010 */
|
||||
u32 pad2;
|
||||
u32 ideal_cfg; /* 0x018 */
|
||||
u8 pad3[0x04C - 0x018 - 4];
|
||||
u32 lcdcrc; /* 0x04C */
|
||||
u32 cciccrc; /* 0x050 */
|
||||
u32 sd1crc; /* 0x054 */
|
||||
u32 sd2crc; /* 0x058 */
|
||||
u32 usbcrc; /* 0x05C */
|
||||
u32 nfccrc; /* 0x060 */
|
||||
u32 dmacrc; /* 0x064 */
|
||||
u32 pad4;
|
||||
u32 buscrc; /* 0x06C */
|
||||
u8 pad5[0x07C - 0x06C - 4];
|
||||
u32 wake_clr; /* 0x07C */
|
||||
u8 pad6[0x090 - 0x07C - 4];
|
||||
u32 core_status; /* 0x090 */
|
||||
u32 rfsc; /* 0x094 */
|
||||
u32 imr; /* 0x098 */
|
||||
u32 irwc; /* 0x09C */
|
||||
u32 isr; /* 0x0A0 */
|
||||
u8 pad7[0x0B0 - 0x0A0 - 4];
|
||||
u32 mhst; /* 0x0B0 */
|
||||
u32 msr; /* 0x0B4 */
|
||||
u8 pad8[0x0C0 - 0x0B4 - 4];
|
||||
u32 msst; /* 0x0C0 */
|
||||
u32 pllss; /* 0x0C4 */
|
||||
u32 smb; /* 0x0C8 */
|
||||
u32 gccrc; /* 0x0CC */
|
||||
u8 pad9[0x0D4 - 0x0CC - 4];
|
||||
u32 smccrc; /* 0x0D4 */
|
||||
u32 pad10;
|
||||
u32 xdcrc; /* 0x0DC */
|
||||
u32 sd3crc; /* 0x0E0 */
|
||||
u32 sd4crc; /* 0x0E4 */
|
||||
u8 pad11[0x0F0 - 0x0E4 - 4];
|
||||
u32 cfcrc; /* 0x0F0 */
|
||||
u32 mspcrc; /* 0x0F4 */
|
||||
u32 cmucrc; /* 0x0F8 */
|
||||
u32 fecrc; /* 0x0FC */
|
||||
u32 pciecrc; /* 0x100 */
|
||||
u32 epdcrc; /* 0x104 */
|
||||
};
|
||||
|
||||
/*
|
||||
* APB1 Clock Reset/Control Registers
|
||||
* Refer Datasheet Appendix A.10
|
||||
*/
|
||||
struct armd1apb1_registers {
|
||||
u32 uart1; /*0x000*/
|
||||
u32 uart2; /*0x004*/
|
||||
u32 gpio; /*0x008*/
|
||||
u32 pwm1; /*0x00c*/
|
||||
u32 pwm2; /*0x010*/
|
||||
u32 pwm3; /*0x014*/
|
||||
u32 pwm4; /*0x018*/
|
||||
u8 pad0[0x028 - 0x018 - 4];
|
||||
u32 rtc; /*0x028*/
|
||||
u32 twsi0; /*0x02c*/
|
||||
u32 kpc; /*0x030*/
|
||||
u32 timers; /*0x034*/
|
||||
u8 pad1[0x03c - 0x034 - 4];
|
||||
u32 aib; /*0x03c*/
|
||||
u32 sw_jtag; /*0x040*/
|
||||
u32 timer1; /*0x044*/
|
||||
u32 onewire; /*0x048*/
|
||||
u8 pad2[0x050 - 0x048 - 4];
|
||||
u32 asfar; /*0x050 AIB Secure First Access Reg*/
|
||||
u32 assar; /*0x054 AIB Secure Second Access Reg*/
|
||||
u8 pad3[0x06c - 0x054 - 4];
|
||||
u32 twsi1; /*0x06c*/
|
||||
u32 uart3; /*0x070*/
|
||||
u8 pad4[0x07c - 0x070 - 4];
|
||||
u32 timer2; /*0x07C*/
|
||||
u8 pad5[0x084 - 0x07c - 4];
|
||||
u32 ac97; /*0x084*/
|
||||
};
|
||||
|
||||
/*
|
||||
* APB2 Clock Reset/Control Registers
|
||||
* Refer Datasheet Appendix A.11
|
||||
*/
|
||||
struct armd1apb2_registers {
|
||||
u32 pad1[0x01C - 0x000];
|
||||
u32 ssp1_clkrst; /* 0x01C */
|
||||
u32 ssp2_clkrst; /* 0x020 */
|
||||
u32 pad2[0x04C - 0x020 - 4];
|
||||
u32 ssp3_clkrst; /* 0x04C */
|
||||
u32 pad3[0x058 - 0x04C - 4];
|
||||
u32 ssp4_clkrst; /* 0x058 */
|
||||
u32 ssp5_clkrst; /* 0x05C */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPU Interface Registers
|
||||
* Refer Datasheet Appendix A.2
|
||||
*/
|
||||
struct armd1cpu_registers {
|
||||
u32 chip_id; /* Chip Id Reg */
|
||||
u32 pad;
|
||||
u32 cpu_conf; /* CPU Conf Reg */
|
||||
u32 pad1;
|
||||
u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
|
||||
u32 pad2;
|
||||
u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
|
||||
u32 mcb_conf; /* MCB Conf Reg */
|
||||
u32 sys_boot_ctl; /* Sytem Boot Control */
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions
|
||||
*/
|
||||
u32 armd1_sdram_base(int);
|
||||
u32 armd1_sdram_size(int);
|
||||
|
||||
#endif /* _ARMADA100CPU_H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* eInfochips Ltd. <www.einfochips.com>
|
||||
* Written-by: Ajay Bhargav <contact@8051projects.net>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_GPIO_H
|
||||
#define _ASM_ARCH_GPIO_H
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/arch/armada100.h>
|
||||
|
||||
#define GPIO_HIGH 1
|
||||
#define GPIO_LOW 0
|
||||
|
||||
#define GPIO_TO_REG(gp) (gp >> 5)
|
||||
#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F))
|
||||
#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
|
||||
|
||||
static inline void *get_gpio_base(int bank)
|
||||
{
|
||||
const unsigned int offset[4] = {0, 4, 8, 0x100};
|
||||
/* gpio register bank offset - refer Appendix A.36 */
|
||||
return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
|
||||
}
|
||||
|
||||
#endif /* _ASM_ARCH_GPIO_H */
|
||||
@@ -0,0 +1,79 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
|
||||
* (C) Copyright 2007
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* 2007-08-21: eric miao <eric.miao@marvell.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
* Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef __ARMADA100_MFP_H
|
||||
#define __ARMADA100_MFP_H
|
||||
|
||||
/*
|
||||
* Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
|
||||
*
|
||||
* offset, pull,pF, drv,dF, edge,eF ,afn,aF
|
||||
*/
|
||||
/* UART1 */
|
||||
#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
|
||||
#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
|
||||
#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
|
||||
#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
|
||||
#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* UART2 */
|
||||
#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* UART3 */
|
||||
#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* I2c */
|
||||
#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* Fast Ethernet */
|
||||
#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* SPI */
|
||||
#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
|
||||
#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
|
||||
|
||||
/* More macros can be defined here... */
|
||||
|
||||
#define MFP_PIN_MAX 117
|
||||
|
||||
#endif /* __ARMADA100_MFP_H */
|
||||
@@ -0,0 +1,78 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* eInfochips Ltd. <www.einfochips.com>
|
||||
* Written-by: Ajay Bhargav <contact@8051projects.net>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef __ARMADA100_SPI_H_
|
||||
#define __ARMADA100_SPI_H_
|
||||
|
||||
#include <asm/arch/armada100.h>
|
||||
|
||||
#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
|
||||
#define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
|
||||
|
||||
/*
|
||||
* SSP Serial Port Registers
|
||||
* refer Appendix A.26
|
||||
*/
|
||||
struct ssp_reg {
|
||||
u32 sscr0; /* SSP Control Register 0 - 0x000 */
|
||||
u32 sscr1; /* SSP Control Register 1 - 0x004 */
|
||||
u32 sssr; /* SSP Status Register - 0x008 */
|
||||
u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
|
||||
u32 ssdr; /* SSP Data Register - 0x010 */
|
||||
u32 pad1[5];
|
||||
u32 ssto; /* SSP Timeout Register - 0x028 */
|
||||
u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
|
||||
u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
|
||||
u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
|
||||
u32 sstss; /* SSP Timeslot Status Register - 0x038 */
|
||||
};
|
||||
|
||||
#define DEFAULT_WORD_LEN 8
|
||||
#define SSP_FLUSH_NUM 0x2000
|
||||
#define RX_THRESH_DEF 8
|
||||
#define TX_THRESH_DEF 8
|
||||
#define TIMEOUT_DEF 1000
|
||||
|
||||
#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
|
||||
#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
|
||||
#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
|
||||
#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
|
||||
setting */
|
||||
#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
|
||||
#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
|
||||
#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
|
||||
#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
|
||||
|
||||
#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
|
||||
#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
|
||||
#define SSCR1_TINTE (1 << 19) /* Receiver Time-out
|
||||
Interrupt enable */
|
||||
|
||||
#define SSCR0_DSS 0x0f /* Data Size Select (mask) */
|
||||
#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
|
||||
#define SSCR0_FRF 0x30 /* FRame Format (mask) */
|
||||
#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
|
||||
Peripheral Interface */
|
||||
#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
|
||||
Serial Protocol (SSP) */
|
||||
#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
|
||||
#define SSCR0_ECS (1 << 6) /* External clock select */
|
||||
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
|
||||
Enable */
|
||||
|
||||
#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
|
||||
#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
|
||||
#define SSSR_BSY (1 << 4) /* SSP Busy */
|
||||
#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
|
||||
#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
|
||||
#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
|
||||
#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
|
||||
|
||||
#endif /* __ARMADA100_SPI_H_ */
|
||||
@@ -0,0 +1,62 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* eInfochips Ltd. <www.einfochips.com>
|
||||
* Written-by: Ajay Bhargav <contact@8051projects.net>
|
||||
*
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef __UTMI_ARMADA100__
|
||||
#define __UTMI_ARMADA100__
|
||||
|
||||
#define UTMI_PHY_BASE 0xD4206000
|
||||
|
||||
/* utmi_ctrl - bits */
|
||||
#define INPKT_DELAY_SOF (1 << 28)
|
||||
#define PLL_PWR_UP 2
|
||||
#define PHY_PWR_UP 1
|
||||
|
||||
/* utmi_pll - bits */
|
||||
#define PLL_FBDIV_MASK 0x00000FF0
|
||||
#define PLL_FBDIV 4
|
||||
#define PLL_REFDIV_MASK 0x0000000F
|
||||
#define PLL_REFDIV 0
|
||||
#define PLL_READY 0x800000
|
||||
#define VCOCAL_START (1 << 21)
|
||||
|
||||
#define N_DIVIDER 0xEE
|
||||
#define M_DIVIDER 0x0B
|
||||
|
||||
/* utmi_tx - bits */
|
||||
#define CK60_PHSEL 17
|
||||
#define PHSEL_VAL 0x4
|
||||
#define RCAL_START (1 << 12)
|
||||
|
||||
/*
|
||||
* USB PHY registers
|
||||
* Refer Datasheet Appendix A.21
|
||||
*/
|
||||
struct armd1usb_phy_reg {
|
||||
u32 utmi_rev; /* USB PHY Revision */
|
||||
u32 utmi_ctrl; /* USB PHY Control register */
|
||||
u32 utmi_pll; /* PLL register */
|
||||
u32 utmi_tx; /* Tx register */
|
||||
u32 utmi_rx; /* Rx register */
|
||||
u32 utmi_ivref; /* IVREF register */
|
||||
u32 utmi_tst_g0; /* Test group 0 register */
|
||||
u32 utmi_tst_g1; /* Test group 1 register */
|
||||
u32 utmi_tst_g2; /* Test group 2 register */
|
||||
u32 utmi_tst_g3; /* Test group 3 register */
|
||||
u32 utmi_tst_g4; /* Test group 4 register */
|
||||
u32 utmi_tst_g5; /* Test group 5 register */
|
||||
u32 utmi_reserve; /* Reserve Register */
|
||||
u32 utmi_usb_int; /* USB interuppt register */
|
||||
u32 utmi_dbg_ctl; /* Debug control register */
|
||||
u32 utmi_otg_addon; /* OTG addon register */
|
||||
};
|
||||
|
||||
int utmi_init(void);
|
||||
|
||||
#endif /* __UTMI_ARMADA100__ */
|
||||
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell International Ltd.
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef _CACHE_LLC_H_
|
||||
#define _CACHE_LLC_H_
|
||||
|
||||
/* Armada-7K/8K last level cache */
|
||||
|
||||
#define MVEBU_A8K_REGS_BASE_MSB 0xf000
|
||||
#define LLC_BASE_ADDR 0x8000
|
||||
#define LLC_CACHE_SYNC 0x700
|
||||
#define LLC_CACHE_SYNC_COMPLETE 0x730
|
||||
#define LLC_FLUSH_BY_WAY 0x7fc
|
||||
#define LLC_WAY_MASK 0xffffffff
|
||||
#define LLC_CACHE_SYNC_MASK 0x1
|
||||
|
||||
#endif /* _CACHE_LLC_H_ */
|
||||
@@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell International Ltd.
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef _SOC_INFO_H_
|
||||
#define _SOC_INFO_H_
|
||||
|
||||
/* Pin Ctrl driver definitions */
|
||||
#define BITS_PER_PIN 4
|
||||
#define PIN_FUNC_MASK ((1 << BITS_PER_PIN) - 1)
|
||||
#define PIN_REG_SHIFT 3
|
||||
#define PIN_FIELD_MASK ((1 << PIN_REG_SHIFT) - 1)
|
||||
|
||||
#endif /* _SOC_INFO_H_ */
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (C) 2013 - ARM Ltd
|
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
*
|
||||
* Based on code by Carl van Schaik <carl@ok-labs.com>.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _GENERICTIMER_H_
|
||||
#define _GENERICTIMER_H_
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* This macro provide a physical timer that can be used for delay in the code.
|
||||
* The macro is moved from sunxi/psci_sun7i.S
|
||||
*
|
||||
* reg: is used in this macro.
|
||||
* ticks: The freq is based on generic timer.
|
||||
*/
|
||||
.macro timer_wait reg, ticks
|
||||
movw \reg, #(\ticks & 0xffff)
|
||||
movt \reg, #(\ticks >> 16)
|
||||
mcr p15, 0, \reg, c14, c2, 0
|
||||
isb
|
||||
mov \reg, #3
|
||||
mcr p15, 0, \reg, c14, c2, 1
|
||||
1 : isb
|
||||
mrc p15, 0, \reg, c14, c2, 1
|
||||
ands \reg, \reg, #4
|
||||
bne 1b
|
||||
mov \reg, #0
|
||||
mcr p15, 0, \reg, c14, c2, 1
|
||||
isb
|
||||
.endm
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _GENERICTIMER_H_ */
|
||||
@@ -0,0 +1,19 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
* (C) Copyright 2012 Renesas Solutions Corp.
|
||||
*/
|
||||
#ifndef _GLOBALTIMER_H_
|
||||
#define _GLOBALTIMER_H_
|
||||
|
||||
struct globaltimer {
|
||||
u32 cnt_l; /* 0x00 */
|
||||
u32 cnt_h;
|
||||
u32 ctl;
|
||||
u32 stat;
|
||||
u32 cmp_l; /* 0x10 */
|
||||
u32 cmp_h;
|
||||
u32 inc;
|
||||
};
|
||||
|
||||
#endif /* _GLOBALTIMER_H_ */
|
||||
@@ -0,0 +1,53 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2010 Linaro
|
||||
* Matt Waddel, <matt.waddel@linaro.org>
|
||||
*/
|
||||
#ifndef _SYSCTRL_H_
|
||||
#define _SYSCTRL_H_
|
||||
|
||||
/* System controller (SP810) register definitions */
|
||||
#define SP810_TIMER0_ENSEL (1 << 15)
|
||||
#define SP810_TIMER1_ENSEL (1 << 17)
|
||||
#define SP810_TIMER2_ENSEL (1 << 19)
|
||||
#define SP810_TIMER3_ENSEL (1 << 21)
|
||||
|
||||
struct sysctrl {
|
||||
u32 scctrl; /* 0x000 */
|
||||
u32 scsysstat;
|
||||
u32 scimctrl;
|
||||
u32 scimstat;
|
||||
u32 scxtalctrl;
|
||||
u32 scpllctrl;
|
||||
u32 scpllfctrl;
|
||||
u32 scperctrl0;
|
||||
u32 scperctrl1;
|
||||
u32 scperen;
|
||||
u32 scperdis;
|
||||
u32 scperclken;
|
||||
u32 scperstat;
|
||||
u32 res1[0x006];
|
||||
u32 scflashctrl; /* 0x04c */
|
||||
u32 res2[0x3a4];
|
||||
u32 scsysid0; /* 0xee0 */
|
||||
u32 scsysid1;
|
||||
u32 scsysid2;
|
||||
u32 scsysid3;
|
||||
u32 scitcr;
|
||||
u32 scitir0;
|
||||
u32 scitir1;
|
||||
u32 scitor;
|
||||
u32 sccntctrl;
|
||||
u32 sccntdata;
|
||||
u32 sccntstep;
|
||||
u32 res3[0x32];
|
||||
u32 scperiphid0; /* 0xfe0 */
|
||||
u32 scperiphid1;
|
||||
u32 scperiphid2;
|
||||
u32 scperiphid3;
|
||||
u32 scpcellid0;
|
||||
u32 scpcellid1;
|
||||
u32 scpcellid2;
|
||||
u32 scpcellid3;
|
||||
};
|
||||
#endif /* _SYSCTRL_H_ */
|
||||
@@ -0,0 +1,35 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2010 Linaro
|
||||
* Matt Waddel, <matt.waddel@linaro.org>
|
||||
*/
|
||||
#ifndef _SYSTIMER_H_
|
||||
#define _SYSTIMER_H_
|
||||
|
||||
/* AMBA timer register base address */
|
||||
#define SYSTIMER_BASE 0x10011000
|
||||
|
||||
#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */
|
||||
#define SYSTIMER_RELOAD 0xFFFFFFFF
|
||||
#define SYSTIMER_EN (1 << 7)
|
||||
#define SYSTIMER_32BIT (1 << 1)
|
||||
#define SYSTIMER_PRESC_16 (1 << 2)
|
||||
#define SYSTIMER_PRESC_256 (1 << 3)
|
||||
|
||||
struct systimer {
|
||||
u32 timer0load; /* 0x00 */
|
||||
u32 timer0value;
|
||||
u32 timer0control;
|
||||
u32 timer0intclr;
|
||||
u32 timer0ris;
|
||||
u32 timer0mis;
|
||||
u32 timer0bgload;
|
||||
u32 timer1load; /* 0x20 */
|
||||
u32 timer1value;
|
||||
u32 timer1control;
|
||||
u32 timer1intclr;
|
||||
u32 timer1ris;
|
||||
u32 timer1mis;
|
||||
u32 timer1bgload;
|
||||
};
|
||||
#endif /* _SYSTIMER_H_ */
|
||||
@@ -0,0 +1,38 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Matt Waddel, <matt.waddel@linaro.org>
|
||||
*/
|
||||
#ifndef _WDT_H_
|
||||
#define _WDT_H_
|
||||
|
||||
/* Watchdog timer (SP805) register base address */
|
||||
#define WDT_BASE 0x100E5000
|
||||
|
||||
#define WDT_EN 0x2
|
||||
#define WDT_RESET_LOAD 0x0
|
||||
|
||||
struct wdt {
|
||||
u32 wdogload; /* 0x000 */
|
||||
u32 wdogvalue;
|
||||
u32 wdogcontrol;
|
||||
u32 wdogintclr;
|
||||
u32 wdogris;
|
||||
u32 wdogmis;
|
||||
u32 res1[0x2F9];
|
||||
u32 wdoglock; /* 0xC00 */
|
||||
u32 res2[0xBE];
|
||||
u32 wdogitcr; /* 0xF00 */
|
||||
u32 wdogitop;
|
||||
u32 res3[0x35];
|
||||
u32 wdogperiphid0; /* 0xFE0 */
|
||||
u32 wdogperiphid1;
|
||||
u32 wdogperiphid2;
|
||||
u32 wdogperiphid3;
|
||||
u32 wdogpcellid0;
|
||||
u32 wdogpcellid1;
|
||||
u32 wdogpcellid2;
|
||||
u32 wdogpcellid3;
|
||||
};
|
||||
|
||||
#endif /* _WDT_H_ */
|
||||
@@ -0,0 +1,51 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2017 Google, Inc
|
||||
*/
|
||||
#ifndef _ASM_ARCH_PERIPH_H
|
||||
#define _ASM_ARCH_PERIPH_H
|
||||
|
||||
/*
|
||||
* Peripherals supported by the hardware.
|
||||
* These are used to specify pinctrl settings.
|
||||
*/
|
||||
|
||||
enum periph_id {
|
||||
PERIPH_ID_UART1,
|
||||
PERIPH_ID_UART2,
|
||||
PERIPH_ID_UART3,
|
||||
PERIPH_ID_UART4,
|
||||
PERIPH_ID_LPC,
|
||||
PERIPH_ID_PWM0,
|
||||
PERIPH_ID_PWM1,
|
||||
PERIPH_ID_PWM2,
|
||||
PERIPH_ID_PWM3,
|
||||
PERIPH_ID_PWM4,
|
||||
PERIPH_ID_PWM5,
|
||||
PERIPH_ID_PWM6,
|
||||
PERIPH_ID_PWM7,
|
||||
PERIPH_ID_PWM8,
|
||||
PERIPH_ID_MAC1,
|
||||
PERIPH_ID_MAC2,
|
||||
PERIPH_ID_VIDEO,
|
||||
PERIPH_ID_SPI1,
|
||||
PERIPH_ID_SPI2,
|
||||
PERIPH_ID_I2C1,
|
||||
PERIPH_ID_I2C2,
|
||||
PERIPH_ID_I2C3,
|
||||
PERIPH_ID_I2C4,
|
||||
PERIPH_ID_I2C5,
|
||||
PERIPH_ID_I2C6,
|
||||
PERIPH_ID_I2C7,
|
||||
PERIPH_ID_I2C8,
|
||||
PERIPH_ID_I2C9,
|
||||
PERIPH_ID_I2C10,
|
||||
PERIPH_ID_I2C11,
|
||||
PERIPH_ID_I2C12,
|
||||
PERIPH_ID_I2C13,
|
||||
PERIPH_ID_I2C14,
|
||||
PERIPH_ID_SD1,
|
||||
PERIPH_ID_SD2,
|
||||
};
|
||||
|
||||
#endif /* _ASM_ARCH_SCU_AST2500_H */
|
||||
@@ -0,0 +1,247 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2016 Google, Inc
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SCU_AST2500_H
|
||||
#define _ASM_ARCH_SCU_AST2500_H
|
||||
|
||||
#define SCU_UNLOCK_VALUE 0x1688a8a8
|
||||
|
||||
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
|
||||
#define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT)
|
||||
#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
|
||||
#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
|
||||
#define SCU_HWSTRAP_DDR4 (1 << 24)
|
||||
#define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23)
|
||||
|
||||
#define SCU_MPLL_DENUM_SHIFT 0
|
||||
#define SCU_MPLL_DENUM_MASK 0x1f
|
||||
#define SCU_MPLL_NUM_SHIFT 5
|
||||
#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
|
||||
#define SCU_MPLL_POST_SHIFT 13
|
||||
#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
|
||||
#define SCU_PCLK_DIV_SHIFT 23
|
||||
#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
|
||||
#define SCU_SDCLK_DIV_SHIFT 12
|
||||
#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT)
|
||||
#define SCU_HPLL_DENUM_SHIFT 0
|
||||
#define SCU_HPLL_DENUM_MASK 0x1f
|
||||
#define SCU_HPLL_NUM_SHIFT 5
|
||||
#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
|
||||
#define SCU_HPLL_POST_SHIFT 13
|
||||
#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
|
||||
|
||||
#define SCU_MACCLK_SHIFT 16
|
||||
#define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT)
|
||||
|
||||
#define SCU_MISC2_RGMII_HPLL (1 << 23)
|
||||
#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20
|
||||
#define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
|
||||
#define SCU_MISC2_RMII_MPLL (1 << 19)
|
||||
#define SCU_MISC2_RMII_CLKDIV_SHIFT 16
|
||||
#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
|
||||
#define SCU_MISC2_UARTCLK_SHIFT 24
|
||||
|
||||
#define SCU_MISC_D2PLL_OFF (1 << 4)
|
||||
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
|
||||
#define SCU_MISC_GCRT_USB20CLK (1 << 21)
|
||||
|
||||
#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0
|
||||
#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\
|
||||
<< SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
|
||||
#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6
|
||||
#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\
|
||||
<< SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
|
||||
#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12
|
||||
#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
|
||||
#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18
|
||||
#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
|
||||
#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24)
|
||||
#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25)
|
||||
#define SCU_MICDS_RMII1_RCLKEN (1 << 29)
|
||||
#define SCU_MICDS_RMII2_RCLKEN (1 << 30)
|
||||
#define SCU_MICDS_RGMIIPLL (1 << 31)
|
||||
|
||||
/*
|
||||
* SYSRESET is actually more like a Power register,
|
||||
* except that corresponding bit set to 1 means that
|
||||
* the peripheral is off.
|
||||
*/
|
||||
#define SCU_SYSRESET_XDMA (1 << 25)
|
||||
#define SCU_SYSRESET_MCTP (1 << 24)
|
||||
#define SCU_SYSRESET_ADC (1 << 23)
|
||||
#define SCU_SYSRESET_JTAG (1 << 22)
|
||||
#define SCU_SYSRESET_MIC (1 << 18)
|
||||
#define SCU_SYSRESET_SDIO (1 << 16)
|
||||
#define SCU_SYSRESET_USB11HOST (1 << 15)
|
||||
#define SCU_SYSRESET_USBHUB (1 << 14)
|
||||
#define SCU_SYSRESET_CRT (1 << 13)
|
||||
#define SCU_SYSRESET_MAC2 (1 << 12)
|
||||
#define SCU_SYSRESET_MAC1 (1 << 11)
|
||||
#define SCU_SYSRESET_PECI (1 << 10)
|
||||
#define SCU_SYSRESET_PWM (1 << 9)
|
||||
#define SCU_SYSRESET_PCI_VGA (1 << 8)
|
||||
#define SCU_SYSRESET_2D (1 << 7)
|
||||
#define SCU_SYSRESET_VIDEO (1 << 6)
|
||||
#define SCU_SYSRESET_LPC (1 << 5)
|
||||
#define SCU_SYSRESET_HAC (1 << 4)
|
||||
#define SCU_SYSRESET_USBHID (1 << 3)
|
||||
#define SCU_SYSRESET_I2C (1 << 2)
|
||||
#define SCU_SYSRESET_AHB (1 << 1)
|
||||
#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
|
||||
|
||||
/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
|
||||
#define SCU_PINMUX_CTRL5_I2C (1 << 16)
|
||||
|
||||
/*
|
||||
* The values are grouped by function, not by register.
|
||||
* They are actually scattered across multiple loosely related registers.
|
||||
*/
|
||||
#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
|
||||
#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
|
||||
#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
|
||||
#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
|
||||
#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
|
||||
#define SCU_PIN_FUN_SCL1 (1 << 12)
|
||||
#define SCU_PIN_FUN_SCL2 (1 << 14)
|
||||
#define SCU_PIN_FUN_SDA1 (1 << 13)
|
||||
#define SCU_PIN_FUN_SDA2 (1 << 15)
|
||||
|
||||
#define SCU_CLKSTOP_MAC1 (1 << 20)
|
||||
#define SCU_CLKSTOP_MAC2 (1 << 21)
|
||||
#define SCU_CLKSTOP_SDCLK (1 << 27)
|
||||
|
||||
#define SCU_D2PLL_EXT1_OFF (1 << 0)
|
||||
#define SCU_D2PLL_EXT1_BYPASS (1 << 1)
|
||||
#define SCU_D2PLL_EXT1_RESET (1 << 2)
|
||||
#define SCU_D2PLL_EXT1_MODE_SHIFT 3
|
||||
#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT)
|
||||
#define SCU_D2PLL_EXT1_PARAM_SHIFT 5
|
||||
#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
|
||||
|
||||
#define SCU_D2PLL_NUM_SHIFT 0
|
||||
#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT)
|
||||
#define SCU_D2PLL_DENUM_SHIFT 8
|
||||
#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT)
|
||||
#define SCU_D2PLL_POST_SHIFT 13
|
||||
#define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT)
|
||||
#define SCU_D2PLL_ODIV_SHIFT 19
|
||||
#define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT)
|
||||
#define SCU_D2PLL_SIC_SHIFT 22
|
||||
#define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT)
|
||||
#define SCU_D2PLL_SIP_SHIFT 27
|
||||
#define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT)
|
||||
|
||||
#define SCU_CLKDUTY_DCLK_SHIFT 0
|
||||
#define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT)
|
||||
#define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8
|
||||
#define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT)
|
||||
#define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16
|
||||
#define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct ast2500_clk_priv {
|
||||
struct ast2500_scu *scu;
|
||||
};
|
||||
|
||||
struct ast2500_scu {
|
||||
u32 protection_key;
|
||||
u32 sysreset_ctrl1;
|
||||
u32 clk_sel1;
|
||||
u32 clk_stop_ctrl1;
|
||||
u32 freq_counter_ctrl;
|
||||
u32 freq_counter_cmp;
|
||||
u32 intr_ctrl;
|
||||
u32 d2_pll_param;
|
||||
u32 m_pll_param;
|
||||
u32 h_pll_param;
|
||||
u32 d_pll_param;
|
||||
u32 misc_ctrl1;
|
||||
u32 pci_config[3];
|
||||
u32 sysreset_status;
|
||||
u32 vga_handshake[2];
|
||||
u32 mac_clk_delay;
|
||||
u32 misc_ctrl2;
|
||||
u32 vga_scratch[8];
|
||||
u32 hwstrap;
|
||||
u32 rng_ctrl;
|
||||
u32 rng_data;
|
||||
u32 rev_id;
|
||||
u32 pinmux_ctrl[6];
|
||||
u32 reserved0;
|
||||
u32 extrst_sel;
|
||||
u32 pinmux_ctrl1[4];
|
||||
u32 reserved1[2];
|
||||
u32 mac_clk_delay_100M;
|
||||
u32 mac_clk_delay_10M;
|
||||
u32 wakeup_enable;
|
||||
u32 wakeup_control;
|
||||
u32 reserved2[3];
|
||||
u32 sysreset_ctrl2;
|
||||
u32 clk_sel2;
|
||||
u32 clk_stop_ctrl2;
|
||||
u32 freerun_counter;
|
||||
u32 freerun_counter_ext;
|
||||
u32 clk_duty_meas_ctrl;
|
||||
u32 clk_duty_meas_res;
|
||||
u32 reserved3[4];
|
||||
/* The next registers are not key-protected */
|
||||
struct ast2500_cpu2 {
|
||||
u32 ctrl;
|
||||
u32 base_addr[9];
|
||||
u32 cache_ctrl;
|
||||
} cpu2;
|
||||
u32 reserved4;
|
||||
u32 d_pll_ext_param[3];
|
||||
u32 d2_pll_ext_param[3];
|
||||
u32 mh_pll_ext_param;
|
||||
u32 reserved5;
|
||||
u32 chip_id[2];
|
||||
u32 reserved6[2];
|
||||
u32 uart_clk_ctrl;
|
||||
u32 reserved7[7];
|
||||
u32 pcie_config;
|
||||
u32 mmio_decode;
|
||||
u32 reloc_ctrl_decode[2];
|
||||
u32 mailbox_addr;
|
||||
u32 shared_sram_decode[2];
|
||||
u32 bmc_rev_id;
|
||||
u32 reserved8;
|
||||
u32 bmc_device_id;
|
||||
u32 reserved9[13];
|
||||
u32 clk_duty_sel;
|
||||
};
|
||||
|
||||
/**
|
||||
* ast_get_clk() - get a pointer to Clock Driver
|
||||
*
|
||||
* @devp, OUT - pointer to Clock Driver
|
||||
* @return zero on success, error code (< 0) otherwise.
|
||||
*/
|
||||
int ast_get_clk(struct udevice **devp);
|
||||
|
||||
/**
|
||||
* ast_get_scu() - get a pointer to SCU registers
|
||||
*
|
||||
* @return pointer to struct ast2500_scu on success, ERR_PTR otherwise
|
||||
*/
|
||||
void *ast_get_scu(void);
|
||||
|
||||
/**
|
||||
* ast_scu_unlock() - unlock protected registers
|
||||
*
|
||||
* @scu, pointer to ast2500_scu
|
||||
*/
|
||||
void ast_scu_unlock(struct ast2500_scu *scu);
|
||||
|
||||
/**
|
||||
* ast_scu_lock() - lock protected registers
|
||||
*
|
||||
* @scu, pointer to ast2500_scu
|
||||
*/
|
||||
void ast_scu_lock(struct ast2500_scu *scu);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_ARCH_SCU_AST2500_H */
|
||||
@@ -0,0 +1,137 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2016 Google, Inc
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SDRAM_AST2500_H
|
||||
#define _ASM_ARCH_SDRAM_AST2500_H
|
||||
|
||||
#define SDRAM_UNLOCK_KEY 0xfc600309
|
||||
#define SDRAM_VIDEO_UNLOCK_KEY 0x2003000f
|
||||
|
||||
#define SDRAM_PCR_CKE_EN (1 << 0)
|
||||
#define SDRAM_PCR_AUTOPWRDN_EN (1 << 1)
|
||||
#define SDRAM_PCR_CKE_DELAY_SHIFT 4
|
||||
#define SDRAM_PCR_CKE_DELAY_MASK 7
|
||||
#define SDRAM_PCR_RESETN_DIS (1 << 7)
|
||||
#define SDRAM_PCR_ODT_EN (1 << 8)
|
||||
#define SDRAM_PCR_ODT_AUTO_ON (1 << 10)
|
||||
#define SDRAM_PCR_ODT_EXT_EN (1 << 11)
|
||||
#define SDRAM_PCR_TCKE_PW_SHIFT 12
|
||||
#define SDRAM_PCR_TCKE_PW_MASK 7
|
||||
#define SDRAM_PCR_RGAP_CTRL_EN (1 << 15)
|
||||
#define SDRAM_PCR_MREQI_DIS (1 << 17)
|
||||
|
||||
/* Fixed priority DRAM Requests mask */
|
||||
#define SDRAM_REQ_VGA_HW_CURSOR (1 << 0)
|
||||
#define SDRAM_REQ_VGA_TEXT_CG_FONT (1 << 1)
|
||||
#define SDRAM_REQ_VGA_TEXT_ASCII (1 << 2)
|
||||
#define SDRAM_REQ_VGA_CRT (1 << 3)
|
||||
#define SDRAM_REQ_SOC_DC_CURSOR (1 << 4)
|
||||
#define SDRAM_REQ_SOC_DC_OCD (1 << 5)
|
||||
#define SDRAM_REQ_SOC_DC_CRT (1 << 6)
|
||||
#define SDRAM_REQ_VIDEO_HIPRI_WRITE (1 << 7)
|
||||
#define SDRAM_REQ_USB20_EHCI1 (1 << 8)
|
||||
#define SDRAM_REQ_USB20_EHCI2 (1 << 9)
|
||||
#define SDRAM_REQ_CPU (1 << 10)
|
||||
#define SDRAM_REQ_AHB2 (1 << 11)
|
||||
#define SDRAM_REQ_AHB (1 << 12)
|
||||
#define SDRAM_REQ_MAC0 (1 << 13)
|
||||
#define SDRAM_REQ_MAC1 (1 << 14)
|
||||
#define SDRAM_REQ_PCIE (1 << 16)
|
||||
#define SDRAM_REQ_XDMA (1 << 17)
|
||||
#define SDRAM_REQ_ENCRYPTION (1 << 18)
|
||||
#define SDRAM_REQ_VIDEO_FLAG (1 << 21)
|
||||
#define SDRAM_REQ_VIDEO_LOW_PRI_WRITE (1 << 28)
|
||||
#define SDRAM_REQ_2D_RW (1 << 29)
|
||||
#define SDRAM_REQ_MEMCHECK (1 << 30)
|
||||
|
||||
#define SDRAM_ICR_RESET_ALL (1 << 31)
|
||||
|
||||
#define SDRAM_CONF_CAP_SHIFT 0
|
||||
#define SDRAM_CONF_CAP_MASK 3
|
||||
#define SDRAM_CONF_DDR4 (1 << 4)
|
||||
#define SDRAM_CONF_SCRAMBLE (1 << 8)
|
||||
#define SDRAM_CONF_SCRAMBLE_PAT2 (1 << 9)
|
||||
#define SDRAM_CONF_CACHE_EN (1 << 10)
|
||||
#define SDRAM_CONF_CACHE_INIT_EN (1 << 12)
|
||||
#define SDRAM_CONF_DUALX8 (1 << 13)
|
||||
#define SDRAM_CONF_CACHE_INIT_DONE (1 << 19)
|
||||
|
||||
#define SDRAM_CONF_CAP_128M 0
|
||||
#define SDRAM_CONF_CAP_256M 1
|
||||
#define SDRAM_CONF_CAP_512M 2
|
||||
#define SDRAM_CONF_CAP_1024M 3
|
||||
|
||||
#define SDRAM_MISC_DDR4_TREFRESH (1 << 3)
|
||||
|
||||
#define SDRAM_PHYCTRL0_INIT (1 << 0)
|
||||
#define SDRAM_PHYCTRL0_AUTO_UPDATE (1 << 1)
|
||||
#define SDRAM_PHYCTRL0_NRST (1 << 2)
|
||||
|
||||
#define SDRAM_REFRESH_CYCLES_SHIFT 0
|
||||
#define SDRAM_REFRESH_CYCLES_MASK 0xf
|
||||
#define SDRAM_REFRESH_ZQCS_EN (1 << 7)
|
||||
#define SDRAM_REFRESH_PERIOD_SHIFT 8
|
||||
#define SDRAM_REFRESH_PERIOD_MASK 0xf
|
||||
|
||||
#define SDRAM_TEST_LEN_SHIFT 4
|
||||
#define SDRAM_TEST_LEN_MASK 0xfffff
|
||||
#define SDRAM_TEST_START_ADDR_SHIFT 24
|
||||
#define SDRAM_TEST_START_ADDR_MASK 0x3f
|
||||
|
||||
#define SDRAM_TEST_EN (1 << 0)
|
||||
#define SDRAM_TEST_MODE_SHIFT 1
|
||||
#define SDRAM_TEST_MODE_MASK 3
|
||||
#define SDRAM_TEST_MODE_WO 0
|
||||
#define SDRAM_TEST_MODE_RB 1
|
||||
#define SDRAM_TEST_MODE_RW 2
|
||||
#define SDRAM_TEST_GEN_MODE_SHIFT 3
|
||||
#define SDRAM_TEST_GEN_MODE_MASK 7
|
||||
#define SDRAM_TEST_TWO_MODES (1 << 6)
|
||||
#define SDRAM_TEST_ERRSTOP (1 << 7)
|
||||
#define SDRAM_TEST_DONE (1 << 12)
|
||||
#define SDRAM_TEST_FAIL (1 << 13)
|
||||
|
||||
#define SDRAM_AC_TRFC_SHIFT 0
|
||||
#define SDRAM_AC_TRFC_MASK 0xff
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct ast2500_sdrammc_regs {
|
||||
u32 protection_key;
|
||||
u32 config;
|
||||
u32 gm_protection_key;
|
||||
u32 refresh_timing;
|
||||
u32 ac_timing[3];
|
||||
u32 misc_control;
|
||||
u32 mr46_mode_setting;
|
||||
u32 mr5_mode_setting;
|
||||
u32 mode_setting_control;
|
||||
u32 mr02_mode_setting;
|
||||
u32 mr13_mode_setting;
|
||||
u32 power_control;
|
||||
u32 req_limit_mask;
|
||||
u32 pri_group_setting;
|
||||
u32 max_grant_len[4];
|
||||
u32 intr_ctrl;
|
||||
u32 ecc_range_ctrl;
|
||||
u32 first_ecc_err_addr;
|
||||
u32 last_ecc_err_addr;
|
||||
u32 phy_ctrl[4];
|
||||
u32 ecc_test_ctrl;
|
||||
u32 test_addr;
|
||||
u32 test_fail_dq_bit;
|
||||
u32 test_init_val;
|
||||
u32 phy_debug_ctrl;
|
||||
u32 phy_debug_data;
|
||||
u32 reserved1[30];
|
||||
u32 scu_passwd;
|
||||
u32 reserved2[7];
|
||||
u32 scu_mpll;
|
||||
u32 reserved3[19];
|
||||
u32 scu_hwstrap;
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_ARCH_SDRAM_AST2500_H */
|
||||
@@ -0,0 +1,53 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2016 Google, Inc
|
||||
*/
|
||||
#ifndef _ASM_ARCH_TIMER_H
|
||||
#define _ASM_ARCH_TIMER_H
|
||||
|
||||
/* Each timer has 4 control bits in ctrl1 register.
|
||||
* Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
|
||||
* such that timer X uses bits (4 * X - 4):(4 * X - 1)
|
||||
* If the timer does not support PWM, bit 4 is reserved.
|
||||
*/
|
||||
#define AST_TMC_EN (1 << 0)
|
||||
#define AST_TMC_1MHZ (1 << 1)
|
||||
#define AST_TMC_OVFINTR (1 << 2)
|
||||
#define AST_TMC_PWM (1 << 3)
|
||||
|
||||
/* Timers are counted from 1 in the datasheet. */
|
||||
#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
|
||||
|
||||
#define AST_TMC_RATE (1000*1000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* All timers share control registers, which makes it harder to make them
|
||||
* separate devices. Since only one timer is needed at the moment, making
|
||||
* it this just one device.
|
||||
*/
|
||||
|
||||
struct ast_timer_counter {
|
||||
u32 status;
|
||||
u32 reload_val;
|
||||
u32 match1;
|
||||
u32 match2;
|
||||
};
|
||||
|
||||
struct ast_timer {
|
||||
struct ast_timer_counter timers1[3];
|
||||
u32 ctrl1;
|
||||
u32 ctrl2;
|
||||
#ifdef CONFIG_ASPEED_AST2500
|
||||
u32 ctrl3;
|
||||
u32 ctrl1_clr;
|
||||
#else
|
||||
u32 reserved[2];
|
||||
#endif
|
||||
struct ast_timer_counter timers2[5];
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_ARCH_TIMER_H */
|
||||
@@ -0,0 +1,113 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2016 Google, Inc
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_WDT_H
|
||||
#define _ASM_ARCH_WDT_H
|
||||
|
||||
#define WDT_BASE 0x1e785000
|
||||
|
||||
/*
|
||||
* Special value that needs to be written to counter_restart register to
|
||||
* (re)start the timer
|
||||
*/
|
||||
#define WDT_COUNTER_RESTART_VAL 0x4755
|
||||
|
||||
/* Control register */
|
||||
#define WDT_CTRL_RESET_MODE_SHIFT 5
|
||||
#define WDT_CTRL_RESET_MODE_MASK 3
|
||||
|
||||
#define WDT_CTRL_EN (1 << 0)
|
||||
#define WDT_CTRL_RESET (1 << 1)
|
||||
#define WDT_CTRL_CLK1MHZ (1 << 4)
|
||||
#define WDT_CTRL_2ND_BOOT (1 << 7)
|
||||
|
||||
/* Values for Reset Mode */
|
||||
#define WDT_CTRL_RESET_SOC 0
|
||||
#define WDT_CTRL_RESET_CHIP 1
|
||||
#define WDT_CTRL_RESET_CPU 2
|
||||
#define WDT_CTRL_RESET_MASK 3
|
||||
|
||||
/* Reset Mask register */
|
||||
#define WDT_RESET_ARM (1 << 0)
|
||||
#define WDT_RESET_COPROC (1 << 1)
|
||||
#define WDT_RESET_SDRAM (1 << 2)
|
||||
#define WDT_RESET_AHB (1 << 3)
|
||||
#define WDT_RESET_I2C (1 << 4)
|
||||
#define WDT_RESET_MAC1 (1 << 5)
|
||||
#define WDT_RESET_MAC2 (1 << 6)
|
||||
#define WDT_RESET_GCRT (1 << 7)
|
||||
#define WDT_RESET_USB20 (1 << 8)
|
||||
#define WDT_RESET_USB11_HOST (1 << 9)
|
||||
#define WDT_RESET_USB11_EHCI2 (1 << 10)
|
||||
#define WDT_RESET_VIDEO (1 << 11)
|
||||
#define WDT_RESET_HAC (1 << 12)
|
||||
#define WDT_RESET_LPC (1 << 13)
|
||||
#define WDT_RESET_SDSDIO (1 << 14)
|
||||
#define WDT_RESET_MIC (1 << 15)
|
||||
#define WDT_RESET_CRT2C (1 << 16)
|
||||
#define WDT_RESET_PWM (1 << 17)
|
||||
#define WDT_RESET_PECI (1 << 18)
|
||||
#define WDT_RESET_JTAG (1 << 19)
|
||||
#define WDT_RESET_ADC (1 << 20)
|
||||
#define WDT_RESET_GPIO (1 << 21)
|
||||
#define WDT_RESET_MCTP (1 << 22)
|
||||
#define WDT_RESET_XDMA (1 << 23)
|
||||
#define WDT_RESET_SPI (1 << 24)
|
||||
#define WDT_RESET_MISC (1 << 25)
|
||||
|
||||
#define WDT_RESET_DEFAULT \
|
||||
(WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C | \
|
||||
WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT | \
|
||||
WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \
|
||||
WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC | \
|
||||
WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C | \
|
||||
WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG | \
|
||||
WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct ast_wdt {
|
||||
u32 counter_status;
|
||||
u32 counter_reload_val;
|
||||
u32 counter_restart;
|
||||
u32 ctrl;
|
||||
u32 timeout_status;
|
||||
u32 clr_timeout_status;
|
||||
u32 reset_width;
|
||||
/* On pre-ast2500 SoCs this register is reserved. */
|
||||
u32 reset_mask;
|
||||
};
|
||||
|
||||
/**
|
||||
* Given flags parameter passed to wdt_reset or wdt_start uclass functions,
|
||||
* gets Reset Mode value from it.
|
||||
*
|
||||
* @flags: flags parameter passed into wdt_reset or wdt_start
|
||||
* @return Reset Mode value
|
||||
*/
|
||||
u32 ast_reset_mode_from_flags(ulong flags);
|
||||
|
||||
/**
|
||||
* Given flags parameter passed to wdt_reset or wdt_start uclass functions,
|
||||
* gets Reset Mask value from it. Reset Mask is only supported on ast2500
|
||||
*
|
||||
* @flags: flags parameter passed into wdt_reset or wdt_start
|
||||
* @return Reset Mask value
|
||||
*/
|
||||
u32 ast_reset_mask_from_flags(ulong flags);
|
||||
|
||||
/**
|
||||
* Given Reset Mask and Reset Mode values, converts them to flags,
|
||||
* suitable for passing into wdt_start or wdt_reset uclass functions.
|
||||
*
|
||||
* On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
|
||||
* can both be packed into single 32 bits wide value.
|
||||
*
|
||||
* @reset_mode: Reset Mode
|
||||
* @reset_mask: Reset Mask
|
||||
*/
|
||||
ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_ARCH_WDT_H */
|
||||
@@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2016 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
/* BOOT0 header information */
|
||||
_start:
|
||||
ARM_VECTORS
|
||||
.word 0xbabeface
|
||||
.word _end - _start
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM235XX_GPIO_H
|
||||
#define __ARCH_BCM235XX_GPIO_H
|
||||
|
||||
/*
|
||||
* Empty file - cmd_gpio.c requires this. The implementation
|
||||
* is in drivers/gpio/kona_gpio.c instead of inlined here.
|
||||
*/
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM235XX_SYSMAP_H
|
||||
|
||||
#define BSC1_BASE_ADDR 0x3e016000
|
||||
#define BSC2_BASE_ADDR 0x3e017000
|
||||
#define BSC3_BASE_ADDR 0x3e018000
|
||||
#define GPIO2_BASE_ADDR 0x35003000
|
||||
#define HSOTG_BASE_ADDR 0x3f120000
|
||||
#define HSOTG_CTRL_BASE_ADDR 0x3f130000
|
||||
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
|
||||
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
|
||||
#define PMU_BSC_BASE_ADDR 0x3500d000
|
||||
#define SDIO1_BASE_ADDR 0x3f180000
|
||||
#define SDIO2_BASE_ADDR 0x3f190000
|
||||
#define SDIO3_BASE_ADDR 0x3f1a0000
|
||||
#define SDIO4_BASE_ADDR 0x3f1b0000
|
||||
#define TIMER_BASE_ADDR 0x3e00d000
|
||||
|
||||
#define HSOTG_DCTL_OFFSET 0x00000804
|
||||
#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
|
||||
|
||||
#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
|
||||
#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
|
||||
#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2016 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
/* BOOT0 header information */
|
||||
_start:
|
||||
ARM_VECTORS
|
||||
.word 0xbabeface
|
||||
.word _end - _start
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM281XX_GPIO_H
|
||||
#define __ARCH_BCM281XX_GPIO_H
|
||||
|
||||
/*
|
||||
* Empty file - cmd_gpio.c requires this. The implementation
|
||||
* is in drivers/gpio/kona_gpio.c instead of inlined here.
|
||||
*/
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_BCM281XX_SYSMAP_H
|
||||
|
||||
#define BSC1_BASE_ADDR 0x3e016000
|
||||
#define BSC2_BASE_ADDR 0x3e017000
|
||||
#define BSC3_BASE_ADDR 0x3e018000
|
||||
#define DWDMA_AHB_BASE_ADDR 0x38100000
|
||||
#define ESUB_CLK_BASE_ADDR 0x38000000
|
||||
#define ESW_CONTRL_BASE_ADDR 0x38200000
|
||||
#define GPIO2_BASE_ADDR 0x35003000
|
||||
#define HSOTG_BASE_ADDR 0x3f120000
|
||||
#define HSOTG_CTRL_BASE_ADDR 0x3f130000
|
||||
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
|
||||
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
|
||||
#define PMU_BSC_BASE_ADDR 0x3500d000
|
||||
#define PWRMGR_BASE_ADDR 0x35010000
|
||||
#define SDIO1_BASE_ADDR 0x3f180000
|
||||
#define SDIO2_BASE_ADDR 0x3f190000
|
||||
#define SDIO3_BASE_ADDR 0x3f1a0000
|
||||
#define SDIO4_BASE_ADDR 0x3f1b0000
|
||||
#define SECWD_BASE_ADDR 0x3500c000
|
||||
#define SECWD2_BASE_ADDR 0x35002f40
|
||||
#define TIMER_BASE_ADDR 0x3e00d000
|
||||
|
||||
#define HSOTG_DCTL_OFFSET 0x00000804
|
||||
#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
|
||||
|
||||
#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
|
||||
#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
|
||||
#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,27 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2014-2017 Broadcom.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_CONFIGS_H
|
||||
#define __ARCH_CONFIGS_H
|
||||
|
||||
#include <asm/iproc-common/configs.h>
|
||||
|
||||
/* uArchitecture specifics */
|
||||
|
||||
/* Serial Info */
|
||||
/* Post pad 3 bytes after each reg addr */
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_MEM32
|
||||
|
||||
#define CONFIG_SYS_NS16550_CLK 100000000
|
||||
#define CONFIG_SYS_NS16550_CLK_DIV 54
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_SYS_NS16550_COM3 0x18023000
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_PHY_BROADCOM
|
||||
#define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
|
||||
|
||||
#endif /* __ARCH_CONFIGS_H */
|
||||
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2014 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_CONFIGS_H
|
||||
#define __ARCH_CONFIGS_H
|
||||
|
||||
#include <asm/iproc-common/configs.h>
|
||||
|
||||
/* uArchitecture specifics */
|
||||
|
||||
/* Serial Info */
|
||||
/* no padding */
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
|
||||
#define CONFIG_SYS_NS16550_CLK 0x03b9aca0
|
||||
#define CONFIG_SYS_NS16550_COM1 0x18000300
|
||||
|
||||
#endif /* __ARCH_CONFIGS_H */
|
||||
@@ -0,0 +1,666 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Cirrus Logic EP93xx register definitions.
|
||||
*
|
||||
* Copyright (C) 2013
|
||||
* Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
|
||||
*
|
||||
* Copyright (C) 2009
|
||||
* Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*
|
||||
* Copyright (C) 2006
|
||||
* Dominic Rath <Dominic.Rath@gmx.de>
|
||||
*
|
||||
* Copyright (C) 2004, 2005
|
||||
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
|
||||
*
|
||||
* Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
|
||||
*
|
||||
* Copyright (C) 2004 Ray Lehtiniemi
|
||||
* Copyright (C) 2003 Cirrus Logic, Inc
|
||||
* Copyright (C) 1999 ARM Limited.
|
||||
*/
|
||||
|
||||
#define EP93XX_AHB_BASE 0x80000000
|
||||
#define EP93XX_APB_BASE 0x80800000
|
||||
|
||||
/*
|
||||
* 0x80000000 - 0x8000FFFF: DMA
|
||||
*/
|
||||
#define DMA_OFFSET 0x000000
|
||||
#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct dma_channel {
|
||||
uint32_t control;
|
||||
uint32_t interrupt;
|
||||
uint32_t ppalloc;
|
||||
uint32_t status;
|
||||
uint32_t reserved0;
|
||||
uint32_t remain;
|
||||
uint32_t reserved1[2];
|
||||
uint32_t maxcnt0;
|
||||
uint32_t base0;
|
||||
uint32_t current0;
|
||||
uint32_t reserved2;
|
||||
uint32_t maxcnt1;
|
||||
uint32_t base1;
|
||||
uint32_t current1;
|
||||
uint32_t reserved3;
|
||||
};
|
||||
|
||||
struct dma_regs {
|
||||
struct dma_channel m2p_channel_0;
|
||||
struct dma_channel m2p_channel_1;
|
||||
struct dma_channel m2p_channel_2;
|
||||
struct dma_channel m2p_channel_3;
|
||||
struct dma_channel m2m_channel_0;
|
||||
struct dma_channel m2m_channel_1;
|
||||
struct dma_channel reserved0[2];
|
||||
struct dma_channel m2p_channel_5;
|
||||
struct dma_channel m2p_channel_4;
|
||||
struct dma_channel m2p_channel_7;
|
||||
struct dma_channel m2p_channel_6;
|
||||
struct dma_channel m2p_channel_9;
|
||||
struct dma_channel m2p_channel_8;
|
||||
uint32_t channel_arbitration;
|
||||
uint32_t reserved[15];
|
||||
uint32_t global_interrupt;
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80010000 - 0x8001FFFF: Ethernet MAC
|
||||
*/
|
||||
#define MAC_OFFSET 0x010000
|
||||
#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mac_queue {
|
||||
uint32_t badd;
|
||||
union { /* deal with half-word aligned registers */
|
||||
uint32_t blen;
|
||||
union {
|
||||
uint16_t filler;
|
||||
uint16_t curlen;
|
||||
};
|
||||
};
|
||||
uint32_t curadd;
|
||||
};
|
||||
|
||||
struct mac_regs {
|
||||
uint32_t rxctl;
|
||||
uint32_t txctl;
|
||||
uint32_t testctl;
|
||||
uint32_t reserved0;
|
||||
uint32_t miicmd;
|
||||
uint32_t miidata;
|
||||
uint32_t miists;
|
||||
uint32_t reserved1;
|
||||
uint32_t selfctl;
|
||||
uint32_t inten;
|
||||
uint32_t intstsp;
|
||||
uint32_t intstsc;
|
||||
uint32_t reserved2[2];
|
||||
uint32_t diagad;
|
||||
uint32_t diagdata;
|
||||
uint32_t gt;
|
||||
uint32_t fct;
|
||||
uint32_t fcf;
|
||||
uint32_t afp;
|
||||
union {
|
||||
struct {
|
||||
uint32_t indad;
|
||||
uint32_t indad_upper;
|
||||
};
|
||||
uint32_t hashtbl;
|
||||
};
|
||||
uint32_t reserved3[2];
|
||||
uint32_t giintsts;
|
||||
uint32_t giintmsk;
|
||||
uint32_t giintrosts;
|
||||
uint32_t giintfrc;
|
||||
uint32_t txcollcnt;
|
||||
uint32_t rxmissnct;
|
||||
uint32_t rxruntcnt;
|
||||
uint32_t reserved4;
|
||||
uint32_t bmctl;
|
||||
uint32_t bmsts;
|
||||
uint32_t rxbca;
|
||||
uint32_t reserved5;
|
||||
struct mac_queue rxdq;
|
||||
uint32_t rxdqenq;
|
||||
struct mac_queue rxstsq;
|
||||
uint32_t rxstsqenq;
|
||||
struct mac_queue txdq;
|
||||
uint32_t txdqenq;
|
||||
struct mac_queue txstsq;
|
||||
uint32_t reserved6;
|
||||
uint32_t rxbufthrshld;
|
||||
uint32_t txbufthrshld;
|
||||
uint32_t rxststhrshld;
|
||||
uint32_t txststhrshld;
|
||||
uint32_t rxdthrshld;
|
||||
uint32_t txdthrshld;
|
||||
uint32_t maxfrmlen;
|
||||
uint32_t maxhdrlen;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define SELFCTL_RWP (1 << 7)
|
||||
#define SELFCTL_GPO0 (1 << 5)
|
||||
#define SELFCTL_PUWE (1 << 4)
|
||||
#define SELFCTL_PDWE (1 << 3)
|
||||
#define SELFCTL_MIIL (1 << 2)
|
||||
#define SELFCTL_RESET (1 << 0)
|
||||
|
||||
#define INTSTS_RWI (1 << 30)
|
||||
#define INTSTS_RXMI (1 << 29)
|
||||
#define INTSTS_RXBI (1 << 28)
|
||||
#define INTSTS_RXSQI (1 << 27)
|
||||
#define INTSTS_TXLEI (1 << 26)
|
||||
#define INTSTS_ECIE (1 << 25)
|
||||
#define INTSTS_TXUHI (1 << 24)
|
||||
#define INTSTS_MOI (1 << 18)
|
||||
#define INTSTS_TXCOI (1 << 17)
|
||||
#define INTSTS_RXROI (1 << 16)
|
||||
#define INTSTS_MIII (1 << 12)
|
||||
#define INTSTS_PHYI (1 << 11)
|
||||
#define INTSTS_TI (1 << 10)
|
||||
#define INTSTS_AHBE (1 << 8)
|
||||
#define INTSTS_OTHER (1 << 4)
|
||||
#define INTSTS_TXSQ (1 << 3)
|
||||
#define INTSTS_RXSQ (1 << 2)
|
||||
|
||||
#define BMCTL_MT (1 << 13)
|
||||
#define BMCTL_TT (1 << 12)
|
||||
#define BMCTL_UNH (1 << 11)
|
||||
#define BMCTL_TXCHR (1 << 10)
|
||||
#define BMCTL_TXDIS (1 << 9)
|
||||
#define BMCTL_TXEN (1 << 8)
|
||||
#define BMCTL_EH2 (1 << 6)
|
||||
#define BMCTL_EH1 (1 << 5)
|
||||
#define BMCTL_EEOB (1 << 4)
|
||||
#define BMCTL_RXCHR (1 << 2)
|
||||
#define BMCTL_RXDIS (1 << 1)
|
||||
#define BMCTL_RXEN (1 << 0)
|
||||
|
||||
#define BMSTS_TXACT (1 << 7)
|
||||
#define BMSTS_TP (1 << 4)
|
||||
#define BMSTS_RXACT (1 << 3)
|
||||
#define BMSTS_QID_MASK 0x07
|
||||
#define BMSTS_QID_RXDATA 0x00
|
||||
#define BMSTS_QID_TXDATA 0x01
|
||||
#define BMSTS_QID_RXSTS 0x02
|
||||
#define BMSTS_QID_TXSTS 0x03
|
||||
#define BMSTS_QID_RXDESC 0x04
|
||||
#define BMSTS_QID_TXDESC 0x05
|
||||
|
||||
#define AFP_MASK 0x07
|
||||
#define AFP_IAPRIMARY 0x00
|
||||
#define AFP_IASECONDARY1 0x01
|
||||
#define AFP_IASECONDARY2 0x02
|
||||
#define AFP_IASECONDARY3 0x03
|
||||
#define AFP_TX 0x06
|
||||
#define AFP_HASH 0x07
|
||||
|
||||
#define RXCTL_PAUSEA (1 << 20)
|
||||
#define RXCTL_RXFCE1 (1 << 19)
|
||||
#define RXCTL_RXFCE0 (1 << 18)
|
||||
#define RXCTL_BCRC (1 << 17)
|
||||
#define RXCTL_SRXON (1 << 16)
|
||||
#define RXCTL_RCRCA (1 << 13)
|
||||
#define RXCTL_RA (1 << 12)
|
||||
#define RXCTL_PA (1 << 11)
|
||||
#define RXCTL_BA (1 << 10)
|
||||
#define RXCTL_MA (1 << 9)
|
||||
#define RXCTL_IAHA (1 << 8)
|
||||
#define RXCTL_IA3 (1 << 3)
|
||||
#define RXCTL_IA2 (1 << 2)
|
||||
#define RXCTL_IA1 (1 << 1)
|
||||
#define RXCTL_IA0 (1 << 0)
|
||||
|
||||
#define TXCTL_DEFDIS (1 << 7)
|
||||
#define TXCTL_MBE (1 << 6)
|
||||
#define TXCTL_ICRC (1 << 5)
|
||||
#define TXCTL_TPD (1 << 4)
|
||||
#define TXCTL_OCOLL (1 << 3)
|
||||
#define TXCTL_SP (1 << 2)
|
||||
#define TXCTL_PB (1 << 1)
|
||||
#define TXCTL_STXON (1 << 0)
|
||||
|
||||
#define MIICMD_REGAD_MASK (0x001F)
|
||||
#define MIICMD_PHYAD_MASK (0x03E0)
|
||||
#define MIICMD_OPCODE_MASK (0xC000)
|
||||
#define MIICMD_PHYAD_8950 (0x0000)
|
||||
#define MIICMD_OPCODE_READ (0x8000)
|
||||
#define MIICMD_OPCODE_WRITE (0x4000)
|
||||
|
||||
#define MIISTS_BUSY (1 << 0)
|
||||
|
||||
/*
|
||||
* 0x80020000 - 0x8002FFFF: USB OHCI
|
||||
*/
|
||||
#define USB_OFFSET 0x020000
|
||||
#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80030000 - 0x8003FFFF: Raster engine
|
||||
*/
|
||||
#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
|
||||
#define RASTER_OFFSET 0x030000
|
||||
#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80040000 - 0x8004FFFF: Graphics accelerator
|
||||
*/
|
||||
#if defined(CONFIG_EP9315)
|
||||
#define GFX_OFFSET 0x040000
|
||||
#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80050000 - 0x8005FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80060000 - 0x8006FFFF: SDRAM controller
|
||||
*/
|
||||
#define SDRAM_OFFSET 0x060000
|
||||
#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct sdram_regs {
|
||||
uint32_t reserved;
|
||||
uint32_t glconfig;
|
||||
uint32_t refrshtimr;
|
||||
uint32_t bootsts;
|
||||
uint32_t devcfg0;
|
||||
uint32_t devcfg1;
|
||||
uint32_t devcfg2;
|
||||
uint32_t devcfg3;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
|
||||
#define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
|
||||
#define SDRAM_DEVCFG_SROMLL (1 << 5)
|
||||
#define SDRAM_DEVCFG_CASLAT_2 0x00010000
|
||||
#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
|
||||
|
||||
#define SDRAM_OFF_GLCONFIG 0x0004
|
||||
#define SDRAM_OFF_REFRSHTIMR 0x0008
|
||||
|
||||
#define SDRAM_OFF_DEVCFG0 0x0010
|
||||
#define SDRAM_OFF_DEVCFG1 0x0014
|
||||
#define SDRAM_OFF_DEVCFG2 0x0018
|
||||
#define SDRAM_OFF_DEVCFG3 0x001C
|
||||
|
||||
#define SDRAM_DEVCFG0_BASE 0xC0000000
|
||||
#define SDRAM_DEVCFG1_BASE 0xD0000000
|
||||
#define SDRAM_DEVCFG2_BASE 0xE0000000
|
||||
#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
|
||||
#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
|
||||
|
||||
#define GLCONFIG_INIT (1 << 0)
|
||||
#define GLCONFIG_MRS (1 << 1)
|
||||
#define GLCONFIG_SMEMBUSY (1 << 5)
|
||||
#define GLCONFIG_LCR (1 << 6)
|
||||
#define GLCONFIG_REARBEN (1 << 7)
|
||||
#define GLCONFIG_CLKSHUTDOWN (1 << 30)
|
||||
#define GLCONFIG_CKE (1 << 31)
|
||||
|
||||
#define EP93XX_SDRAMCTRL 0x80060000
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
|
||||
#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
|
||||
|
||||
#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
|
||||
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
|
||||
#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
|
||||
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
|
||||
#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
|
||||
|
||||
/*
|
||||
* 0x80070000 - 0x8007FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
|
||||
*/
|
||||
#define SMC_OFFSET 0x080000
|
||||
#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct smc_regs {
|
||||
uint32_t bcr0;
|
||||
uint32_t bcr1;
|
||||
uint32_t bcr2;
|
||||
uint32_t bcr3;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t bcr6;
|
||||
uint32_t bcr7;
|
||||
#if defined(CONFIG_EP9315)
|
||||
uint32_t pcattribute;
|
||||
uint32_t pccommon;
|
||||
uint32_t pcio;
|
||||
uint32_t reserved1[5];
|
||||
uint32_t pcmciactrl;
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#define EP93XX_OFF_SMCBCR0 0x00
|
||||
#define EP93XX_OFF_SMCBCR1 0x04
|
||||
#define EP93XX_OFF_SMCBCR2 0x08
|
||||
#define EP93XX_OFF_SMCBCR3 0x0C
|
||||
#define EP93XX_OFF_SMCBCR6 0x18
|
||||
#define EP93XX_OFF_SMCBCR7 0x1C
|
||||
|
||||
#define SMC_BCR_IDCY_SHIFT 0
|
||||
#define SMC_BCR_WST1_SHIFT 5
|
||||
#define SMC_BCR_BLE (1 << 10)
|
||||
#define SMC_BCR_WST2_SHIFT 11
|
||||
#define SMC_BCR_MW_SHIFT 28
|
||||
|
||||
/*
|
||||
* 0x80090000 - 0x8009FFFF: Boot ROM
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800A0000 - 0x800AFFFF: IDE interface
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800B0000 - 0x800BFFFF: VIC1
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800C0000 - 0x800CFFFF: VIC2
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x800D0000 - 0x800FFFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80800000 - 0x8080FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80810000 - 0x8081FFFF: Timers
|
||||
*/
|
||||
#define TIMER_OFFSET 0x010000
|
||||
#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct timer {
|
||||
uint32_t load;
|
||||
uint32_t value;
|
||||
uint32_t control;
|
||||
uint32_t clear;
|
||||
};
|
||||
|
||||
struct timer4 {
|
||||
uint32_t value_low;
|
||||
uint32_t value_high;
|
||||
};
|
||||
|
||||
struct timer_regs {
|
||||
struct timer timer1;
|
||||
uint32_t reserved0[4];
|
||||
struct timer timer2;
|
||||
uint32_t reserved1[12];
|
||||
struct timer4 timer4;
|
||||
uint32_t reserved2[6];
|
||||
struct timer timer3;
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 0x80820000 - 0x8082FFFF: I2S
|
||||
*/
|
||||
#define I2S_OFFSET 0x020000
|
||||
#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80830000 - 0x8083FFFF: Security
|
||||
*/
|
||||
#define SECURITY_OFFSET 0x030000
|
||||
#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
|
||||
|
||||
#define EXTENSIONID (SECURITY_BASE + 0x2714)
|
||||
|
||||
/*
|
||||
* 0x80840000 - 0x8084FFFF: GPIO
|
||||
*/
|
||||
#define GPIO_OFFSET 0x040000
|
||||
#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct gpio_int {
|
||||
uint32_t inttype1;
|
||||
uint32_t inttype2;
|
||||
uint32_t eoi;
|
||||
uint32_t inten;
|
||||
uint32_t intsts;
|
||||
uint32_t rawintsts;
|
||||
uint32_t db;
|
||||
};
|
||||
|
||||
struct gpio_regs {
|
||||
uint32_t padr;
|
||||
uint32_t pbdr;
|
||||
uint32_t pcdr;
|
||||
uint32_t pddr;
|
||||
uint32_t paddr;
|
||||
uint32_t pbddr;
|
||||
uint32_t pcddr;
|
||||
uint32_t pdddr;
|
||||
uint32_t pedr;
|
||||
uint32_t peddr;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t pfdr;
|
||||
uint32_t pfddr;
|
||||
uint32_t pgdr;
|
||||
uint32_t pgddr;
|
||||
uint32_t phdr;
|
||||
uint32_t phddr;
|
||||
uint32_t reserved1;
|
||||
uint32_t finttype1;
|
||||
uint32_t finttype2;
|
||||
uint32_t reserved2;
|
||||
struct gpio_int pfint;
|
||||
uint32_t reserved3[10];
|
||||
struct gpio_int paint;
|
||||
struct gpio_int pbint;
|
||||
uint32_t eedrive;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define EP93XX_LED_DATA 0x80840020
|
||||
#define EP93XX_LED_GREEN_ON 0x0001
|
||||
#define EP93XX_LED_RED_ON 0x0002
|
||||
|
||||
#define EP93XX_LED_DDR 0x80840024
|
||||
#define EP93XX_LED_GREEN_ENABLE 0x0001
|
||||
#define EP93XX_LED_RED_ENABLE 0x00020000
|
||||
|
||||
/*
|
||||
* 0x80850000 - 0x8087FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x80880000 - 0x8088FFFF: AAC
|
||||
*/
|
||||
#define AAC_OFFSET 0x080000
|
||||
#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80890000 - 0x8089FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* 0x808A0000 - 0x808AFFFF: SPI
|
||||
*/
|
||||
#define SPI_OFFSET 0x0A0000
|
||||
#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808B0000 - 0x808BFFFF: IrDA
|
||||
*/
|
||||
#define IRDA_OFFSET 0x0B0000
|
||||
#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808C0000 - 0x808CFFFF: UART1
|
||||
*/
|
||||
#define UART1_OFFSET 0x0C0000
|
||||
#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808D0000 - 0x808DFFFF: UART2
|
||||
*/
|
||||
#define UART2_OFFSET 0x0D0000
|
||||
#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808E0000 - 0x808EFFFF: UART3
|
||||
*/
|
||||
#define UART3_OFFSET 0x0E0000
|
||||
#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x808F0000 - 0x808FFFFF: Key Matrix
|
||||
*/
|
||||
#define KEY_OFFSET 0x0F0000
|
||||
#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80900000 - 0x8090FFFF: Touchscreen
|
||||
*/
|
||||
#define TOUCH_OFFSET 0x900000
|
||||
#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80910000 - 0x8091FFFF: Pulse Width Modulation
|
||||
*/
|
||||
#define PWM_OFFSET 0x910000
|
||||
#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80920000 - 0x8092FFFF: Real time clock
|
||||
*/
|
||||
#define RTC_OFFSET 0x920000
|
||||
#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80930000 - 0x8093FFFF: Syscon
|
||||
*/
|
||||
#define SYSCON_OFFSET 0x930000
|
||||
#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
|
||||
|
||||
/* Security */
|
||||
#define SECURITY_EXTENSIONID 0x80832714
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct syscon_regs {
|
||||
uint32_t pwrsts;
|
||||
uint32_t pwrcnt;
|
||||
uint32_t halt;
|
||||
uint32_t stby;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t teoi;
|
||||
uint32_t stfclr;
|
||||
uint32_t clkset1;
|
||||
uint32_t clkset2;
|
||||
uint32_t reserved1[6];
|
||||
uint32_t scratch0;
|
||||
uint32_t scratch1;
|
||||
uint32_t reserved2[2];
|
||||
uint32_t apbwait;
|
||||
uint32_t bustmstrarb;
|
||||
uint32_t bootmodeclr;
|
||||
uint32_t reserved3[9];
|
||||
uint32_t devicecfg;
|
||||
uint32_t vidclkdiv;
|
||||
uint32_t mirclkdiv;
|
||||
uint32_t i2sclkdiv;
|
||||
uint32_t keytchclkdiv;
|
||||
uint32_t chipid;
|
||||
uint32_t reserved4;
|
||||
uint32_t syscfg;
|
||||
uint32_t reserved5[8];
|
||||
uint32_t sysswlock;
|
||||
};
|
||||
#else
|
||||
#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
|
||||
#endif
|
||||
|
||||
#define SYSCON_OFF_CLKSET1 0x0020
|
||||
#define SYSCON_OFF_SYSCFG 0x009c
|
||||
|
||||
#define SYSCON_PWRCNT_UART_BAUD (1 << 29)
|
||||
#define SYSCON_PWRCNT_USH_EN (1 << 28)
|
||||
|
||||
#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
|
||||
#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
|
||||
#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
|
||||
#define SYSCON_CLKSET_PLL_PS_SHIFT 16
|
||||
#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
|
||||
#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
|
||||
#define SYSCON_CLKSET1_NBYP1 (1 << 23)
|
||||
#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
|
||||
|
||||
#define SYSCON_CLKSET2_PLL2_EN (1 << 18)
|
||||
#define SYSCON_CLKSET2_NBYP2 (1 << 19)
|
||||
#define SYSCON_CLKSET2_USB_DIV_SHIFT 28
|
||||
|
||||
#define SYSCON_CHIPID_REV_MASK 0xF0000000
|
||||
#define SYSCON_DEVICECFG_SWRST (1 << 31)
|
||||
|
||||
#define SYSCON_SYSCFG_LASDO 0x00000020
|
||||
|
||||
/*
|
||||
* 0x80930000 - 0x8093FFFF: Watchdog Timer
|
||||
*/
|
||||
#define WATCHDOG_OFFSET 0x940000
|
||||
#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
|
||||
|
||||
/*
|
||||
* 0x80950000 - 0x9000FFFF: Reserved
|
||||
*/
|
||||
|
||||
/*
|
||||
* During low_level init we store memory layout in memory at specific location
|
||||
*/
|
||||
#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
|
||||
#define UBOOT_MEMORYCNF_BANK_MASK 0x2004
|
||||
#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008
|
||||
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2019 NXP Semiconductors
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
|
||||
#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
|
||||
|
||||
#include <common.h>
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_BUS_CLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_DSPI_CLK,
|
||||
};
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
ulong get_ddr_freq(ulong);
|
||||
uint get_svr(void);
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
|
||||
@@ -0,0 +1,404 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2016-2018 NXP
|
||||
* Copyright 2015, Freescale Semiconductor
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
|
||||
|
||||
#include <linux/kconfig.h>
|
||||
#include <fsl_ddrc_version.h>
|
||||
|
||||
#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
|
||||
|
||||
/*
|
||||
* Reserve secure memory
|
||||
* To be aligned with MMU block size
|
||||
*/
|
||||
#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
|
||||
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
|
||||
|
||||
#ifdef CONFIG_ARCH_LS2080A
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
|
||||
#define SRDS_MAX_LANES 8
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
#ifndef L1_CACHE_BYTES
|
||||
#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
#define CONFIG_SYS_FSL_IFC_LE
|
||||
#define CONFIG_SYS_FSL_PEX_LUT_LE
|
||||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06100000
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
|
||||
/* Cache Coherent Interconnect */
|
||||
#define CCI_MN_BASE 0x04000000
|
||||
#define CCI_MN_RNF_NODEID_LIST 0x180
|
||||
#define CCI_MN_DVM_DOMAIN_CTL 0x200
|
||||
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
|
||||
|
||||
#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
|
||||
#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
|
||||
#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
|
||||
#define CCN_HN_F_SAM_NODEID_MASK 0x7f
|
||||
#define CCN_HN_F_SAM_NODEID_DDR0 0x4
|
||||
#define CCN_HN_F_SAM_NODEID_DDR1 0xe
|
||||
|
||||
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
|
||||
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
|
||||
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
|
||||
#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
|
||||
#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
|
||||
#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
|
||||
|
||||
#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
|
||||
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
|
||||
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
|
||||
|
||||
#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
|
||||
|
||||
/* TZ Protection Controller Definitions */
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCR0SIZE_BASE (TZPC_BASE)
|
||||
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
|
||||
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
|
||||
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
|
||||
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
|
||||
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
|
||||
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
|
||||
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
|
||||
|
||||
#define DCSR_CGACRE5 0x700070914ULL
|
||||
#define EPU_EPCMPR5 0x700060914ULL
|
||||
#define EPU_EPCCR5 0x700060814ULL
|
||||
#define EPU_EPSMCR5 0x700060228ULL
|
||||
#define EPU_EPECR5 0x700060314ULL
|
||||
#define EPU_EPCTR5 0x700060a14ULL
|
||||
#define EPU_EPGCR 0x700060000ULL
|
||||
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008751
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1088A)
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#define CONFIG_GICV3
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
|
||||
/* TZ Protection Controller Definitions */
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCR0SIZE_BASE (TZPC_BASE)
|
||||
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
|
||||
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
|
||||
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
|
||||
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
|
||||
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
|
||||
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
|
||||
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06100000
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
#define CONFIG_SYS_FSL_IFC_LE
|
||||
#define CONFIG_SYS_FSL_PEX_LUT_LE
|
||||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
||||
/* LX2160A Soc Support */
|
||||
#elif defined(CONFIG_ARCH_LX2160A)
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#if !defined(CONFIG_DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_EARLY_INIT
|
||||
#endif
|
||||
#define SRDS_MAX_LANES 8
|
||||
#ifndef L1_CACHE_BYTES
|
||||
#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
||||
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
#define CONFIG_SYS_FSL_PEX_LUT_LE
|
||||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06200000
|
||||
|
||||
/* SMMU Definitions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1028A)
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#define CONFIG_GICV3
|
||||
#define CONFIG_FSL_TZPC_BP147
|
||||
#define CONFIG_FSL_TZASC_400
|
||||
|
||||
/* TZ Protection Controller Definitions */
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCR0SIZE_BASE (TZPC_BASE)
|
||||
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
|
||||
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
|
||||
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
|
||||
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
|
||||
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
|
||||
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
|
||||
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06040000
|
||||
|
||||
/* SMMU Definitions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
#define CONFIG_SYS_FSL_PEX_LUT_LE
|
||||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* SEC */
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
||||
#define DCSR_DCFG_SBEESR2 0x20140534
|
||||
#define DCSR_DCFG_MBEESR2 0x20140544
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
|
||||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
#define CONFIG_SYS_FSL_QSPI_BE
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_BE
|
||||
#define CONFIG_SYS_FSL_PEX_LUT_BE
|
||||
|
||||
/* SoC related */
|
||||
#ifdef CONFIG_ARCH_LS1043A
|
||||
#define CONFIG_SYS_FMAN_V3
|
||||
#define CONFIG_SYS_FSL_QMAN_V3
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 7
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SEC_MON_BE
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x09000000
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x01401000
|
||||
#define GICC_BASE 0x01402000
|
||||
#define GICH_BASE 0x01404000
|
||||
#define GICV_BASE 0x01406000
|
||||
#define GICD_SIZE 0x1000
|
||||
#define GICC_SIZE 0x2000
|
||||
#define GICH_SIZE 0x2000
|
||||
#define GICV_SIZE 0x2000
|
||||
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
|
||||
#define GICD_BASE_64K 0x01410000
|
||||
#define GICC_BASE_64K 0x01420000
|
||||
#define GICH_BASE_64K 0x01440000
|
||||
#define GICV_BASE_64K 0x01460000
|
||||
#define GICD_SIZE_64K 0x10000
|
||||
#define GICC_SIZE_64K 0x20000
|
||||
#define GICH_SIZE_64K 0x20000
|
||||
#define GICV_SIZE_64K 0x20000
|
||||
#endif
|
||||
|
||||
#define DCFG_CCSR_SVR 0x1ee00a4
|
||||
#define REV1_0 0x10
|
||||
#define REV1_1 0x11
|
||||
#define GIC_ADDR_BIT 31
|
||||
#define SCFG_GIC400_ALIGN 0x1570188
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1012A)
|
||||
#define GICD_BASE 0x01401000
|
||||
#define GICC_BASE 0x01402000
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SEC_MON_BE
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1046A)
|
||||
#define CONFIG_SYS_FMAN_V3
|
||||
#define CONFIG_SYS_FSL_QMAN_V3
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SEC_MON_BE
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x09000000
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x01410000
|
||||
#define GICC_BASE 0x01420000
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
|
||||
@@ -0,0 +1,98 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_CPU_H
|
||||
#define _FSL_LAYERSCAPE_CPU_H
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
|
||||
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
|
||||
#ifndef CONFIG_NXP_LSCH3_2
|
||||
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
|
||||
#ifndef CONFIG_NXP_LSCH3_2
|
||||
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
|
||||
#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
|
||||
#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
|
||||
#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
|
||||
#define CONFIG_SYS_FSL_NI_BASE 0x810000000
|
||||
#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
|
||||
#ifdef CONFIG_ARCH_LS2080A
|
||||
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
|
||||
#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000
|
||||
#define SYS_PCIE5_PHYS_SIZE 0x800000000
|
||||
#define SYS_PCIE6_PHYS_SIZE 0x800000000
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
|
||||
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
|
||||
#ifndef CONFIG_ARCH_LX2160A
|
||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
|
||||
#ifdef CONFIG_NXP_LSCH3_2
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
|
||||
#endif
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
|
||||
#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
|
||||
#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
|
||||
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
|
||||
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
|
||||
#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
|
||||
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
|
||||
#endif
|
||||
|
||||
int fsl_qoriq_core_to_cluster(unsigned int core);
|
||||
u32 cpu_mask(void);
|
||||
|
||||
#endif /* _FSL_LAYERSCAPE_CPU_H */
|
||||
@@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
|
||||
void fdt_fixup_board_enet(void *fdt);
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
|
||||
@@ -0,0 +1,193 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef _FSL_ICID_H_
|
||||
#define _FSL_ICID_H_
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <fsl_qbman.h>
|
||||
#include <fsl_sec.h>
|
||||
#include <asm/armv8/sec_firmware.h>
|
||||
|
||||
struct icid_id_table {
|
||||
const char *compat;
|
||||
u32 id;
|
||||
u32 reg;
|
||||
phys_addr_t compat_addr;
|
||||
phys_addr_t reg_addr;
|
||||
bool le;
|
||||
};
|
||||
|
||||
struct fman_icid_id_table {
|
||||
u32 port_id;
|
||||
u32 icid;
|
||||
};
|
||||
|
||||
u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
|
||||
int fdt_get_smmu_phandle(void *blob);
|
||||
int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
|
||||
void set_icids(void);
|
||||
void fdt_fixup_icid(void *blob);
|
||||
|
||||
#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
|
||||
{ .compat = name, \
|
||||
.id = idA, \
|
||||
.reg = regA, \
|
||||
.compat_addr = compataddr, \
|
||||
.reg_addr = addr, \
|
||||
.le = _le \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SEC_LE
|
||||
#define SEC_IS_LE true
|
||||
#elif defined(CONFIG_SYS_FSL_SEC_BE)
|
||||
#define SEC_IS_LE false
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH2
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define SCFG_IS_LE true
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
|
||||
#define SCFG_IS_LE false
|
||||
#endif
|
||||
|
||||
#define QDMA_IS_LE false
|
||||
|
||||
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
|
||||
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
|
||||
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
|
||||
compataddr, SCFG_IS_LE)
|
||||
|
||||
#define SET_USB_ICID(usb_num, compat, streamid) \
|
||||
SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
|
||||
CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
|
||||
|
||||
#define SET_SATA_ICID(compat, streamid) \
|
||||
SET_SCFG_ICID(compat, streamid, sata_icid,\
|
||||
AHCI_BASE_ADDR)
|
||||
|
||||
#define SET_SDHC_ICID(streamid) \
|
||||
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
|
||||
CONFIG_SYS_FSL_ESDHC_ADDR)
|
||||
|
||||
#define SET_EDMA_ICID(streamid) \
|
||||
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
|
||||
EDMA_BASE_ADDR)
|
||||
|
||||
#define SET_ETR_ICID(streamid) \
|
||||
SET_SCFG_ICID(NULL, streamid, etr_icid, 0)
|
||||
|
||||
#define SET_DEBUG_ICID(streamid) \
|
||||
SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
|
||||
|
||||
#define SET_QE_ICID(streamid) \
|
||||
SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
|
||||
QE_BASE_ADDR)
|
||||
|
||||
#define SET_QMAN_ICID(streamid) \
|
||||
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
|
||||
offsetof(struct ccsr_qman, liodnr) + \
|
||||
CONFIG_SYS_FSL_QMAN_ADDR, \
|
||||
CONFIG_SYS_FSL_QMAN_ADDR, false)
|
||||
|
||||
#define SET_BMAN_ICID(streamid) \
|
||||
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
|
||||
offsetof(struct ccsr_bman, liodnr) + \
|
||||
CONFIG_SYS_FSL_BMAN_ADDR, \
|
||||
CONFIG_SYS_FSL_BMAN_ADDR, false)
|
||||
|
||||
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
|
||||
{ .port_id = (_port_id), .icid = (streamid) }
|
||||
|
||||
#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
|
||||
|
||||
#define SET_SEC_QI_ICID(streamid) \
|
||||
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
|
||||
0, offsetof(ccsr_sec_t, qilcr_ls) + \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
|
||||
|
||||
extern struct fman_icid_id_table fman_icid_tbl[];
|
||||
extern int fman_icid_tbl_sz;
|
||||
|
||||
#else /* CONFIG_FSL_LSCH2 */
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define GUR_IS_LE true
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
|
||||
#define GUR_IS_LE false
|
||||
#endif
|
||||
|
||||
#define QDMA_IS_LE true
|
||||
|
||||
#define SET_GUR_ICID(compat, streamid, name, compataddr) \
|
||||
SET_ICID_ENTRY(compat, streamid, streamid, \
|
||||
offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
|
||||
compataddr, GUR_IS_LE)
|
||||
|
||||
#define SET_USB_ICID(usb_num, compat, streamid) \
|
||||
SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
|
||||
CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
|
||||
|
||||
#define SET_SATA_ICID(sata_num, compat, streamid) \
|
||||
SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
|
||||
AHCI_BASE_ADDR##sata_num)
|
||||
|
||||
#define SET_SDHC_ICID(sdhc_num, streamid) \
|
||||
SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
|
||||
FSL_ESDHC##sdhc_num##_BASE_ADDR)
|
||||
|
||||
#define SET_EDMA_ICID(streamid) \
|
||||
SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
|
||||
EDMA_BASE_ADDR)
|
||||
|
||||
#define SET_GPU_ICID(compat, streamid) \
|
||||
SET_GUR_ICID(compat, streamid, misc1_amqr,\
|
||||
GPU_BASE_ADDR)
|
||||
|
||||
#define SET_DISPLAY_ICID(streamid) \
|
||||
SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
|
||||
DISPLAY_BASE_ADDR)
|
||||
|
||||
#define SEC_ICID_REG_VAL(streamid) (streamid)
|
||||
|
||||
#endif /* CONFIG_FSL_LSCH2 */
|
||||
|
||||
#define SET_QDMA_ICID(compat, streamid) \
|
||||
SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
|
||||
QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
|
||||
QDMA_BASE_ADDR, QDMA_IS_LE), \
|
||||
SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
|
||||
QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
|
||||
QDMA_BASE_ADDR, QDMA_IS_LE)
|
||||
|
||||
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
|
||||
SET_ICID_ENTRY( \
|
||||
(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
|
||||
(FSL_SEC_JR##jr_num##_OFFSET == \
|
||||
SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
|
||||
? NULL \
|
||||
: "fsl,sec-v4.0-job-ring"), \
|
||||
streamid, \
|
||||
SEC_ICID_REG_VAL(streamid), \
|
||||
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, \
|
||||
FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
|
||||
|
||||
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
|
||||
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
|
||||
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
|
||||
|
||||
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
|
||||
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
|
||||
offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
|
||||
|
||||
extern struct icid_id_table icid_tbl[];
|
||||
extern int icid_tbl_sz;
|
||||
|
||||
#endif
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef _FSL_PORTALS_H_
|
||||
#define _FSL_PORTALS_H_
|
||||
|
||||
struct qportal_info {
|
||||
u16 dicid; /* DQRR ICID */
|
||||
u16 ficid; /* frame data ICID */
|
||||
u16 icid;
|
||||
u8 sdest;
|
||||
};
|
||||
|
||||
#define SET_QP_INFO(streamid, dest) \
|
||||
{ .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \
|
||||
.sdest = (dest) }
|
||||
|
||||
extern struct qportal_info qp_info[];
|
||||
void fdt_portal(void *blob, const char *compat, const char *container,
|
||||
u64 addr, u32 size);
|
||||
|
||||
#endif
|
||||
+218
@@ -0,0 +1,218 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H__
|
||||
#define __FSL_SERDES_H__
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
enum srds_prtcl {
|
||||
/*
|
||||
* Nobody will check whether the device 'NONE' has been configured,
|
||||
* So use it to indicate if the serdes_prtcl_map has been initialized.
|
||||
*/
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
PCIE5,
|
||||
PCIE6,
|
||||
SATA1,
|
||||
SATA2,
|
||||
SATA3,
|
||||
SATA4,
|
||||
XAUI1,
|
||||
XAUI2,
|
||||
XFI1,
|
||||
XFI2,
|
||||
XFI3,
|
||||
XFI4,
|
||||
XFI5,
|
||||
XFI6,
|
||||
XFI7,
|
||||
XFI8,
|
||||
XFI9,
|
||||
XFI10,
|
||||
XFI11,
|
||||
XFI12,
|
||||
XFI13,
|
||||
XFI14,
|
||||
SGMII1,
|
||||
SGMII2,
|
||||
SGMII3,
|
||||
SGMII4,
|
||||
SGMII5,
|
||||
SGMII6,
|
||||
SGMII7,
|
||||
SGMII8,
|
||||
SGMII9,
|
||||
SGMII10,
|
||||
SGMII11,
|
||||
SGMII12,
|
||||
SGMII13,
|
||||
SGMII14,
|
||||
SGMII15,
|
||||
SGMII16,
|
||||
SGMII17,
|
||||
SGMII18,
|
||||
QSGMII_A,
|
||||
QSGMII_B,
|
||||
QSGMII_C,
|
||||
QSGMII_D,
|
||||
SGMII_T1,
|
||||
SGMII_T2,
|
||||
SGMII_T3,
|
||||
SGMII_T4,
|
||||
SXGMII1,
|
||||
SXGMII2,
|
||||
SXGMII3,
|
||||
SXGMII4,
|
||||
QXGMII1,
|
||||
QXGMII2,
|
||||
QXGMII3,
|
||||
QXGMII4,
|
||||
_25GE1,
|
||||
_25GE2,
|
||||
_25GE3,
|
||||
_25GE4,
|
||||
_25GE5,
|
||||
_25GE6,
|
||||
_25GE7,
|
||||
_25GE8,
|
||||
_25GE9,
|
||||
_25GE10,
|
||||
_40GE1,
|
||||
_40GE2,
|
||||
_50GE1,
|
||||
_50GE2,
|
||||
_100GE1,
|
||||
_100GE2,
|
||||
SERDES_PRCTL_COUNT
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
NXP_SRDS_3 = 2,
|
||||
};
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
enum srds_prtcl {
|
||||
/*
|
||||
* Nobody will check whether the device 'NONE' has been configured,
|
||||
* So use it to indicate if the serdes_prtcl_map has been initialized.
|
||||
*/
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
SATA1,
|
||||
SATA2,
|
||||
SRIO1,
|
||||
SRIO2,
|
||||
SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3,
|
||||
SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5,
|
||||
SGMII_FM1_DTSEC6,
|
||||
SGMII_FM1_DTSEC9,
|
||||
SGMII_FM1_DTSEC10,
|
||||
SGMII_FM2_DTSEC1,
|
||||
SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3,
|
||||
SGMII_FM2_DTSEC4,
|
||||
SGMII_FM2_DTSEC5,
|
||||
SGMII_FM2_DTSEC6,
|
||||
SGMII_FM2_DTSEC9,
|
||||
SGMII_FM2_DTSEC10,
|
||||
SGMII_TSEC1,
|
||||
SGMII_TSEC2,
|
||||
SGMII_TSEC3,
|
||||
SGMII_TSEC4,
|
||||
XAUI_FM1,
|
||||
XAUI_FM2,
|
||||
AURORA,
|
||||
CPRI1,
|
||||
CPRI2,
|
||||
CPRI3,
|
||||
CPRI4,
|
||||
CPRI5,
|
||||
CPRI6,
|
||||
CPRI7,
|
||||
CPRI8,
|
||||
XAUI_FM1_MAC9,
|
||||
XAUI_FM1_MAC10,
|
||||
XAUI_FM2_MAC9,
|
||||
XAUI_FM2_MAC10,
|
||||
HIGIG_FM1_MAC9,
|
||||
HIGIG_FM1_MAC10,
|
||||
HIGIG_FM2_MAC9,
|
||||
HIGIG_FM2_MAC10,
|
||||
QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
|
||||
QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
|
||||
QSGMII_FM2_A,
|
||||
QSGMII_FM2_B,
|
||||
XFI_FM1_MAC1,
|
||||
XFI_FM1_MAC2,
|
||||
XFI_FM1_MAC9,
|
||||
XFI_FM1_MAC10,
|
||||
XFI_FM2_MAC9,
|
||||
XFI_FM2_MAC10,
|
||||
INTERLAKEN,
|
||||
QSGMII_SW1_A, /* Indicates ports on L2 Switch */
|
||||
QSGMII_SW1_B,
|
||||
SGMII_2500_FM1_DTSEC1,
|
||||
SGMII_2500_FM1_DTSEC2,
|
||||
SGMII_2500_FM1_DTSEC3,
|
||||
SGMII_2500_FM1_DTSEC4,
|
||||
SGMII_2500_FM1_DTSEC5,
|
||||
SGMII_2500_FM1_DTSEC6,
|
||||
SGMII_2500_FM1_DTSEC9,
|
||||
SGMII_2500_FM1_DTSEC10,
|
||||
SGMII_2500_FM2_DTSEC1,
|
||||
SGMII_2500_FM2_DTSEC2,
|
||||
SGMII_2500_FM2_DTSEC3,
|
||||
SGMII_2500_FM2_DTSEC4,
|
||||
SGMII_2500_FM2_DTSEC5,
|
||||
SGMII_2500_FM2_DTSEC6,
|
||||
SGMII_2500_FM2_DTSEC9,
|
||||
SGMII_2500_FM2_DTSEC10,
|
||||
TX_CLK,
|
||||
SERDES_PRCTL_COUNT
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
void fsl_serdes_init(void);
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
|
||||
int serdes_get_number(int serdes, int cfg);
|
||||
void fsl_rgmii_init(void);
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH2
|
||||
const char *serdes_clock_to_string(u32 clock);
|
||||
int get_serdes_protocol(void);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_HAS_SERDES
|
||||
/* Get the volt of SVDD in unit mV */
|
||||
int get_serdes_volt(void);
|
||||
/* Set the volt of SVDD in unit mV */
|
||||
int set_serdes_volt(int svdd);
|
||||
/* The target volt of SVDD in unit mV */
|
||||
int setup_serdes_volt(u32 svdd);
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_SERDES_H__ */
|
||||
+709
@@ -0,0 +1,709 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013-2015 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_FSL_LSCH2_IMMAP_H__
|
||||
#define __ARCH_FSL_LSCH2_IMMAP_H__
|
||||
|
||||
#include <fsl_immap.h>
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_DCSRBAR 0x20000000
|
||||
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
|
||||
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
|
||||
#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
|
||||
#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
|
||||
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
|
||||
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
|
||||
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
|
||||
#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
|
||||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
|
||||
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
|
||||
CONFIG_SYS_BMAN_MEM_BASE)
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
|
||||
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000)
|
||||
|
||||
#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
|
||||
|
||||
#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
|
||||
#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
|
||||
|
||||
#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000)
|
||||
#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000)
|
||||
#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000)
|
||||
#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000)
|
||||
|
||||
#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000)
|
||||
|
||||
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
|
||||
|
||||
#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000)
|
||||
|
||||
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
|
||||
|
||||
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
|
||||
#define QMAN_CQSIDR_REG 0x20a80
|
||||
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
|
||||
/* LUT registers */
|
||||
#ifdef CONFIG_ARCH_LS1012A
|
||||
#define PCIE_LUT_BASE 0xC0000
|
||||
#else
|
||||
#define PCIE_LUT_BASE 0x10000
|
||||
#endif
|
||||
#define PCIE_LUT_LCTRL0 0x7F8
|
||||
#define PCIE_LUT_DBG 0x7FC
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
|
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
|
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
|
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
|
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
|
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
|
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
|
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
|
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
|
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
|
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
|
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
|
||||
|
||||
#define TP_ITYP_AV 0x00000001 /* Initiator available */
|
||||
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
|
||||
#define TP_ITYP_TYPE_ARM 0x0
|
||||
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
|
||||
#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
|
||||
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
|
||||
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
|
||||
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
|
||||
#define TY_ITYP_VER_A7 0x1
|
||||
#define TY_ITYP_VER_A53 0x2
|
||||
#define TY_ITYP_VER_A57 0x3
|
||||
#define TY_ITYP_VER_A72 0x4
|
||||
|
||||
#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
|
||||
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
|
||||
#define TP_INIT_PER_CLUSTER 4
|
||||
|
||||
/*
|
||||
* Define default values for some CCSR macros to make header files cleaner*
|
||||
*
|
||||
* To completely disable CCSR relocation in a board header file, define
|
||||
* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
|
||||
* to a value that is the same as CONFIG_SYS_CCSRBAR.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_CCSRBAR_PHYS
|
||||
#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
|
||||
CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
|
||||
#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
|
||||
#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR
|
||||
#define CONFIG_SYS_CCSRBAR 0x01000000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
|
||||
CONFIG_SYS_CCSRBAR_PHYS_LOW)
|
||||
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
/* frequency of platform PLL */
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
unsigned long freq_localbus;
|
||||
unsigned long freq_cga_m2;
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
|
||||
#endif
|
||||
unsigned long freq_qman;
|
||||
};
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
|
||||
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
|
||||
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
|
||||
#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
|
||||
#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
|
||||
#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
|
||||
#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
|
||||
#define CONFIG_SYS_FSL_FM1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
|
||||
#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
|
||||
#define FSL_SEC_JR1_OFFSET 0x720000ull
|
||||
#define FSL_SEC_JR2_OFFSET 0x730000ull
|
||||
#define FSL_SEC_JR3_OFFSET 0x740000ull
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
|
||||
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
|
||||
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
|
||||
#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
|
||||
|
||||
/* Device Configuration and Pin Control */
|
||||
#define DCFG_DCSR_PORCR1 0x0
|
||||
#define DCFG_DCSR_ECCCR2 0x524
|
||||
#define DISABLE_PFE_ECC BIT(13)
|
||||
|
||||
struct ccsr_gur {
|
||||
u32 porsr1; /* POR status 1 */
|
||||
#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
|
||||
u32 porsr2; /* POR status 2 */
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u32 gpporcr2;
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F
|
||||
u32 dcfg_fusesr; /* Fuse status register */
|
||||
u8 res_02c[0x70-0x2c];
|
||||
u32 devdisr; /* Device disable control */
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
|
||||
u32 devdisr2; /* Device disable control 2 */
|
||||
u32 devdisr3; /* Device disable control 3 */
|
||||
u32 devdisr4; /* Device disable control 4 */
|
||||
u32 devdisr5; /* Device disable control 5 */
|
||||
u32 devdisr6; /* Device disable control 6 */
|
||||
u32 devdisr7; /* Device disable control 7 */
|
||||
u8 res_08c[0x94-0x8c];
|
||||
u32 coredisru; /* uppper portion for support of 64 cores */
|
||||
u32 coredisrl; /* lower portion for support of 64 cores */
|
||||
u8 res_09c[0xa0-0x9c];
|
||||
u32 pvr; /* Processor version */
|
||||
u32 svr; /* System version */
|
||||
u32 mvr; /* Manufacturing version */
|
||||
u8 res_0ac[0xb0-0xac];
|
||||
u32 rstcr; /* Reset control */
|
||||
u32 rstrqpblsr; /* Reset request preboot loader status */
|
||||
u8 res_0b8[0xc0-0xb8];
|
||||
u32 rstrqmr1; /* Reset request mask */
|
||||
u8 res_0c4[0xc8-0xc4];
|
||||
u32 rstrqsr1; /* Reset request status */
|
||||
u8 res_0cc[0xd4-0xcc];
|
||||
u32 rstrqwdtmrl; /* Reset request WDT mask */
|
||||
u8 res_0d8[0xdc-0xd8];
|
||||
u32 rstrqwdtsrl; /* Reset request WDT status */
|
||||
u8 res_0e0[0xe4-0xe0];
|
||||
u32 brrl; /* Boot release */
|
||||
u8 res_0e8[0x100-0xe8];
|
||||
u32 rcwsr[16]; /* Reset control word status */
|
||||
#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
|
||||
#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
|
||||
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
|
||||
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
|
||||
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
|
||||
#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
|
||||
#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
|
||||
#define RCW_SB_EN_REG_INDEX 7
|
||||
#define RCW_SB_EN_MASK 0x00200000
|
||||
|
||||
u8 res_140[0x200-0x140];
|
||||
u32 scratchrw[4]; /* Scratch Read/Write */
|
||||
u8 res_210[0x300-0x210];
|
||||
u32 scratchw1r[4]; /* Scratch Read (Write once) */
|
||||
u8 res_310[0x400-0x310];
|
||||
u32 crstsr[12];
|
||||
u8 res_430[0x500-0x430];
|
||||
|
||||
/* PCI Express n Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_pex1liodnr;
|
||||
u32 dcfg_ccsr_pex2liodnr;
|
||||
u32 dcfg_ccsr_pex3liodnr;
|
||||
u32 dcfg_ccsr_pex4liodnr;
|
||||
/* RIO n Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_rio1liodnr;
|
||||
u32 dcfg_ccsr_rio2liodnr;
|
||||
u32 dcfg_ccsr_rio3liodnr;
|
||||
u32 dcfg_ccsr_rio4liodnr;
|
||||
/* USB Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_usb1liodnr;
|
||||
u32 dcfg_ccsr_usb2liodnr;
|
||||
u32 dcfg_ccsr_usb3liodnr;
|
||||
u32 dcfg_ccsr_usb4liodnr;
|
||||
/* SD/MMC Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_sdmmc1liodnr;
|
||||
u32 dcfg_ccsr_sdmmc2liodnr;
|
||||
u32 dcfg_ccsr_sdmmc3liodnr;
|
||||
u32 dcfg_ccsr_sdmmc4liodnr;
|
||||
/* RIO Message Unit Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_riomaintliodnr;
|
||||
|
||||
u8 res_544[0x550-0x544];
|
||||
u32 sataliodnr[4];
|
||||
u8 res_560[0x570-0x560];
|
||||
|
||||
u32 dcfg_ccsr_misc1liodnr;
|
||||
u32 dcfg_ccsr_misc2liodnr;
|
||||
u32 dcfg_ccsr_misc3liodnr;
|
||||
u32 dcfg_ccsr_misc4liodnr;
|
||||
u32 dcfg_ccsr_dma1liodnr;
|
||||
u32 dcfg_ccsr_dma2liodnr;
|
||||
u32 dcfg_ccsr_dma3liodnr;
|
||||
u32 dcfg_ccsr_dma4liodnr;
|
||||
u32 dcfg_ccsr_spare1liodnr;
|
||||
u32 dcfg_ccsr_spare2liodnr;
|
||||
u32 dcfg_ccsr_spare3liodnr;
|
||||
u32 dcfg_ccsr_spare4liodnr;
|
||||
u8 res_5a0[0x600-0x5a0];
|
||||
u32 dcfg_ccsr_pblsr;
|
||||
|
||||
u32 pamubypenr;
|
||||
u32 dmacr1;
|
||||
|
||||
u8 res_60c[0x610-0x60c];
|
||||
u32 dcfg_ccsr_gensr1;
|
||||
u32 dcfg_ccsr_gensr2;
|
||||
u32 dcfg_ccsr_gensr3;
|
||||
u32 dcfg_ccsr_gensr4;
|
||||
u32 dcfg_ccsr_gencr1;
|
||||
u32 dcfg_ccsr_gencr2;
|
||||
u32 dcfg_ccsr_gencr3;
|
||||
u32 dcfg_ccsr_gencr4;
|
||||
u32 dcfg_ccsr_gencr5;
|
||||
u32 dcfg_ccsr_gencr6;
|
||||
u32 dcfg_ccsr_gencr7;
|
||||
u8 res_63c[0x658-0x63c];
|
||||
u32 dcfg_ccsr_cgensr1;
|
||||
u32 dcfg_ccsr_cgensr0;
|
||||
u8 res_660[0x678-0x660];
|
||||
u32 dcfg_ccsr_cgencr1;
|
||||
|
||||
u32 dcfg_ccsr_cgencr0;
|
||||
u8 res_680[0x700-0x680];
|
||||
u32 dcfg_ccsr_sriopstecr;
|
||||
u32 dcfg_ccsr_dcsrcr;
|
||||
|
||||
u8 res_708[0x740-0x708]; /* add more registers when needed */
|
||||
u32 tp_ityp[64]; /* Topology Initiator Type Register */
|
||||
struct {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
} tp_cluster[16];
|
||||
u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
|
||||
u32 dcfg_ccsr_qmbm_warmrst;
|
||||
u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
|
||||
u32 dcfg_ccsr_reserved0;
|
||||
u32 dcfg_ccsr_reserved1;
|
||||
};
|
||||
|
||||
#define SCFG_QSPI_CLKSEL 0x40100000
|
||||
#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
|
||||
#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
|
||||
#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002
|
||||
#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
|
||||
#define SCFG_USBPWRFAULT_SHARED 0x00000001
|
||||
#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
|
||||
#define SCFG_USBPWRFAULT_USB3_SHIFT 4
|
||||
#define SCFG_USBPWRFAULT_USB2_SHIFT 2
|
||||
#define SCFG_USBPWRFAULT_USB1_SHIFT 0
|
||||
|
||||
#define SCFG_BASE 0x01570000
|
||||
#define SCFG_USB3PRM1CR_USB1 0x070
|
||||
#define SCFG_USB3PRM2CR_USB1 0x074
|
||||
#define SCFG_USB3PRM1CR_USB2 0x07C
|
||||
#define SCFG_USB3PRM2CR_USB2 0x080
|
||||
#define SCFG_USB3PRM1CR_USB3 0x088
|
||||
#define SCFG_USB3PRM2CR_USB3 0x08c
|
||||
#define SCFG_USB_TXVREFTUNE 0x9
|
||||
#define SCFG_USB_SQRXTUNE_MASK 0x7
|
||||
#define SCFG_USB_PCSTXSWINGFULL 0x47
|
||||
#define SCFG_USB_PHY1 0x084F0000
|
||||
#define SCFG_USB_PHY2 0x08500000
|
||||
#define SCFG_USB_PHY3 0x08510000
|
||||
#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c
|
||||
#define USB_PHY_RX_EQ_VAL_1 0x0000
|
||||
#define USB_PHY_RX_EQ_VAL_2 0x0080
|
||||
#define USB_PHY_RX_EQ_VAL_3 0x0380
|
||||
#define USB_PHY_RX_EQ_VAL_4 0x0b80
|
||||
|
||||
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
|
||||
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
|
||||
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
|
||||
#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
|
||||
#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
|
||||
#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
|
||||
#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
|
||||
#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
|
||||
#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
|
||||
#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
|
||||
|
||||
/* RGMIIPCR bit definitions*/
|
||||
#define SCFG_RGMIIPCR_EN_AUTO BIT(3)
|
||||
#define SCFG_RGMIIPCR_SETSP_1000M BIT(2)
|
||||
#define SCFG_RGMIIPCR_SETSP_100M 0
|
||||
#define SCFG_RGMIIPCR_SETSP_10M BIT(1)
|
||||
#define SCFG_RGMIIPCR_SETFD BIT(0)
|
||||
|
||||
/* PFEASBCR bit definitions */
|
||||
#define SCFG_PFEASBCR_ARCACHE0 BIT(31)
|
||||
#define SCFG_PFEASBCR_AWCACHE0 BIT(30)
|
||||
#define SCFG_PFEASBCR_ARCACHE1 BIT(29)
|
||||
#define SCFG_PFEASBCR_AWCACHE1 BIT(28)
|
||||
#define SCFG_PFEASBCR_ARSNP BIT(27)
|
||||
#define SCFG_PFEASBCR_AWSNP BIT(26)
|
||||
|
||||
/* WR_QoS1 PFE bit definitions */
|
||||
#define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24)
|
||||
#define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20)
|
||||
|
||||
/* RD_QoS1 PFE bit definitions */
|
||||
#define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24)
|
||||
#define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20)
|
||||
|
||||
/* Supplemental Configuration Unit */
|
||||
struct ccsr_scfg {
|
||||
u8 res_000[0x100-0x000];
|
||||
u32 usb2_icid;
|
||||
u32 usb3_icid;
|
||||
u8 res_108[0x114-0x108];
|
||||
u32 dma_icid;
|
||||
u32 sata_icid;
|
||||
u32 usb1_icid;
|
||||
u32 qe_icid;
|
||||
u32 sdhc_icid;
|
||||
u32 edma_icid;
|
||||
u32 etr_icid;
|
||||
u32 core_sft_rst[4];
|
||||
u8 res_140[0x158-0x140];
|
||||
u32 altcbar;
|
||||
u32 qspi_cfg;
|
||||
u8 res_160[0x164 - 0x160];
|
||||
u32 wr_qos1;
|
||||
u32 wr_qos2;
|
||||
u32 rd_qos1;
|
||||
u32 rd_qos2;
|
||||
u8 res_174[0x180 - 0x174];
|
||||
u32 dmamcr;
|
||||
u8 res_184[0x188-0x184];
|
||||
u32 gic_align;
|
||||
u32 debug_icid;
|
||||
u8 res_190[0x1a4-0x190];
|
||||
u32 snpcnfgcr;
|
||||
u8 res_1a8[0x1ac-0x1a8];
|
||||
u32 intpcr;
|
||||
u8 res_1b0[0x204-0x1b0];
|
||||
u32 coresrencr;
|
||||
u8 res_208[0x220-0x208];
|
||||
u32 rvbar0_0;
|
||||
u32 rvbar0_1;
|
||||
u32 rvbar1_0;
|
||||
u32 rvbar1_1;
|
||||
u32 rvbar2_0;
|
||||
u32 rvbar2_1;
|
||||
u32 rvbar3_0;
|
||||
u32 rvbar3_1;
|
||||
u32 lpmcsr;
|
||||
u8 res_244[0x400-0x244];
|
||||
u32 qspidqscr;
|
||||
u32 ecgtxcmcr;
|
||||
u32 sdhciovselcr;
|
||||
u32 rcwpmuxcr0;
|
||||
u32 usbdrvvbus_selcr;
|
||||
u32 usbpwrfault_selcr;
|
||||
u32 usb_refclk_selcr1;
|
||||
u32 usb_refclk_selcr2;
|
||||
u32 usb_refclk_selcr3;
|
||||
u8 res_424[0x434 - 0x424];
|
||||
u32 rgmiipcr;
|
||||
u32 res_438;
|
||||
u32 rgmiipsr;
|
||||
u32 pfepfcssr1;
|
||||
u32 pfeintencr1;
|
||||
u32 pfepfcssr2;
|
||||
u32 pfeintencr2;
|
||||
u32 pfeerrcr;
|
||||
u32 pfeeerrintencr;
|
||||
u32 pfeasbcr;
|
||||
u32 pfebsbcr;
|
||||
u8 res_460[0x484 - 0x460];
|
||||
u32 mdioselcr;
|
||||
u8 res_468[0x600 - 0x488];
|
||||
u32 scratchrw[4];
|
||||
u8 res_610[0x680-0x610];
|
||||
u32 corebcr;
|
||||
u8 res_684[0x1000-0x684];
|
||||
u32 pex1msiir;
|
||||
u32 pex1msir;
|
||||
u8 res_1008[0x2000-0x1008];
|
||||
u32 pex2;
|
||||
u32 pex2msir;
|
||||
u8 res_2008[0x3000-0x2008];
|
||||
u32 pex3msiir;
|
||||
u32 pex3msir;
|
||||
};
|
||||
|
||||
/* Clocking */
|
||||
struct ccsr_clk {
|
||||
struct {
|
||||
u32 clkcncsr; /* core cluster n clock control status */
|
||||
u8 res_004[0x0c];
|
||||
u32 clkcghwacsr; /* Clock generator n hardware accelerator */
|
||||
u8 res_014[0x0c];
|
||||
} clkcsr[4];
|
||||
u8 res_040[0x780]; /* 0x100 */
|
||||
struct {
|
||||
u32 pllcngsr;
|
||||
u8 res_804[0x1c];
|
||||
} pllcgsr[2];
|
||||
u8 res_840[0x1c0];
|
||||
u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
|
||||
u8 res_a04[0x1fc];
|
||||
u32 pllpgsr; /* 0xc00 Platform PLL General Status */
|
||||
u8 res_c04[0x1c];
|
||||
u32 plldgsr; /* 0xc20 DDR PLL General Status */
|
||||
u8 res_c24[0x3dc];
|
||||
};
|
||||
|
||||
/* System Counter */
|
||||
struct sctr_regs {
|
||||
u32 cntcr;
|
||||
u32 cntsr;
|
||||
u32 cntcv1;
|
||||
u32 cntcv2;
|
||||
u32 resv1[4];
|
||||
u32 cntfid0;
|
||||
u32 cntfid1;
|
||||
u32 resv2[1002];
|
||||
u32 counterid[12];
|
||||
};
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
struct ccsr_serdes {
|
||||
struct {
|
||||
u32 rstctl; /* Reset Control Register */
|
||||
#define SRDS_RSTCTL_RST 0x80000000
|
||||
#define SRDS_RSTCTL_RSTDONE 0x40000000
|
||||
#define SRDS_RSTCTL_RSTERR 0x20000000
|
||||
#define SRDS_RSTCTL_SWRST 0x10000000
|
||||
#define SRDS_RSTCTL_SDEN 0x00000020
|
||||
#define SRDS_RSTCTL_SDRST_B 0x00000040
|
||||
#define SRDS_RSTCTL_PLLRST_B 0x00000080
|
||||
u32 pllcr0; /* PLL Control Register 0 */
|
||||
#define SRDS_PLLCR0_POFF 0x80000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
|
||||
#define SRDS_PLLCR0_PLL_LCK 0x00800000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
|
||||
u32 pllcr1; /* PLL Control Register 1 */
|
||||
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
|
||||
u32 res_0c; /* 0x00c */
|
||||
u32 pllcr3;
|
||||
u32 pllcr4;
|
||||
u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */
|
||||
u8 res_1c[0x20-0x1c];
|
||||
} bank[2];
|
||||
u8 res_40[0x90-0x40];
|
||||
u32 srdstcalcr; /* 0x90 TX Calibration Control */
|
||||
u8 res_94[0xa0-0x94];
|
||||
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
|
||||
u8 res_a4[0xb0-0xa4];
|
||||
u32 srdsgr0; /* 0xb0 General Register 0 */
|
||||
u8 res_b4[0x100-0xb4];
|
||||
struct {
|
||||
u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */
|
||||
u8 res_104[0x120-0x104];
|
||||
} lnpssr[4]; /* Lane A, B, C, D */
|
||||
u8 res_180[0x200-0x180];
|
||||
u32 srdspccr0; /* 0x200 Protocol Configuration 0 */
|
||||
u32 srdspccr1; /* 0x204 Protocol Configuration 1 */
|
||||
u32 srdspccr2; /* 0x208 Protocol Configuration 2 */
|
||||
u32 srdspccr3; /* 0x20c Protocol Configuration 3 */
|
||||
u32 srdspccr4; /* 0x210 Protocol Configuration 4 */
|
||||
u32 srdspccr5; /* 0x214 Protocol Configuration 5 */
|
||||
u32 srdspccr6; /* 0x218 Protocol Configuration 6 */
|
||||
u32 srdspccr7; /* 0x21c Protocol Configuration 7 */
|
||||
u32 srdspccr8; /* 0x220 Protocol Configuration 8 */
|
||||
u32 srdspccr9; /* 0x224 Protocol Configuration 9 */
|
||||
u32 srdspccra; /* 0x228 Protocol Configuration A */
|
||||
u32 srdspccrb; /* 0x22c Protocol Configuration B */
|
||||
u8 res_230[0x800-0x230];
|
||||
struct {
|
||||
u32 gcr0; /* 0x800 General Control Register 0 */
|
||||
u32 gcr1; /* 0x804 General Control Register 1 */
|
||||
u32 gcr2; /* 0x808 General Control Register 2 */
|
||||
u32 sscr0;
|
||||
u32 recr0; /* 0x810 Receive Equalization Control */
|
||||
u32 recr1;
|
||||
u32 tecr0; /* 0x818 Transmit Equalization Control */
|
||||
u32 sscr1;
|
||||
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
|
||||
u8 res_824[0x83c-0x824];
|
||||
u32 tcsr3;
|
||||
} lane[4]; /* Lane A, B, C, D */
|
||||
u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */
|
||||
struct {
|
||||
u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */
|
||||
u8 res_1004[0x1040-0x1004];
|
||||
} pcie[3];
|
||||
u8 res_10c0[0x1800-0x10c0];
|
||||
struct {
|
||||
u8 res_1800[0x1804-0x1800];
|
||||
u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */
|
||||
u8 res_1808[0x180c-0x1808];
|
||||
u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */
|
||||
} sgmii[4]; /* Lane A, B, C, D */
|
||||
u8 res_1840[0x1880-0x1840];
|
||||
struct {
|
||||
u8 res_1880[0x1884-0x1880];
|
||||
u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */
|
||||
u8 res_1888[0x188c-0x1888];
|
||||
u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */
|
||||
} qsgmii[2]; /* Lane A, B */
|
||||
u8 res_18a0[0x1980-0x18a0];
|
||||
struct {
|
||||
u8 res_1980[0x1984-0x1980];
|
||||
u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */
|
||||
u8 res_1988[0x198c-0x1988];
|
||||
u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
|
||||
} xfi[2]; /* Lane A, B */
|
||||
u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
|
||||
};
|
||||
|
||||
struct ccsr_gpio {
|
||||
u32 gpdir;
|
||||
u32 gpodr;
|
||||
u32 gpdat;
|
||||
u32 gpier;
|
||||
u32 gpimr;
|
||||
u32 gpicr;
|
||||
u32 gpibe;
|
||||
};
|
||||
|
||||
/* MMU 500 */
|
||||
#define SMMU_SCR0 (SMMU_BASE + 0x0)
|
||||
#define SMMU_SCR1 (SMMU_BASE + 0x4)
|
||||
#define SMMU_SCR2 (SMMU_BASE + 0x8)
|
||||
#define SMMU_SACR (SMMU_BASE + 0x10)
|
||||
#define SMMU_IDR0 (SMMU_BASE + 0x20)
|
||||
#define SMMU_IDR1 (SMMU_BASE + 0x24)
|
||||
|
||||
#define SMMU_NSCR0 (SMMU_BASE + 0x400)
|
||||
#define SMMU_NSCR2 (SMMU_BASE + 0x408)
|
||||
#define SMMU_NSACR (SMMU_BASE + 0x410)
|
||||
|
||||
#define SCR0_CLIENTPD_MASK 0x00000001
|
||||
#define SCR0_USFCFG_MASK 0x00000400
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
#define RCW_SRC_MASK (0xFF800000)
|
||||
#define RCW_SRC_BIT 23
|
||||
|
||||
/* RCW SRC NAND */
|
||||
#define RCW_SRC_NAND_MASK (0x100)
|
||||
#define RCW_SRC_NAND_VAL (0x100)
|
||||
#define NAND_RESERVED_MASK (0xFC)
|
||||
#define NAND_RESERVED_1 (0x0)
|
||||
#define NAND_RESERVED_2 (0x80)
|
||||
|
||||
/* RCW SRC NOR */
|
||||
#define RCW_SRC_NOR_MASK (0x1F0)
|
||||
#define NOR_8B_VAL (0x10)
|
||||
#define NOR_16B_VAL (0x20)
|
||||
#define SD_VAL (0x40)
|
||||
#define QSPI_VAL1 (0x44)
|
||||
#define QSPI_VAL2 (0x45)
|
||||
#endif
|
||||
|
||||
uint get_svr(void);
|
||||
|
||||
#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/
|
||||
+576
@@ -0,0 +1,576 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* LayerScape Internal Memory Map
|
||||
*
|
||||
* Copyright 2017-2019 NXP
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
#define __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
|
||||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||
#ifdef CONFIG_ARCH_LX2160A
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
|
||||
#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR
|
||||
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
|
||||
#ifndef CONFIG_NXP_LSCH3_2
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
|
||||
#endif
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
|
||||
#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
|
||||
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
|
||||
0x18A0)
|
||||
#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
|
||||
#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
|
||||
|
||||
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
|
||||
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
|
||||
#ifdef CONFIG_NXP_LSCH3_2
|
||||
#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000)
|
||||
#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000)
|
||||
#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000)
|
||||
#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000)
|
||||
#endif
|
||||
#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
|
||||
#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
|
||||
#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
|
||||
|
||||
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
|
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
|
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
|
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
|
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
|
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
|
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
|
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
|
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
|
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
|
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
|
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
|
||||
|
||||
/* EDMA */
|
||||
#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000)
|
||||
|
||||
/* SATA */
|
||||
#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
|
||||
#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
|
||||
#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000)
|
||||
#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000)
|
||||
|
||||
/* QDMA */
|
||||
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
|
||||
#define QMAN_CQSIDR_REG 0x20a80
|
||||
|
||||
/* DISPLAY */
|
||||
#define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000)
|
||||
|
||||
/* GPU */
|
||||
#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
|
||||
|
||||
/* SEC */
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
|
||||
#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
|
||||
#define FSL_SEC_JR1_OFFSET 0x07020000ull
|
||||
#define FSL_SEC_JR2_OFFSET 0x07030000ull
|
||||
#define FSL_SEC_JR3_OFFSET 0x07040000ull
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
|
||||
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
|
||||
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
|
||||
#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
#ifdef CONFIG_NXP_LSCH3_2
|
||||
/* RCW_SRC field in Power-On Reset Control Register 1 */
|
||||
#define RCW_SRC_MASK 0x07800000
|
||||
#define RCW_SRC_BIT 23
|
||||
|
||||
/* CFG_RCW_SRC[3:0] */
|
||||
#define RCW_SRC_TYPE_MASK 0x8
|
||||
#define RCW_SRC_ADDR_OFFSET_8MB 0x800000
|
||||
|
||||
/* RCW SRC HARDCODED */
|
||||
#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */
|
||||
|
||||
#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */
|
||||
#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */
|
||||
#define RCW_SRC_I2C1_VAL 0xa /* 0xa */
|
||||
#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */
|
||||
#define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */
|
||||
#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */
|
||||
#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */
|
||||
#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */
|
||||
#else
|
||||
#define RCW_SRC_MASK (0xFF800000)
|
||||
#define RCW_SRC_BIT 23
|
||||
/* CFG_RCW_SRC[6:0] */
|
||||
#define RCW_SRC_TYPE_MASK (0x70)
|
||||
|
||||
/* RCW SRC HARDCODED */
|
||||
#define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */
|
||||
/* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */
|
||||
|
||||
/* RCW SRC NOR */
|
||||
#define RCW_SRC_NOR_VAL (0x20)
|
||||
#define NOR_TYPE_MASK (0x10)
|
||||
#define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */
|
||||
#define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */
|
||||
|
||||
/* RCW SRC Serial Flash
|
||||
* 1. SERIAL NOR (QSPI)
|
||||
* 2. OTHERS (SD/MMC, SPI, I2C1
|
||||
*/
|
||||
#define RCW_SRC_SERIAL_MASK (0x7F)
|
||||
#define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */
|
||||
#define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */
|
||||
#define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */
|
||||
#define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
|
||||
|
||||
/* MMU 500 */
|
||||
#define SMMU_SCR0 (SMMU_BASE + 0x0)
|
||||
#define SMMU_SCR1 (SMMU_BASE + 0x4)
|
||||
#define SMMU_SCR2 (SMMU_BASE + 0x8)
|
||||
#define SMMU_SACR (SMMU_BASE + 0x10)
|
||||
#define SMMU_IDR0 (SMMU_BASE + 0x20)
|
||||
#define SMMU_IDR1 (SMMU_BASE + 0x24)
|
||||
|
||||
#define SMMU_NSCR0 (SMMU_BASE + 0x400)
|
||||
#define SMMU_NSCR2 (SMMU_BASE + 0x408)
|
||||
#define SMMU_NSACR (SMMU_BASE + 0x410)
|
||||
|
||||
#define SCR0_CLIENTPD_MASK 0x00000001
|
||||
#define SCR0_USFCFG_MASK 0x00000400
|
||||
|
||||
|
||||
/* PCIe */
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
|
||||
#ifdef CONFIG_ARCH_LX2160A
|
||||
#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
|
||||
#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_LX2160A
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
|
||||
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL
|
||||
#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL
|
||||
#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL
|
||||
#elif CONFIG_ARCH_LS1088A
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
|
||||
#elif CONFIG_ARCH_LS1028A
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL
|
||||
/* this is used by integrated PCI on LS1028, includes ECAM and register space */
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
|
||||
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
|
||||
#endif
|
||||
|
||||
/* Device Configuration */
|
||||
#define DCFG_BASE 0x01e00000
|
||||
#define DCFG_PORSR1 0x000
|
||||
#define DCFG_PORSR1_RCW_SRC 0xff800000
|
||||
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
|
||||
#define DCFG_RCWSR13 0x130
|
||||
#define DCFG_RCWSR13_DSPI (0 << 8)
|
||||
#define DCFG_RCWSR15 0x138
|
||||
#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
|
||||
|
||||
#define DCFG_DCSR_BASE 0X700100000ULL
|
||||
#define DCFG_DCSR_PORCR1 0x000
|
||||
|
||||
/* Interrupt Sampling Control */
|
||||
#define ISC_BASE 0x01F70000
|
||||
#define IRQCR_OFFSET 0x14
|
||||
|
||||
/* Supplemental Configuration */
|
||||
#define SCFG_BASE 0x01fc0000
|
||||
#define SCFG_USB3PRM1CR 0x000
|
||||
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
|
||||
#define SCFG_USB_TXVREFTUNE 0x9
|
||||
#define SCFG_USB_SQRXTUNE_MASK 0x7
|
||||
#define SCFG_QSPICLKCTLR 0x10
|
||||
|
||||
#define DCSR_BASE 0x700000000ULL
|
||||
#define DCSR_USB_PHY1 0x4600000
|
||||
#define DCSR_USB_PHY2 0x4610000
|
||||
#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
|
||||
#define USB_PHY_RX_EQ_VAL_1 0x0000
|
||||
#define USB_PHY_RX_EQ_VAL_2 0x0080
|
||||
#define USB_PHY_RX_EQ_VAL_3 0x0380
|
||||
#define USB_PHY_RX_EQ_VAL_4 0x0b80
|
||||
#define DCSR_USB_IOCR1 0x108004
|
||||
#define DCSR_USB_PCSTXSWINGFULL 0x71
|
||||
|
||||
#define TP_ITYP_AV 0x00000001 /* Initiator available */
|
||||
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
|
||||
#define TP_ITYP_TYPE_ARM 0x0
|
||||
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
|
||||
#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
|
||||
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
|
||||
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
|
||||
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
|
||||
#define TY_ITYP_VER_A7 0x1
|
||||
#define TY_ITYP_VER_A53 0x2
|
||||
#define TY_ITYP_VER_A57 0x3
|
||||
#define TY_ITYP_VER_A72 0x4
|
||||
|
||||
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
|
||||
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
|
||||
#define TP_INIT_PER_CLUSTER 4
|
||||
/* This is chassis generation 3 */
|
||||
#ifndef __ASSEMBLY__
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
/* frequency of platform PLL */
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
unsigned long freq_cga_m2;
|
||||
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
||||
unsigned long freq_ddrbus2;
|
||||
#endif
|
||||
unsigned long freq_localbus;
|
||||
unsigned long freq_qe;
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN
|
||||
unsigned long freq_qman;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DPAA_PME
|
||||
unsigned long freq_pme;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Global Utilities Block */
|
||||
struct ccsr_gur {
|
||||
u32 porsr1; /* POR status 1 */
|
||||
u32 porsr2; /* POR status 2 */
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u32 gpporcr2; /* General-purpose POR configuration 2 */
|
||||
u32 gpporcr3;
|
||||
u32 gpporcr4;
|
||||
u8 res_030[0x60-0x30];
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
|
||||
#if defined(CONFIG_ARCH_LS1088A)
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
|
||||
#else
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
|
||||
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
|
||||
#endif
|
||||
u32 dcfg_fusesr; /* Fuse status register */
|
||||
u8 res_064[0x70-0x64];
|
||||
u32 devdisr; /* Device disable control 1 */
|
||||
u32 devdisr2; /* Device disable control 2 */
|
||||
u32 devdisr3; /* Device disable control 3 */
|
||||
u32 devdisr4; /* Device disable control 4 */
|
||||
u32 devdisr5; /* Device disable control 5 */
|
||||
u32 devdisr6; /* Device disable control 6 */
|
||||
u8 res_088[0x94-0x88];
|
||||
u32 coredisr; /* Device disable control 7 */
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
|
||||
#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
|
||||
u8 res_098[0xa0-0x98];
|
||||
u32 pvr; /* Processor version */
|
||||
u32 svr; /* System version */
|
||||
u8 res_0a8[0x100-0xa8];
|
||||
u32 rcwsr[30]; /* Reset control word status */
|
||||
|
||||
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
|
||||
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
|
||||
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
|
||||
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
|
||||
#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
|
||||
|
||||
#if defined(CONFIG_ARCH_LS2080A)
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS1_REGSR 29
|
||||
#define FSL_CHASSIS3_SRDS2_REGSR 29
|
||||
#elif defined(CONFIG_ARCH_LX2160A)
|
||||
#define FSL_CHASSIS3_EC1_REGSR 27
|
||||
#define FSL_CHASSIS3_EC2_REGSR 27
|
||||
#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003
|
||||
#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0
|
||||
#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007
|
||||
#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS1_REGSR 29
|
||||
#define FSL_CHASSIS3_SRDS2_REGSR 29
|
||||
#define FSL_CHASSIS3_SRDS3_REGSR 29
|
||||
#define FSL_CHASSIS3_RCWSR12_REGSR 12
|
||||
#define FSL_CHASSIS3_RCWSR13_REGSR 13
|
||||
#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
|
||||
#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
|
||||
#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
|
||||
#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
|
||||
#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
|
||||
#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
|
||||
#elif defined(CONFIG_ARCH_LS1088A)
|
||||
#define FSL_CHASSIS3_EC1_REGSR 26
|
||||
#define FSL_CHASSIS3_EC2_REGSR 26
|
||||
#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
|
||||
#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
|
||||
#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
|
||||
#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
|
||||
#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
|
||||
#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
|
||||
#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
|
||||
#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS1_REGSR 29
|
||||
#define FSL_CHASSIS3_SRDS2_REGSR 30
|
||||
#elif defined(CONFIG_ARCH_LS1028A)
|
||||
#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
|
||||
#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS1_REGSR 29
|
||||
#endif
|
||||
#define RCW_SB_EN_REG_INDEX 9
|
||||
#define RCW_SB_EN_MASK 0x00000400
|
||||
|
||||
u8 res_178[0x200-0x178];
|
||||
u32 scratchrw[16]; /* Scratch Read/Write */
|
||||
u8 res_240[0x300-0x240];
|
||||
u32 scratchw1r[4]; /* Scratch Read (Write once) */
|
||||
u8 res_310[0x400-0x310];
|
||||
u32 bootlocptrl; /* Boot location pointer low-order addr */
|
||||
u32 bootlocptrh; /* Boot location pointer high-order addr */
|
||||
u8 res_408[0x520-0x408];
|
||||
u32 usb1_amqr;
|
||||
u32 usb2_amqr;
|
||||
u8 res_528[0x530-0x528]; /* add more registers when needed */
|
||||
u32 sdmm1_amqr;
|
||||
u32 sdmm2_amqr;
|
||||
u8 res_538[0x550 - 0x538]; /* add more registers when needed */
|
||||
u32 sata1_amqr;
|
||||
u32 sata2_amqr;
|
||||
u32 sata3_amqr;
|
||||
u32 sata4_amqr;
|
||||
u8 res_560[0x570 - 0x560]; /* add more registers when needed */
|
||||
u32 misc1_amqr;
|
||||
u8 res_574[0x590-0x574]; /* add more registers when needed */
|
||||
u32 spare1_amqr;
|
||||
u32 spare2_amqr;
|
||||
u32 spare3_amqr;
|
||||
u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */
|
||||
u32 gencr[7]; /* General Control Registers */
|
||||
u8 res_63c[0x640-0x63c]; /* add more registers when needed */
|
||||
u32 cgensr1; /* Core General Status Register */
|
||||
u8 res_644[0x660-0x644]; /* add more registers when needed */
|
||||
u32 cgencr1; /* Core General Control Register */
|
||||
u8 res_664[0x740-0x664]; /* add more registers when needed */
|
||||
u32 tp_ityp[64]; /* Topology Initiator Type Register */
|
||||
struct {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
} tp_cluster[4]; /* Core cluster n Topology Register */
|
||||
u8 res_864[0x920-0x864]; /* add more registers when needed */
|
||||
u32 ioqoscr[8]; /*I/O Quality of Services Register */
|
||||
u32 uccr;
|
||||
u8 res_944[0x960-0x944]; /* add more registers when needed */
|
||||
u32 ftmcr;
|
||||
u8 res_964[0x990-0x964]; /* add more registers when needed */
|
||||
u32 coredisablesr;
|
||||
u8 res_994[0xa00-0x994]; /* add more registers when needed */
|
||||
u32 sdbgcr; /*Secure Debug Confifuration Register */
|
||||
u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
|
||||
u32 ipbrr1;
|
||||
u32 ipbrr2;
|
||||
u8 res_858[0x1000-0xc00];
|
||||
};
|
||||
|
||||
struct ccsr_clk_cluster_group {
|
||||
struct {
|
||||
u8 res_00[0x10];
|
||||
u32 csr;
|
||||
u8 res_14[0x20-0x14];
|
||||
} hwncsr[3];
|
||||
u8 res_60[0x80-0x60];
|
||||
struct {
|
||||
u32 gsr;
|
||||
u8 res_84[0xa0-0x84];
|
||||
} pllngsr[3];
|
||||
u8 res_e0[0x100-0xe0];
|
||||
};
|
||||
|
||||
struct ccsr_clk_ctrl {
|
||||
struct {
|
||||
u32 csr; /* core cluster n clock control status */
|
||||
u8 res_04[0x20-0x04];
|
||||
} clkcncsr[8];
|
||||
};
|
||||
|
||||
struct ccsr_reset {
|
||||
u32 rstcr; /* 0x000 */
|
||||
u32 rstcrsp; /* 0x004 */
|
||||
u8 res_008[0x10-0x08]; /* 0x008 */
|
||||
u32 rstrqmr1; /* 0x010 */
|
||||
u32 rstrqmr2; /* 0x014 */
|
||||
u32 rstrqsr1; /* 0x018 */
|
||||
u32 rstrqsr2; /* 0x01c */
|
||||
u32 rstrqwdtmrl; /* 0x020 */
|
||||
u32 rstrqwdtmru; /* 0x024 */
|
||||
u8 res_028[0x30-0x28]; /* 0x028 */
|
||||
u32 rstrqwdtsrl; /* 0x030 */
|
||||
u32 rstrqwdtsru; /* 0x034 */
|
||||
u8 res_038[0x60-0x38]; /* 0x038 */
|
||||
u32 brrl; /* 0x060 */
|
||||
u32 brru; /* 0x064 */
|
||||
u8 res_068[0x80-0x68]; /* 0x068 */
|
||||
u32 pirset; /* 0x080 */
|
||||
u32 pirclr; /* 0x084 */
|
||||
u8 res_088[0x90-0x88]; /* 0x088 */
|
||||
u32 brcorenbr; /* 0x090 */
|
||||
u8 res_094[0x100-0x94]; /* 0x094 */
|
||||
u32 rcw_reqr; /* 0x100 */
|
||||
u32 rcw_completion; /* 0x104 */
|
||||
u8 res_108[0x110-0x108]; /* 0x108 */
|
||||
u32 pbi_reqr; /* 0x110 */
|
||||
u32 pbi_completion; /* 0x114 */
|
||||
u8 res_118[0xa00-0x118]; /* 0x118 */
|
||||
u32 qmbm_warmrst; /* 0xa00 */
|
||||
u32 soc_warmrst; /* 0xa04 */
|
||||
u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
|
||||
u32 ip_rev1; /* 0xbf8 */
|
||||
u32 ip_rev2; /* 0xbfc */
|
||||
};
|
||||
|
||||
struct ccsr_serdes {
|
||||
struct {
|
||||
u32 rstctl; /* Reset Control Register */
|
||||
u32 pllcr0; /* PLL Control Register 0 */
|
||||
u32 pllcr1; /* PLL Control Register 1 */
|
||||
u32 pllcr2; /* PLL Control Register 2 */
|
||||
u32 pllcr3; /* PLL Control Register 3 */
|
||||
u32 pllcr4; /* PLL Control Register 4 */
|
||||
u32 pllcr5; /* PLL Control Register 5 */
|
||||
u8 res[0x20 - 0x1c];
|
||||
} bank[2];
|
||||
u8 res1[0x90 - 0x40];
|
||||
u32 srdstcalcr; /* TX Calibration Control */
|
||||
u32 srdstcalcr1; /* TX Calibration Control1 */
|
||||
u8 res2[0xa0 - 0x98];
|
||||
u32 srdsrcalcr; /* RX Calibration Control */
|
||||
u32 srdsrcalcr1; /* RX Calibration Control1 */
|
||||
u8 res3[0xb0 - 0xa8];
|
||||
u32 srdsgr0; /* General Register 0 */
|
||||
u8 res4[0x800 - 0xb4];
|
||||
struct serdes_lane {
|
||||
u32 gcr0; /* General Control Register 0 */
|
||||
u32 gcr1; /* General Control Register 1 */
|
||||
u32 gcr2; /* General Control Register 2 */
|
||||
u32 ssc0; /* Speed Switch Control 0 */
|
||||
u32 rec0; /* Receive Equalization Control 0 */
|
||||
u32 rec1; /* Receive Equalization Control 1 */
|
||||
u32 tec0; /* Transmit Equalization Control 0 */
|
||||
u32 ssc1; /* Speed Switch Control 1 */
|
||||
u8 res1[0x840 - 0x820];
|
||||
} lane[8];
|
||||
u8 res5[0x19fc - 0xa00];
|
||||
};
|
||||
|
||||
#endif /*__ASSEMBLY__*/
|
||||
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
|
||||
@@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
|
||||
#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
|
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
|
||||
@@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015, Freescale Semiconductor
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
|
||||
void update_early_mmu_table(void);
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
|
||||
@@ -0,0 +1,51 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_MP_H
|
||||
#define _FSL_LAYERSCAPE_MP_H
|
||||
|
||||
/*
|
||||
* Each spin table element is defined as
|
||||
* struct {
|
||||
* uint64_t entry_addr;
|
||||
* uint64_t status;
|
||||
* uint64_t lpid;
|
||||
* uint64_t arch_comp;
|
||||
* };
|
||||
* we pad this struct to 64 bytes so each entry is in its own cacheline
|
||||
* the actual spin table is an array of these structures
|
||||
*/
|
||||
#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
|
||||
#define SPIN_TABLE_ELEM_STATUS_IDX 1
|
||||
#define SPIN_TABLE_ELEM_LPID_IDX 2
|
||||
/* compare os arch and cpu arch */
|
||||
#define SPIN_TABLE_ELEM_ARCH_COMP_IDX 3
|
||||
#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
|
||||
#define SPIN_TABLE_ELEM_SIZE 64
|
||||
|
||||
/* os arch is same as cpu arch */
|
||||
#define OS_ARCH_SAME 0
|
||||
/* os arch is different from cpu arch */
|
||||
#define OS_ARCH_DIFF 1
|
||||
|
||||
#define id_to_core(x) ((x & 3) | (x >> 6))
|
||||
#ifndef __ASSEMBLY__
|
||||
extern u64 __spin_table[];
|
||||
extern u64 __real_cntfrq;
|
||||
extern u64 *secondary_boot_code;
|
||||
extern size_t __secondary_boot_code_size;
|
||||
#ifdef CONFIG_MP
|
||||
int fsl_layerscape_wake_seconday_cores(void);
|
||||
#else
|
||||
static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
|
||||
#endif
|
||||
void *get_spin_tbl_addr(void);
|
||||
phys_addr_t determine_mp_bootpg(void);
|
||||
void secondary_boot_func(void);
|
||||
int is_core_online(u64 cpu_id);
|
||||
u32 cpu_pos_mask(void);
|
||||
#endif
|
||||
|
||||
#endif /* _FSL_LAYERSCAPE_MP_H */
|
||||
@@ -0,0 +1,91 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __FSL_NS_ACCESS_H_
|
||||
#define __FSL_NS_ACCESS_H_
|
||||
#include <fsl_csu.h>
|
||||
|
||||
enum csu_cslx_ind {
|
||||
CSU_CSLX_PCIE2_IO = 0,
|
||||
CSU_CSLX_PCIE1_IO,
|
||||
CSU_CSLX_MG2TPR_IP,
|
||||
CSU_CSLX_IFC_MEM,
|
||||
CSU_CSLX_OCRAM,
|
||||
CSU_CSLX_GIC,
|
||||
CSU_CSLX_PCIE1,
|
||||
CSU_CSLX_OCRAM2,
|
||||
CSU_CSLX_QSPI_MEM,
|
||||
CSU_CSLX_PCIE2,
|
||||
CSU_CSLX_SATA,
|
||||
CSU_CSLX_USB1,
|
||||
CSU_CSLX_QM_BM_SWPORTAL,
|
||||
CSU_CSLX_PCIE3 = 16,
|
||||
CSU_CSLX_PCIE3_IO,
|
||||
CSU_CSLX_USB3 = 20,
|
||||
CSU_CSLX_USB2,
|
||||
CSU_CSLX_PFE = 23,
|
||||
CSU_CSLX_SERDES = 32,
|
||||
CSU_CSLX_QDMA,
|
||||
CSU_CSLX_LPUART2,
|
||||
CSU_CSLX_LPUART1,
|
||||
CSU_CSLX_LPUART4,
|
||||
CSU_CSLX_LPUART3,
|
||||
CSU_CSLX_LPUART6,
|
||||
CSU_CSLX_LPUART5,
|
||||
CSU_CSLX_DSPI1 = 41,
|
||||
CSU_CSLX_QSPI,
|
||||
CSU_CSLX_ESDHC,
|
||||
CSU_CSLX_IFC = 45,
|
||||
CSU_CSLX_I2C1,
|
||||
CSU_CSLX_USB_2,
|
||||
CSU_CSLX_I2C3 = 48,
|
||||
CSU_CSLX_I2C2,
|
||||
CSU_CSLX_DUART2 = 50,
|
||||
CSU_CSLX_DUART1,
|
||||
CSU_CSLX_WDT2,
|
||||
CSU_CSLX_WDT1,
|
||||
CSU_CSLX_EDMA,
|
||||
CSU_CSLX_SYS_CNT,
|
||||
CSU_CSLX_DMA_MUX2,
|
||||
CSU_CSLX_DMA_MUX1,
|
||||
CSU_CSLX_DDR,
|
||||
CSU_CSLX_QUICC,
|
||||
CSU_CSLX_DCFG_CCU_RCPM = 60,
|
||||
CSU_CSLX_SECURE_BOOTROM,
|
||||
CSU_CSLX_SFP,
|
||||
CSU_CSLX_TMU,
|
||||
CSU_CSLX_SECURE_MONITOR,
|
||||
CSU_CSLX_SCFG,
|
||||
CSU_CSLX_FM = 66,
|
||||
CSU_CSLX_SEC5_5,
|
||||
CSU_CSLX_BM,
|
||||
CSU_CSLX_QM,
|
||||
CSU_CSLX_GPIO2 = 70,
|
||||
CSU_CSLX_GPIO1,
|
||||
CSU_CSLX_GPIO4,
|
||||
CSU_CSLX_GPIO3,
|
||||
CSU_CSLX_PLATFORM_CONT,
|
||||
CSU_CSLX_CSU,
|
||||
CSU_CSLX_IIC4 = 77,
|
||||
CSU_CSLX_WDT4,
|
||||
CSU_CSLX_WDT3,
|
||||
CSU_CSLX_ESDHC2 = 80,
|
||||
CSU_CSLX_WDT5 = 81,
|
||||
CSU_CSLX_SAI2,
|
||||
CSU_CSLX_SAI1,
|
||||
CSU_CSLX_SAI4,
|
||||
CSU_CSLX_SAI3,
|
||||
CSU_CSLX_FTM2 = 86,
|
||||
CSU_CSLX_FTM1,
|
||||
CSU_CSLX_FTM4,
|
||||
CSU_CSLX_FTM3,
|
||||
CSU_CSLX_FTM6 = 90,
|
||||
CSU_CSLX_FTM5,
|
||||
CSU_CSLX_FTM8,
|
||||
CSU_CSLX_FTM7,
|
||||
CSU_CSLX_DSCR = 121,
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2016 NXP Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __FSL_PPA_H_
|
||||
#define __FSL_PPA_H_
|
||||
|
||||
#ifdef CONFIG_FSL_LS_PPA
|
||||
int ppa_init(void);
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,156 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* Copyright 2015 Freescale Semiconductor
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/types.h>
|
||||
#ifdef CONFIG_FSL_LSCH2
|
||||
#include <asm/arch/immap_lsch2.h>
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#include <asm/arch/immap_lsch3.h>
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define gur_in32(a) in_le32(a)
|
||||
#define gur_out32(a, v) out_le32(a, v)
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
|
||||
#define gur_in32(a) in_be32(a)
|
||||
#define gur_out32(a, v) out_be32(a, v)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define scfg_in32(a) in_le32(a)
|
||||
#define scfg_out32(a, v) out_le32(a, v)
|
||||
#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
|
||||
#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
|
||||
#define scfg_in32(a) in_be32(a)
|
||||
#define scfg_out32(a, v) out_be32(a, v)
|
||||
#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
|
||||
#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
|
||||
#define pex_lut_in32(a) in_le32(a)
|
||||
#define pex_lut_out32(a, v) out_le32(a, v)
|
||||
#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
|
||||
#define pex_lut_in32(a) in_be32(a)
|
||||
#define pex_lut_out32(a, v) out_be32(a, v)
|
||||
#endif
|
||||
#ifndef __ASSEMBLY__
|
||||
struct cpu_type {
|
||||
char name[15];
|
||||
u32 soc_ver;
|
||||
u32 num_cores;
|
||||
};
|
||||
|
||||
#define CPU_TYPE_ENTRY(n, v, nc) \
|
||||
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
|
||||
|
||||
#ifdef CONFIG_TFABOOT
|
||||
#define SMC_DRAM_BANK_INFO (0xC200FF12)
|
||||
#define SIP_SVC_RCW 0xC200FF18
|
||||
|
||||
phys_size_t tfa_get_dram_size(void);
|
||||
|
||||
enum boot_src {
|
||||
BOOT_SOURCE_RESERVED = 0,
|
||||
BOOT_SOURCE_IFC_NOR,
|
||||
BOOT_SOURCE_IFC_NAND,
|
||||
BOOT_SOURCE_QSPI_NOR,
|
||||
BOOT_SOURCE_QSPI_NAND,
|
||||
BOOT_SOURCE_XSPI_NOR,
|
||||
BOOT_SOURCE_XSPI_NAND,
|
||||
BOOT_SOURCE_SD_MMC,
|
||||
BOOT_SOURCE_SD_MMC2,
|
||||
BOOT_SOURCE_I2C1_EXTENDED,
|
||||
};
|
||||
|
||||
enum boot_src get_boot_src(void);
|
||||
#endif
|
||||
#endif
|
||||
#define SVR_WO_E 0xFFFFFE
|
||||
#define SVR_LS1012A 0x870400
|
||||
#define SVR_LS1043A 0x879200
|
||||
#define SVR_LS1023A 0x879208
|
||||
/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
|
||||
#define SVR_LS1043A_P23 0x879202
|
||||
#define SVR_LS1023A_P23 0x87920A
|
||||
#define SVR_LS1017A 0x870B24
|
||||
#define SVR_LS1018A 0x870B20
|
||||
#define SVR_LS1027A 0x870B04
|
||||
#define SVR_LS1028A 0x870B00
|
||||
#define SVR_LS1046A 0x870700
|
||||
#define SVR_LS1026A 0x870708
|
||||
#define SVR_LS1048A 0x870320
|
||||
#define SVR_LS1084A 0x870302
|
||||
#define SVR_LS1088A 0x870300
|
||||
#define SVR_LS1044A 0x870322
|
||||
#define SVR_LS2045A 0x870120
|
||||
#define SVR_LS2080A 0x870110
|
||||
#define SVR_LS2085A 0x870100
|
||||
#define SVR_LS2040A 0x870130
|
||||
#define SVR_LS2088A 0x870900
|
||||
#define SVR_LS2084A 0x870910
|
||||
#define SVR_LS2048A 0x870920
|
||||
#define SVR_LS2044A 0x870930
|
||||
#define SVR_LS2081A 0x870918
|
||||
#define SVR_LS2041A 0x870914
|
||||
#define SVR_LX2160A 0x873600
|
||||
#define SVR_LX2120A 0x873620
|
||||
#define SVR_LX2080A 0x873602
|
||||
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
|
||||
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
|
||||
#ifdef CONFIG_ARCH_LX2160A
|
||||
#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LS1028A
|
||||
#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1))
|
||||
#endif
|
||||
#define IS_SVR_REV(svr, maj, min) \
|
||||
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
|
||||
#define SVR_DEV(svr) ((svr) >> 8)
|
||||
#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
void fsl_lsch3_early_init_f(void);
|
||||
int get_core_volt_from_fuse(void);
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
void fsl_lsch2_early_init_f(void);
|
||||
int setup_chip_volt(void);
|
||||
/* Setup core vdd in unit mV */
|
||||
int board_setup_core_volt(u32 vdd);
|
||||
#ifdef CONFIG_FSL_PFE
|
||||
void init_pfe_scfg_dcfg_regs(void);
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_QSPI_AHB_INIT
|
||||
int qspi_ahb_init(void);
|
||||
#endif
|
||||
|
||||
void cpu_name(char *name);
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
|
||||
void erratum_a009635(void);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
|
||||
void erratum_a010315(void);
|
||||
#endif
|
||||
|
||||
bool soc_has_dp_ddr(void);
|
||||
bool soc_has_aiop(void);
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
|
||||
@@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_SPEED_H
|
||||
#define _FSL_LAYERSCAPE_SPEED_H
|
||||
void get_sys_info(struct sys_info *sys_info);
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN
|
||||
unsigned long get_qman_freq(void);
|
||||
#endif
|
||||
#endif /* _FSL_LAYERSCAPE_SPEED_H */
|
||||
+63
@@ -0,0 +1,63 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2017 NXP Semiconductor, Inc.
|
||||
*
|
||||
*/
|
||||
#ifndef __FSL_STREAM_ID_H
|
||||
#define __FSL_STREAM_ID_H
|
||||
|
||||
/*
|
||||
* Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
|
||||
* are not hardwired and are programmed by sw. There are a limited number
|
||||
* of stream IDs available, and the partitioning of them is scenario
|
||||
* dependent. This header defines the partitioning between legacy, PCI,
|
||||
* and DPAA1 devices.
|
||||
*
|
||||
* This partitioning can be customized in this file depending
|
||||
* on the specific hardware config:
|
||||
*
|
||||
* -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
|
||||
* -all legacy devices get a unique stream ID assigned and programmed in
|
||||
* their AMQR registers by u-boot
|
||||
*
|
||||
* -PCIe
|
||||
* -there is a range of stream IDs set aside for PCI in this
|
||||
* file. U-boot will scan the PCI bus and for each device discovered:
|
||||
* -allocate a streamID
|
||||
* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
|
||||
* -set a msi-map entry in the PEXn controller node in the
|
||||
* device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
|
||||
* for more info on the msi-map definition)
|
||||
* -set a iommu-map entry in the PEXn controller node in the
|
||||
* device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
|
||||
* for more info on the iommu-map definition)
|
||||
*
|
||||
* -DPAA1
|
||||
* - Stream ids for DPAA1 use are reserved for future usecase.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#define FSL_INVALID_STREAM_ID 0
|
||||
|
||||
/* legacy devices */
|
||||
#define FSL_USB1_STREAM_ID 1
|
||||
#define FSL_USB2_STREAM_ID 2
|
||||
#define FSL_USB3_STREAM_ID 3
|
||||
#define FSL_SDHC_STREAM_ID 4
|
||||
#define FSL_SATA_STREAM_ID 5
|
||||
#define FSL_QE_STREAM_ID 6
|
||||
#define FSL_QDMA_STREAM_ID 7
|
||||
#define FSL_EDMA_STREAM_ID 8
|
||||
#define FSL_ETR_STREAM_ID 9
|
||||
#define FSL_DEBUG_STREAM_ID 10
|
||||
|
||||
/* PCI - programmed in PEXn_LUT */
|
||||
#define FSL_PEX_STREAM_ID_START 11
|
||||
#define FSL_PEX_STREAM_ID_END 26
|
||||
|
||||
/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */
|
||||
#define FSL_DPAA1_STREAM_ID_START 27
|
||||
#define FSL_DPAA1_STREAM_ID_END 63
|
||||
|
||||
#endif
|
||||
+129
@@ -0,0 +1,129 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015-2018 NXP
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
*/
|
||||
#ifndef __FSL_STREAM_ID_H
|
||||
#define __FSL_STREAM_ID_H
|
||||
|
||||
/*
|
||||
* Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
|
||||
* devices are not hardwired and are programmed by sw. There are a limited
|
||||
* number of stream IDs available, and the partitioning of them is scenario
|
||||
* dependent. This header defines the partitioning between legacy,
|
||||
* PCI, and DPAA2 devices.
|
||||
*
|
||||
* This partitioning can be customized in this file depending
|
||||
* on the specific hardware config:
|
||||
*
|
||||
* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
|
||||
* -all legacy devices get a unique stream ID assigned and programmed in
|
||||
* their AMQR registers by u-boot
|
||||
*
|
||||
* -PCIe
|
||||
* -there is a range of stream IDs set aside for PCI in this
|
||||
* file. U-boot will scan the PCI bus and for each device discovered:
|
||||
* -allocate a streamID
|
||||
* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
|
||||
* -set a msi-map entry in the PEXn controller node in the
|
||||
* device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
|
||||
* for more info on the msi-map definition)
|
||||
* -set a iommu-map entry in the PEXn controller node in the
|
||||
* device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
|
||||
* for more info on the iommu-map definition)
|
||||
*
|
||||
* -DPAA2
|
||||
* -u-boot will allocate a range of stream IDs to be used by the Management
|
||||
* Complex for containers and will set these values in the MC DPC image.
|
||||
* -u-boot will fixup the iommu-map property in the fsl-mc node in the
|
||||
* device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
|
||||
* for more info on the msi-map definition)
|
||||
* -the MC is responsible for allocating and setting up 'isolation context
|
||||
* IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
|
||||
*
|
||||
* On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
|
||||
* each of the different bus masters. The relationship between
|
||||
* the AMQ registers and stream IDs is defined in the table below:
|
||||
* AMQ bit streamID bit
|
||||
* ---------------------------
|
||||
* PL[18] 9 // privilege bit
|
||||
* BMT[17] 8 // bypass translation
|
||||
* VA[16] 7 // reserved
|
||||
* [15] - // unused
|
||||
* ICID[14:7] - // unused
|
||||
* ICID[6:0] 6-0 // isolation context id
|
||||
* ----------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
|
||||
#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
|
||||
|
||||
#define FSL_INVALID_STREAM_ID 0
|
||||
|
||||
#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
|
||||
|
||||
/* legacy devices */
|
||||
#define FSL_USB1_STREAM_ID 1
|
||||
#define FSL_USB2_STREAM_ID 2
|
||||
#define FSL_SDMMC_STREAM_ID 3
|
||||
#define FSL_SATA1_STREAM_ID 4
|
||||
|
||||
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
|
||||
#define FSL_SATA2_STREAM_ID 5
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
|
||||
#define FSL_DMA_STREAM_ID 6
|
||||
#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
|
||||
#define FSL_DMA_STREAM_ID 5
|
||||
#endif
|
||||
|
||||
/* PCI - programmed in PEXn_LUT */
|
||||
#define FSL_PEX_STREAM_ID_START 7
|
||||
|
||||
#ifdef CONFIG_ARCH_LX2160A
|
||||
#define FSL_PEX_STREAM_ID_NUM (0x100)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A)
|
||||
#define FSL_PEX_STREAM_ID_END 22
|
||||
#elif defined(CONFIG_ARCH_LS1088A)
|
||||
#define FSL_PEX_STREAM_ID_END 18
|
||||
#endif
|
||||
|
||||
|
||||
/* DPAA2 - set in MC DPC and alloced by MC */
|
||||
#define FSL_DPAA2_STREAM_ID_START 23
|
||||
#define FSL_DPAA2_STREAM_ID_END 63
|
||||
|
||||
#define FSL_SEC_STREAM_ID 64
|
||||
#define FSL_SEC_JR1_STREAM_ID 65
|
||||
#define FSL_SEC_JR2_STREAM_ID 66
|
||||
#define FSL_SEC_JR3_STREAM_ID 67
|
||||
#define FSL_SEC_JR4_STREAM_ID 68
|
||||
|
||||
#define FSL_SDMMC2_STREAM_ID 69
|
||||
|
||||
/*
|
||||
* Erratum A-050382 workaround
|
||||
*
|
||||
* Description:
|
||||
* The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not
|
||||
* correctly forwarded to the SMMU.
|
||||
* Workaround:
|
||||
* Program eDMA ICID in the eDMA_AMQR register in DCFG to 40.
|
||||
*/
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A050382
|
||||
#define FSL_EDMA_STREAM_ID 40
|
||||
#else
|
||||
#define FSL_EDMA_STREAM_ID 70
|
||||
#endif
|
||||
|
||||
#define FSL_GPU_STREAM_ID 71
|
||||
#define FSL_DISPLAY_STREAM_ID 72
|
||||
#define FSL_SATA3_STREAM_ID 73
|
||||
#define FSL_SATA4_STREAM_ID 74
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,52 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2019 Linaro
|
||||
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __HI3660_H__
|
||||
#define __HI3660_H__
|
||||
|
||||
#define HI3660_UART6_BASE 0xfff32000
|
||||
|
||||
#define PMU_REG_BASE 0xfff34000
|
||||
#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2))
|
||||
|
||||
#define SCTRL_REG_BASE 0xfff0a000
|
||||
#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120)
|
||||
#define SCTRL_SCFPLLCTRL0_FPLL0_EN BIT(0)
|
||||
|
||||
#define CRG_REG_BASE 0xfff35000
|
||||
#define CRG_PEREN2 (CRG_REG_BASE + 0x020)
|
||||
#define CRG_PERDIS2 (CRG_REG_BASE + 0x024)
|
||||
#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028)
|
||||
#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C)
|
||||
#define CRG_PEREN4 (CRG_REG_BASE + 0x040)
|
||||
#define CRG_PERDIS4 (CRG_REG_BASE + 0x044)
|
||||
#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048)
|
||||
#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C)
|
||||
#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078)
|
||||
#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C)
|
||||
#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080)
|
||||
#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084)
|
||||
#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088)
|
||||
#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C)
|
||||
#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090)
|
||||
#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094)
|
||||
#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098)
|
||||
#define CRG_ISOEN (CRG_REG_BASE + 0x144)
|
||||
#define CRG_ISODIS (CRG_REG_BASE + 0x148)
|
||||
#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C)
|
||||
|
||||
#define PINMUX4_BASE 0xfff11000
|
||||
#define PINMUX4_SDDET (PINMUX4_BASE + 0x60)
|
||||
|
||||
#define PINCONF3_BASE 0xff37e800
|
||||
#define PINCONF3_SDCLK (PINCONF3_BASE + 0x00)
|
||||
#define PINCONF3_SDCMD (PINCONF3_BASE + 0x04)
|
||||
#define PINCONF3_SDDATA0 (PINCONF3_BASE + 0x08)
|
||||
#define PINCONF3_SDDATA1 (PINCONF3_BASE + 0x0c)
|
||||
#define PINCONF3_SDDATA2 (PINCONF3_BASE + 0x10)
|
||||
#define PINCONF3_SDDATA3 (PINCONF3_BASE + 0x14)
|
||||
|
||||
#endif /*__HI3660_H__*/
|
||||
@@ -0,0 +1,53 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2017 Linaro
|
||||
* Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __HI3798cv200_H__
|
||||
#define __HI3798cv200_H__
|
||||
|
||||
#define REG_BASE_PERI_CTRL 0xF8A20000
|
||||
#define REG_BASE_CRG 0xF8A22000
|
||||
|
||||
/* DEVICES */
|
||||
#define REG_BASE_UART0 0xF8B00000
|
||||
#define HIOTG_BASE_ADDR 0xF98C0000
|
||||
|
||||
/* PERI control registers (4KB) */
|
||||
/* USB2 PHY01 configuration register */
|
||||
#define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120)
|
||||
|
||||
/* USB2 controller configuration register */
|
||||
#define PERI_CTRL_USB3 (REG_BASE_PERI_CTRL + 0x12c)
|
||||
#define USB2_2P_CHIPID (1 << 28)
|
||||
|
||||
/* PERI CRG registers (4KB) */
|
||||
/* USB2 CTRL0 clock and soft reset */
|
||||
#define PERI_CRG46 (REG_BASE_CRG + 0xb8)
|
||||
#define USB2_BUS_CKEN (1<<0)
|
||||
#define USB2_OHCI48M_CKEN (1<<1)
|
||||
#define USB2_OHCI12M_CKEN (1<<2)
|
||||
#define USB2_OTG_UTMI_CKEN (1<<3)
|
||||
#define USB2_HST_PHY_CKEN (1<<4)
|
||||
#define USB2_UTMI0_CKEN (1<<5)
|
||||
#define USB2_BUS_SRST_REQ (1<<12)
|
||||
#define USB2_UTMI0_SRST_REQ (1<<13)
|
||||
#define USB2_HST_PHY_SYST_REQ (1<<16)
|
||||
#define USB2_OTG_PHY_SYST_REQ (1<<17)
|
||||
#define USB2_CLK48_SEL (1<<20)
|
||||
|
||||
/* USB2 PHY clock and soft reset */
|
||||
#define PERI_CRG47 (REG_BASE_CRG + 0xbc)
|
||||
#define USB2_PHY01_REF_CKEN (1 << 0)
|
||||
#define USB2_PHY2_REF_CKEN (1 << 2)
|
||||
#define USB2_PHY01_SRST_REQ (1 << 4)
|
||||
#define USB2_PHY2_SRST_REQ (1 << 6)
|
||||
#define USB2_PHY01_SRST_TREQ0 (1 << 8)
|
||||
#define USB2_PHY01_SRST_TREQ1 (1 << 9)
|
||||
#define USB2_PHY2_SRST_TREQ (1 << 10)
|
||||
#define USB2_PHY01_REFCLK_SEL (1 << 12)
|
||||
#define USB2_PHY2_REFCLK_SEL (1 << 14)
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*/
|
||||
|
||||
int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
|
||||
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef _HI6220_GPIO_H_
|
||||
#define _HI6220_GPIO_H_
|
||||
|
||||
#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \
|
||||
0xf7020000 - 0x4000) + (0x1000 * bank))
|
||||
|
||||
#define HI6220_GPIO_PER_BANK 8
|
||||
#define HI6220_GPIO_DIR 0x400
|
||||
|
||||
struct gpio_bank {
|
||||
u8 *base; /* address of registers in physical memory */
|
||||
};
|
||||
|
||||
/* Information about a GPIO bank */
|
||||
struct hikey_gpio_platdata {
|
||||
int bank_index;
|
||||
ulong base; /* address of registers in physical memory */
|
||||
};
|
||||
|
||||
#endif /* _HI6220_GPIO_H_ */
|
||||
@@ -0,0 +1,389 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __HI6220_H__
|
||||
#define __HI6220_H__
|
||||
|
||||
#include "hi6220_regs_alwayson.h"
|
||||
|
||||
#define HI6220_MMC0_BASE 0xF723D000
|
||||
#define HI6220_MMC1_BASE 0xF723E000
|
||||
|
||||
#define HI6220_UART0_BASE 0xF8015000
|
||||
#define HI6220_UART3_BASE 0xF7113000
|
||||
|
||||
#define HI6220_PMUSSI_BASE 0xF8000000
|
||||
|
||||
#define HI6220_PERI_BASE 0xF7030000
|
||||
|
||||
struct peri_sc_periph_regs {
|
||||
u32 ctrl1; /*0x0*/
|
||||
u32 ctrl2;
|
||||
u32 ctrl3;
|
||||
u32 ctrl4;
|
||||
u32 ctrl5;
|
||||
u32 ctrl6;
|
||||
u32 ctrl8;
|
||||
u32 ctrl9;
|
||||
u32 ctrl10;
|
||||
u32 ctrl12;
|
||||
u32 ctrl13;
|
||||
u32 ctrl14;
|
||||
|
||||
u32 unknown_1[8];
|
||||
|
||||
u32 ddr_ctrl0; /*0x50*/
|
||||
|
||||
u32 unknown_2[16];
|
||||
|
||||
u32 stat1; /*0x94*/
|
||||
|
||||
u32 unknown_3[90];
|
||||
|
||||
u32 clk0_en; /*0x200*/
|
||||
u32 clk0_dis;
|
||||
u32 clk0_stat;
|
||||
|
||||
u32 unknown_4;
|
||||
|
||||
u32 clk1_en; /*0x210*/
|
||||
u32 clk1_dis;
|
||||
u32 clk1_stat;
|
||||
|
||||
u32 unknown_5;
|
||||
|
||||
u32 clk2_en; /*0x220*/
|
||||
u32 clk2_dis;
|
||||
u32 clk2_stat;
|
||||
|
||||
u32 unknown_6;
|
||||
|
||||
u32 clk3_en; /*0x230*/
|
||||
u32 clk3_dis;
|
||||
u32 clk3_stat;
|
||||
|
||||
u32 unknown_7;
|
||||
|
||||
u32 clk8_en; /*0x240*/
|
||||
u32 clk8_dis;
|
||||
u32 clk8_stat;
|
||||
|
||||
u32 unknown_8;
|
||||
|
||||
u32 clk9_en; /*0x250*/
|
||||
u32 clk9_dis;
|
||||
u32 clk9_stat;
|
||||
|
||||
u32 unknown_9;
|
||||
|
||||
u32 clk10_en; /*0x260*/
|
||||
u32 clk10_dis;
|
||||
u32 clk10_stat;
|
||||
|
||||
u32 unknown_10;
|
||||
|
||||
u32 clk12_en; /*0x270*/
|
||||
u32 clk12_dis;
|
||||
u32 clk12_stat;
|
||||
|
||||
u32 unknown_11[33];
|
||||
|
||||
u32 rst0_en; /*0x300*/
|
||||
u32 rst0_dis;
|
||||
u32 rst0_stat;
|
||||
|
||||
u32 unknown_12;
|
||||
|
||||
u32 rst1_en; /*0x310*/
|
||||
u32 rst1_dis;
|
||||
u32 rst1_stat;
|
||||
|
||||
u32 unknown_13;
|
||||
|
||||
u32 rst2_en; /*0x320*/
|
||||
u32 rst2_dis;
|
||||
u32 rst2_stat;
|
||||
|
||||
u32 unknown_14;
|
||||
|
||||
u32 rst3_en; /*0x330*/
|
||||
u32 rst3_dis;
|
||||
u32 rst3_stat;
|
||||
|
||||
u32 unknown_15;
|
||||
|
||||
u32 rst8_en; /*0x340*/
|
||||
u32 rst8_dis;
|
||||
u32 rst8_stat;
|
||||
|
||||
u32 unknown_16[45];
|
||||
|
||||
u32 clk0_sel; /*0x400*/
|
||||
|
||||
u32 unknown_17[36];
|
||||
|
||||
u32 clkcfg8bit1; /*0x494*/
|
||||
u32 clkcfg8bit2;
|
||||
|
||||
u32 unknown_18[538];
|
||||
|
||||
u32 reserved8_addr; /*0xd04*/
|
||||
};
|
||||
|
||||
|
||||
/* CTRL1 bit definitions */
|
||||
|
||||
#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0)
|
||||
#define PERI_CTRL1_HIFI_INT_MASK (1 << 1)
|
||||
#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2)
|
||||
#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16)
|
||||
#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17)
|
||||
#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18)
|
||||
|
||||
|
||||
/* CTRL2 bit definitions */
|
||||
|
||||
#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0)
|
||||
#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2)
|
||||
#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6)
|
||||
#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7)
|
||||
#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8)
|
||||
#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9)
|
||||
#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12)
|
||||
#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28)
|
||||
|
||||
/* CTRL3 bit definitions */
|
||||
|
||||
#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0)
|
||||
#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12)
|
||||
#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24)
|
||||
|
||||
/* CTRL4 bit definitions */
|
||||
|
||||
#define PERI_CTRL4_PICO_FSELV (1 << 0)
|
||||
#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3)
|
||||
#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4)
|
||||
#define PERI_CTRL4_PICO_SIDDQ (1 << 6)
|
||||
#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7)
|
||||
#define PERI_CTRL4_PICO_OGDISABLE (1 << 8)
|
||||
#define PERI_CTRL4_PICO_COMMONONN (1 << 9)
|
||||
#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10)
|
||||
#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11)
|
||||
#define PERI_CTRL4_PICO_VATESTENB (1 << 12)
|
||||
#define PERI_CTRL4_PICO_SUSPENDM (1 << 14)
|
||||
#define PERI_CTRL4_PICO_SLEEPM (1 << 15)
|
||||
#define PERI_CTRL4_BC11_C (1 << 16)
|
||||
#define PERI_CTRL4_BC11_B (1 << 17)
|
||||
#define PERI_CTRL4_BC11_A (1 << 18)
|
||||
#define PERI_CTRL4_BC11_GND (1 << 19)
|
||||
#define PERI_CTRL4_BC11_FLOAT (1 << 20)
|
||||
#define PERI_CTRL4_OTG_PHY_SEL (1 << 21)
|
||||
#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22)
|
||||
#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24)
|
||||
#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25)
|
||||
#define PERI_CTRL4_OTG_IDPULLUP (1 << 26)
|
||||
#define PERI_CTRL4_OTG_DRVBUS (1 << 27)
|
||||
#define PERI_CTRL4_OTG_SESSEND (1 << 28)
|
||||
#define PERI_CTRL4_OTG_BVALID (1 << 29)
|
||||
#define PERI_CTRL4_OTG_AVALID (1 << 30)
|
||||
#define PERI_CTRL4_OTG_VBUSVALID (1 << 31)
|
||||
|
||||
/* CTRL5 bit definitions */
|
||||
|
||||
#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3)
|
||||
#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4)
|
||||
#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5)
|
||||
#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6)
|
||||
#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7)
|
||||
#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8)
|
||||
#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9)
|
||||
#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10)
|
||||
#define PERI_CTRL5_DBG_MUX (1 << 11)
|
||||
|
||||
/* CTRL6 bit definitions */
|
||||
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12)
|
||||
|
||||
/* CTRL8 bit definitions */
|
||||
|
||||
#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0)
|
||||
#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2)
|
||||
#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4)
|
||||
#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6)
|
||||
#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8)
|
||||
#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11)
|
||||
#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12)
|
||||
#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16)
|
||||
#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20)
|
||||
#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28)
|
||||
|
||||
/* CTRL9 bit definitions */
|
||||
|
||||
#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0)
|
||||
#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1)
|
||||
#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4)
|
||||
#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8)
|
||||
|
||||
/* CLK0 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK0_MMC0 (1 << 0)
|
||||
#define PERI_CLK0_MMC1 (1 << 1)
|
||||
#define PERI_CLK0_MMC2 (1 << 2)
|
||||
#define PERI_CLK0_NANDC (1 << 3)
|
||||
#define PERI_CLK0_USBOTG (1 << 4)
|
||||
#define PERI_CLK0_PICOPHY (1 << 5)
|
||||
#define PERI_CLK0_PLL (1 << 6)
|
||||
|
||||
/* CLK1 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK1_HIFI (1 << 0)
|
||||
#define PERI_CLK1_DIGACODEC (1 << 5)
|
||||
|
||||
/* CLK2 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK2_IPF (1 << 0)
|
||||
#define PERI_CLK2_SOCP (1 << 1)
|
||||
#define PERI_CLK2_DMAC (1 << 2)
|
||||
#define PERI_CLK2_SECENG (1 << 3)
|
||||
#define PERI_CLK2_HPM0 (1 << 5)
|
||||
#define PERI_CLK2_HPM1 (1 << 6)
|
||||
#define PERI_CLK2_HPM2 (1 << 7)
|
||||
#define PERI_CLK2_HPM3 (1 << 8)
|
||||
|
||||
/* CLK8 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK8_RS0 (1 << 0)
|
||||
#define PERI_CLK8_RS2 (1 << 1)
|
||||
#define PERI_CLK8_RS3 (1 << 2)
|
||||
#define PERI_CLK8_MS0 (1 << 3)
|
||||
#define PERI_CLK8_MS2 (1 << 5)
|
||||
#define PERI_CLK8_XG2RAM0 (1 << 6)
|
||||
#define PERI_CLK8_X2SRAM (1 << 7)
|
||||
#define PERI_CLK8_SRAM (1 << 8)
|
||||
#define PERI_CLK8_ROM (1 << 9)
|
||||
#define PERI_CLK8_HARQ (1 << 10)
|
||||
#define PERI_CLK8_MMU (1 << 11)
|
||||
#define PERI_CLK8_DDRC (1 << 12)
|
||||
#define PERI_CLK8_DDRPHY (1 << 13)
|
||||
#define PERI_CLK8_DDRPHY_REF (1 << 14)
|
||||
#define PERI_CLK8_X2X_SYSNOC (1 << 15)
|
||||
#define PERI_CLK8_X2X_CCPU (1 << 16)
|
||||
#define PERI_CLK8_DDRT (1 << 17)
|
||||
#define PERI_CLK8_DDRPACK_RS (1 << 18)
|
||||
|
||||
/* CLK9 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK9_CARM_DAP (1 << 0)
|
||||
#define PERI_CLK9_CARM_ATB (1 << 1)
|
||||
#define PERI_CLK9_CARM_LBUS (1 << 2)
|
||||
#define PERI_CLK9_CARM_KERNEL (1 << 3)
|
||||
|
||||
/* CLK10 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK10_IPF_CCPU (1 << 0)
|
||||
#define PERI_CLK10_SOCP_CCPU (1 << 1)
|
||||
#define PERI_CLK10_SECENG_CCPU (1 << 2)
|
||||
#define PERI_CLK10_HARQ_CCPU (1 << 3)
|
||||
#define PERI_CLK10_IPF_MCU (1 << 16)
|
||||
#define PERI_CLK10_SOCP_MCU (1 << 17)
|
||||
#define PERI_CLK10_SECENG_MCU (1 << 18)
|
||||
#define PERI_CLK10_HARQ_MCU (1 << 19)
|
||||
|
||||
/* CLK12 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_CLK12_HIFI_SRC (1 << 0)
|
||||
#define PERI_CLK12_MMC0_SRC (1 << 1)
|
||||
#define PERI_CLK12_MMC1_SRC (1 << 2)
|
||||
#define PERI_CLK12_MMC2_SRC (1 << 3)
|
||||
#define PERI_CLK12_SYSPLL_DIV (1 << 4)
|
||||
#define PERI_CLK12_TPIU_SRC (1 << 5)
|
||||
#define PERI_CLK12_MMC0_HF (1 << 6)
|
||||
#define PERI_CLK12_MMC1_HF (1 << 7)
|
||||
#define PERI_CLK12_PLL_TEST_SRC (1 << 8)
|
||||
#define PERI_CLK12_CODEC_SOC (1 << 9)
|
||||
#define PERI_CLK12_MEDIA (1 << 10)
|
||||
|
||||
/* RST0 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST0_MMC0 (1 << 0)
|
||||
#define PERI_RST0_MMC1 (1 << 1)
|
||||
#define PERI_RST0_MMC2 (1 << 2)
|
||||
#define PERI_RST0_NANDC (1 << 3)
|
||||
#define PERI_RST0_USBOTG_BUS (1 << 4)
|
||||
#define PERI_RST0_POR_PICOPHY (1 << 5)
|
||||
#define PERI_RST0_USBOTG (1 << 6)
|
||||
#define PERI_RST0_USBOTG_32K (1 << 7)
|
||||
|
||||
/* RST1 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST1_HIFI (1 << 0)
|
||||
#define PERI_RST1_DIGACODEC (1 << 5)
|
||||
|
||||
/* RST2 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST2_IPF (1 << 0)
|
||||
#define PERI_RST2_SOCP (1 << 1)
|
||||
#define PERI_RST2_DMAC (1 << 2)
|
||||
#define PERI_RST2_SECENG (1 << 3)
|
||||
#define PERI_RST2_ABB (1 << 4)
|
||||
#define PERI_RST2_HPM0 (1 << 5)
|
||||
#define PERI_RST2_HPM1 (1 << 6)
|
||||
#define PERI_RST2_HPM2 (1 << 7)
|
||||
#define PERI_RST2_HPM3 (1 << 8)
|
||||
|
||||
/* RST3 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST3_CSSYS (1 << 0)
|
||||
#define PERI_RST3_I2C0 (1 << 1)
|
||||
#define PERI_RST3_I2C1 (1 << 2)
|
||||
#define PERI_RST3_I2C2 (1 << 3)
|
||||
#define PERI_RST3_I2C3 (1 << 4)
|
||||
#define PERI_RST3_UART1 (1 << 5)
|
||||
#define PERI_RST3_UART2 (1 << 6)
|
||||
#define PERI_RST3_UART3 (1 << 7)
|
||||
#define PERI_RST3_UART4 (1 << 8)
|
||||
#define PERI_RST3_SSP (1 << 9)
|
||||
#define PERI_RST3_PWM (1 << 10)
|
||||
#define PERI_RST3_BLPWM (1 << 11)
|
||||
#define PERI_RST3_TSENSOR (1 << 12)
|
||||
#define PERI_RST3_DAPB (1 << 18)
|
||||
#define PERI_RST3_HKADC (1 << 19)
|
||||
#define PERI_RST3_CODEC (1 << 20)
|
||||
|
||||
/* RST8 EN/DIS/STAT bit definitions */
|
||||
|
||||
#define PERI_RST8_RS0 (1 << 0)
|
||||
#define PERI_RST8_RS2 (1 << 1)
|
||||
#define PERI_RST8_RS3 (1 << 2)
|
||||
#define PERI_RST8_MS0 (1 << 3)
|
||||
#define PERI_RST8_MS2 (1 << 5)
|
||||
#define PERI_RST8_XG2RAM0 (1 << 6)
|
||||
#define PERI_RST8_X2SRAM_TZMA (1 << 7)
|
||||
#define PERI_RST8_SRAM (1 << 8)
|
||||
#define PERI_RST8_HARQ (1 << 10)
|
||||
#define PERI_RST8_DDRC (1 << 12)
|
||||
#define PERI_RST8_DDRC_APB (1 << 13)
|
||||
#define PERI_RST8_DDRPACK_APB (1 << 14)
|
||||
#define PERI_RST8_DDRT (1 << 17)
|
||||
|
||||
#endif /*__HI62220_H__*/
|
||||
+419
@@ -0,0 +1,419 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __HI6220_ALWAYSON_H__
|
||||
#define __HI6220_ALWAYSON_H__
|
||||
|
||||
#define ALWAYSON_CTRL_BASE 0xF7800000
|
||||
|
||||
struct alwayson_sc_regs {
|
||||
u32 ctrl0; /*0x0*/
|
||||
u32 ctrl1;
|
||||
u32 ctrl2;
|
||||
|
||||
u32 unknown;
|
||||
|
||||
u32 stat0; /*0x10*/
|
||||
u32 stat1;
|
||||
u32 mcu_imctrl;
|
||||
u32 mcu_imstat;
|
||||
|
||||
u32 unknown_1[9];
|
||||
|
||||
u32 secondary_int_en0; /*0x44*/
|
||||
u32 secondary_int_statr0;
|
||||
u32 secondary_int_statm0;
|
||||
|
||||
u32 unknown_2;
|
||||
|
||||
u32 mcu_wkup_int_en6; /*0x54*/
|
||||
u32 mcu_wkup_int_statr6;
|
||||
u32 mcu_wkup_int_statm6;
|
||||
|
||||
u32 unknown_3;
|
||||
|
||||
u32 mcu_wkup_int_en5; /*0x64*/
|
||||
u32 mcu_wkup_int_statr5;
|
||||
u32 mcu_wkup_int_statm5;
|
||||
|
||||
u32 unknown_4[9];
|
||||
|
||||
u32 mcu_wkup_int_en4; /*0x94*/
|
||||
u32 mcu_wkup_int_statr4;
|
||||
u32 mcu_wkup_int_statm4;
|
||||
|
||||
u32 unknown_5[2];
|
||||
|
||||
u32 mcu_wkup_int_en0; /*0xa8*/
|
||||
u32 mcu_wkup_int_statr0;
|
||||
u32 mcu_wkup_int_statm0;
|
||||
|
||||
u32 mcu_wkup_int_en1; /*0xb4*/
|
||||
u32 mcu_wkup_int_statr1;
|
||||
u32 mcu_wkup_int_statm1;
|
||||
|
||||
u32 unknown_6;
|
||||
|
||||
u32 int_statr; /*0xc4*/
|
||||
u32 int_statm;
|
||||
u32 int_clear;
|
||||
|
||||
u32 int_en_set; /*0xd0*/
|
||||
u32 int_en_dis;
|
||||
u32 int_en_stat;
|
||||
|
||||
u32 unknown_7[2];
|
||||
|
||||
u32 int_statr1; /*0xc4*/
|
||||
u32 int_statm1;
|
||||
u32 int_clear1;
|
||||
|
||||
u32 int_en_set1; /*0xf0*/
|
||||
u32 int_en_dis1;
|
||||
u32 int_en_stat1;
|
||||
|
||||
u32 unknown_8[53];
|
||||
|
||||
u32 timer_en0; /*0x1d0*/
|
||||
u32 timer_en1;
|
||||
|
||||
u32 unknown_9[6];
|
||||
|
||||
u32 timer_en4; /*0x1f0*/
|
||||
u32 timer_en5;
|
||||
|
||||
u32 unknown_10[130];
|
||||
|
||||
u32 mcu_subsys_ctrl0; /*0x400*/
|
||||
u32 mcu_subsys_ctrl1;
|
||||
u32 mcu_subsys_ctrl2;
|
||||
u32 mcu_subsys_ctrl3;
|
||||
u32 mcu_subsys_ctrl4;
|
||||
u32 mcu_subsys_ctrl5;
|
||||
u32 mcu_subsys_ctrl6;
|
||||
u32 mcu_subsys_ctrl7;
|
||||
|
||||
u32 unknown_10_1[8];
|
||||
|
||||
u32 mcu_subsys_stat0; /*0x440*/
|
||||
u32 mcu_subsys_stat1;
|
||||
u32 mcu_subsys_stat2;
|
||||
u32 mcu_subsys_stat3;
|
||||
u32 mcu_subsys_stat4;
|
||||
u32 mcu_subsys_stat5;
|
||||
u32 mcu_subsys_stat6;
|
||||
u32 mcu_subsys_stat7;
|
||||
|
||||
u32 unknown_11[116];
|
||||
|
||||
u32 clk4_en; /*0x630*/
|
||||
u32 clk4_dis;
|
||||
u32 clk4_stat;
|
||||
|
||||
u32 clk5_en; /*0x63c*/
|
||||
u32 clk5_dis;
|
||||
u32 clk5_stat;
|
||||
|
||||
u32 unknown_12[42];
|
||||
|
||||
u32 rst4_en; /*0x6f0*/
|
||||
u32 rst4_dis;
|
||||
u32 rst4_stat;
|
||||
|
||||
u32 rst5_en; /*0x6fc*/
|
||||
u32 rst5_dis;
|
||||
u32 rst5_stat;
|
||||
|
||||
u32 unknown_13[62];
|
||||
|
||||
u32 pw_clk0_en; /*0x800*/
|
||||
u32 pw_clk0_dis;
|
||||
u32 pw_clk0_stat;
|
||||
|
||||
u32 unknown_13_1;
|
||||
|
||||
u32 pw_rst0_en; /*0x810*/
|
||||
u32 pw_rst0_dis;
|
||||
u32 pw_rst0_stat;
|
||||
|
||||
u32 unknown_14;
|
||||
|
||||
u32 pw_isoen0; /*0x820*/
|
||||
u32 pw_isodis0;
|
||||
u32 pw_iso_stat0;
|
||||
|
||||
u32 unknown_14_1;
|
||||
|
||||
u32 pw_mtcmos_en0; /*0x830*/
|
||||
u32 pw_mtcmos_dis0;
|
||||
u32 pw_mtcmos_stat0;
|
||||
u32 pw_mtcmos_ack_stat0;
|
||||
u32 pw_mtcmos_timeout_stat0;
|
||||
|
||||
u32 unknown_14_2[3];
|
||||
|
||||
u32 pw_stat0; /*0x850*/
|
||||
u32 pw_stat1;
|
||||
|
||||
u32 unknown_15[10];
|
||||
|
||||
u32 systest_stat; /*0x880*/
|
||||
|
||||
u32 unknown_16[3];
|
||||
|
||||
u32 systest_slicer_cnt0;/*0x890*/
|
||||
u32 systest_slicer_cnt1;
|
||||
|
||||
u32 unknown_17[12];
|
||||
|
||||
u32 pw_ctrl1; /*0x8C8*/
|
||||
u32 pw_ctrl;
|
||||
|
||||
u32 mcpu_voteen;
|
||||
u32 mcpu_votedis;
|
||||
u32 mcpu_votestat;
|
||||
|
||||
u32 unknown_17_1;
|
||||
|
||||
u32 mcpu_vote_msk0; /*0x8E0*/
|
||||
u32 mcpu_vote_msk1;
|
||||
u32 mcpu_votestat0_msk;
|
||||
u32 mcpu_votestat1_msk;
|
||||
|
||||
u32 peri_voteen; /*0x8F0*/
|
||||
u32 peri_votedis;
|
||||
u32 peri_votestat;
|
||||
|
||||
u32 unknown_17_2;
|
||||
|
||||
u32 peri_vote_msk0; /*0x900*/
|
||||
u32 peri_vote_msk1;
|
||||
u32 peri_votestat0_msk;
|
||||
u32 erpi_votestat1_msk;
|
||||
u32 acpu_voteen;
|
||||
u32 acpu_votedis;
|
||||
u32 acpu_votestat;
|
||||
|
||||
u32 unknown_18;
|
||||
|
||||
u32 acpu_vote_msk0; /*0x920*/
|
||||
u32 acpu_vote_msk1;
|
||||
u32 acpu_votestat0_msk;
|
||||
u32 acpu_votestat1_msk;
|
||||
u32 mcu_voteen;
|
||||
u32 mcu_votedis;
|
||||
u32 mcu_votestat;
|
||||
|
||||
u32 unknown_18_1;
|
||||
|
||||
u32 mcu_vote_msk0; /*0x940*/
|
||||
u32 mcu_vote_msk1;
|
||||
u32 mcu_vote_votestat0_msk;
|
||||
u32 mcu_vote_votestat1_msk;
|
||||
|
||||
u32 unknown_18_1_2[4];
|
||||
|
||||
u32 mcu_vote_vote1en; /*0x960*/
|
||||
u32 mcu_vote_vote1dis;
|
||||
u32 mcu_vote_vote1stat;
|
||||
|
||||
u32 unknown_18_2;
|
||||
|
||||
u32 mcu_vote_vote1_msk0;/*0x970*/
|
||||
u32 mcu_vote_vote1_msk1;
|
||||
u32 mcu_vote_vote1stat0_msk;
|
||||
u32 mcu_vote_vote1stat1_msk;
|
||||
u32 mcu_vote_vote2en;
|
||||
u32 mcu_vote_vote2dis;
|
||||
u32 mcu_vote_vote2stat;
|
||||
|
||||
u32 unknown_18_3;
|
||||
|
||||
u32 mcu_vote2_msk0; /*0x990*/
|
||||
u32 mcu_vote2_msk1;
|
||||
u32 mcu_vote2stat0_msk;
|
||||
u32 mcu_vote2stat1_msk;
|
||||
u32 vote_ctrl;
|
||||
u32 vote_stat; /*0x9a4*/
|
||||
|
||||
u32 unknown_19[342];
|
||||
|
||||
u32 econum; /*0xf00*/
|
||||
|
||||
u32 unknown_20_1[3];
|
||||
|
||||
u32 scchipid; /*0xf10*/
|
||||
|
||||
u32 unknown_20_2[2];
|
||||
|
||||
u32 scsocid; /*0xf1c*/
|
||||
|
||||
u32 unknown_20[48];
|
||||
|
||||
u32 soc_fpga_rtl_def; /*0xfe0*/
|
||||
u32 soc_fpga_pr_def;
|
||||
u32 soc_fpga_res_def0;
|
||||
u32 soc_fpga_res_def1; /*0xfec*/
|
||||
};
|
||||
|
||||
/* ctrl0 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004
|
||||
#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007
|
||||
|
||||
/* ctrl1 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29)
|
||||
#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31)
|
||||
|
||||
/* ctrl2 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30)
|
||||
#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31)
|
||||
|
||||
/* stat0 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25)
|
||||
#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26)
|
||||
#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27)
|
||||
#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28)
|
||||
#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29)
|
||||
#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30)
|
||||
#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31)
|
||||
|
||||
/* stat1 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0)
|
||||
#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16)
|
||||
#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17)
|
||||
#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19)
|
||||
#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20)
|
||||
#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27)
|
||||
#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28)
|
||||
#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29)
|
||||
|
||||
/* ctrl3 bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10)
|
||||
#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11)
|
||||
|
||||
/* clk4_en bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30)
|
||||
#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31)
|
||||
|
||||
/* clk5_en bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18)
|
||||
#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19)
|
||||
|
||||
/* rst4_dis bit definitions */
|
||||
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29)
|
||||
#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30)
|
||||
|
||||
#define PCLK_TIMER1 (1 << 16)
|
||||
#define PCLK_TIMER0 (1 << 15)
|
||||
|
||||
#endif /* __HI6220_ALWAYSON_H__ */
|
||||
@@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_PERIPH_H
|
||||
#define __ASM_ARM_ARCH_PERIPH_H
|
||||
|
||||
/*
|
||||
* Peripherals required for pinmux configuration. List will
|
||||
* grow with support for more devices getting added.
|
||||
* Numbering based on interrupt table.
|
||||
*
|
||||
*/
|
||||
enum periph_id {
|
||||
PERIPH_ID_UART0 = 36,
|
||||
PERIPH_ID_UART1,
|
||||
PERIPH_ID_UART2,
|
||||
PERIPH_ID_UART3,
|
||||
PERIPH_ID_UART4,
|
||||
PERIPH_ID_UART5,
|
||||
PERIPH_ID_SDMMC0 = 72,
|
||||
PERIPH_ID_SDMMC1,
|
||||
|
||||
PERIPH_ID_NONE = -1,
|
||||
};
|
||||
|
||||
#endif /* __ASM_ARM_ARCH_PERIPH_H */
|
||||
@@ -0,0 +1,81 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2015 Linaro
|
||||
* Peter Griffin <peter.griffin@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_PINMUX_H
|
||||
#define __ASM_ARM_ARCH_PINMUX_H
|
||||
|
||||
#include "periph.h"
|
||||
|
||||
|
||||
/* iomg bit definition */
|
||||
#define MUX_M0 0
|
||||
#define MUX_M1 1
|
||||
#define MUX_M2 2
|
||||
#define MUX_M3 3
|
||||
#define MUX_M4 4
|
||||
#define MUX_M5 5
|
||||
#define MUX_M6 6
|
||||
#define MUX_M7 7
|
||||
|
||||
/* iocg bit definition */
|
||||
#define PULL_MASK (3)
|
||||
#define PULL_DIS (0)
|
||||
#define PULL_UP (1 << 0)
|
||||
#define PULL_DOWN (1 << 1)
|
||||
|
||||
/* drive strength definition */
|
||||
#define DRIVE_MASK (7 << 4)
|
||||
#define DRIVE1_02MA (0 << 4)
|
||||
#define DRIVE1_04MA (1 << 4)
|
||||
#define DRIVE1_08MA (2 << 4)
|
||||
#define DRIVE1_10MA (3 << 4)
|
||||
#define DRIVE2_02MA (0 << 4)
|
||||
#define DRIVE2_04MA (1 << 4)
|
||||
#define DRIVE2_08MA (2 << 4)
|
||||
#define DRIVE2_10MA (3 << 4)
|
||||
#define DRIVE3_04MA (0 << 4)
|
||||
#define DRIVE3_08MA (1 << 4)
|
||||
#define DRIVE3_12MA (2 << 4)
|
||||
#define DRIVE3_16MA (3 << 4)
|
||||
#define DRIVE3_20MA (4 << 4)
|
||||
#define DRIVE3_24MA (5 << 4)
|
||||
#define DRIVE3_32MA (6 << 4)
|
||||
#define DRIVE3_40MA (7 << 4)
|
||||
#define DRIVE4_02MA (0 << 4)
|
||||
#define DRIVE4_04MA (2 << 4)
|
||||
#define DRIVE4_08MA (4 << 4)
|
||||
#define DRIVE4_10MA (6 << 4)
|
||||
|
||||
#define HI6220_PINMUX0_BASE 0xf7010000
|
||||
#define HI6220_PINMUX1_BASE 0xf7010800
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* maybe more registers, but highest used is 123 */
|
||||
#define REG_NUM 123
|
||||
|
||||
struct hi6220_pinmux0_regs {
|
||||
uint32_t iomg[REG_NUM];
|
||||
};
|
||||
|
||||
struct hi6220_pinmux1_regs {
|
||||
uint32_t iocfg[REG_NUM];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Configures the pinmux for a particular peripheral.
|
||||
*
|
||||
* This function will configure the peripheral pinmux along with
|
||||
* pull-up/down and drive strength.
|
||||
*
|
||||
* @param peripheral peripheral to be configured
|
||||
* @return 0 if ok, -1 on error (e.g. unsupported peripheral)
|
||||
*/
|
||||
int hi6220_pinmux_config(int peripheral);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,76 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#define MXC_CPU_MX23 0x23
|
||||
#define MXC_CPU_MX25 0x25
|
||||
#define MXC_CPU_MX27 0x27
|
||||
#define MXC_CPU_MX28 0x28
|
||||
#define MXC_CPU_MX31 0x31
|
||||
#define MXC_CPU_MX35 0x35
|
||||
#define MXC_CPU_MX51 0x51
|
||||
#define MXC_CPU_MX53 0x53
|
||||
#define MXC_CPU_MX6SL 0x60
|
||||
#define MXC_CPU_MX6DL 0x61
|
||||
#define MXC_CPU_MX6SX 0x62
|
||||
#define MXC_CPU_MX6Q 0x63
|
||||
#define MXC_CPU_MX6UL 0x64
|
||||
#define MXC_CPU_MX6ULL 0x65
|
||||
#define MXC_CPU_MX6ULZ 0x6B
|
||||
#define MXC_CPU_MX6SOLO 0x66 /* dummy */
|
||||
#define MXC_CPU_MX6SLL 0x67
|
||||
#define MXC_CPU_MX6D 0x6A
|
||||
#define MXC_CPU_MX6DP 0x68
|
||||
#define MXC_CPU_MX6QP 0x69
|
||||
#define MXC_CPU_MX7S 0x71 /* dummy ID */
|
||||
#define MXC_CPU_MX7D 0x72
|
||||
#define MXC_CPU_IMX8MQ 0x82
|
||||
#define MXC_CPU_IMX8MM 0x85 /* dummy ID */
|
||||
#define MXC_CPU_IMX8MML 0x86 /* dummy ID */
|
||||
#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */
|
||||
#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
|
||||
#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
|
||||
#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
|
||||
#define MXC_CPU_IMX8MN 0x8b /* dummy ID */
|
||||
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
|
||||
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
|
||||
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
|
||||
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
|
||||
#define MXC_CPU_VF610 0xF6 /* dummy ID */
|
||||
|
||||
#define MXC_SOC_MX6 0x60
|
||||
#define MXC_SOC_MX7 0x70
|
||||
#define MXC_SOC_IMX8M 0x80
|
||||
#define MXC_SOC_IMX8 0x90 /* dummy */
|
||||
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
|
||||
|
||||
#define CHIP_REV_1_0 0x10
|
||||
#define CHIP_REV_1_1 0x11
|
||||
#define CHIP_REV_1_2 0x12
|
||||
#define CHIP_REV_1_5 0x15
|
||||
#define CHIP_REV_2_0 0x20
|
||||
#define CHIP_REV_2_1 0x21
|
||||
#define CHIP_REV_2_5 0x25
|
||||
#define CHIP_REV_3_0 0x30
|
||||
|
||||
#define CHIP_REV_A 0x0
|
||||
#define CHIP_REV_B 0x1
|
||||
|
||||
#define BOARD_REV_1_0 0x0
|
||||
#define BOARD_REV_2_0 0x1
|
||||
#define BOARD_VER_OFFSET 0x8
|
||||
|
||||
#define CS0_128 0
|
||||
#define CS0_64M_CS1_64M 1
|
||||
#define CS0_64M_CS1_32M_CS2_32M 2
|
||||
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
|
||||
|
||||
u32 get_imx_reset_cause(void);
|
||||
ulong get_systemPLLCLK(void);
|
||||
ulong get_FCLK(void);
|
||||
ulong get_HCLK(void);
|
||||
ulong get_BCLK(void);
|
||||
ulong get_PERCLK1(void);
|
||||
ulong get_PERCLK2(void);
|
||||
ulong get_PERCLK3(void);
|
||||
@@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
/*
|
||||
* We use absolute address not PC relative address to jump.
|
||||
* When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000,
|
||||
* our linker address for SPL is from 0x100000. So using absolute address can jump to
|
||||
* the OCRAM address from the alias.
|
||||
* The alias only map first 96KB of OCRAM, so this require the SPL size can't beyond 96KB.
|
||||
* But when using SPL DM, the size increase significantly and may exceed 96KB.
|
||||
* That's why we have to jump to OCRAM.
|
||||
*/
|
||||
|
||||
ldr x0, =reset
|
||||
br x0
|
||||
#else
|
||||
b reset
|
||||
#endif
|
||||
@@ -0,0 +1,27 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IMX8_CLOCK_H__
|
||||
#define __ASM_ARCH_IMX8_CLOCK_H__
|
||||
|
||||
/* Mainly for compatible to imx common code. */
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_AHB_CLK,
|
||||
MXC_IPG_CLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_CSPI_CLK,
|
||||
MXC_AXI_CLK,
|
||||
MXC_DDR_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_ESDHC2_CLK,
|
||||
MXC_ESDHC3_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_FEC_CLK,
|
||||
};
|
||||
|
||||
u32 mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_IMX8_CLOCK_H__ */
|
||||
@@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IMX8_GPIO_H
|
||||
#define __ASM_ARCH_IMX8_GPIO_H
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
/* GPIO registers */
|
||||
struct gpio_regs {
|
||||
u32 gpio_dr; /* data */
|
||||
u32 gpio_dir; /* direction */
|
||||
u32 gpio_psr; /* pad satus */
|
||||
};
|
||||
#endif
|
||||
|
||||
/* IMX8 the GPIO index is from 0 not 1 */
|
||||
#define IMX_GPIO_NR(port, index) (((port) * 32) + ((index) & 31))
|
||||
|
||||
#endif /* __ASM_ARCH_IMX8_GPIO_H */
|
||||
@@ -0,0 +1,56 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __CONTAINER_HEADER_H_
|
||||
#define __CONTAINER_HEADER_H_
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define IV_MAX_LEN 32
|
||||
#define HASH_MAX_LEN 64
|
||||
|
||||
#define CONTAINER_HDR_ALIGNMENT 0x400
|
||||
#define CONTAINER_HDR_EMMC_OFFSET 0
|
||||
#define CONTAINER_HDR_MMCSD_OFFSET SZ_32K
|
||||
#define CONTAINER_HDR_QSPI_OFFSET SZ_4K
|
||||
#define CONTAINER_HDR_NAND_OFFSET SZ_128M
|
||||
|
||||
struct container_hdr {
|
||||
u8 version;
|
||||
u8 length_lsb;
|
||||
u8 length_msb;
|
||||
u8 tag;
|
||||
u32 flags;
|
||||
u16 sw_version;
|
||||
u8 fuse_version;
|
||||
u8 num_images;
|
||||
u16 sig_blk_offset;
|
||||
u16 reserved;
|
||||
} __packed;
|
||||
|
||||
struct boot_img_t {
|
||||
u32 offset;
|
||||
u32 size;
|
||||
u64 dst;
|
||||
u64 entry;
|
||||
u32 hab_flags;
|
||||
u32 meta;
|
||||
u8 hash[HASH_MAX_LEN];
|
||||
u8 iv[IV_MAX_LEN];
|
||||
} __packed;
|
||||
|
||||
struct signature_block_hdr {
|
||||
u8 version;
|
||||
u8 length_lsb;
|
||||
u8 length_msb;
|
||||
u8 tag;
|
||||
u16 srk_table_offset;
|
||||
u16 cert_offset;
|
||||
u16 blob_offset;
|
||||
u16 signature_offset;
|
||||
u32 reserved;
|
||||
} __packed;
|
||||
#endif
|
||||
@@ -0,0 +1,48 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IMX8_REGS_H__
|
||||
#define __ASM_ARCH_IMX8_REGS_H__
|
||||
|
||||
#define ARCH_MXC
|
||||
|
||||
#define LPUART_BASE 0x5A060000
|
||||
|
||||
#define GPT1_BASE_ADDR 0x5D140000
|
||||
#define SCU_LPUART_BASE 0x33220000
|
||||
#define GPIO1_BASE_ADDR 0x5D080000
|
||||
#define GPIO2_BASE_ADDR 0x5D090000
|
||||
#define GPIO3_BASE_ADDR 0x5D0A0000
|
||||
#define GPIO4_BASE_ADDR 0x5D0B0000
|
||||
#define GPIO5_BASE_ADDR 0x5D0C0000
|
||||
#define GPIO6_BASE_ADDR 0x5D0D0000
|
||||
#define GPIO7_BASE_ADDR 0x5D0E0000
|
||||
#define GPIO8_BASE_ADDR 0x5D0F0000
|
||||
#define LPI2C1_BASE_ADDR 0x5A800000
|
||||
#define LPI2C2_BASE_ADDR 0x5A810000
|
||||
#define LPI2C3_BASE_ADDR 0x5A820000
|
||||
#define LPI2C4_BASE_ADDR 0x5A830000
|
||||
#define LPI2C5_BASE_ADDR 0x5A840000
|
||||
|
||||
#ifdef CONFIG_IMX8QXP
|
||||
#define LVDS0_PHYCTRL_BASE 0x56221000
|
||||
#define LVDS1_PHYCTRL_BASE 0x56241000
|
||||
#define MIPI0_SS_BASE 0x56220000
|
||||
#define MIPI1_SS_BASE 0x56240000
|
||||
#endif
|
||||
|
||||
#define APBH_DMA_ARB_BASE_ADDR 0x5B810000
|
||||
#define APBH_DMA_ARB_END_ADDR 0x5B81FFFF
|
||||
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
|
||||
|
||||
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
|
||||
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
|
||||
|
||||
#define PASS_OVER_INFO_ADDR 0x0010fe00
|
||||
|
||||
#define USB_BASE_ADDR 0x5b0d0000
|
||||
#define USB_PHY0_BASE_ADDR 0x5b100000
|
||||
|
||||
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
|
||||
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IMX8_PINS_H__
|
||||
#define __ASM_ARCH_IMX8_PINS_H__
|
||||
|
||||
#if defined(CONFIG_IMX8QXP)
|
||||
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
|
||||
#elif defined(CONFIG_IMX8QM)
|
||||
#include <dt-bindings/pinctrl/pads-imx8qm.h>
|
||||
#else
|
||||
#error "No pin header"
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_IMX8_PINS_H__ */
|
||||
@@ -0,0 +1,40 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IMX8_IOMUX_H__
|
||||
#define __ASM_ARCH_IMX8_IOMUX_H__
|
||||
|
||||
/*
|
||||
* We use 64bits value for iomux settings.
|
||||
* High 32bits are used for padring register value,
|
||||
* low 16bits are used for pin index.
|
||||
*/
|
||||
typedef u64 iomux_cfg_t;
|
||||
|
||||
#define PADRING_IFMUX_EN_SHIFT 31
|
||||
#define PADRING_IFMUX_EN_MASK BIT(31)
|
||||
#define PADRING_GP_EN_SHIFT 30
|
||||
#define PADRING_GP_EN_MASK BIT(30)
|
||||
#define PADRING_IFMUX_SHIFT 27
|
||||
#define PADRING_IFMUX_MASK GENMASK(29, 27)
|
||||
#define PADRING_CONFIG_SHIFT 25
|
||||
#define PADRING_LPCONFIG_SHIFT 23
|
||||
#define PADRING_PULL_SHIFT 5
|
||||
#define PADRING_DSE_SHIFT 0
|
||||
|
||||
#define MUX_PAD_CTRL_SHIFT 32
|
||||
#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT)
|
||||
#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
|
||||
#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT)
|
||||
#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT)
|
||||
#define PIN_ID_MASK ((iomux_cfg_t)0xFFFF)
|
||||
|
||||
/* Valid mux alt0 to alt7 */
|
||||
#define MUX_MODE_ALT(x) (((iomux_cfg_t)(x) << MUX_MODE_SHIFT) & \
|
||||
MUX_MODE_MASK)
|
||||
|
||||
void imx8_iomux_setup_pad(iomux_cfg_t pad);
|
||||
void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count);
|
||||
#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */
|
||||
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H
|
||||
#define _ASM_ARCH_IMX8_POWER_DOMAIN_H
|
||||
|
||||
#include <asm/arch/sci/types.h>
|
||||
|
||||
struct imx8_power_domain_platdata {
|
||||
sc_rsrc_t resource_id;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,185 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SC_RPC_H
|
||||
#define SC_RPC_H
|
||||
|
||||
/* Note: Check SCFW API Released DOC before you want to modify something */
|
||||
#define SC_RPC_VERSION 1U
|
||||
|
||||
#define SC_RPC_MAX_MSG 8U
|
||||
|
||||
#define RPC_VER(MSG) ((MSG)->version)
|
||||
#define RPC_SIZE(MSG) ((MSG)->size)
|
||||
#define RPC_SVC(MSG) ((MSG)->svc)
|
||||
#define RPC_FUNC(MSG) ((MSG)->func)
|
||||
#define RPC_R8(MSG) ((MSG)->func)
|
||||
#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
|
||||
#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
|
||||
#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
|
||||
#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
|
||||
#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
|
||||
#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
|
||||
|
||||
#define SC_RPC_SVC_UNKNOWN 0U
|
||||
#define SC_RPC_SVC_RETURN 1U
|
||||
#define SC_RPC_SVC_PM 2U
|
||||
#define SC_RPC_SVC_RM 3U
|
||||
#define SC_RPC_SVC_TIMER 5U
|
||||
#define SC_RPC_SVC_PAD 6U
|
||||
#define SC_RPC_SVC_MISC 7U
|
||||
#define SC_RPC_SVC_IRQ 8U
|
||||
#define SC_RPC_SVC_SECO 9U
|
||||
#define SC_RPC_SVC_ABORT 10U
|
||||
|
||||
|
||||
/* Types */
|
||||
|
||||
struct sc_rpc_msg_s {
|
||||
u8 version;
|
||||
u8 size;
|
||||
u8 svc;
|
||||
u8 func;
|
||||
union {
|
||||
s32 i32[(SC_RPC_MAX_MSG - 1U)];
|
||||
s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U];
|
||||
s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U];
|
||||
u32 u32[(SC_RPC_MAX_MSG - 1U)];
|
||||
u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U];
|
||||
u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U];
|
||||
} DATA;
|
||||
};
|
||||
|
||||
/* PM RPC */
|
||||
#define PM_FUNC_UNKNOWN 0
|
||||
#define PM_FUNC_SET_SYS_POWER_MODE 19U
|
||||
#define PM_FUNC_SET_PARTITION_POWER_MODE 1U
|
||||
#define PM_FUNC_GET_SYS_POWER_MODE 2U
|
||||
#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U
|
||||
#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U
|
||||
#define PM_FUNC_REQ_LOW_POWER_MODE 16U
|
||||
#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U
|
||||
#define PM_FUNC_SET_CPU_RESUME_ADDR 17U
|
||||
#define PM_FUNC_SET_CPU_RESUME 21U
|
||||
#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U
|
||||
#define PM_FUNC_SET_CLOCK_RATE 5U
|
||||
#define PM_FUNC_GET_CLOCK_RATE 6U
|
||||
#define PM_FUNC_CLOCK_ENABLE 7U
|
||||
#define PM_FUNC_SET_CLOCK_PARENT 14U
|
||||
#define PM_FUNC_GET_CLOCK_PARENT 15U
|
||||
#define PM_FUNC_RESET 13U
|
||||
#define PM_FUNC_RESET_REASON 10U
|
||||
#define PM_FUNC_BOOT 8U
|
||||
#define PM_FUNC_REBOOT 9U
|
||||
#define PM_FUNC_REBOOT_PARTITION 12U
|
||||
#define PM_FUNC_CPU_START 11U
|
||||
#define PM_FUNC_IS_PARTITION_STARTED 24U
|
||||
|
||||
/* MISC RPC */
|
||||
#define MISC_FUNC_UNKNOWN 0
|
||||
#define MISC_FUNC_SET_CONTROL 1U
|
||||
#define MISC_FUNC_GET_CONTROL 2U
|
||||
#define MISC_FUNC_SET_MAX_DMA_GROUP 4U
|
||||
#define MISC_FUNC_SET_DMA_GROUP 5U
|
||||
#define MISC_FUNC_SECO_IMAGE_LOAD 8U
|
||||
#define MISC_FUNC_SECO_AUTHENTICATE 9U
|
||||
#define MISC_FUNC_SECO_FUSE_WRITE 20U
|
||||
#define MISC_FUNC_SECO_ENABLE_DEBUG 21U
|
||||
#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U
|
||||
#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U
|
||||
#define MISC_FUNC_SECO_BUILD_INFO 24U
|
||||
#define MISC_FUNC_DEBUG_OUT 10U
|
||||
#define MISC_FUNC_WAVEFORM_CAPTURE 6U
|
||||
#define MISC_FUNC_BUILD_INFO 15U
|
||||
#define MISC_FUNC_UNIQUE_ID 19U
|
||||
#define MISC_FUNC_SET_ARI 3U
|
||||
#define MISC_FUNC_BOOT_STATUS 7U
|
||||
#define MISC_FUNC_BOOT_DONE 14U
|
||||
#define MISC_FUNC_OTP_FUSE_READ 11U
|
||||
#define MISC_FUNC_OTP_FUSE_WRITE 17U
|
||||
#define MISC_FUNC_SET_TEMP 12U
|
||||
#define MISC_FUNC_GET_TEMP 13U
|
||||
#define MISC_FUNC_GET_BOOT_DEV 16U
|
||||
#define MISC_FUNC_GET_BUTTON_STATUS 18U
|
||||
|
||||
/* PAD RPC */
|
||||
#define PAD_FUNC_UNKNOWN 0
|
||||
#define PAD_FUNC_SET_MUX 1U
|
||||
#define PAD_FUNC_GET_MUX 6U
|
||||
#define PAD_FUNC_SET_GP 2U
|
||||
#define PAD_FUNC_GET_GP 7U
|
||||
#define PAD_FUNC_SET_WAKEUP 4U
|
||||
#define PAD_FUNC_GET_WAKEUP 9U
|
||||
#define PAD_FUNC_SET_ALL 5U
|
||||
#define PAD_FUNC_GET_ALL 10U
|
||||
#define PAD_FUNC_SET 15U
|
||||
#define PAD_FUNC_GET 16U
|
||||
#define PAD_FUNC_SET_GP_28FDSOI 11U
|
||||
#define PAD_FUNC_GET_GP_28FDSOI 12U
|
||||
#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U
|
||||
#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U
|
||||
#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U
|
||||
#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U
|
||||
|
||||
/* RM RPC */
|
||||
#define RM_FUNC_UNKNOWN 0
|
||||
#define RM_FUNC_PARTITION_ALLOC 1U
|
||||
#define RM_FUNC_SET_CONFIDENTIAL 31U
|
||||
#define RM_FUNC_PARTITION_FREE 2U
|
||||
#define RM_FUNC_GET_DID 26U
|
||||
#define RM_FUNC_PARTITION_STATIC 3U
|
||||
#define RM_FUNC_PARTITION_LOCK 4U
|
||||
#define RM_FUNC_GET_PARTITION 5U
|
||||
#define RM_FUNC_SET_PARENT 6U
|
||||
#define RM_FUNC_MOVE_ALL 7U
|
||||
#define RM_FUNC_ASSIGN_RESOURCE 8U
|
||||
#define RM_FUNC_SET_RESOURCE_MOVABLE 9U
|
||||
#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U
|
||||
#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U
|
||||
#define RM_FUNC_SET_MASTER_SID 11U
|
||||
#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U
|
||||
#define RM_FUNC_IS_RESOURCE_OWNED 13U
|
||||
#define RM_FUNC_GET_RESOURCE_OWNER 33U
|
||||
#define RM_FUNC_IS_RESOURCE_MASTER 14U
|
||||
#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U
|
||||
#define RM_FUNC_GET_RESOURCE_INFO 16U
|
||||
#define RM_FUNC_MEMREG_ALLOC 17U
|
||||
#define RM_FUNC_MEMREG_SPLIT 29U
|
||||
#define RM_FUNC_MEMREG_FREE 18U
|
||||
#define RM_FUNC_FIND_MEMREG 30U
|
||||
#define RM_FUNC_ASSIGN_MEMREG 19U
|
||||
#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U
|
||||
#define RM_FUNC_IS_MEMREG_OWNED 21U
|
||||
#define RM_FUNC_GET_MEMREG_INFO 22U
|
||||
#define RM_FUNC_ASSIGN_PAD 23U
|
||||
#define RM_FUNC_SET_PAD_MOVABLE 24U
|
||||
#define RM_FUNC_IS_PAD_OWNED 25U
|
||||
#define RM_FUNC_DUMP 27U
|
||||
|
||||
/* SECO RPC */
|
||||
#define SECO_FUNC_UNKNOWN 0
|
||||
#define SECO_FUNC_IMAGE_LOAD 1U
|
||||
#define SECO_FUNC_AUTHENTICATE 2U
|
||||
#define SECO_FUNC_FORWARD_LIFECYCLE 3U
|
||||
#define SECO_FUNC_RETURN_LIFECYCLE 4U
|
||||
#define SECO_FUNC_COMMIT 5U
|
||||
#define SECO_FUNC_ATTEST_MODE 6U
|
||||
#define SECO_FUNC_ATTEST 7U
|
||||
#define SECO_FUNC_GET_ATTEST_PKEY 8U
|
||||
#define SECO_FUNC_GET_ATTEST_SIGN 9U
|
||||
#define SECO_FUNC_ATTEST_VERIFY 10U
|
||||
#define SECO_FUNC_GEN_KEY_BLOB 11U
|
||||
#define SECO_FUNC_LOAD_KEY 12U
|
||||
#define SECO_FUNC_GET_MP_KEY 13U
|
||||
#define SECO_FUNC_UPDATE_MPMR 14U
|
||||
#define SECO_FUNC_GET_MP_SIGN 15U
|
||||
#define SECO_FUNC_BUILD_INFO 16U
|
||||
#define SECO_FUNC_CHIP_INFO 17U
|
||||
#define SECO_FUNC_ENABLE_DEBUG 18U
|
||||
#define SECO_FUNC_GET_EVENT 19U
|
||||
#define SECO_FUNC_FUSE_WRITE 20U
|
||||
|
||||
#endif /* SC_RPC_H */
|
||||
@@ -0,0 +1,126 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef _SC_SCI_H
|
||||
#define _SC_SCI_H
|
||||
|
||||
#include <asm/arch/sci/types.h>
|
||||
#include <asm/arch/sci/svc/misc/api.h>
|
||||
#include <asm/arch/sci/svc/pad/api.h>
|
||||
#include <asm/arch/sci/svc/pm/api.h>
|
||||
#include <asm/arch/sci/svc/rm/api.h>
|
||||
#include <asm/arch/sci/svc/seco/api.h>
|
||||
#include <asm/arch/sci/rpc.h>
|
||||
#include <dt-bindings/soc/imx_rsrc.h>
|
||||
#include <linux/errno.h>
|
||||
|
||||
static inline int sc_err_to_linux(sc_err_t err)
|
||||
{
|
||||
int ret;
|
||||
|
||||
switch (err) {
|
||||
case SC_ERR_NONE:
|
||||
return 0;
|
||||
case SC_ERR_VERSION:
|
||||
case SC_ERR_CONFIG:
|
||||
case SC_ERR_PARM:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
case SC_ERR_NOACCESS:
|
||||
case SC_ERR_LOCKED:
|
||||
case SC_ERR_UNAVAILABLE:
|
||||
ret = -EACCES;
|
||||
break;
|
||||
case SC_ERR_NOTFOUND:
|
||||
case SC_ERR_NOPOWER:
|
||||
ret = -ENODEV;
|
||||
break;
|
||||
case SC_ERR_IPC:
|
||||
ret = -EIO;
|
||||
break;
|
||||
case SC_ERR_BUSY:
|
||||
ret = -EBUSY;
|
||||
break;
|
||||
case SC_ERR_FAIL:
|
||||
ret = -EIO;
|
||||
break;
|
||||
default:
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
debug("%s %d %d\n", __func__, err, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* PM API*/
|
||||
int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t mode);
|
||||
int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t *mode);
|
||||
int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
|
||||
sc_pm_clock_rate_t *rate);
|
||||
int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
|
||||
sc_pm_clock_rate_t *rate);
|
||||
int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
|
||||
sc_bool_t enable, sc_bool_t autog);
|
||||
int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
|
||||
sc_pm_clk_parent_t parent);
|
||||
int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
|
||||
sc_faddr_t address);
|
||||
sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
|
||||
|
||||
/* MISC API */
|
||||
int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_ctrl_t ctrl, u32 val);
|
||||
int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
|
||||
u32 *val);
|
||||
void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
|
||||
void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
|
||||
void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
|
||||
int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
|
||||
int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
|
||||
s16 *celsius, s8 *tenths);
|
||||
|
||||
/* RM API */
|
||||
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
|
||||
int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start,
|
||||
sc_faddr_t addr_end);
|
||||
int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
|
||||
sc_rm_pt_t pt, sc_rm_perm_t perm);
|
||||
int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
|
||||
sc_faddr_t *addr_end);
|
||||
sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
|
||||
int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
|
||||
sc_bool_t isolated, sc_bool_t restricted,
|
||||
sc_bool_t grant, sc_bool_t coherent);
|
||||
int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
|
||||
int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
|
||||
int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
|
||||
int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
|
||||
int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
|
||||
sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
|
||||
int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rm_pt_t *pt);
|
||||
|
||||
/* PAD API */
|
||||
int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
|
||||
|
||||
/* SMMU API */
|
||||
int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
|
||||
|
||||
/* SECO API */
|
||||
int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
|
||||
sc_faddr_t addr);
|
||||
int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
|
||||
int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
|
||||
u32 *uid_h);
|
||||
void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
|
||||
int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
|
||||
int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
|
||||
sc_faddr_t export_addr, u16 max_size);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef SC_MISC_API_H
|
||||
#define SC_MISC_API_H
|
||||
|
||||
/* Defines for sc_misc_boot_status_t */
|
||||
#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */
|
||||
#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */
|
||||
|
||||
/* Defines for sc_misc_seco_auth_cmd_t */
|
||||
#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */
|
||||
#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */
|
||||
#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */
|
||||
|
||||
/* Defines for sc_misc_temp_t */
|
||||
#define SC_MISC_TEMP 0U /* Temp sensor */
|
||||
#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */
|
||||
#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */
|
||||
|
||||
/* Defines for sc_misc_seco_auth_cmd_t */
|
||||
#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */
|
||||
#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */
|
||||
#define SC_MISC_REL_CONTAINER 2U /* Release container */
|
||||
|
||||
typedef u8 sc_misc_boot_status_t;
|
||||
typedef u8 sc_misc_temp_t;
|
||||
|
||||
#endif /* SC_MISC_API_H */
|
||||
@@ -0,0 +1,57 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef SC_PAD_API_H
|
||||
#define SC_PAD_API_H
|
||||
|
||||
/* Defines for sc_pad_config_t */
|
||||
#define SC_PAD_CONFIG_NORMAL 0U /* Normal */
|
||||
#define SC_PAD_CONFIG_OD 1U /* Open Drain */
|
||||
#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */
|
||||
#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */
|
||||
|
||||
/* Defines for sc_pad_iso_t */
|
||||
#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */
|
||||
#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */
|
||||
#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */
|
||||
#define SC_PAD_ISO_ON 3U /* ISO latched data is held */
|
||||
|
||||
/* Defines for sc_pad_28fdsoi_dse_t */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */
|
||||
#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */
|
||||
#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */
|
||||
#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */
|
||||
#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength dual volt */
|
||||
#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength dual volt */
|
||||
|
||||
/* Defines for sc_pad_28fdsoi_ps_t */
|
||||
#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */
|
||||
#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */
|
||||
#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */
|
||||
#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */
|
||||
|
||||
/* Defines for sc_pad_28fdsoi_pus_t */
|
||||
#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */
|
||||
#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */
|
||||
#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */
|
||||
#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */
|
||||
|
||||
/* Defines for sc_pad_wakeup_t */
|
||||
#define SC_PAD_WAKEUP_OFF 0U /* Off */
|
||||
#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */
|
||||
#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */
|
||||
#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */
|
||||
#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */
|
||||
#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */
|
||||
|
||||
#endif /* SC_PAD_API_H */
|
||||
@@ -0,0 +1,44 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef SC_PM_API_H
|
||||
#define SC_PM_API_H
|
||||
|
||||
/* Defines for sc_pm_power_mode_t */
|
||||
#define SC_PM_PW_MODE_OFF 0U /* Power off */
|
||||
#define SC_PM_PW_MODE_STBY 1U /* Power in standby */
|
||||
#define SC_PM_PW_MODE_LP 2U /* Power in low-power */
|
||||
#define SC_PM_PW_MODE_ON 3U /* Power on */
|
||||
|
||||
/* Defines for sc_pm_clk_t */
|
||||
#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */
|
||||
#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */
|
||||
#define SC_PM_CLK_PER 2U /* Peripheral clock */
|
||||
#define SC_PM_CLK_PHY 3U /* Phy clock */
|
||||
#define SC_PM_CLK_MISC 4U /* Misc clock */
|
||||
#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */
|
||||
#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */
|
||||
#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */
|
||||
#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */
|
||||
#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */
|
||||
#define SC_PM_CLK_CPU 2U /* CPU clock */
|
||||
#define SC_PM_CLK_PLL 4U /* PLL */
|
||||
#define SC_PM_CLK_BYPASS 4U /* Bypass clock */
|
||||
|
||||
/* Defines for sc_pm_clk_mode_t */
|
||||
#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */
|
||||
#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */
|
||||
#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */
|
||||
#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */
|
||||
#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */
|
||||
#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */
|
||||
|
||||
typedef u8 sc_pm_power_mode_t;
|
||||
typedef u8 sc_pm_clk_t;
|
||||
typedef u8 sc_pm_clk_mode_t;
|
||||
typedef u8 sc_pm_clk_parent_t;
|
||||
typedef u32 sc_pm_clock_rate_t;
|
||||
|
||||
#endif /* SC_PM_API_H */
|
||||
@@ -0,0 +1,69 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef SC_RM_API_H
|
||||
#define SC_RM_API_H
|
||||
|
||||
#include <asm/arch/sci/types.h>
|
||||
|
||||
/* Defines for type widths */
|
||||
#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */
|
||||
#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */
|
||||
#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */
|
||||
#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */
|
||||
#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */
|
||||
#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */
|
||||
|
||||
/* Defines for ALL parameters */
|
||||
#define SC_RM_PT_ALL ((sc_rm_pt_t)UINT8_MAX) /* All partitions */
|
||||
#define SC_RM_MR_ALL ((sc_rm_mr_t)UINT8_MAX) /* All memory regions */
|
||||
|
||||
/* Defines for sc_rm_spa_t */
|
||||
#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */
|
||||
#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */
|
||||
#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */
|
||||
#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */
|
||||
|
||||
/* Defines for sc_rm_perm_t */
|
||||
#define SC_RM_PERM_NONE 0U /* No access */
|
||||
#define SC_RM_PERM_SEC_R 1U /* Secure RO */
|
||||
#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */
|
||||
#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */
|
||||
#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */
|
||||
#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */
|
||||
#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */
|
||||
#define SC_RM_PERM_FULL 7U /* Full access */
|
||||
|
||||
/* Types */
|
||||
|
||||
/*!
|
||||
* This type is used to declare a resource partition.
|
||||
*/
|
||||
typedef u8 sc_rm_pt_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a memory region.
|
||||
*/
|
||||
typedef u8 sc_rm_mr_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a resource domain ID used by the
|
||||
* isolation HW.
|
||||
*/
|
||||
typedef u8 sc_rm_did_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare an SMMU StreamID.
|
||||
*/
|
||||
typedef u16 sc_rm_sid_t;
|
||||
|
||||
/*!
|
||||
* This type is a used to declare master transaction attributes.
|
||||
*/
|
||||
typedef u8 sc_rm_spa_t;
|
||||
|
||||
typedef u8 sc_rm_perm_t;
|
||||
|
||||
#endif /* SC_RM_API_H */
|
||||
@@ -0,0 +1,37 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef SC_SECO_API_H
|
||||
#define SC_SECO_API_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <asm/arch/sci/types.h>
|
||||
|
||||
/* Defines */
|
||||
#define SC_SECO_AUTH_CONTAINER 0U /* Authenticate container */
|
||||
#define SC_SECO_VERIFY_IMAGE 1U /* Verify image */
|
||||
#define SC_SECO_REL_CONTAINER 2U /* Release container */
|
||||
#define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */
|
||||
#define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */
|
||||
#define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */
|
||||
|
||||
#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */
|
||||
#define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */
|
||||
#define SC_SECO_RNG_STAT_READY 2U /* Initialized */
|
||||
|
||||
/* Types */
|
||||
|
||||
/*!
|
||||
* This type is used to issue SECO authenticate commands.
|
||||
*/
|
||||
typedef u8 sc_seco_auth_cmd_t;
|
||||
|
||||
/*!
|
||||
* This type is used to return the RNG initialization status.
|
||||
*/
|
||||
typedef u32 sc_seco_rng_stat_t;
|
||||
|
||||
#endif /* SC_SECO_API_H */
|
||||
@@ -0,0 +1,220 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef SC_TYPES_H
|
||||
#define SC_TYPES_H
|
||||
|
||||
/* Includes */
|
||||
#include <linux/types.h>
|
||||
|
||||
/* Defines */
|
||||
/*
|
||||
* This type is used to declare a handle for an IPC communication
|
||||
* channel. Its meaning is specific to the IPC implementation.
|
||||
*/
|
||||
typedef u64 sc_ipc_t;
|
||||
|
||||
/* Defines for common frequencies */
|
||||
#define SC_32KHZ 32768U /* 32KHz */
|
||||
#define SC_10MHZ 10000000U /* 10MHz */
|
||||
#define SC_20MHZ 20000000U /* 20MHz */
|
||||
#define SC_25MHZ 25000000U /* 25MHz */
|
||||
#define SC_27MHZ 27000000U /* 27MHz */
|
||||
#define SC_40MHZ 40000000U /* 40MHz */
|
||||
#define SC_45MHZ 45000000U /* 45MHz */
|
||||
#define SC_50MHZ 50000000U /* 50MHz */
|
||||
#define SC_60MHZ 60000000U /* 60MHz */
|
||||
#define SC_66MHZ 66666666U /* 66MHz */
|
||||
#define SC_74MHZ 74250000U /* 74.25MHz */
|
||||
#define SC_80MHZ 80000000U /* 80MHz */
|
||||
#define SC_83MHZ 83333333U /* 83MHz */
|
||||
#define SC_84MHZ 84375000U /* 84.37MHz */
|
||||
#define SC_100MHZ 100000000U /* 100MHz */
|
||||
#define SC_125MHZ 125000000U /* 125MHz */
|
||||
#define SC_133MHZ 133333333U /* 133MHz */
|
||||
#define SC_135MHZ 135000000U /* 135MHz */
|
||||
#define SC_150MHZ 150000000U /* 150MHz */
|
||||
#define SC_160MHZ 160000000U /* 160MHz */
|
||||
#define SC_166MHZ 166666666U /* 166MHz */
|
||||
#define SC_175MHZ 175000000U /* 175MHz */
|
||||
#define SC_180MHZ 180000000U /* 180MHz */
|
||||
#define SC_200MHZ 200000000U /* 200MHz */
|
||||
#define SC_250MHZ 250000000U /* 250MHz */
|
||||
#define SC_266MHZ 266666666U /* 266MHz */
|
||||
#define SC_300MHZ 300000000U /* 300MHz */
|
||||
#define SC_312MHZ 312500000U /* 312.5MHZ */
|
||||
#define SC_320MHZ 320000000U /* 320MHz */
|
||||
#define SC_325MHZ 325000000U /* 325MHz */
|
||||
#define SC_333MHZ 333333333U /* 333MHz */
|
||||
#define SC_350MHZ 350000000U /* 350MHz */
|
||||
#define SC_372MHZ 372000000U /* 372MHz */
|
||||
#define SC_375MHZ 375000000U /* 375MHz */
|
||||
#define SC_400MHZ 400000000U /* 400MHz */
|
||||
#define SC_500MHZ 500000000U /* 500MHz */
|
||||
#define SC_594MHZ 594000000U /* 594MHz */
|
||||
#define SC_625MHZ 625000000U /* 625MHz */
|
||||
#define SC_640MHZ 640000000U /* 640MHz */
|
||||
#define SC_650MHZ 650000000U /* 650MHz */
|
||||
#define SC_667MHZ 666666667U /* 667MHz */
|
||||
#define SC_675MHZ 675000000U /* 675MHz */
|
||||
#define SC_700MHZ 700000000U /* 700MHz */
|
||||
#define SC_720MHZ 720000000U /* 720MHz */
|
||||
#define SC_750MHZ 750000000U /* 750MHz */
|
||||
#define SC_800MHZ 800000000U /* 800MHz */
|
||||
#define SC_850MHZ 850000000U /* 850MHz */
|
||||
#define SC_900MHZ 900000000U /* 900MHz */
|
||||
#define SC_1000MHZ 1000000000U /* 1GHz */
|
||||
#define SC_1060MHZ 1060000000U /* 1.06GHz */
|
||||
#define SC_1188MHZ 1188000000U /* 1.188GHz */
|
||||
#define SC_1260MHZ 1260000000U /* 1.26GHz */
|
||||
#define SC_1280MHZ 1280000000U /* 1.28GHz */
|
||||
#define SC_1300MHZ 1300000000U /* 1.3GHz */
|
||||
#define SC_1400MHZ 1400000000U /* 1.4GHz */
|
||||
#define SC_1500MHZ 1500000000U /* 1.5GHz */
|
||||
#define SC_1600MHZ 1600000000U /* 1.6GHz */
|
||||
#define SC_1800MHZ 1800000000U /* 1.8GHz */
|
||||
#define SC_2000MHZ 2000000000U /* 2.0GHz */
|
||||
#define SC_2112MHZ 2112000000U /* 2.12GHz */
|
||||
|
||||
/* Defines for 24M related frequencies */
|
||||
#define SC_8MHZ 8000000U /* 8MHz */
|
||||
#define SC_12MHZ 12000000U /* 12MHz */
|
||||
#define SC_19MHZ 19800000U /* 19.8MHz */
|
||||
#define SC_24MHZ 24000000U /* 24MHz */
|
||||
#define SC_48MHZ 48000000U /* 48MHz */
|
||||
#define SC_120MHZ 120000000U /* 120MHz */
|
||||
#define SC_132MHZ 132000000U /* 132MHz */
|
||||
#define SC_144MHZ 144000000U /* 144MHz */
|
||||
#define SC_192MHZ 192000000U /* 192MHz */
|
||||
#define SC_211MHZ 211200000U /* 211.2MHz */
|
||||
#define SC_240MHZ 240000000U /* 240MHz */
|
||||
#define SC_264MHZ 264000000U /* 264MHz */
|
||||
#define SC_352MHZ 352000000U /* 352MHz */
|
||||
#define SC_360MHZ 360000000U /* 360MHz */
|
||||
#define SC_384MHZ 384000000U /* 384MHz */
|
||||
#define SC_396MHZ 396000000U /* 396MHz */
|
||||
#define SC_432MHZ 432000000U /* 432MHz */
|
||||
#define SC_480MHZ 480000000U /* 480MHz */
|
||||
#define SC_600MHZ 600000000U /* 600MHz */
|
||||
#define SC_744MHZ 744000000U /* 744MHz */
|
||||
#define SC_792MHZ 792000000U /* 792MHz */
|
||||
#define SC_864MHZ 864000000U /* 864MHz */
|
||||
#define SC_960MHZ 960000000U /* 960MHz */
|
||||
#define SC_1056MHZ 1056000000U /* 1056MHz */
|
||||
#define SC_1104MHZ 1104000000U /* 1104MHz */
|
||||
#define SC_1200MHZ 1200000000U /* 1.2GHz */
|
||||
#define SC_1464MHZ 1464000000U /* 1.464GHz */
|
||||
#define SC_2400MHZ 2400000000U /* 2.4GHz */
|
||||
|
||||
/* Defines for A/V related frequencies */
|
||||
#define SC_62MHZ 62937500U /* 62.9375MHz */
|
||||
#define SC_755MHZ 755250000U /* 755.25MHz */
|
||||
|
||||
/* Defines for type widths */
|
||||
#define SC_FADDR_W 36U /* Width of sc_faddr_t */
|
||||
#define SC_BOOL_W 1U /* Width of sc_bool_t */
|
||||
#define SC_ERR_W 4U /* Width of sc_err_t */
|
||||
#define SC_RSRC_W 10U /* Width of sc_rsrc_t */
|
||||
#define SC_CTRL_W 6U /* Width of sc_ctrl_t */
|
||||
|
||||
/* Defines for sc_bool_t */
|
||||
#define SC_FALSE ((sc_bool_t)0U)
|
||||
#define SC_TRUE ((sc_bool_t)1U)
|
||||
|
||||
/* Defines for sc_err_t */
|
||||
#define SC_ERR_NONE 0U /* Success */
|
||||
#define SC_ERR_VERSION 1U /* Incompatible API version */
|
||||
#define SC_ERR_CONFIG 2U /* Configuration error */
|
||||
#define SC_ERR_PARM 3U /* Bad parameter */
|
||||
#define SC_ERR_NOACCESS 4U /* Permission error (no access) */
|
||||
#define SC_ERR_LOCKED 5U /* Permission error (locked) */
|
||||
#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */
|
||||
#define SC_ERR_NOTFOUND 7U /* Not found */
|
||||
#define SC_ERR_NOPOWER 8U /* No power */
|
||||
#define SC_ERR_IPC 9U /* Generic IPC error */
|
||||
#define SC_ERR_BUSY 10U /* Resource is currently busy/active */
|
||||
#define SC_ERR_FAIL 11U /* General I/O failure */
|
||||
#define SC_ERR_LAST 12U
|
||||
|
||||
/* Defines for sc_ctrl_t. */
|
||||
#define SC_C_TEMP 0U
|
||||
#define SC_C_TEMP_HI 1U
|
||||
#define SC_C_TEMP_LOW 2U
|
||||
#define SC_C_PXL_LINK_MST1_ADDR 3U
|
||||
#define SC_C_PXL_LINK_MST2_ADDR 4U
|
||||
#define SC_C_PXL_LINK_MST_ENB 5U
|
||||
#define SC_C_PXL_LINK_MST1_ENB 6U
|
||||
#define SC_C_PXL_LINK_MST2_ENB 7U
|
||||
#define SC_C_PXL_LINK_SLV1_ADDR 8U
|
||||
#define SC_C_PXL_LINK_SLV2_ADDR 9U
|
||||
#define SC_C_PXL_LINK_MST_VLD 10U
|
||||
#define SC_C_PXL_LINK_MST1_VLD 11U
|
||||
#define SC_C_PXL_LINK_MST2_VLD 12U
|
||||
#define SC_C_SINGLE_MODE 13U
|
||||
#define SC_C_ID 14U
|
||||
#define SC_C_PXL_CLK_POLARITY 15U
|
||||
#define SC_C_LINESTATE 16U
|
||||
#define SC_C_PCIE_G_RST 17U
|
||||
#define SC_C_PCIE_BUTTON_RST 18U
|
||||
#define SC_C_PCIE_PERST 19U
|
||||
#define SC_C_PHY_RESET 20U
|
||||
#define SC_C_PXL_LINK_RATE_CORRECTION 21U
|
||||
#define SC_C_PANIC 22U
|
||||
#define SC_C_PRIORITY_GROUP 23U
|
||||
#define SC_C_TXCLK 24U
|
||||
#define SC_C_CLKDIV 25U
|
||||
#define SC_C_DISABLE_50 26U
|
||||
#define SC_C_DISABLE_125 27U
|
||||
#define SC_C_SEL_125 28U
|
||||
#define SC_C_MODE 29U
|
||||
#define SC_C_SYNC_CTRL0 30U
|
||||
#define SC_C_KACHUNK_CNT 31U
|
||||
#define SC_C_KACHUNK_SEL 32U
|
||||
#define SC_C_SYNC_CTRL1 33U
|
||||
#define SC_C_DPI_RESET 34U
|
||||
#define SC_C_MIPI_RESET 35U
|
||||
#define SC_C_DUAL_MODE 36U
|
||||
#define SC_C_VOLTAGE 37U
|
||||
#define SC_C_PXL_LINK_SEL 38U
|
||||
#define SC_C_OFS_SEL 39U
|
||||
#define SC_C_OFS_AUDIO 40U
|
||||
#define SC_C_OFS_PERIPH 41U
|
||||
#define SC_C_OFS_IRQ 42U
|
||||
#define SC_C_RST0 43U
|
||||
#define SC_C_RST1 44U
|
||||
#define SC_C_SEL0 45U
|
||||
#define SC_C_LAST 46U
|
||||
|
||||
#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */
|
||||
|
||||
/* Types */
|
||||
|
||||
/* This type is used to store a boolean */
|
||||
typedef u8 sc_bool_t;
|
||||
|
||||
/* This type is used to store a system (full-size) address. */
|
||||
typedef u64 sc_faddr_t;
|
||||
|
||||
/* This type is used to indicate error response for most functions. */
|
||||
typedef u8 sc_err_t;
|
||||
|
||||
/*
|
||||
* This type is used to indicate a resource. Resources include peripherals
|
||||
* and bus masters (but not memory regions). Note items from list should
|
||||
* never be changed or removed (only added to at the end of the list).
|
||||
*/
|
||||
typedef u16 sc_rsrc_t;
|
||||
|
||||
/* This type is used to indicate a control. */
|
||||
typedef u8 sc_ctrl_t;
|
||||
|
||||
/*
|
||||
* This type is used to indicate a pad. Valid values are SoC specific.
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
typedef u16 sc_pad_t;
|
||||
|
||||
#endif /* SC_TYPES_H */
|
||||
@@ -0,0 +1,23 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#include <asm/arch/sci/sci.h>
|
||||
#include <asm/mach-imx/sys_proto.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct pass_over_info_t {
|
||||
u16 barker;
|
||||
u16 len;
|
||||
u32 g_bt_cfg_shadow;
|
||||
u32 card_address_mode;
|
||||
u32 bad_block_count_met;
|
||||
u32 g_ap_mu;
|
||||
};
|
||||
|
||||
extern unsigned long boot_pointer[];
|
||||
void build_info(void);
|
||||
enum boot_device get_boot_device(void);
|
||||
int print_bootinfo(void);
|
||||
int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
|
||||
@@ -0,0 +1,275 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan at nxp.com>
|
||||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#ifdef CONFIG_IMX8MQ
|
||||
#include <asm/arch/clock_imx8mq.h>
|
||||
#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
|
||||
#include <asm/arch/clock_imx8mm.h>
|
||||
#else
|
||||
#error "Error no clock.h"
|
||||
#endif
|
||||
|
||||
#define MHZ(X) ((X) * 1000000UL)
|
||||
|
||||
/* Mainly for compatible to imx common code. */
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_IPG_CLK,
|
||||
MXC_CSPI_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_ESDHC2_CLK,
|
||||
MXC_ESDHC3_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_QSPI_CLK,
|
||||
};
|
||||
|
||||
enum clk_slice_type {
|
||||
CORE_CLOCK_SLICE,
|
||||
BUS_CLOCK_SLICE,
|
||||
IP_CLOCK_SLICE,
|
||||
AHB_CLOCK_SLICE,
|
||||
IPG_CLOCK_SLICE,
|
||||
CORE_SEL_CLOCK_SLICE,
|
||||
DRAM_SEL_CLOCK_SLICE,
|
||||
};
|
||||
|
||||
enum root_pre_div {
|
||||
CLK_ROOT_PRE_DIV1 = 0,
|
||||
CLK_ROOT_PRE_DIV2,
|
||||
CLK_ROOT_PRE_DIV3,
|
||||
CLK_ROOT_PRE_DIV4,
|
||||
CLK_ROOT_PRE_DIV5,
|
||||
CLK_ROOT_PRE_DIV6,
|
||||
CLK_ROOT_PRE_DIV7,
|
||||
CLK_ROOT_PRE_DIV8,
|
||||
};
|
||||
|
||||
enum root_post_div {
|
||||
CLK_ROOT_POST_DIV1 = 0,
|
||||
CLK_ROOT_POST_DIV2,
|
||||
CLK_ROOT_POST_DIV3,
|
||||
CLK_ROOT_POST_DIV4,
|
||||
CLK_ROOT_POST_DIV5,
|
||||
CLK_ROOT_POST_DIV6,
|
||||
CLK_ROOT_POST_DIV7,
|
||||
CLK_ROOT_POST_DIV8,
|
||||
CLK_ROOT_POST_DIV9,
|
||||
CLK_ROOT_POST_DIV10,
|
||||
CLK_ROOT_POST_DIV11,
|
||||
CLK_ROOT_POST_DIV12,
|
||||
CLK_ROOT_POST_DIV13,
|
||||
CLK_ROOT_POST_DIV14,
|
||||
CLK_ROOT_POST_DIV15,
|
||||
CLK_ROOT_POST_DIV16,
|
||||
CLK_ROOT_POST_DIV17,
|
||||
CLK_ROOT_POST_DIV18,
|
||||
CLK_ROOT_POST_DIV19,
|
||||
CLK_ROOT_POST_DIV20,
|
||||
CLK_ROOT_POST_DIV21,
|
||||
CLK_ROOT_POST_DIV22,
|
||||
CLK_ROOT_POST_DIV23,
|
||||
CLK_ROOT_POST_DIV24,
|
||||
CLK_ROOT_POST_DIV25,
|
||||
CLK_ROOT_POST_DIV26,
|
||||
CLK_ROOT_POST_DIV27,
|
||||
CLK_ROOT_POST_DIV28,
|
||||
CLK_ROOT_POST_DIV29,
|
||||
CLK_ROOT_POST_DIV30,
|
||||
CLK_ROOT_POST_DIV31,
|
||||
CLK_ROOT_POST_DIV32,
|
||||
CLK_ROOT_POST_DIV33,
|
||||
CLK_ROOT_POST_DIV34,
|
||||
CLK_ROOT_POST_DIV35,
|
||||
CLK_ROOT_POST_DIV36,
|
||||
CLK_ROOT_POST_DIV37,
|
||||
CLK_ROOT_POST_DIV38,
|
||||
CLK_ROOT_POST_DIV39,
|
||||
CLK_ROOT_POST_DIV40,
|
||||
CLK_ROOT_POST_DIV41,
|
||||
CLK_ROOT_POST_DIV42,
|
||||
CLK_ROOT_POST_DIV43,
|
||||
CLK_ROOT_POST_DIV44,
|
||||
CLK_ROOT_POST_DIV45,
|
||||
CLK_ROOT_POST_DIV46,
|
||||
CLK_ROOT_POST_DIV47,
|
||||
CLK_ROOT_POST_DIV48,
|
||||
CLK_ROOT_POST_DIV49,
|
||||
CLK_ROOT_POST_DIV50,
|
||||
CLK_ROOT_POST_DIV51,
|
||||
CLK_ROOT_POST_DIV52,
|
||||
CLK_ROOT_POST_DIV53,
|
||||
CLK_ROOT_POST_DIV54,
|
||||
CLK_ROOT_POST_DIV55,
|
||||
CLK_ROOT_POST_DIV56,
|
||||
CLK_ROOT_POST_DIV57,
|
||||
CLK_ROOT_POST_DIV58,
|
||||
CLK_ROOT_POST_DIV59,
|
||||
CLK_ROOT_POST_DIV60,
|
||||
CLK_ROOT_POST_DIV61,
|
||||
CLK_ROOT_POST_DIV62,
|
||||
CLK_ROOT_POST_DIV63,
|
||||
CLK_ROOT_POST_DIV64,
|
||||
};
|
||||
|
||||
struct clk_root_map {
|
||||
enum clk_root_index entry;
|
||||
enum clk_slice_type slice_type;
|
||||
u32 slice_index;
|
||||
u8 src_mux[8];
|
||||
};
|
||||
|
||||
struct ccm_ccgr {
|
||||
u32 ccgr;
|
||||
u32 ccgr_set;
|
||||
u32 ccgr_clr;
|
||||
u32 ccgr_tog;
|
||||
};
|
||||
|
||||
struct ccm_root {
|
||||
u32 target_root;
|
||||
u32 target_root_set;
|
||||
u32 target_root_clr;
|
||||
u32 target_root_tog;
|
||||
u32 misc;
|
||||
u32 misc_set;
|
||||
u32 misc_clr;
|
||||
u32 misc_tog;
|
||||
u32 nm_post;
|
||||
u32 nm_post_root_set;
|
||||
u32 nm_post_root_clr;
|
||||
u32 nm_post_root_tog;
|
||||
u32 nm_pre;
|
||||
u32 nm_pre_root_set;
|
||||
u32 nm_pre_root_clr;
|
||||
u32 nm_pre_root_tog;
|
||||
u32 db_post;
|
||||
u32 db_post_root_set;
|
||||
u32 db_post_root_clr;
|
||||
u32 db_post_root_tog;
|
||||
u32 db_pre;
|
||||
u32 db_pre_root_set;
|
||||
u32 db_pre_root_clr;
|
||||
u32 db_pre_root_tog;
|
||||
u32 reserved[4];
|
||||
u32 access_ctrl;
|
||||
u32 access_ctrl_root_set;
|
||||
u32 access_ctrl_root_clr;
|
||||
u32 access_ctrl_root_tog;
|
||||
};
|
||||
|
||||
struct ccm_reg {
|
||||
u32 reserved_0[4096];
|
||||
struct ccm_ccgr ccgr_array[192];
|
||||
u32 reserved_1[3328];
|
||||
struct ccm_root core_root[5];
|
||||
u32 reserved_2[352];
|
||||
struct ccm_root bus_root[12];
|
||||
u32 reserved_3[128];
|
||||
struct ccm_root ahb_ipg_root[4];
|
||||
u32 reserved_4[384];
|
||||
struct ccm_root dram_sel;
|
||||
struct ccm_root core_sel;
|
||||
u32 reserved_5[448];
|
||||
struct ccm_root ip_root[78];
|
||||
};
|
||||
|
||||
enum enet_freq {
|
||||
ENET_25MHZ = 0,
|
||||
ENET_50MHZ,
|
||||
ENET_125MHZ,
|
||||
};
|
||||
|
||||
#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
|
||||
{ \
|
||||
.clk = (_rate), \
|
||||
.alt_root_sel = (_m), \
|
||||
.alt_pre_div = (_p), \
|
||||
.apb_root_sel = (_s), \
|
||||
.apb_pre_div = (_k), \
|
||||
}
|
||||
|
||||
struct dram_bypass_clk_setting {
|
||||
ulong clk;
|
||||
int alt_root_sel;
|
||||
enum root_pre_div alt_pre_div;
|
||||
int apb_root_sel;
|
||||
enum root_pre_div apb_pre_div;
|
||||
};
|
||||
|
||||
#define CCGR_CLK_ON_MASK 0x03
|
||||
#define CLK_SRC_ON_MASK 0x03
|
||||
|
||||
#define CLK_ROOT_ON BIT(28)
|
||||
#define CLK_ROOT_OFF (0 << 28)
|
||||
#define CLK_ROOT_ENABLE_MASK BIT(28)
|
||||
#define CLK_ROOT_ENABLE_SHIFT 28
|
||||
#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
|
||||
|
||||
/* For SEL, only use 1 bit */
|
||||
#define CLK_ROOT_SRC_MUX_MASK 0x07000000
|
||||
#define CLK_ROOT_SRC_MUX_SHIFT 24
|
||||
#define CLK_ROOT_SRC_0 0x00000000
|
||||
#define CLK_ROOT_SRC_1 0x01000000
|
||||
#define CLK_ROOT_SRC_2 0x02000000
|
||||
#define CLK_ROOT_SRC_3 0x03000000
|
||||
#define CLK_ROOT_SRC_4 0x04000000
|
||||
#define CLK_ROOT_SRC_5 0x05000000
|
||||
#define CLK_ROOT_SRC_6 0x06000000
|
||||
#define CLK_ROOT_SRC_7 0x07000000
|
||||
|
||||
#define CLK_ROOT_PRE_DIV_MASK (0x00070000)
|
||||
#define CLK_ROOT_PRE_DIV_SHIFT 16
|
||||
#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
|
||||
|
||||
#define CLK_ROOT_AUDO_SLOW_EN 0x1000
|
||||
|
||||
#define CLK_ROOT_AUDO_DIV_MASK 0x700
|
||||
#define CLK_ROOT_AUDO_DIV_SHIFT 0x8
|
||||
#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
|
||||
|
||||
/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
|
||||
#define CLK_ROOT_POST_DIV_MASK 0x3f
|
||||
#define CLK_ROOT_CORE_POST_DIV_MASK 0x7
|
||||
#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
|
||||
#define CLK_ROOT_POST_DIV_SHIFT 0
|
||||
#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
|
||||
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
|
||||
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
|
||||
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
|
||||
#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
|
||||
#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
|
||||
#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
|
||||
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
|
||||
|
||||
void dram_pll_init(ulong pll_val);
|
||||
void dram_enable_bypass(ulong clk_val);
|
||||
void dram_disable_bypass(void);
|
||||
u32 imx_get_fecclk(void);
|
||||
u32 imx_get_uartclk(void);
|
||||
int clock_init(void);
|
||||
void init_clk_usdhc(u32 index);
|
||||
void init_uart_clk(u32 index);
|
||||
void init_wdog_clk(void);
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
int clock_enable(enum clk_ccgr_index index, bool enable);
|
||||
int clock_root_enabled(enum clk_root_index clock_id);
|
||||
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
|
||||
enum root_post_div post_div, enum clk_root_src clock_src);
|
||||
int clock_set_target_val(enum clk_root_index clock_id, u32 val);
|
||||
int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
|
||||
int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
|
||||
int clock_get_postdiv(enum clk_root_index clock_id,
|
||||
enum root_post_div *post_div);
|
||||
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
|
||||
void mxs_set_lcdclk(u32 base_addr, u32 freq);
|
||||
int set_clk_qspi(void);
|
||||
void enable_ocotp_clk(unsigned char enable);
|
||||
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
|
||||
int set_clk_enet(enum enet_freq type);
|
||||
@@ -0,0 +1,465 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
|
||||
#define _ASM_ARCH_IMX8MM_CLOCK_H
|
||||
|
||||
#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
.kdiv = (_k), \
|
||||
}
|
||||
|
||||
#define LOCK_STATUS BIT(31)
|
||||
#define LOCK_SEL_MASK BIT(29)
|
||||
#define CLKE_MASK BIT(11)
|
||||
#define RST_MASK BIT(9)
|
||||
#define BYPASS_MASK BIT(4)
|
||||
#define MDIV_SHIFT 12
|
||||
#define MDIV_MASK GENMASK(21, 12)
|
||||
#define PDIV_SHIFT 4
|
||||
#define PDIV_MASK GENMASK(9, 4)
|
||||
#define SDIV_SHIFT 0
|
||||
#define SDIV_MASK GENMASK(2, 0)
|
||||
#define KDIV_SHIFT 0
|
||||
#define KDIV_MASK GENMASK(15, 0)
|
||||
|
||||
struct imx_int_pll_rate_table {
|
||||
u32 rate;
|
||||
int mdiv;
|
||||
int pdiv;
|
||||
int sdiv;
|
||||
int kdiv;
|
||||
};
|
||||
|
||||
enum pll_clocks {
|
||||
ANATOP_ARM_PLL,
|
||||
ANATOP_VPU_PLL,
|
||||
ANATOP_GPU_PLL,
|
||||
ANATOP_SYSTEM_PLL1,
|
||||
ANATOP_SYSTEM_PLL2,
|
||||
ANATOP_SYSTEM_PLL3,
|
||||
ANATOP_AUDIO_PLL1,
|
||||
ANATOP_AUDIO_PLL2,
|
||||
ANATOP_VIDEO_PLL,
|
||||
ANATOP_DRAM_PLL,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_IMX8MN
|
||||
enum clk_root_index {
|
||||
ARM_A53_CLK_ROOT = 0,
|
||||
ARM_M7_CLK_ROOT = 1,
|
||||
GPU_CORE_CLK_ROOT = 3,
|
||||
GPU_SHADER_CLK_ROOT = 4,
|
||||
MAIN_AXI_CLK_ROOT = 16,
|
||||
ENET_AXI_CLK_ROOT = 17,
|
||||
NAND_USDHC_BUS_CLK_ROOT = 18,
|
||||
DISPLAY_AXI_CLK_ROOT = 20,
|
||||
DISPLAY_APB_CLK_ROOT = 21,
|
||||
USB_BUS_CLK_ROOT = 23,
|
||||
GPU_AXI_CLK_ROOT = 24,
|
||||
GPU_AHB_CLK_ROOT = 25,
|
||||
NOC_CLK_ROOT = 26,
|
||||
AHB_CLK_ROOT = 32,
|
||||
IPG_CLK_ROOT = 33,
|
||||
AUDIO_AHB_CLK_ROOT = 34,
|
||||
DRAM_SEL_CFG = 48,
|
||||
CORE_SEL_CFG = 49,
|
||||
DRAM_ALT_CLK_ROOT = 64,
|
||||
DRAM_APB_CLK_ROOT = 65,
|
||||
DISPLAY_PIXEL_CLK_ROOT = 74,
|
||||
SAI2_CLK_ROOT = 76,
|
||||
SAI3_CLK_ROOT = 77,
|
||||
SAI5_CLK_ROOT = 79,
|
||||
SAI6_CLK_ROOT = 80,
|
||||
SPDIF1_CLK_ROOT = 81,
|
||||
ENET_REF_CLK_ROOT = 83,
|
||||
ENET_TIMER_CLK_ROOT = 84,
|
||||
ENET_PHY_REF_CLK_ROOT = 85,
|
||||
NAND_CLK_ROOT = 86,
|
||||
QSPI_CLK_ROOT = 87,
|
||||
USDHC1_CLK_ROOT = 88,
|
||||
USDHC2_CLK_ROOT = 89,
|
||||
I2C1_CLK_ROOT = 90,
|
||||
I2C2_CLK_ROOT = 91,
|
||||
I2C3_CLK_ROOT = 92,
|
||||
I2C4_CLK_ROOT = 93,
|
||||
UART1_CLK_ROOT = 94,
|
||||
UART2_CLK_ROOT = 95,
|
||||
UART3_CLK_ROOT = 96,
|
||||
UART4_CLK_ROOT = 97,
|
||||
USB_CORE_REF_CLK_ROOT = 98,
|
||||
USB_PHY_REF_CLK_ROOT = 99,
|
||||
GIC_CLK_ROOT = 100,
|
||||
ECSPI1_CLK_ROOT = 101,
|
||||
ECSPI2_CLK_ROOT = 102,
|
||||
PWM1_CLK_ROOT = 103,
|
||||
PWM2_CLK_ROOT = 104,
|
||||
PWM3_CLK_ROOT = 105,
|
||||
PWM4_CLK_ROOT = 106,
|
||||
GPT1_CLK_ROOT = 107,
|
||||
GPT2_CLK_ROOT = 108,
|
||||
GPT3_CLK_ROOT = 109,
|
||||
GPT4_CLK_ROOT = 110,
|
||||
GPT5_CLK_ROOT = 111,
|
||||
GPT6_CLK_ROOT = 112,
|
||||
TRACE_CLK_ROOT = 113,
|
||||
WDOG_CLK_ROOT = 114,
|
||||
WRCLK_CLK_ROOT = 115,
|
||||
IPP_DO_CLKO1 = 116,
|
||||
IPP_DO_CLKO2 = 117,
|
||||
MIPI_DSI_CORE_CLK_ROOT = 118,
|
||||
DISPLAY_DSI_PHY_REF_CLK_ROOT = 119,
|
||||
MIPI_DSI_DBI_CLK_ROOT = 120,
|
||||
USDHC3_CLK_ROOT = 121,
|
||||
DISPLAY_CAMERA_PIXEL_CLK_ROOT = 122,
|
||||
MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
|
||||
MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
|
||||
MIPI_CSI2_ESC_CLK_ROOT = 127,
|
||||
ECSPI3_CLK_ROOT = 131,
|
||||
PDM_CLK_ROOT = 132,
|
||||
SAI7_CLK_ROOT = 134,
|
||||
CLK_ROOT_MAX,
|
||||
};
|
||||
#else
|
||||
enum clk_root_index {
|
||||
ARM_A53_CLK_ROOT = 0,
|
||||
ARM_M4_CLK_ROOT = 1,
|
||||
VPU_A53_CLK_ROOT = 2,
|
||||
GPU3D_CLK_ROOT = 3,
|
||||
GPU2D_CLK_ROOT = 4,
|
||||
MAIN_AXI_CLK_ROOT = 16,
|
||||
ENET_AXI_CLK_ROOT = 17,
|
||||
NAND_USDHC_BUS_CLK_ROOT = 18,
|
||||
VPU_BUS_CLK_ROOT = 19,
|
||||
DISPLAY_AXI_CLK_ROOT = 20,
|
||||
DISPLAY_APB_CLK_ROOT = 21,
|
||||
DISPLAY_RTRM_CLK_ROOT = 22,
|
||||
USB_BUS_CLK_ROOT = 23,
|
||||
GPU_AXI_CLK_ROOT = 24,
|
||||
GPU_AHB_CLK_ROOT = 25,
|
||||
NOC_CLK_ROOT = 26,
|
||||
NOC_APB_CLK_ROOT = 27,
|
||||
AHB_CLK_ROOT = 32,
|
||||
IPG_CLK_ROOT = 33,
|
||||
AUDIO_AHB_CLK_ROOT = 34,
|
||||
MIPI_DSI_ESC_RX_CLK_ROOT = 36,
|
||||
DRAM_SEL_CFG = 48,
|
||||
CORE_SEL_CFG = 49,
|
||||
DRAM_ALT_CLK_ROOT = 64,
|
||||
DRAM_APB_CLK_ROOT = 65,
|
||||
VPU_G1_CLK_ROOT = 66,
|
||||
VPU_G2_CLK_ROOT = 67,
|
||||
DISPLAY_DTRC_CLK_ROOT = 68,
|
||||
DISPLAY_DC8000_CLK_ROOT = 69,
|
||||
PCIE_CTRL_CLK_ROOT = 70,
|
||||
PCIE_PHY_CLK_ROOT = 71,
|
||||
PCIE_AUX_CLK_ROOT = 72,
|
||||
DC_PIXEL_CLK_ROOT = 73,
|
||||
LCDIF_PIXEL_CLK_ROOT = 74,
|
||||
SAI1_CLK_ROOT = 75,
|
||||
SAI2_CLK_ROOT = 76,
|
||||
SAI3_CLK_ROOT = 77,
|
||||
SAI4_CLK_ROOT = 78,
|
||||
SAI5_CLK_ROOT = 79,
|
||||
SAI6_CLK_ROOT = 80,
|
||||
SPDIF1_CLK_ROOT = 81,
|
||||
SPDIF2_CLK_ROOT = 82,
|
||||
ENET_REF_CLK_ROOT = 83,
|
||||
ENET_TIMER_CLK_ROOT = 84,
|
||||
ENET_PHY_REF_CLK_ROOT = 85,
|
||||
NAND_CLK_ROOT = 86,
|
||||
QSPI_CLK_ROOT = 87,
|
||||
USDHC1_CLK_ROOT = 88,
|
||||
USDHC2_CLK_ROOT = 89,
|
||||
I2C1_CLK_ROOT = 90,
|
||||
I2C2_CLK_ROOT = 91,
|
||||
I2C3_CLK_ROOT = 92,
|
||||
I2C4_CLK_ROOT = 93,
|
||||
UART1_CLK_ROOT = 94,
|
||||
UART2_CLK_ROOT = 95,
|
||||
UART3_CLK_ROOT = 96,
|
||||
UART4_CLK_ROOT = 97,
|
||||
USB_CORE_REF_CLK_ROOT = 98,
|
||||
USB_PHY_REF_CLK_ROOT = 99,
|
||||
GIC_CLK_ROOT = 100,
|
||||
ECSPI1_CLK_ROOT = 101,
|
||||
ECSPI2_CLK_ROOT = 102,
|
||||
PWM1_CLK_ROOT = 103,
|
||||
PWM2_CLK_ROOT = 104,
|
||||
PWM3_CLK_ROOT = 105,
|
||||
PWM4_CLK_ROOT = 106,
|
||||
GPT1_CLK_ROOT = 107,
|
||||
GPT2_CLK_ROOT = 108,
|
||||
GPT3_CLK_ROOT = 109,
|
||||
GPT4_CLK_ROOT = 110,
|
||||
GPT5_CLK_ROOT = 111,
|
||||
GPT6_CLK_ROOT = 112,
|
||||
TRACE_CLK_ROOT = 113,
|
||||
WDOG_CLK_ROOT = 114,
|
||||
WRCLK_CLK_ROOT = 115,
|
||||
IPP_DO_CLKO1 = 116,
|
||||
IPP_DO_CLKO2 = 117,
|
||||
MIPI_DSI_CORE_CLK_ROOT = 118,
|
||||
MIPI_DSI_PHY_REF_CLK_ROOT = 119,
|
||||
MIPI_DSI_DBI_CLK_ROOT = 120,
|
||||
USDHC3_CLK_ROOT = 121,
|
||||
MIPI_CSI1_CORE_CLK_ROOT = 122,
|
||||
MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
|
||||
MIPI_CSI1_ESC_CLK_ROOT = 124,
|
||||
MIPI_CSI2_CORE_CLK_ROOT = 125,
|
||||
MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
|
||||
MIPI_CSI2_ESC_CLK_ROOT = 127,
|
||||
PCIE2_CTRL_CLK_ROOT = 128,
|
||||
PCIE2_PHY_CLK_ROOT = 129,
|
||||
PCIE2_AUX_CLK_ROOT = 130,
|
||||
ECSPI3_CLK_ROOT = 131,
|
||||
PDM_CLK_ROOT = 132,
|
||||
VPU_H1_CLK_ROOT = 133,
|
||||
CLK_ROOT_MAX,
|
||||
};
|
||||
#endif
|
||||
|
||||
enum clk_root_src {
|
||||
OSC_24M_CLK,
|
||||
ARM_PLL_CLK,
|
||||
DRAM_PLL1_CLK,
|
||||
VIDEO_PLL2_CLK,
|
||||
VPU_PLL_CLK,
|
||||
GPU_PLL_CLK,
|
||||
SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK,
|
||||
SYSTEM_PLL1_200M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_133M_CLK,
|
||||
SYSTEM_PLL1_100M_CLK,
|
||||
SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK,
|
||||
SYSTEM_PLL2_333M_CLK,
|
||||
SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_166M_CLK,
|
||||
SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK,
|
||||
AUDIO_PLL1_CLK,
|
||||
AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK,
|
||||
OSC_32K_CLK,
|
||||
EXT_CLK_1,
|
||||
EXT_CLK_2,
|
||||
EXT_CLK_3,
|
||||
EXT_CLK_4,
|
||||
OSC_HDMI_CLK
|
||||
};
|
||||
|
||||
enum clk_ccgr_index {
|
||||
CCGR_DVFS = 0,
|
||||
CCGR_ANAMIX = 1,
|
||||
CCGR_CPU = 2,
|
||||
CCGR_CSU = 3,
|
||||
CCGR_DEBUG = 4,
|
||||
CCGR_DDR1 = 5,
|
||||
CCGR_ECSPI1 = 7,
|
||||
CCGR_ECSPI2 = 8,
|
||||
CCGR_ECSPI3 = 9,
|
||||
CCGR_ENET1 = 10,
|
||||
CCGR_GPIO1 = 11,
|
||||
CCGR_GPIO2 = 12,
|
||||
CCGR_GPIO3 = 13,
|
||||
CCGR_GPIO4 = 14,
|
||||
CCGR_GPIO5 = 15,
|
||||
CCGR_GPT1 = 16,
|
||||
CCGR_GPT2 = 17,
|
||||
CCGR_GPT3 = 18,
|
||||
CCGR_GPT4 = 19,
|
||||
CCGR_GPT5 = 20,
|
||||
CCGR_GPT6 = 21,
|
||||
CCGR_HS = 22,
|
||||
CCGR_I2C1 = 23,
|
||||
CCGR_I2C2 = 24,
|
||||
CCGR_I2C3 = 25,
|
||||
CCGR_I2C4 = 26,
|
||||
CCGR_IOMUX = 27,
|
||||
CCGR_IOMUX1 = 28,
|
||||
CCGR_IOMUX2 = 29,
|
||||
CCGR_IOMUX3 = 30,
|
||||
CCGR_IOMUX4 = 31,
|
||||
CCGR_SNVSMIX_IPG_CLK = 32,
|
||||
CCGR_MU = 33,
|
||||
CCGR_OCOTP = 34,
|
||||
CCGR_OCRAM = 35,
|
||||
CCGR_OCRAM_S = 36,
|
||||
CCGR_PCIE = 37,
|
||||
CCGR_PERFMON1 = 38,
|
||||
CCGR_PERFMON2 = 39,
|
||||
CCGR_PWM1 = 40,
|
||||
CCGR_PWM2 = 41,
|
||||
CCGR_PWM3 = 42,
|
||||
CCGR_PWM4 = 43,
|
||||
CCGR_QOS = 44,
|
||||
CCGR_QOS_DISPMIX = 45,
|
||||
CCGR_QOS_ETHENET = 46,
|
||||
CCGR_QSPI = 47,
|
||||
CCGR_RAWNAND = 48,
|
||||
CCGR_RDC = 49,
|
||||
CCGR_ROM = 50,
|
||||
CCGR_SAI1 = 51,
|
||||
CCGR_SAI2 = 52,
|
||||
CCGR_SAI3 = 53,
|
||||
CCGR_SAI4 = 54,
|
||||
CCGR_SAI5 = 55,
|
||||
CCGR_SAI6 = 56,
|
||||
CCGR_SCTR = 57,
|
||||
CCGR_SDMA1 = 58,
|
||||
CCGR_SDMA2 = 59,
|
||||
CCGR_SEC_DEBUG = 60,
|
||||
CCGR_SEMA1 = 61,
|
||||
CCGR_SEMA2 = 62,
|
||||
CCGR_SIM_DISPLAY = 63,
|
||||
CCGR_SIM_ENET = 64,
|
||||
CCGR_SIM_M = 65,
|
||||
CCGR_SIM_MAIN = 66,
|
||||
CCGR_SIM_S = 67,
|
||||
CCGR_SIM_WAKEUP = 68,
|
||||
CCGR_SIM_HSIO = 69,
|
||||
CCGR_SIM_VPU = 70,
|
||||
CCGR_SNVS = 71,
|
||||
CCGR_TRACE = 72,
|
||||
CCGR_UART1 = 73,
|
||||
CCGR_UART2 = 74,
|
||||
CCGR_UART3 = 75,
|
||||
CCGR_UART4 = 76,
|
||||
CCGR_USB_MSCALE_PL301 = 77,
|
||||
CCGR_GPU3D = 79,
|
||||
CCGR_USDHC1 = 81,
|
||||
CCGR_USDHC2 = 82,
|
||||
CCGR_WDOG1 = 83,
|
||||
CCGR_WDOG2 = 84,
|
||||
CCGR_WDOG3 = 85,
|
||||
CCGR_VPUG1 = 86,
|
||||
CCGR_GPU_BUS = 87,
|
||||
CCGR_VPUH1 = 89,
|
||||
CCGR_VPUG2 = 90,
|
||||
CCGR_PDM = 91,
|
||||
CCGR_GIC = 92,
|
||||
CCGR_DISPMIX = 93,
|
||||
CCGR_USDHC3 = 94,
|
||||
CCGR_SDMA3 = 95,
|
||||
CCGR_XTAL = 96,
|
||||
CCGR_PLL = 97,
|
||||
CCGR_TEMP_SENSOR = 98,
|
||||
CCGR_VPUMIX_BUS = 99,
|
||||
CCGR_GPU2D = 102,
|
||||
CCGR_MAX
|
||||
};
|
||||
|
||||
enum clk_src_index {
|
||||
CLK_SRC_CKIL_SYNC_REQ = 0,
|
||||
CLK_SRC_ARM_PLL_EN = 1,
|
||||
CLK_SRC_GPU_PLL_EN = 2,
|
||||
CLK_SRC_VPU_PLL_EN = 3,
|
||||
CLK_SRC_DRAM_PLL_EN = 4,
|
||||
CLK_SRC_SYSTEM_PLL1_EN = 5,
|
||||
CLK_SRC_SYSTEM_PLL2_EN = 6,
|
||||
CLK_SRC_SYSTEM_PLL3_EN = 7,
|
||||
CLK_SRC_AUDIO_PLL1_EN = 8,
|
||||
CLK_SRC_AUDIO_PLL2_EN = 9,
|
||||
CLK_SRC_VIDEO_PLL1_EN = 10,
|
||||
CLK_SRC_RESERVED = 11,
|
||||
CLK_SRC_ARM_PLL = 12,
|
||||
CLK_SRC_GPU_PLL = 13,
|
||||
CLK_SRC_VPU_PLL = 14,
|
||||
CLK_SRC_DRAM_PLL = 15,
|
||||
CLK_SRC_SYSTEM_PLL1_800M = 16,
|
||||
CLK_SRC_SYSTEM_PLL1_400M = 17,
|
||||
CLK_SRC_SYSTEM_PLL1_266M = 18,
|
||||
CLK_SRC_SYSTEM_PLL1_200M = 19,
|
||||
CLK_SRC_SYSTEM_PLL1_160M = 20,
|
||||
CLK_SRC_SYSTEM_PLL1_133M = 21,
|
||||
CLK_SRC_SYSTEM_PLL1_100M = 22,
|
||||
CLK_SRC_SYSTEM_PLL1_80M = 23,
|
||||
CLK_SRC_SYSTEM_PLL1_40M = 24,
|
||||
CLK_SRC_SYSTEM_PLL2_1000M = 25,
|
||||
CLK_SRC_SYSTEM_PLL2_500M = 26,
|
||||
CLK_SRC_SYSTEM_PLL2_333M = 27,
|
||||
CLK_SRC_SYSTEM_PLL2_250M = 28,
|
||||
CLK_SRC_SYSTEM_PLL2_200M = 29,
|
||||
CLK_SRC_SYSTEM_PLL2_166M = 30,
|
||||
CLK_SRC_SYSTEM_PLL2_125M = 31,
|
||||
CLK_SRC_SYSTEM_PLL2_100M = 32,
|
||||
CLK_SRC_SYSTEM_PLL2_50M = 33,
|
||||
CLK_SRC_SYSTEM_PLL3 = 34,
|
||||
CLK_SRC_AUDIO_PLL1 = 35,
|
||||
CLK_SRC_AUDIO_PLL2 = 36,
|
||||
CLK_SRC_VIDEO_PLL1 = 37,
|
||||
};
|
||||
|
||||
#define INTPLL_LOCK_MASK BIT(31)
|
||||
#define INTPLL_LOCK_SEL_MASK BIT(29)
|
||||
#define INTPLL_EXT_BYPASS_MASK BIT(28)
|
||||
#define INTPLL_DIV20_CLKE_MASK BIT(27)
|
||||
#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
|
||||
#define INTPLL_DIV10_CLKE_MASK BIT(25)
|
||||
#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
|
||||
#define INTPLL_DIV8_CLKE_MASK BIT(23)
|
||||
#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
|
||||
#define INTPLL_DIV6_CLKE_MASK BIT(21)
|
||||
#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
|
||||
#define INTPLL_DIV5_CLKE_MASK BIT(19)
|
||||
#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
|
||||
#define INTPLL_DIV4_CLKE_MASK BIT(17)
|
||||
#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
|
||||
#define INTPLL_DIV3_CLKE_MASK BIT(15)
|
||||
#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
|
||||
#define INTPLL_DIV2_CLKE_MASK BIT(13)
|
||||
#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
|
||||
#define INTPLL_CLKE_MASK BIT(11)
|
||||
#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
|
||||
#define INTPLL_RST_MASK BIT(9)
|
||||
#define INTPLL_RST_OVERRIDE_MASK BIT(8)
|
||||
#define INTPLL_BYPASS_MASK BIT(4)
|
||||
#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
|
||||
#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
|
||||
|
||||
#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
|
||||
#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
|
||||
#define INTPLL_MAIN_DIV_SHIFT 12
|
||||
#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
|
||||
#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
|
||||
#define INTPLL_PRE_DIV_SHIFT 4
|
||||
#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
|
||||
#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
|
||||
#define INTPLL_POST_DIV_SHIFT 0
|
||||
|
||||
#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
|
||||
#define INTPLL_LOCK_CON_DLY_SHIFT 4
|
||||
#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
|
||||
#define INTPLL_LOCK_CON_OUT_SHIFT 2
|
||||
#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
|
||||
#define INTPLL_LOCK_CON_IN_SHIFT 0
|
||||
|
||||
#define INTPLL_LRD_EN_MASK BIT(21)
|
||||
#define INTPLL_FOUT_MASK BIT(20)
|
||||
#define INTPLL_AFC_SEL_MASK BIT(19)
|
||||
#define INTPLL_PBIAS_CTRL_MASK BIT(18)
|
||||
#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
|
||||
#define INTPLL_AFCINIT_SEL_MASK BIT(16)
|
||||
#define INTPLL_FSEL_MASK BIT(14)
|
||||
#define INTPLL_FEED_EN_MASK BIT(13)
|
||||
#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
|
||||
#define INTPLL_AFC_EN_MASK BIT(2)
|
||||
#define INTPLL_ICP_MASK GENMASK(1, 0)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,426 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_IMX8M_CLOCK_H
|
||||
#define _ASM_ARCH_IMX8M_CLOCK_H
|
||||
|
||||
enum pll_clocks {
|
||||
ANATOP_ARM_PLL,
|
||||
ANATOP_GPU_PLL,
|
||||
ANATOP_SYSTEM_PLL1,
|
||||
ANATOP_SYSTEM_PLL2,
|
||||
ANATOP_SYSTEM_PLL3,
|
||||
ANATOP_AUDIO_PLL1,
|
||||
ANATOP_AUDIO_PLL2,
|
||||
ANATOP_VIDEO_PLL1,
|
||||
ANATOP_VIDEO_PLL2,
|
||||
ANATOP_DRAM_PLL,
|
||||
};
|
||||
|
||||
enum clk_root_index {
|
||||
ARM_A53_CLK_ROOT = 0,
|
||||
ARM_M4_CLK_ROOT = 1,
|
||||
VPU_A53_CLK_ROOT = 2,
|
||||
GPU_CORE_CLK_ROOT = 3,
|
||||
GPU_SHADER_CLK_ROOT = 4,
|
||||
MAIN_AXI_CLK_ROOT = 16,
|
||||
ENET_AXI_CLK_ROOT = 17,
|
||||
NAND_USDHC_BUS_CLK_ROOT = 18,
|
||||
VPU_BUS_CLK_ROOT = 19,
|
||||
DISPLAY_AXI_CLK_ROOT = 20,
|
||||
DISPLAY_APB_CLK_ROOT = 21,
|
||||
DISPLAY_RTRM_CLK_ROOT = 22,
|
||||
USB_BUS_CLK_ROOT = 23,
|
||||
GPU_AXI_CLK_ROOT = 24,
|
||||
GPU_AHB_CLK_ROOT = 25,
|
||||
NOC_CLK_ROOT = 26,
|
||||
NOC_APB_CLK_ROOT = 27,
|
||||
AHB_CLK_ROOT = 32,
|
||||
IPG_CLK_ROOT = 33,
|
||||
AUDIO_AHB_CLK_ROOT = 34,
|
||||
MIPI_DSI_ESC_RX_CLK_ROOT = 36,
|
||||
DRAM_SEL_CFG = 48,
|
||||
CORE_SEL_CFG = 49,
|
||||
DRAM_ALT_CLK_ROOT = 64,
|
||||
DRAM_APB_CLK_ROOT = 65,
|
||||
VPU_G1_CLK_ROOT = 66,
|
||||
VPU_G2_CLK_ROOT = 67,
|
||||
DISPLAY_DTRC_CLK_ROOT = 68,
|
||||
DISPLAY_DC8000_CLK_ROOT = 69,
|
||||
PCIE1_CTRL_CLK_ROOT = 70,
|
||||
PCIE1_PHY_CLK_ROOT = 71,
|
||||
PCIE1_AUX_CLK_ROOT = 72,
|
||||
DC_PIXEL_CLK_ROOT = 73,
|
||||
LCDIF_PIXEL_CLK_ROOT = 74,
|
||||
SAI1_CLK_ROOT = 75,
|
||||
SAI2_CLK_ROOT = 76,
|
||||
SAI3_CLK_ROOT = 77,
|
||||
SAI4_CLK_ROOT = 78,
|
||||
SAI5_CLK_ROOT = 79,
|
||||
SAI6_CLK_ROOT = 80,
|
||||
SPDIF1_CLK_ROOT = 81,
|
||||
SPDIF2_CLK_ROOT = 82,
|
||||
ENET_REF_CLK_ROOT = 83,
|
||||
ENET_TIMER_CLK_ROOT = 84,
|
||||
ENET_PHY_REF_CLK_ROOT = 85,
|
||||
NAND_CLK_ROOT = 86,
|
||||
QSPI_CLK_ROOT = 87,
|
||||
USDHC1_CLK_ROOT = 88,
|
||||
USDHC2_CLK_ROOT = 89,
|
||||
I2C1_CLK_ROOT = 90,
|
||||
I2C2_CLK_ROOT = 91,
|
||||
I2C3_CLK_ROOT = 92,
|
||||
I2C4_CLK_ROOT = 93,
|
||||
UART1_CLK_ROOT = 94,
|
||||
UART2_CLK_ROOT = 95,
|
||||
UART3_CLK_ROOT = 96,
|
||||
UART4_CLK_ROOT = 97,
|
||||
USB_CORE_REF_CLK_ROOT = 98,
|
||||
USB_PHY_REF_CLK_ROOT = 99,
|
||||
GIC_CLK_ROOT = 100,
|
||||
ECSPI1_CLK_ROOT = 101,
|
||||
ECSPI2_CLK_ROOT = 102,
|
||||
PWM1_CLK_ROOT = 103,
|
||||
PWM2_CLK_ROOT = 104,
|
||||
PWM3_CLK_ROOT = 105,
|
||||
PWM4_CLK_ROOT = 106,
|
||||
GPT1_CLK_ROOT = 107,
|
||||
GPT2_CLK_ROOT = 108,
|
||||
GPT3_CLK_ROOT = 109,
|
||||
GPT4_CLK_ROOT = 110,
|
||||
GPT5_CLK_ROOT = 111,
|
||||
GPT6_CLK_ROOT = 112,
|
||||
TRACE_CLK_ROOT = 113,
|
||||
WDOG_CLK_ROOT = 114,
|
||||
WRCLK_CLK_ROOT = 115,
|
||||
IPP_DO_CLKO1 = 116,
|
||||
IPP_DO_CLKO2 = 117,
|
||||
MIPI_DSI_CORE_CLK_ROOT = 118,
|
||||
MIPI_DSI_PHY_REF_CLK_ROOT = 119,
|
||||
MIPI_DSI_DBI_CLK_ROOT = 120,
|
||||
OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
|
||||
MIPI_CSI1_CORE_CLK_ROOT = 122,
|
||||
MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
|
||||
MIPI_CSI1_ESC_CLK_ROOT = 124,
|
||||
MIPI_CSI2_CORE_CLK_ROOT = 125,
|
||||
MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
|
||||
MIPI_CSI2_ESC_CLK_ROOT = 127,
|
||||
PCIE2_CTRL_CLK_ROOT = 128,
|
||||
PCIE2_PHY_CLK_ROOT = 129,
|
||||
PCIE2_AUX_CLK_ROOT = 130,
|
||||
ECSPI3_CLK_ROOT = 131,
|
||||
OLD_MIPI_DSI_ESC_RX_ROOT = 132,
|
||||
DISPLAY_HDMI_CLK_ROOT = 133,
|
||||
CLK_ROOT_MAX,
|
||||
};
|
||||
|
||||
enum clk_root_src {
|
||||
OSC_25M_CLK,
|
||||
ARM_PLL_CLK,
|
||||
DRAM_PLL1_CLK,
|
||||
VIDEO_PLL2_CLK,
|
||||
VPU_PLL_CLK,
|
||||
GPU_PLL_CLK,
|
||||
SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK,
|
||||
SYSTEM_PLL1_200M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_133M_CLK,
|
||||
SYSTEM_PLL1_100M_CLK,
|
||||
SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK,
|
||||
SYSTEM_PLL2_333M_CLK,
|
||||
SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_166M_CLK,
|
||||
SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK,
|
||||
AUDIO_PLL1_CLK,
|
||||
AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK,
|
||||
OSC_32K_CLK,
|
||||
EXT_CLK_1,
|
||||
EXT_CLK_2,
|
||||
EXT_CLK_3,
|
||||
EXT_CLK_4,
|
||||
OSC_27M_CLK,
|
||||
};
|
||||
|
||||
/* CCGR index */
|
||||
enum clk_ccgr_index {
|
||||
CCGR_DVFS = 0,
|
||||
CCGR_ANAMIX = 1,
|
||||
CCGR_CPU = 2,
|
||||
CCGR_CSU = 4,
|
||||
CCGR_DRAM1 = 5,
|
||||
CCGR_DRAM2_OBSOLETE = 6,
|
||||
CCGR_ECSPI1 = 7,
|
||||
CCGR_ECSPI2 = 8,
|
||||
CCGR_ECSPI3 = 9,
|
||||
CCGR_ENET1 = 10,
|
||||
CCGR_GPIO1 = 11,
|
||||
CCGR_GPIO2 = 12,
|
||||
CCGR_GPIO3 = 13,
|
||||
CCGR_GPIO4 = 14,
|
||||
CCGR_GPIO5 = 15,
|
||||
CCGR_GPT1 = 16,
|
||||
CCGR_GPT2 = 17,
|
||||
CCGR_GPT3 = 18,
|
||||
CCGR_GPT4 = 19,
|
||||
CCGR_GPT5 = 20,
|
||||
CCGR_GPT6 = 21,
|
||||
CCGR_HS = 22,
|
||||
CCGR_I2C1 = 23,
|
||||
CCGR_I2C2 = 24,
|
||||
CCGR_I2C3 = 25,
|
||||
CCGR_I2C4 = 26,
|
||||
CCGR_IOMUX = 27,
|
||||
CCGR_IOMUX1 = 28,
|
||||
CCGR_IOMUX2 = 29,
|
||||
CCGR_IOMUX3 = 30,
|
||||
CCGR_IOMUX4 = 31,
|
||||
CCGR_M4 = 32,
|
||||
CCGR_MU = 33,
|
||||
CCGR_OCOTP = 34,
|
||||
CCGR_OCRAM = 35,
|
||||
CCGR_OCRAM_S = 36,
|
||||
CCGR_PCIE = 37,
|
||||
CCGR_PERFMON1 = 38,
|
||||
CCGR_PERFMON2 = 39,
|
||||
CCGR_PWM1 = 40,
|
||||
CCGR_PWM2 = 41,
|
||||
CCGR_PWM3 = 42,
|
||||
CCGR_PWM4 = 43,
|
||||
CCGR_QOS = 44,
|
||||
CCGR_DISMIX = 45,
|
||||
CCGR_MEGAMIX = 46,
|
||||
CCGR_QSPI = 47,
|
||||
CCGR_RAWNAND = 48,
|
||||
CCGR_RDC = 49,
|
||||
CCGR_ROM = 50,
|
||||
CCGR_SAI1 = 51,
|
||||
CCGR_SAI2 = 52,
|
||||
CCGR_SAI3 = 53,
|
||||
CCGR_SAI4 = 54,
|
||||
CCGR_SAI5 = 55,
|
||||
CCGR_SAI6 = 56,
|
||||
CCGR_SCTR = 57,
|
||||
CCGR_SDMA1 = 58,
|
||||
CCGR_SDMA2 = 59,
|
||||
CCGR_SEC_DEBUG = 60,
|
||||
CCGR_SEMA1 = 61,
|
||||
CCGR_SEMA2 = 62,
|
||||
CCGR_SIM_DISPLAY = 63,
|
||||
CCGR_SIM_ENET = 64,
|
||||
CCGR_SIM_M = 65,
|
||||
CCGR_SIM_MAIN = 66,
|
||||
CCGR_SIM_S = 67,
|
||||
CCGR_SIM_WAKEUP = 68,
|
||||
CCGR_SIM_USB = 69,
|
||||
CCGR_SIM_VPU = 70,
|
||||
CCGR_SNVS = 71,
|
||||
CCGR_TRACE = 72,
|
||||
CCGR_UART1 = 73,
|
||||
CCGR_UART2 = 74,
|
||||
CCGR_UART3 = 75,
|
||||
CCGR_UART4 = 76,
|
||||
CCGR_USB_CTRL1 = 77,
|
||||
CCGR_USB_CTRL2 = 78,
|
||||
CCGR_USB_PHY1 = 79,
|
||||
CCGR_USB_PHY2 = 80,
|
||||
CCGR_USDHC1 = 81,
|
||||
CCGR_USDHC2 = 82,
|
||||
CCGR_WDOG1 = 83,
|
||||
CCGR_WDOG2 = 84,
|
||||
CCGR_WDOG3 = 85,
|
||||
CCGR_VA53 = 86,
|
||||
CCGR_GPU = 87,
|
||||
CCGR_HEVC = 88,
|
||||
CCGR_AVC = 89,
|
||||
CCGR_VP9 = 90,
|
||||
CCGR_HEVC_INTER = 91,
|
||||
CCGR_GIC = 92,
|
||||
CCGR_DISPLAY = 93,
|
||||
CCGR_HDMI = 94,
|
||||
CCGR_HDMI_PHY = 95,
|
||||
CCGR_XTAL = 96,
|
||||
CCGR_PLL = 97,
|
||||
CCGR_TSENSOR = 98,
|
||||
CCGR_VPU_DEC = 99,
|
||||
CCGR_PCIE2 = 100,
|
||||
CCGR_MIPI_CSI1 = 101,
|
||||
CCGR_MIPI_CSI2 = 102,
|
||||
CCGR_MAX,
|
||||
};
|
||||
|
||||
/* src index */
|
||||
enum clk_src_index {
|
||||
CLK_SRC_CKIL_SYNC_REQ = 0,
|
||||
CLK_SRC_ARM_PLL_EN = 1,
|
||||
CLK_SRC_GPU_PLL_EN = 2,
|
||||
CLK_SRC_VPU_PLL_EN = 3,
|
||||
CLK_SRC_DRAM_PLL_EN = 4,
|
||||
CLK_SRC_SYSTEM_PLL1_EN = 5,
|
||||
CLK_SRC_SYSTEM_PLL2_EN = 6,
|
||||
CLK_SRC_SYSTEM_PLL3_EN = 7,
|
||||
CLK_SRC_AUDIO_PLL1_EN = 8,
|
||||
CLK_SRC_AUDIO_PLL2_EN = 9,
|
||||
CLK_SRC_VIDEO_PLL1_EN = 10,
|
||||
CLK_SRC_VIDEO_PLL2_EN = 11,
|
||||
CLK_SRC_ARM_PLL = 12,
|
||||
CLK_SRC_GPU_PLL = 13,
|
||||
CLK_SRC_VPU_PLL = 14,
|
||||
CLK_SRC_DRAM_PLL = 15,
|
||||
CLK_SRC_SYSTEM_PLL1_800M = 16,
|
||||
CLK_SRC_SYSTEM_PLL1_400M = 17,
|
||||
CLK_SRC_SYSTEM_PLL1_266M = 18,
|
||||
CLK_SRC_SYSTEM_PLL1_200M = 19,
|
||||
CLK_SRC_SYSTEM_PLL1_160M = 20,
|
||||
CLK_SRC_SYSTEM_PLL1_133M = 21,
|
||||
CLK_SRC_SYSTEM_PLL1_100M = 22,
|
||||
CLK_SRC_SYSTEM_PLL1_80M = 23,
|
||||
CLK_SRC_SYSTEM_PLL1_40M = 24,
|
||||
CLK_SRC_SYSTEM_PLL2_1000M = 25,
|
||||
CLK_SRC_SYSTEM_PLL2_500M = 26,
|
||||
CLK_SRC_SYSTEM_PLL2_333M = 27,
|
||||
CLK_SRC_SYSTEM_PLL2_250M = 28,
|
||||
CLK_SRC_SYSTEM_PLL2_200M = 29,
|
||||
CLK_SRC_SYSTEM_PLL2_166M = 30,
|
||||
CLK_SRC_SYSTEM_PLL2_125M = 31,
|
||||
CLK_SRC_SYSTEM_PLL2_100M = 32,
|
||||
CLK_SRC_SYSTEM_PLL2_50M = 33,
|
||||
CLK_SRC_SYSTEM_PLL3 = 34,
|
||||
CLK_SRC_AUDIO_PLL1 = 35,
|
||||
CLK_SRC_AUDIO_PLL2 = 36,
|
||||
CLK_SRC_VIDEO_PLL1 = 37,
|
||||
CLK_SRC_VIDEO_PLL2 = 38,
|
||||
CLK_SRC_OSC_25M = 39,
|
||||
CLK_SRC_OSC_27M = 40,
|
||||
};
|
||||
|
||||
/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
|
||||
#define FRAC_PLL_LOCK_MASK BIT(31)
|
||||
#define FRAC_PLL_CLKE_MASK BIT(21)
|
||||
#define FRAC_PLL_PD_MASK BIT(19)
|
||||
#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
|
||||
#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
|
||||
#define FRAC_PLL_BYPASS_MASK BIT(14)
|
||||
#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
|
||||
#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
|
||||
#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
|
||||
#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
|
||||
#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
|
||||
#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
|
||||
#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
|
||||
#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
|
||||
|
||||
#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
|
||||
#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
|
||||
#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
|
||||
#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
|
||||
|
||||
#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
|
||||
#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
|
||||
#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
|
||||
#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
|
||||
|
||||
/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
|
||||
#define SSCG_PLL_LOCK_MASK BIT(31)
|
||||
#define SSCG_PLL_CLKE_MASK BIT(25)
|
||||
#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
|
||||
#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
|
||||
#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
|
||||
#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
|
||||
#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
|
||||
#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
|
||||
#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
|
||||
#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
|
||||
#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
|
||||
#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
|
||||
#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
|
||||
#define SSCG_PLL_PD_MASK BIT(7)
|
||||
#define SSCG_PLL_BYPASS1_MASK BIT(5)
|
||||
#define SSCG_PLL_BYPASS2_MASK BIT(4)
|
||||
#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
|
||||
#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
|
||||
#define SSCG_PLL_REFCLK_SEL_MASK 0x3
|
||||
#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
|
||||
#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
|
||||
#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
|
||||
#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
|
||||
|
||||
#define SSCG_PLL_SSDS_MASK BIT(8)
|
||||
#define SSCG_PLL_SSMD_MASK (0x7 << 5)
|
||||
#define SSCG_PLL_SSMF_MASK (0xf << 1)
|
||||
#define SSCG_PLL_SSE_MASK 0x1
|
||||
|
||||
#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
|
||||
#define SSCG_PLL_REF_DIVR1_SHIFT 25
|
||||
#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
|
||||
#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
|
||||
#define SSCG_PLL_REF_DIVR2_SHIFT 19
|
||||
#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
|
||||
SSCG_PLL_FEEDBACK_DIV_F1_MASK)
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
|
||||
#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
|
||||
SSCG_PLL_FEEDBACK_DIV_F2_MASK)
|
||||
#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
|
||||
#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
|
||||
#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
|
||||
SSCG_PLL_OUTPUT_DIV_VAL_MASK)
|
||||
#define SSCG_PLL_FILTER_RANGE_MASK 0x1
|
||||
|
||||
#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
|
||||
#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
|
||||
#define HW_DIGPROG_MINOR_MASK 0xff
|
||||
|
||||
#define HW_OSC_27M_CLKE_MASK BIT(4)
|
||||
#define HW_OSC_25M_CLKE_MASK BIT(2)
|
||||
#define HW_OSC_32K_SEL_MASK 0x1
|
||||
#define HW_OSC_32K_SEL_RTC 0x1
|
||||
#define HW_OSC_32K_SEL_25M_DIV800 0x0
|
||||
|
||||
#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
|
||||
#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
|
||||
#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
|
||||
#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
|
||||
#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
|
||||
#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
|
||||
#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
|
||||
#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
|
||||
#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
|
||||
#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
|
||||
#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
|
||||
#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
|
||||
|
||||
#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
|
||||
#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
|
||||
#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
|
||||
#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
|
||||
#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
|
||||
#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
|
||||
#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
|
||||
#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
|
||||
#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
|
||||
#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
|
||||
|
||||
enum frac_pll_out_val {
|
||||
FRAC_PLL_OUT_1000M,
|
||||
FRAC_PLL_OUT_1600M,
|
||||
};
|
||||
|
||||
void init_nand_clk(void);
|
||||
#endif
|
||||
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Reference in New Issue
Block a user