GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

This commit is contained in:
lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef _STM32_GPIO_H_
#define _STM32_GPIO_H_
#include <asm/arch-stm32/gpio.h>
#endif /* _STM32_GPIO_H_ */
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
#include <asm/arch-stm32/stm32f.h>
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 32 * 1024,
[4] = 128 * 1024,
[5 ... 7] = 256 * 1024
};
#endif /* _ASM_ARCH_HARDWARE_H */
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
*/
#ifndef __STM32_PWR_H_
/*
* Offsets of some PWR registers
*/
#define PWR_CR1_ODEN BIT(16)
#define PWR_CR1_ODSWEN BIT(17)
#define PWR_CSR1_ODRDY BIT(16)
#define PWR_CSR1_ODSWRDY BIT(17)
struct stm32_pwr_regs {
u32 cr1; /* power control register 1 */
u32 csr1; /* power control/status register 2 */
u32 cr2; /* power control register 2 */
u32 csr2; /* power control/status register 2 */
};
#endif /* __STM32_PWR_H_ */
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2016
* Michael Kurz, michi.kurz@gmail.com.
*/
#ifndef _STM32_SYSCFG_H
#define _STM32_SYSCFG_H
struct stm32_syscfg_regs {
u32 memrmp;
u32 pmc;
u32 exticr1;
u32 exticr2;
u32 exticr3;
u32 exticr4;
u32 cmpcr;
};
/*
* SYSCFG registers base
*/
#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
/* SYSCFG peripheral mode configuration register */
#define SYSCFG_PMC_MII_RMII_SEL BIT(23)
#endif