GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#ifndef _STM32_GPIO_H_
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#define _STM32_GPIO_H_
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#include <asm/arch-stm32/gpio.h>
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#endif /* _STM32_GPIO_H_ */
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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#include <asm/arch-stm32/stm32f.h>
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static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
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[0 ... 3] = 32 * 1024,
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[4] = 128 * 1024,
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[5 ... 7] = 256 * 1024
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};
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#endif /* _ASM_ARCH_HARDWARE_H */
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
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*/
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#ifndef __STM32_PWR_H_
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/*
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* Offsets of some PWR registers
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*/
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#define PWR_CR1_ODEN BIT(16)
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#define PWR_CR1_ODSWEN BIT(17)
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#define PWR_CSR1_ODRDY BIT(16)
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#define PWR_CSR1_ODSWRDY BIT(17)
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struct stm32_pwr_regs {
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u32 cr1; /* power control register 1 */
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u32 csr1; /* power control/status register 2 */
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u32 cr2; /* power control register 2 */
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u32 csr2; /* power control/status register 2 */
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};
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#endif /* __STM32_PWR_H_ */
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016
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* Michael Kurz, michi.kurz@gmail.com.
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*/
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#ifndef _STM32_SYSCFG_H
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#define _STM32_SYSCFG_H
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struct stm32_syscfg_regs {
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u32 memrmp;
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u32 pmc;
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u32 exticr1;
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u32 exticr2;
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u32 exticr3;
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u32 exticr4;
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u32 cmpcr;
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};
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/*
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* SYSCFG registers base
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*/
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#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
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/* SYSCFG peripheral mode configuration register */
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#define SYSCFG_PMC_MII_RMII_SEL BIT(23)
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#endif
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