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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/Kconfig
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if ARCH_IMX8M
config IMX8M
bool
select ROM_UNIFIED_SECTIONS
config IMX8MQ
bool
select IMX8M
config IMX8MM
bool
select IMX8M
config IMX8MN
bool
select IMX8M
config SYS_SOC
default "imx8m"
choice
prompt "NXP i.MX8M board select"
optional
config TARGET_IMX8MQ_EVK
bool "imx8mq_evk"
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MM_EVK
bool "imx8mm LPDDR4 EVK board"
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_EVK
bool "imx8mn DDR4 EVK board"
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
endif
source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/Makefile
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# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2017 NXP
obj-y += lowlevel_init.o
obj-y += clock_slice.o soc.o
obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN) += clock_imx8mm.o
source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/clock_imx8mm.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <clk.h>
#include <clk-uclass.h>
#include <dt-bindings/clock/imx8mm-clock.h>
#include <div64.h>
#include <errno.h>
DECLARE_GLOBAL_DATA_PTR;
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
void enable_ocotp_clk(unsigned char enable)
{
struct clk *clkp;
int ret;
ret = clk_get_by_id(IMX8MM_CLK_OCOTP_ROOT, &clkp);
if (ret) {
printf("%s: err: %d\n", __func__, ret);
return;
}
enable ? clk_enable(clkp) : clk_disable(clkp);
}
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
struct clk *clkp;
int ret;
ret = clk_get_by_id(IMX8MM_CLK_I2C1_ROOT + i2c_num, &clkp);
if (ret) {
printf("%s: err: %d\n", __func__, ret);
return ret;
}
return enable ? clk_enable(clkp) : clk_disable(clkp);
}
#ifdef CONFIG_SPL_BUILD
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
};
int fracpll_configure(enum pll_clocks pll, u32 freq)
{
int i;
u32 tmp, div_val;
void *pll_base;
struct imx_int_pll_rate_table *rate;
for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
if (freq == imx8mm_fracpll_tbl[i].rate)
break;
}
if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
printf("No matched freq table %u\n", freq);
return -EINVAL;
}
rate = &imx8mm_fracpll_tbl[i];
switch (pll) {
case ANATOP_DRAM_PLL:
setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
pll_base = &ana_pll->dram_pll_gnrl_ctl;
break;
case ANATOP_VIDEO_PLL:
pll_base = &ana_pll->video_pll1_gnrl_ctl;
break;
default:
return 0;
}
/* Bypass clock and set lock to pll output lock */
tmp = readl(pll_base);
tmp |= BYPASS_MASK;
writel(tmp, pll_base);
/* Enable RST */
tmp &= ~RST_MASK;
writel(tmp, pll_base);
div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
(rate->sdiv << SDIV_SHIFT);
writel(div_val, pll_base + 4);
writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
__udelay(100);
/* Disable RST */
tmp |= RST_MASK;
writel(tmp, pll_base);
/* Wait Lock*/
while (!(readl(pll_base) & LOCK_STATUS))
;
/* Bypass */
tmp &= ~BYPASS_MASK;
writel(tmp, pll_base);
return 0;
}
void dram_pll_init(ulong pll_val)
{
fracpll_configure(ANATOP_DRAM_PLL, pll_val);
}
static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
CLK_ROOT_PRE_DIV2),
DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
CLK_ROOT_PRE_DIV2),
DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
CLK_ROOT_PRE_DIV2),
};
void dram_enable_bypass(ulong clk_val)
{
int i;
struct dram_bypass_clk_setting *config;
for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
break;
}
if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
printf("No matched freq table %lu\n", clk_val);
return;
}
config = &imx8mm_dram_bypass_tbl[i];
clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
CLK_ROOT_PRE_DIV(config->alt_pre_div));
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
CLK_ROOT_PRE_DIV(config->apb_pre_div));
clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
}
void dram_disable_bypass(void)
{
clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(4) |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
}
#endif
void init_uart_clk(u32 index)
{
/*
* set uart clock root
* 24M OSC
*/
switch (index) {
case 0:
clock_enable(CCGR_UART1, 0);
clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_UART1, 1);
return;
case 1:
clock_enable(CCGR_UART2, 0);
clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_UART2, 1);
return;
case 2:
clock_enable(CCGR_UART3, 0);
clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_UART3, 1);
return;
case 3:
clock_enable(CCGR_UART4, 0);
clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_UART4, 1);
return;
default:
printf("Invalid uart index\n");
return;
}
}
void init_wdog_clk(void)
{
clock_enable(CCGR_WDOG1, 0);
clock_enable(CCGR_WDOG2, 0);
clock_enable(CCGR_WDOG3, 0);
clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_WDOG1, 1);
clock_enable(CCGR_WDOG2, 1);
clock_enable(CCGR_WDOG3, 1);
}
int clock_init(void)
{
u32 val_cfg0;
/*
* The gate is not exported to clk tree, so configure them here.
* According to ANAMIX SPEC
* sys pll1 fixed at 800MHz
* sys pll2 fixed at 1GHz
* Here we only enable the outputs.
*/
val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
INTPLL_DIV20_CLKE_MASK;
writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
INTPLL_DIV20_CLKE_MASK;
writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
/* config GIC to sys_pll2_100m */
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(3));
clock_enable(CCGR_GIC, 1);
clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
clock_enable(CCGR_DDR1, 0);
clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
clock_enable(CCGR_DDR1, 1);
init_wdog_clk();
clock_enable(CCGR_TEMP_SENSOR, 1);
clock_enable(CCGR_SEC_DEBUG, 1);
return 0;
};
u32 imx_get_uartclk(void)
{
return 24000000U;
}
u32 mxc_get_clock(enum mxc_clock clk)
{
struct clk *clkp;
int ret;
switch (clk) {
case MXC_IPG_CLK:
ret = clk_get_by_id(IMX8MM_CLK_IPG_ROOT, &clkp);
if (ret)
return 0;
return clk_get_rate(clkp);
case MXC_ARM_CLK:
ret = clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp);
if (ret)
return 0;
return clk_get_rate(clkp);
default:
printf("%s: %d not supported\n", __func__, clk);
}
return 0;
}
source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/clock_imx8mq.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <errno.h>
#include <linux/iopoll.h>
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
static u32 decode_frac_pll(enum clk_root_src frac_pll)
{
u32 pll_cfg0, pll_cfg1, pllout;
u32 pll_refclk_sel, pll_refclk;
u32 divr_val, divq_val, divf_val, divff, divfi;
u32 pllout_div_shift, pllout_div_mask, pllout_div;
switch (frac_pll) {
case ARM_PLL_CLK:
pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
break;
default:
printf("Frac PLL %d not supporte\n", frac_pll);
return 0;
}
pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
/* Power down */
if (pll_cfg0 & FRAC_PLL_PD_MASK)
return 0;
/* output not enabled */
if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
return 0;
pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
pll_refclk = 25000000u;
else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
pll_refclk = 27000000u;
else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
pll_refclk = 27000000u;
else
pll_refclk = 0;
if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
return pll_refclk;
divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
FRAC_PLL_FRAC_DIV_CTL_SHIFT;
divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
divf_val = 1 + divfi + divff / (1 << 24);
pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
((divq_val + 1) * 2);
return pllout / (pllout_div + 1);
}
static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
{
u32 pll_cfg0, pll_cfg1, pll_cfg2;
u32 pll_refclk_sel, pll_refclk;
u32 divr1, divr2, divf1, divf2, divq, div;
u32 sse;
u32 pll_clke;
u32 pllout_div_shift, pllout_div_mask, pllout_div;
u32 pllout;
switch (sscg_pll) {
case SYSTEM_PLL1_800M_CLK:
case SYSTEM_PLL1_400M_CLK:
case SYSTEM_PLL1_266M_CLK:
case SYSTEM_PLL1_200M_CLK:
case SYSTEM_PLL1_160M_CLK:
case SYSTEM_PLL1_133M_CLK:
case SYSTEM_PLL1_100M_CLK:
case SYSTEM_PLL1_80M_CLK:
case SYSTEM_PLL1_40M_CLK:
pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
break;
case SYSTEM_PLL2_1000M_CLK:
case SYSTEM_PLL2_500M_CLK:
case SYSTEM_PLL2_333M_CLK:
case SYSTEM_PLL2_250M_CLK:
case SYSTEM_PLL2_200M_CLK:
case SYSTEM_PLL2_166M_CLK:
case SYSTEM_PLL2_125M_CLK:
case SYSTEM_PLL2_100M_CLK:
case SYSTEM_PLL2_50M_CLK:
pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
break;
case SYSTEM_PLL3_CLK:
pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
break;
case DRAM_PLL1_CLK:
pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
break;
default:
printf("sscg pll %d not supporte\n", sscg_pll);
return 0;
}
switch (sscg_pll) {
case DRAM_PLL1_CLK:
pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
div = 1;
break;
case SYSTEM_PLL3_CLK:
pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
div = 1;
break;
case SYSTEM_PLL2_1000M_CLK:
case SYSTEM_PLL1_800M_CLK:
pll_clke = SSCG_PLL_CLKE_MASK;
div = 1;
break;
case SYSTEM_PLL2_500M_CLK:
case SYSTEM_PLL1_400M_CLK:
pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
div = 2;
break;
case SYSTEM_PLL2_333M_CLK:
case SYSTEM_PLL1_266M_CLK:
pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
div = 3;
break;
case SYSTEM_PLL2_250M_CLK:
case SYSTEM_PLL1_200M_CLK:
pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
div = 4;
break;
case SYSTEM_PLL2_200M_CLK:
case SYSTEM_PLL1_160M_CLK:
pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
div = 5;
break;
case SYSTEM_PLL2_166M_CLK:
case SYSTEM_PLL1_133M_CLK:
pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
div = 6;
break;
case SYSTEM_PLL2_125M_CLK:
case SYSTEM_PLL1_100M_CLK:
pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
div = 8;
break;
case SYSTEM_PLL2_100M_CLK:
case SYSTEM_PLL1_80M_CLK:
pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
div = 10;
break;
case SYSTEM_PLL2_50M_CLK:
case SYSTEM_PLL1_40M_CLK:
pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
div = 20;
break;
default:
printf("sscg pll %d not supporte\n", sscg_pll);
return 0;
}
/* Power down */
if (pll_cfg0 & SSCG_PLL_PD_MASK)
return 0;
/* output not enabled */
if ((pll_cfg0 & pll_clke) == 0)
return 0;
pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
pll_refclk = 25000000u;
else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
pll_refclk = 27000000u;
else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
pll_refclk = 27000000u;
else
pll_refclk = 0;
/* We assume bypass1/2 are the same value */
if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
(pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
return pll_refclk;
divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
SSCG_PLL_REF_DIVR1_SHIFT;
divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
SSCG_PLL_REF_DIVR2_SHIFT;
divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
if (sse)
sse = 8;
else
sse = 2;
pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
(divr2 + 1) * (divf2 + 1) / (divq + 1);
return pllout / (pllout_div + 1) / div;
}
static u32 get_root_src_clk(enum clk_root_src root_src)
{
switch (root_src) {
case OSC_25M_CLK:
return 25000000;
case OSC_27M_CLK:
return 27000000;
case OSC_32K_CLK:
return 32768;
case ARM_PLL_CLK:
return decode_frac_pll(root_src);
case SYSTEM_PLL1_800M_CLK:
case SYSTEM_PLL1_400M_CLK:
case SYSTEM_PLL1_266M_CLK:
case SYSTEM_PLL1_200M_CLK:
case SYSTEM_PLL1_160M_CLK:
case SYSTEM_PLL1_133M_CLK:
case SYSTEM_PLL1_100M_CLK:
case SYSTEM_PLL1_80M_CLK:
case SYSTEM_PLL1_40M_CLK:
case SYSTEM_PLL2_1000M_CLK:
case SYSTEM_PLL2_500M_CLK:
case SYSTEM_PLL2_333M_CLK:
case SYSTEM_PLL2_250M_CLK:
case SYSTEM_PLL2_200M_CLK:
case SYSTEM_PLL2_166M_CLK:
case SYSTEM_PLL2_125M_CLK:
case SYSTEM_PLL2_100M_CLK:
case SYSTEM_PLL2_50M_CLK:
case SYSTEM_PLL3_CLK:
return decode_sscg_pll(root_src);
default:
return 0;
}
return 0;
}
static u32 get_root_clk(enum clk_root_index clock_id)
{
enum clk_root_src root_src;
u32 post_podf, pre_podf, root_src_clk;
if (clock_root_enabled(clock_id) <= 0)
return 0;
if (clock_get_prediv(clock_id, &pre_podf) < 0)
return 0;
if (clock_get_postdiv(clock_id, &post_podf) < 0)
return 0;
if (clock_get_src(clock_id, &root_src) < 0)
return 0;
root_src_clk = get_root_src_clk(root_src);
return root_src_clk / (post_podf + 1) / (pre_podf + 1);
}
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable)
{
clock_enable(CCGR_OCOTP, !!enable);
}
#endif
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
{
/* 0 - 3 is valid i2c num */
if (i2c_num > 3)
return -EINVAL;
clock_enable(CCGR_I2C1 + i2c_num, !!enable);
return 0;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
u32 val;
if (clk == MXC_ARM_CLK)
return get_root_clk(ARM_A53_CLK_ROOT);
if (clk == MXC_IPG_CLK) {
clock_get_target_val(IPG_CLK_ROOT, &val);
val = val & 0x3;
return get_root_clk(AHB_CLK_ROOT) / (val + 1);
}
return get_root_clk(clk);
}
u32 imx_get_uartclk(void)
{
return mxc_get_clock(UART1_CLK_ROOT);
}
void mxs_set_lcdclk(u32 base_addr, u32 freq)
{
/*
* LCDIF_PIXEL_CLK: select 800MHz root clock,
* select pre divider 8, output is 100 MHz
*/
clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(4) |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
}
void init_wdog_clk(void)
{
clock_enable(CCGR_WDOG1, 0);
clock_enable(CCGR_WDOG2, 0);
clock_enable(CCGR_WDOG3, 0);
clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_WDOG1, 1);
clock_enable(CCGR_WDOG2, 1);
clock_enable(CCGR_WDOG3, 1);
}
void init_usb_clk(void)
{
if (!is_usb_boot()) {
clock_enable(CCGR_USB_CTRL1, 0);
clock_enable(CCGR_USB_CTRL2, 0);
clock_enable(CCGR_USB_PHY1, 0);
clock_enable(CCGR_USB_PHY2, 0);
/* 500MHz */
clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
/* 100MHz */
clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
/* 100MHz */
clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
clock_enable(CCGR_USB_CTRL1, 1);
clock_enable(CCGR_USB_CTRL2, 1);
clock_enable(CCGR_USB_PHY1, 1);
clock_enable(CCGR_USB_PHY2, 1);
}
}
void init_nand_clk(void)
{
clock_enable(CCGR_RAWNAND, 0);
clock_set_target_val(NAND_CLK_ROOT,
CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
clock_enable(CCGR_RAWNAND, 1);
}
void init_uart_clk(u32 index)
{
/* Set uart clock root 25M OSC */
switch (index) {
case 0:
clock_enable(CCGR_UART1, 0);
clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_UART1, 1);
return;
case 1:
clock_enable(CCGR_UART2, 0);
clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_UART2, 1);
return;
case 2:
clock_enable(CCGR_UART3, 0);
clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_UART3, 1);
return;
case 3:
clock_enable(CCGR_UART4, 0);
clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_UART4, 1);
return;
default:
printf("Invalid uart index\n");
return;
}
}
void init_clk_usdhc(u32 index)
{
/*
* set usdhc clock root
* sys pll1 400M
*/
switch (index) {
case 0:
clock_enable(CCGR_USDHC1, 0);
clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
clock_enable(CCGR_USDHC1, 1);
return;
case 1:
clock_enable(CCGR_USDHC2, 0);
clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
clock_enable(CCGR_USDHC2, 1);
return;
default:
printf("Invalid usdhc index\n");
return;
}
}
int set_clk_qspi(void)
{
/*
* set qspi root
* sys pll1 100M
*/
clock_enable(CCGR_QSPI, 0);
clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(7));
clock_enable(CCGR_QSPI, 1);
return 0;
}
#ifdef CONFIG_FEC_MXC
int set_clk_enet(enum enet_freq type)
{
u32 target;
u32 enet1_ref;
switch (type) {
case ENET_125MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
break;
case ENET_50MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
break;
case ENET_25MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
break;
default:
return -EINVAL;
}
/* disable the clock first */
clock_enable(CCGR_ENET1, 0);
clock_enable(CCGR_SIM_ENET, 0);
/* set enet axi clock 266Mhz */
target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
clock_set_target_val(ENET_AXI_CLK_ROOT, target);
target = CLK_ROOT_ON | enet1_ref |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
clock_set_target_val(ENET_REF_CLK_ROOT, target);
target = CLK_ROOT_ON |
ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
/* enable clock */
clock_enable(CCGR_SIM_ENET, 1);
clock_enable(CCGR_ENET1, 1);
return 0;
}
#endif
u32 imx_get_fecclk(void)
{
return get_root_clk(ENET_AXI_CLK_ROOT);
}
static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
CLK_ROOT_PRE_DIV2),
DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
CLK_ROOT_PRE_DIV2),
DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
CLK_ROOT_PRE_DIV2),
};
void dram_enable_bypass(ulong clk_val)
{
int i;
struct dram_bypass_clk_setting *config;
for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
break;
}
if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
printf("No matched freq table %lu\n", clk_val);
return;
}
config = &imx8mq_dram_bypass_tbl[i];
clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
CLK_ROOT_PRE_DIV(config->alt_pre_div));
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
CLK_ROOT_PRE_DIV(config->apb_pre_div));
clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
}
void dram_disable_bypass(void)
{
clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(4) |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
}
#ifdef CONFIG_SPL_BUILD
void dram_pll_init(ulong pll_val)
{
u32 val;
void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
/* Bypass */
setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
switch (pll_val) {
case MHZ(800):
val = readl(pll_cfg_reg2);
val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
SSCG_PLL_FEEDBACK_DIV_F2_MASK |
SSCG_PLL_FEEDBACK_DIV_F1_MASK |
SSCG_PLL_REF_DIVR2_MASK);
val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
val |= SSCG_PLL_REF_DIVR2_VAL(29);
writel(val, pll_cfg_reg2);
break;
case MHZ(600):
val = readl(pll_cfg_reg2);
val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
SSCG_PLL_FEEDBACK_DIV_F2_MASK |
SSCG_PLL_FEEDBACK_DIV_F1_MASK |
SSCG_PLL_REF_DIVR2_MASK);
val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
val |= SSCG_PLL_REF_DIVR2_VAL(29);
writel(val, pll_cfg_reg2);
break;
case MHZ(400):
val = readl(pll_cfg_reg2);
val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
SSCG_PLL_FEEDBACK_DIV_F2_MASK |
SSCG_PLL_FEEDBACK_DIV_F1_MASK |
SSCG_PLL_REF_DIVR2_MASK);
val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
val |= SSCG_PLL_REF_DIVR2_VAL(29);
writel(val, pll_cfg_reg2);
break;
case MHZ(167):
val = readl(pll_cfg_reg2);
val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
SSCG_PLL_FEEDBACK_DIV_F2_MASK |
SSCG_PLL_FEEDBACK_DIV_F1_MASK |
SSCG_PLL_REF_DIVR2_MASK);
val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
val |= SSCG_PLL_REF_DIVR2_VAL(30);
writel(val, pll_cfg_reg2);
break;
default:
break;
}
/* Clear power down bit */
clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
/* Eanble ARM_PLL/SYS_PLL */
setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
/* Clear bypass */
clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
__udelay(100);
clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
/* Wait lock */
while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
;
}
int frac_pll_init(u32 pll, enum frac_pll_out_val val)
{
void __iomem *pll_cfg0, __iomem *pll_cfg1;
u32 val_cfg0, val_cfg1;
int ret;
switch (pll) {
case ANATOP_ARM_PLL:
pll_cfg0 = &ana_pll->arm_pll_cfg0;
pll_cfg1 = &ana_pll->arm_pll_cfg1;
if (val == FRAC_PLL_OUT_1000M)
val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
else
val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
FRAC_PLL_REFCLK_DIV_VAL(4) |
FRAC_PLL_OUTPUT_DIV_VAL(0);
break;
default:
return -EINVAL;
}
/* bypass the clock */
setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
/* Set the value */
writel(val_cfg1, pll_cfg1);
writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
val_cfg0 = readl(pll_cfg0);
/* unbypass the clock */
clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
ret = readl_poll_timeout(pll_cfg0, val_cfg0,
val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
if (ret)
printf("%s timeout\n", __func__);
clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
return 0;
}
int sscg_pll_init(u32 pll)
{
void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
u32 val_cfg0, val_cfg1, val_cfg2, val;
u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
int ret;
switch (pll) {
case ANATOP_SYSTEM_PLL1:
pll_cfg0 = &ana_pll->sys_pll1_cfg0;
pll_cfg1 = &ana_pll->sys_pll1_cfg1;
pll_cfg2 = &ana_pll->sys_pll1_cfg2;
/* 800MHz */
val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
val_cfg1 = 0;
val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
SSCG_PLL_REFCLK_SEL_OSC_25M;
break;
case ANATOP_SYSTEM_PLL2:
pll_cfg0 = &ana_pll->sys_pll2_cfg0;
pll_cfg1 = &ana_pll->sys_pll2_cfg1;
pll_cfg2 = &ana_pll->sys_pll2_cfg2;
/* 1000MHz */
val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
val_cfg1 = 0;
val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
SSCG_PLL_REFCLK_SEL_OSC_25M;
break;
case ANATOP_SYSTEM_PLL3:
pll_cfg0 = &ana_pll->sys_pll3_cfg0;
pll_cfg1 = &ana_pll->sys_pll3_cfg1;
pll_cfg2 = &ana_pll->sys_pll3_cfg2;
/* 800MHz */
val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
val_cfg1 = 0;
val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
SSCG_PLL_REFCLK_SEL_OSC_25M;
break;
default:
return -EINVAL;
}
/*bypass*/
setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
/* set value */
writel(val_cfg2, pll_cfg2);
writel(val_cfg1, pll_cfg1);
/*unbypass1 and wait 70us */
writel(val_cfg0 | bypass2_mask, pll_cfg1);
__udelay(70);
/* unbypass2 and wait lock */
writel(val_cfg0, pll_cfg1);
ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
if (ret)
printf("%s timeout\n", __func__);
return ret;
}
int clock_init(void)
{
u32 grade;
clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
/*
* 8MQ only supports two grades: consumer and industrial.
* We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
*/
grade = get_cpu_temp_grade(NULL, NULL);
if (!grade) {
frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
} else {
frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
}
/*
* According to ANAMIX SPEC
* sys pll1 fixed at 800MHz
* sys pll2 fixed at 1GHz
* Here we only enable the outputs.
*/
setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
init_wdog_clk();
clock_enable(CCGR_TSENSOR, 1);
clock_enable(CCGR_OCOTP, 1);
/* config GIC ROOT to sys_pll2_200m */
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT,
CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
clock_enable(CCGR_GIC, 1);
return 0;
}
#endif
/*
* Dump some clockes.
*/
#ifndef CONFIG_SPL_BUILD
int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
u32 freq;
freq = decode_frac_pll(ARM_PLL_CLK);
printf("ARM_PLL %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
freq = mxc_get_clock(UART1_CLK_ROOT);
printf("UART1 %8d MHz\n", freq / 1000000);
freq = mxc_get_clock(USDHC1_CLK_ROOT);
printf("USDHC1 %8d MHz\n", freq / 1000000);
freq = mxc_get_clock(QSPI_CLK_ROOT);
printf("QSPI %8d MHz\n", freq / 1000000);
return 0;
}
U_BOOT_CMD(
clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
"display clocks",
""
);
#endif
source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/clock_slice.c
+804
View File
@@ -0,0 +1,804 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <errno.h>
static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
#ifdef CONFIG_IMX8MQ
static struct clk_root_map root_array[] = {
{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
{OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
},
{ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
},
{VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
{OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
},
{GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
{OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
{OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
{OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
},
{ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
},
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
},
{VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
},
{DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
EXT_CLK_1, EXT_CLK_4}
},
{DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
EXT_CLK_1, EXT_CLK_3}
},
{DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
EXT_CLK_2, EXT_CLK_3}
},
{USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
{OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
{OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
{AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
{OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
{IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0,
{}
},
{AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
{OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
{MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK },
},
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
},
{DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
{OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
},
{VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
{OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
},
{DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
{OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
},
{DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
{OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
},
{PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
{OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
},
{PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
SYSTEM_PLL1_400M_CLK}
},
{PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
},
{DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
{OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
},
{LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
{OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
},
{SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
},
{SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
},
{SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
},
{SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
},
{SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
},
{SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
},
{SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
},
{SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
{OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
},
{ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
},
{ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
VIDEO_PLL_CLK}
},
{ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
{OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
{NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
{OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
},
{QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
{OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
},
{USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
{OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
},
{USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
{OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
},
{I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
{OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
{OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
{OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
{OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
},
{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
{OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
{OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
{OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
{OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
{OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
{OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
},
{GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
},
{GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
},
{GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
},
{GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
},
{GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
},
{GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
},
{TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
{OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
},
{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
{OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
},
{WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
{OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
},
{IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
{OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
},
{IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
},
{MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
{OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
{OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
},
{MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
{OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
},
{PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
},
{PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
},
{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
{OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68,
{OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
},
{DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69,
{OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK,
VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
},
{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
{DRAM_PLL1_CLK}
},
{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
{DRAM_PLL1_CLK}
},
};
#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
static struct clk_root_map root_array[] = {
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
},
{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
},
#ifdef CONFIG_IMX8MM
{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
},
#endif
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
},
{DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
},
{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
},
{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
},
{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
},
{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
{DRAM_PLL1_CLK}
},
};
#endif
static int select(enum clk_root_index clock_id)
{
int i, size;
struct clk_root_map *p = root_array;
size = ARRAY_SIZE(root_array);
for (i = 0; i < size; i++, p++) {
if (clock_id == p->entry)
return i;
}
return -EINVAL;
}
static void __iomem *get_clk_root_target(enum clk_slice_type slice_type,
u32 slice_index)
{
void __iomem *clk_root_target;
switch (slice_type) {
case CORE_CLOCK_SLICE:
clk_root_target =
(void __iomem *)&ccm_reg->core_root[slice_index];
break;
case BUS_CLOCK_SLICE:
clk_root_target =
(void __iomem *)&ccm_reg->bus_root[slice_index];
break;
case IP_CLOCK_SLICE:
clk_root_target =
(void __iomem *)&ccm_reg->ip_root[slice_index];
break;
case AHB_CLOCK_SLICE:
clk_root_target =
(void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2];
break;
case IPG_CLOCK_SLICE:
clk_root_target =
(void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2 + 1];
break;
case CORE_SEL_CLOCK_SLICE:
clk_root_target = (void __iomem *)&ccm_reg->core_sel;
break;
case DRAM_SEL_CLOCK_SLICE:
clk_root_target = (void __iomem *)&ccm_reg->dram_sel;
break;
default:
return NULL;
}
return clk_root_target;
}
int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
{
int root_entry;
struct clk_root_map *p;
void __iomem *clk_root_target;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
if (!clk_root_target)
return -EINVAL;
*val = readl(clk_root_target);
return 0;
}
int clock_set_target_val(enum clk_root_index clock_id, u32 val)
{
int root_entry;
struct clk_root_map *p;
void __iomem *clk_root_target;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
if (!clk_root_target)
return -EINVAL;
writel(val, clk_root_target);
return 0;
}
int clock_root_enabled(enum clk_root_index clock_id)
{
void __iomem *clk_root_target;
u32 slice_index, slice_type;
u32 val;
int root_entry;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
slice_type = root_array[root_entry].slice_type;
slice_index = root_array[root_entry].slice_index;
if ((slice_type == IPG_CLOCK_SLICE) ||
(slice_type == DRAM_SEL_CLOCK_SLICE) ||
(slice_type == CORE_SEL_CLOCK_SLICE)) {
/*
* Not supported, from CCM doc
* TODO
*/
return 0;
}
clk_root_target = get_clk_root_target(slice_type, slice_index);
if (!clk_root_target)
return -EINVAL;
val = readl(clk_root_target);
return (val & CLK_ROOT_ON) ? 1 : 0;
}
/* CCGR CLK gate operation */
int clock_enable(enum clk_ccgr_index index, bool enable)
{
void __iomem *ccgr;
if (index >= CCGR_MAX)
return -EINVAL;
if (enable)
ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_set;
else
ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_clr;
writel(CCGR_CLK_ON_MASK, ccgr);
return 0;
}
int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
{
u32 val;
int root_entry;
struct clk_root_map *p;
void __iomem *clk_root_target;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
if ((p->slice_type == CORE_CLOCK_SLICE) ||
(p->slice_type == IPG_CLOCK_SLICE) ||
(p->slice_type == CORE_SEL_CLOCK_SLICE) ||
(p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
*pre_div = 0;
return 0;
}
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
if (!clk_root_target)
return -EINVAL;
val = readl(clk_root_target);
val &= CLK_ROOT_PRE_DIV_MASK;
val >>= CLK_ROOT_PRE_DIV_SHIFT;
*pre_div = val;
return 0;
}
int clock_get_postdiv(enum clk_root_index clock_id,
enum root_post_div *post_div)
{
u32 val, mask;
int root_entry;
struct clk_root_map *p;
void __iomem *clk_root_target;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||
(p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
*post_div = 0;
return 0;
}
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
if (!clk_root_target)
return -EINVAL;
if (p->slice_type == IPG_CLOCK_SLICE)
mask = CLK_ROOT_IPG_POST_DIV_MASK;
else if (p->slice_type == CORE_CLOCK_SLICE)
mask = CLK_ROOT_CORE_POST_DIV_MASK;
else
mask = CLK_ROOT_POST_DIV_MASK;
val = readl(clk_root_target);
val &= mask;
val >>= CLK_ROOT_POST_DIV_SHIFT;
*post_div = val;
return 0;
}
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
{
u32 val;
int root_entry;
struct clk_root_map *p;
void __iomem *clk_root_target;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
if (!clk_root_target)
return -EINVAL;
val = readl(clk_root_target);
val &= CLK_ROOT_SRC_MUX_MASK;
val >>= CLK_ROOT_SRC_MUX_SHIFT;
*p_clock_src = p->src_mux[val];
return 0;
}
source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg
+16
View File
@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#define __ASSEMBLY__
FIT
BOOT_FROM sd
LOADER spl/u-boot-spl-ddr.bin 0x7E1000
SECOND_LOADER u-boot.itb 0x40200000 0x60000
DDR_FW lpddr4_pmu_train_1d_imem.bin
DDR_FW lpddr4_pmu_train_1d_dmem.bin
DDR_FW lpddr4_pmu_train_2d_imem.bin
DDR_FW lpddr4_pmu_train_2d_dmem.bin
source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg
+17
View File
@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#define __ASSEMBLY__
FIT
ROM_VERSION v2
BOOT_FROM sd
LOADER spl/u-boot-spl-ddr.bin 0x912000
SECOND_LOADER u-boot.itb 0x40200000 0x60000
DDR_FW ddr4_imem_1d.bin
DDR_FW ddr4_dmem_1d.bin
DDR_FW ddr4_imem_2d.bin
DDR_FW ddr4_dmem_2d.bin
source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/imximage.cfg
+17
View File
@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#define __ASSEMBLY__
FIT
BOOT_FROM sd
SIGNED_HDMI signed_hdmi_imx8m.bin
LOADER spl/u-boot-spl-ddr.bin 0x7E1000
SECOND_LOADER u-boot.itb 0x40200000 0x60000
DDR_FW lpddr4_pmu_train_1d_imem.bin
DDR_FW lpddr4_pmu_train_1d_dmem.bin
DDR_FW lpddr4_pmu_train_2d_imem.bin
DDR_FW lpddr4_pmu_train_2d_dmem.bin
source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/lowlevel_init.S
+62
View File
@@ -0,0 +1,62 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
*/
#include <config.h>
.align 8
.global rom_pointer
rom_pointer:
.space 256
/*
* Routine: save_boot_params (called after reset from start.S)
*/
.global save_boot_params
save_boot_params:
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
adr x0, rom_pointer
stp x1, x2, [x0], #16
stp x3, x4, [x0], #16
stp x5, x6, [x0], #16
stp x7, x8, [x0], #16
stp x9, x10, [x0], #16
stp x11, x12, [x0], #16
stp x13, x14, [x0], #16
stp x15, x16, [x0], #16
stp x17, x18, [x0], #16
stp x19, x20, [x0], #16
stp x21, x22, [x0], #16
stp x23, x24, [x0], #16
stp x25, x26, [x0], #16
stp x27, x28, [x0], #16
stp x29, x30, [x0], #16
mov x30, sp
str x30, [x0], #8
/* Returns */
b save_boot_params_ret
.global restore_boot_params
restore_boot_params:
adr x0, rom_pointer
ldp x1, x2, [x0], #16
ldp x3, x4, [x0], #16
ldp x5, x6, [x0], #16
ldp x7, x8, [x0], #16
ldp x9, x10, [x0], #16
ldp x11, x12, [x0], #16
ldp x13, x14, [x0], #16
ldp x15, x16, [x0], #16
ldp x17, x18, [x0], #16
ldp x19, x20, [x0], #16
ldp x21, x22, [x0], #16
ldp x23, x24, [x0], #16
ldp x25, x26, [x0], #16
ldp x27, x28, [x0], #16
ldp x29, x30, [x0], #16
ldr x0, [x0]
mov sp, x0
ret
source/bootloader/u-boot-2020.01/arch/arm/mach-imx/imx8m/soc.c
+399
View File
@@ -0,0 +1,399 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/syscounter.h>
#include <asm/armv8/mmu.h>
#include <dm/uclass.h>
#include <errno.h>
#include <fdt_support.h>
#include <fsl_wdog.h>
#include <imx_sip.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_IMX_HAB)
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
.bank = 1,
.word = 3,
};
#endif
int timer_init(void)
{
#ifdef CONFIG_SPL_BUILD
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
unsigned long freq = readl(&sctr->cntfid0);
/* Update with accurate clock frequency */
asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
#endif
gd->arch.tbl = 0;
gd->arch.tbu = 0;
return 0;
}
void enable_tzc380(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Enable TZASC and lock setting */
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
if (is_imx8mm() || is_imx8mn())
setbits_le32(&gpr->gpr[10], BIT(1));
/*
* set Region 0 attribute to allow secure and non-secure
* read/write permission. Found some masters like usb dwc3
* controllers can't work with secure memory.
*/
writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
}
void set_wdog_reset(struct wdog_regs *wdog)
{
/*
* Output WDOG_B signal to reset external pmic or POR_B decided by
* the board design. Without external reset, the peripherals/DDR/
* PMIC are not reset, that may cause system working abnormal.
* WDZST bit is write-once only bit. Align this bit in kernel,
* otherwise kernel code will have no chance to set this bit.
*/
setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
}
static struct mm_region imx8m_mem_map[] = {
{
/* ROM */
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x100000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* CAAM */
.virt = 0x100000UL,
.phys = 0x100000UL,
.size = 0x8000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* TCM */
.virt = 0x7C0000UL,
.phys = 0x7C0000UL,
.size = 0x80000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* OCRAM */
.virt = 0x900000UL,
.phys = 0x900000UL,
.size = 0x200000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* AIPS */
.virt = 0xB00000UL,
.phys = 0xB00000UL,
.size = 0x3f500000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* DRAM1 */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = PHYS_SDRAM_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
#ifdef PHYS_SDRAM_2_SIZE
}, {
/* DRAM2 */
.virt = 0x100000000UL,
.phys = 0x100000000UL,
.size = PHYS_SDRAM_2_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
#endif
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = imx8m_mem_map;
void enable_caches(void)
{
/*
* If OPTEE runs, remove OPTEE memory from MMU table to
* avoid speculative prefetch. OPTEE runs at the top of
* the first memory bank
*/
if (rom_pointer[1])
imx8m_mem_map[5].size -= rom_pointer[1];
icache_enable();
dcache_enable();
}
static u32 get_cpu_variant_type(u32 type)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[1];
struct fuse_bank1_regs *fuse =
(struct fuse_bank1_regs *)bank->fuse_regs;
u32 value = readl(&fuse->tester4);
if (type == MXC_CPU_IMX8MM) {
switch (value & 0x3) {
case 2:
if (value & 0x1c0000)
return MXC_CPU_IMX8MMDL;
else
return MXC_CPU_IMX8MMD;
case 3:
if (value & 0x1c0000)
return MXC_CPU_IMX8MMSL;
else
return MXC_CPU_IMX8MMS;
default:
if (value & 0x1c0000)
return MXC_CPU_IMX8MML;
break;
}
}
return type;
}
u32 get_cpu_rev(void)
{
struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
u32 reg = readl(&ana_pll->digprog);
u32 type = (reg >> 16) & 0xff;
u32 major_low = (reg >> 8) & 0xff;
u32 rom_version;
reg &= 0xff;
/* i.MX8MM */
if (major_low == 0x42) {
return (MXC_CPU_IMX8MN << 12) | reg;
} else if (major_low == 0x41) {
type = get_cpu_variant_type(MXC_CPU_IMX8MM);
} else {
if (reg == CHIP_REV_1_0) {
/*
* For B0 chip, the DIGPROG is not updated,
* it is still TO1.0. we have to check ROM
* version or OCOTP_READ_FUSE_DATA.
* 0xff0055aa is magic number for B1.
*/
if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
reg = CHIP_REV_2_1;
} else {
rom_version =
readl((void __iomem *)ROM_VERSION_A0);
if (rom_version != CHIP_REV_1_0) {
rom_version = readl((void __iomem *)ROM_VERSION_B0);
rom_version &= 0xff;
if (rom_version == CHIP_REV_2_0)
reg = CHIP_REV_2_0;
}
}
}
}
return (type << 12) | reg;
}
static void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
writew(enable, &wdog3->wmcr);
}
int arch_cpu_init_dm(void)
{
struct udevice *dev;
int ret;
if (CONFIG_IS_ENABLED(CLK)) {
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0) {
printf("Failed to find clock node. Check device tree\n");
return ret;
}
}
return 0;
}
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
/*
* ROM might disable clock for SCTR,
* enable the clock before timer_init.
*/
if (IS_ENABLED(CONFIG_SPL_BUILD))
clock_enable(CCGR_SCTR, 1);
/*
* Init timer at very early state, because sscg pll setting
* will use it
*/
timer_init();
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
clock_init();
imx_set_wdog_powerdown(false);
}
if (is_imx8mq()) {
clock_enable(CCGR_OCOTP, 1);
if (readl(&ocotp->ctrl) & 0x200)
writel(0x200, &ocotp->ctrl_clr);
}
return 0;
}
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
struct rom_api *g_rom_api = (struct rom_api *)0x980;
enum boot_device get_boot_device(void)
{
volatile gd_t *pgd = gd;
int ret;
u32 boot;
u16 boot_type;
u8 boot_instance;
enum boot_device boot_dev = SD1_BOOT;
ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
((uintptr_t)&boot) ^ QUERY_BT_DEV);
gd = pgd;
if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n");
return -1;
}
boot_type = boot >> 16;
boot_instance = (boot >> 8) & 0xff;
switch (boot_type) {
case BT_DEV_TYPE_SD:
boot_dev = boot_instance + SD1_BOOT;
break;
case BT_DEV_TYPE_MMC:
boot_dev = boot_instance + MMC1_BOOT;
break;
case BT_DEV_TYPE_NAND:
boot_dev = NAND_BOOT;
break;
case BT_DEV_TYPE_FLEXSPINOR:
boot_dev = QSPI_BOOT;
break;
case BT_DEV_TYPE_USB:
boot_dev = USB_BOOT;
break;
default:
break;
}
return boot_dev;
}
#endif
bool is_usb_boot(void)
{
return get_boot_device() == USB_BOOT;
}
#ifdef CONFIG_OF_SYSTEM_SETUP
int ft_system_setup(void *blob, bd_t *bd)
{
int i = 0;
int rc;
int nodeoff;
/* Disable the CPU idle for A0 chip since the HW does not support it */
if (is_soc_rev(CHIP_REV_1_0)) {
static const char * const nodes_path[] = {
"/cpus/cpu@0",
"/cpus/cpu@1",
"/cpus/cpu@2",
"/cpus/cpu@3",
};
for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
nodeoff = fdt_path_offset(blob, nodes_path[i]);
if (nodeoff < 0)
continue; /* Not found, skip it */
printf("Found %s node\n", nodes_path[i]);
rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
if (rc) {
printf("Unable to update property %s:%s, err=%s\n",
nodes_path[i], "status", fdt_strerror(rc));
return rc;
}
printf("Remove %s:%s\n", nodes_path[i],
"cpu-idle-states");
}
}
return 0;
}
#endif
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
void reset_cpu(ulong addr)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
if (!addr)
wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
/* Clear WDA to trigger WDOG_B immediately */
writew((WCR_WDE | WCR_SRS), &wdog->wcr);
while (1) {
/*
* spin for .5 seconds before reset
*/
}
}
#endif