GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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if ARCH_MX6
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config MX6_SMP
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bool
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select ARM_ERRATA_751472
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select ARM_ERRATA_761320
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select ARM_ERRATA_794072
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select ARM_ERRATA_845369
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select MP
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config MX6
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bool
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default y
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select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
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select GPT_TIMER if !MX6UL && !MX6ULL
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imply CMD_FUSE
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config MX6D
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bool
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select HAS_CAAM
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select MX6_SMP
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config MX6DL
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bool
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select HAS_CAAM
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select MX6_SMP
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config MX6Q
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bool
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select HAS_CAAM
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select MX6_SMP
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config MX6QDL
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bool
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select HAS_CAAM
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select MX6_SMP
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config MX6S
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bool
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select HAS_CAAM
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config MX6SL
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bool
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config MX6SX
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bool
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select HAS_CAAM
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select ROM_UNIFIED_SECTIONS
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config MX6SLL
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bool
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select ROM_UNIFIED_SECTIONS
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config MX6UL
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bool
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select HAS_CAAM
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select ROM_UNIFIED_SECTIONS
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select SYSCOUNTER_TIMER
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select SYS_L2CACHE_OFF
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config MX6UL_LITESOM
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bool
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select DM
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select DM_THERMAL
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select MX6UL
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select SUPPORT_SPL
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imply CMD_DM
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config MX6UL_OPOS6UL
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bool
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select BOARD_LATE_INIT
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select DM
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select DM_GPIO
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select DM_MMC
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select DM_THERMAL
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select MX6UL
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select SPL_DM if SPL
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select SPL_OF_CONTROL if SPL
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select SPL_PINCTRL if SPL
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select SPL_SEPARATE_BSS if SPL
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select SUPPORT_SPL
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imply CMD_DM
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config MX6ULL
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bool
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select ROM_UNIFIED_SECTIONS
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select SYSCOUNTER_TIMER
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select SYS_L2CACHE_OFF
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config MX6_OCRAM_256KB
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bool "Support 256KB OCRAM"
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depends on MX6D || MX6Q
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help
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Allows using the full 256KB size of the OCRAM on the MX6Q/MX6D series
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of chips, such as for SPL. The OCRAM of the Lite series of chips is
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only 128KB, so using this option will prevent the resulting code from
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working on those chips.
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config MX6_DDRCAL
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bool "Include dynamic DDR calibration routines"
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depends on SPL
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default n
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help
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Say "Y" if your board uses dynamic (per-boot) DDR calibration.
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If unsure, say N.
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choice
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prompt "MX6 board select"
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optional
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config TARGET_ADVANTECH_DMS_BA16
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bool "Advantech dms-ba16"
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select BOARD_LATE_INIT
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select MX6Q
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imply CMD_SATA
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config TARGET_APALIS_IMX6
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bool "Toradex Apalis iMX6 board"
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select BOARD_LATE_INIT
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select MX6Q
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select DM
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select DM_SERIAL
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select DM_THERMAL
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select SUPPORT_SPL
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imply CMD_DM
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imply CMD_SATA
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config TARGET_ARISTAINETOS
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bool "aristainetos"
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config TARGET_ARISTAINETOS2
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bool "aristainetos2"
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select BOARD_LATE_INIT
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config TARGET_ARISTAINETOS2B
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bool "Support aristainetos2-revB"
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select BOARD_LATE_INIT
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config TARGET_CGTQMX6EVAL
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bool "cgtqmx6eval"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6QDL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_CM_FX6
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bool "CM-FX6"
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select BOARD_LATE_INIT
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select DM
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select DM_GPIO
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select DM_SERIAL
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select MX6QDL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_COLIBRI_IMX6
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bool "Toradex Colibri iMX6 board"
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select BOARD_LATE_INIT
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select DM
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select DM_SERIAL
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select DM_THERMAL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_COLIBRI_IMX6ULL
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bool "Toradex Colibri iMX6ULL"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6ULL
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config TARGET_DART_6UL
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bool "Variscite imx6ULL dart(DART-SOM-6ULL)"
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select MX6ULL
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_I2C
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select DM_MMC
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select DM_SERIAL
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select DM_THERMAL
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select SUPPORT_SPL
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config TARGET_DHCOMIMX6
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bool "dh_imx6"
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6QDL
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select SUPPORT_SPL
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imply CMD_DM
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imply CMD_SPL
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config TARGET_DISPLAY5
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bool "LWN DISPLAY5 board"
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select DM
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select DM_ETH
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select DM_I2C
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select DM_MMC
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select DM_SPI
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select DM_GPIO
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select DM_SERIAL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_EMBESTMX6BOARDS
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bool "embestmx6boards"
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select BOARD_LATE_INIT
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select SUPPORT_SPL
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config TARGET_GE_BX50V3
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bool "General Electric Bx50v3"
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select BOARD_LATE_INIT
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select MX6Q
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config TARGET_GW_VENTANA
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bool "gw_ventana"
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select MX6QDL
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select SUPPORT_SPL
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imply CMD_SATA
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imply CMD_SPL
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config TARGET_KOSAGI_NOVENA
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bool "Kosagi Novena"
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select BOARD_LATE_INIT
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select SUPPORT_SPL
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config TARGET_MCCMON6
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bool "mccmon6"
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select MX6QDL
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select SUPPORT_SPL
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select DM
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select DM_GPIO
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select DM_ETH
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select DM_SERIAL
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select DM_I2C
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select DM_SPI
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imply CMD_DM
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config TARGET_MX6CUBOXI
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bool "Solid-run mx6 boards"
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select BOARD_LATE_INIT
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select MX6QDL
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select SUPPORT_SPL
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config TARGET_MX6LOGICPD
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bool "Logic PD i.MX6 SOM"
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select MX6Q
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select SUPPORT_SPL
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_I2C
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select DM_MMC
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select DM_PMIC
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select OF_CONTROL
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imply CMD_DM
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config TARGET_MX6MEMCAL
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bool "mx6memcal"
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select SUPPORT_SPL
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help
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The mx6memcal board is a virtual board that can be used to validate
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and characterize the memory layout of a new design during the initial
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development and pre-production stages.
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config TARGET_MX6QARM2
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bool "mx6qarm2"
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config TARGET_MX6DL_MAMOJ
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bool "Support BTicino Mamoj"
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_I2C
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select DM_MMC
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select DM_PMIC
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select DM_PMIC_PFUZE100
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select DM_THERMAL
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select MX6QDL
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select OF_CONTROL
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select PINCTRL
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select SPL
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select SPL_DM if SPL
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select SPL_GPIO_SUPPORT if SPL
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select SPL_LIBCOMMON_SUPPORT if SPL
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select SPL_LIBDISK_SUPPORT if SPL
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select SPL_LIBGENERIC_SUPPORT if SPL
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select SPL_MMC_SUPPORT if SPL
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select SPL_OF_CONTROL if SPL
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select SPL_OF_LIBFDT if SPL
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select SPL_PINCTRL if SPL
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select SPL_SEPARATE_BSS if SPL
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select SPL_SERIAL_SUPPORT if SPL
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select SPL_USB_GADGET if SPL
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select SPL_USB_HOST_SUPPORT if SPL
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select SPL_USB_SDP_SUPPORT if SPL
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select SPL_WATCHDOG_SUPPORT if SPL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_MX6Q_ENGICAM
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bool "Support Engicam i.Core(RQS)"
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select BOARD_LATE_INIT
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_I2C
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select DM_MMC
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select DM_THERMAL
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select MX6QDL
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select OF_CONTROL
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select SPL_DM if SPL
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select SPL_OF_CONTROL if SPL
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select SPL_OF_LIBFDT
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select SPL_PINCTRL if SPL
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select SPL_SEPARATE_BSS if SPL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_MX6SABREAUTO
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bool "mx6sabreauto"
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6QDL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_MX6SABRESD
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bool "mx6sabresd"
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6QDL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_MX6SLEVK
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bool "mx6slevk"
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select MX6SL
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select SUPPORT_SPL
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config TARGET_MX6SLLEVK
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bool "mx6sll evk"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6SLL
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imply CMD_DM
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config TARGET_MX6SXSABRESD
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bool "mx6sxsabresd"
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6SX
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select SUPPORT_SPL
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config TARGET_MX6SXSABREAUTO
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bool "mx6sxsabreauto"
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6SX
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imply CMD_DM
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config TARGET_MX6UL_9X9_EVK
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bool "mx6ul_9x9_evk"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6UL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_MX6UL_14X14_EVK
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bool "mx6ul_14x14_evk"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6UL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_MX6UL_ENGICAM
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bool "Support Engicam GEAM6UL/Is.IoT"
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select BOARD_LATE_INIT
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_I2C
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select DM_MMC
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select DM_THERMAL
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select MX6UL
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select OF_CONTROL
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select SPL_DM if SPL
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select SPL_OF_CONTROL if SPL
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select SPL_PINCTRL if SPL
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select SPL_SEPARATE_BSS if SPL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_MX6ULL_14X14_EVK
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bool "Support mx6ull_14x14_evk"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX6ULL
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imply CMD_DM
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config TARGET_NITROGEN6X
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bool "nitrogen6x"
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imply USB_ETHER_ASIX
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imply USB_ETHER_MCS7830
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imply USB_ETHER_SMSC95XX
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imply USB_HOST_ETHER
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select MX6QDL
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config TARGET_OPOS6ULDEV
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bool "Armadeus OPOS6ULDev board"
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select MX6UL_OPOS6UL
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config TARGET_OT1200
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bool "Bachmann OT1200"
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select SUPPORT_SPL
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imply CMD_SATA
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||||
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config TARGET_PICO_IMX6
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bool "PICO-IMX6"
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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||||
select DM
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select DM_THERMAL
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select MX6QDL
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_PICO_IMX6UL
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bool "PICO-IMX6UL-EMMC"
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select MX6UL
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||||
select DM
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||||
select SUPPORT_SPL
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||||
imply CMD_DM
|
||||
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config TARGET_LITEBOARD
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||||
bool "Grinn liteBoard (i.MX6UL)"
|
||||
select BOARD_LATE_INIT
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select MX6UL_LITESOM
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||||
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config TARGET_PLATINUM_PICON
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bool "platinum-picon"
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select SUPPORT_SPL
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config TARGET_PLATINUM_TITANIUM
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bool "platinum-titanium"
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select SUPPORT_SPL
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||||
config TARGET_PCM058
|
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bool "Phytec PCM058 i.MX6 Quad"
|
||||
select BOARD_LATE_INIT
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||||
select SUPPORT_SPL
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||||
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config TARGET_PFLA02
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||||
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
|
||||
select BOARD_LATE_INIT
|
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select MX6QDL
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_PCL063
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bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
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select MX6UL
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||||
select DM
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select DM_ETH
|
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select DM_GPIO
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||||
select DM_I2C
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select DM_MMC
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select DM_SERIAL
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select DM_THERMAL
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select SUPPORT_SPL
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config TARGET_PCL063_ULL
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bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)"
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select MX6ULL
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_I2C
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||||
select DM_MMC
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select DM_SERIAL
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||||
select DM_THERMAL
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||||
select SUPPORT_SPL
|
||||
|
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config TARGET_SECOMX6
|
||||
bool "secomx6 boards"
|
||||
|
||||
config TARGET_SKSIMX6
|
||||
bool "sks-imx6"
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_TBS2910
|
||||
bool "TBS2910 Matrix ARM mini PC"
|
||||
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config TARGET_TITANIUM
|
||||
bool "titanium"
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config TARGET_KP_IMX6Q_TPC
|
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bool "K+P KP_IMX6Q_TPC i.MX6 Quad"
|
||||
select BOARD_EARLY_INIT_F
|
||||
select BOARD_LATE_INIT
|
||||
select DM
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||||
select SPL_DM if SPL
|
||||
select DM_THERMAL
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||||
select DM_MMC
|
||||
select DM_ETH
|
||||
select DM_REGULATOR
|
||||
select SPL_DM_REGULATOR if SPL
|
||||
select DM_SERIAL
|
||||
select DM_I2C
|
||||
select DM_GPIO
|
||||
select DM_USB
|
||||
select MX6QDL
|
||||
select SUPPORT_SPL
|
||||
select SPL_SEPARATE_BSS if SPL
|
||||
imply CMD_DM
|
||||
imply CMD_SPL
|
||||
|
||||
config TARGET_TQMA6
|
||||
bool "TQ Systems TQMa6 board"
|
||||
select BOARD_LATE_INIT
|
||||
|
||||
config TARGET_UDOO
|
||||
bool "udoo"
|
||||
select BOARD_LATE_INIT
|
||||
select MX6QDL
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_UDOO_NEO
|
||||
bool "UDOO Neo"
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select MX6SX
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_SOFTING_VINING_2000
|
||||
bool "Softing VIN|ING 2000"
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select MX6SX
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_WANDBOARD
|
||||
bool "wandboard"
|
||||
select BOARD_LATE_INIT
|
||||
select MX6QDL
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_WARP
|
||||
bool "WaRP"
|
||||
select BOARD_LATE_INIT
|
||||
select MX6SL
|
||||
|
||||
config TARGET_XPRESS
|
||||
bool "CCV xPress"
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select MX6UL
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_ZC5202
|
||||
bool "zc5202"
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_ZC5601
|
||||
bool "zc5601"
|
||||
select BOARD_LATE_INIT
|
||||
select DM
|
||||
select DM_THERMAL
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_BRPPT2
|
||||
bool "brppt2"
|
||||
select BOARD_LATE_INIT
|
||||
select MX6QDL
|
||||
select OF_CONTROL
|
||||
select SPL_OF_LIBFDT
|
||||
select DM
|
||||
select DM_ETH
|
||||
select DM_GPIO
|
||||
select DM_I2C
|
||||
select DM_MMC
|
||||
select SUPPORT_SPL
|
||||
select SPL_DM if SPL
|
||||
select SPL_OF_CONTROL if SPL
|
||||
help
|
||||
Support
|
||||
B&R BRPPT2 platform
|
||||
based on Freescale's iMX6 SoC
|
||||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
default "mx6"
|
||||
|
||||
source "board/ge/bx50v3/Kconfig"
|
||||
source "board/advantech/dms-ba16/Kconfig"
|
||||
source "board/aristainetos/Kconfig"
|
||||
source "board/armadeus/opos6uldev/Kconfig"
|
||||
source "board/bachmann/ot1200/Kconfig"
|
||||
source "board/barco/platinum/Kconfig"
|
||||
source "board/barco/titanium/Kconfig"
|
||||
source "board/boundary/nitrogen6x/Kconfig"
|
||||
source "board/bticino/mamoj/Kconfig"
|
||||
source "board/ccv/xpress/Kconfig"
|
||||
source "board/compulab/cm_fx6/Kconfig"
|
||||
source "board/congatec/cgtqmx6eval/Kconfig"
|
||||
source "board/dhelectronics/dh_imx6/Kconfig"
|
||||
source "board/el/el6x/Kconfig"
|
||||
source "board/embest/mx6boards/Kconfig"
|
||||
source "board/engicam/imx6q/Kconfig"
|
||||
source "board/engicam/imx6ul/Kconfig"
|
||||
source "board/freescale/mx6qarm2/Kconfig"
|
||||
source "board/freescale/mx6memcal/Kconfig"
|
||||
source "board/freescale/mx6sabreauto/Kconfig"
|
||||
source "board/freescale/mx6sabresd/Kconfig"
|
||||
source "board/freescale/mx6slevk/Kconfig"
|
||||
source "board/freescale/mx6sllevk/Kconfig"
|
||||
source "board/freescale/mx6sxsabresd/Kconfig"
|
||||
source "board/freescale/mx6sxsabreauto/Kconfig"
|
||||
source "board/freescale/mx6ul_14x14_evk/Kconfig"
|
||||
source "board/freescale/mx6ullevk/Kconfig"
|
||||
source "board/grinn/liteboard/Kconfig"
|
||||
source "board/phytec/pcm058/Kconfig"
|
||||
source "board/phytec/pfla02/Kconfig"
|
||||
source "board/phytec/pcl063/Kconfig"
|
||||
source "board/gateworks/gw_ventana/Kconfig"
|
||||
source "board/kosagi/novena/Kconfig"
|
||||
source "board/softing/vining_2000/Kconfig"
|
||||
source "board/liebherr/display5/Kconfig"
|
||||
source "board/liebherr/mccmon6/Kconfig"
|
||||
source "board/logicpd/imx6/Kconfig"
|
||||
source "board/seco/Kconfig"
|
||||
source "board/sks-kinkel/sksimx6/Kconfig"
|
||||
source "board/solidrun/mx6cuboxi/Kconfig"
|
||||
source "board/technexion/pico-imx6/Kconfig"
|
||||
source "board/technexion/pico-imx6ul/Kconfig"
|
||||
source "board/tbs/tbs2910/Kconfig"
|
||||
source "board/tqc/tqma6/Kconfig"
|
||||
source "board/toradex/apalis_imx6/Kconfig"
|
||||
source "board/toradex/colibri_imx6/Kconfig"
|
||||
source "board/toradex/colibri-imx6ull/Kconfig"
|
||||
source "board/k+p/kp_imx6q_tpc/Kconfig"
|
||||
source "board/udoo/Kconfig"
|
||||
source "board/udoo/neo/Kconfig"
|
||||
source "board/wandboard/Kconfig"
|
||||
source "board/warp/Kconfig"
|
||||
source "board/BuR/brppt2/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,12 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2011 Freescale Semiconductor, Inc.
|
||||
|
||||
obj-y := soc.o clock.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr.o
|
||||
obj-$(CONFIG_MP) += mp.o
|
||||
obj-$(CONFIG_MX6UL_LITESOM) += litesom.o
|
||||
obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,199 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2016 Grinn
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/mx6ul_pins.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <mmc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = imx_ddr_size();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const emmc_pads[] = {
|
||||
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/* RST_B */
|
||||
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
|
||||
|
||||
#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
|
||||
|
||||
int litesom_mmc_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* eMMC */
|
||||
imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads));
|
||||
gpio_direction_output(EMMC_PWR_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(EMMC_PWR_GPIO, 1);
|
||||
emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &emmc_cfg);
|
||||
if (ret) {
|
||||
printf("Warning: failed to initialize mmc dev 1 (eMMC)\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <linux/libfdt.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
|
||||
|
||||
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_addds = 0x00000030,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_ctlds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_ddr_type = 0x000c0000,
|
||||
};
|
||||
|
||||
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
|
||||
.dram_dqm0 = 0x00000030,
|
||||
.dram_dqm1 = 0x00000030,
|
||||
.dram_ras = 0x00000030,
|
||||
.dram_cas = 0x00000030,
|
||||
.dram_odt0 = 0x00000030,
|
||||
.dram_odt1 = 0x00000030,
|
||||
.dram_sdba2 = 0x00000000,
|
||||
.dram_sdclk_0 = 0x00000030,
|
||||
.dram_sdqs0 = 0x00000030,
|
||||
.dram_sdqs1 = 0x00000030,
|
||||
.dram_reset = 0x00000030,
|
||||
};
|
||||
|
||||
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpwldectrl0 = 0x00000000,
|
||||
.p0_mpdgctrl0 = 0x41570155,
|
||||
.p0_mprddlctl = 0x4040474A,
|
||||
.p0_mpwrdlctl = 0x40405550,
|
||||
};
|
||||
|
||||
struct mx6_ddr_sysinfo ddr_sysinfo = {
|
||||
.dsize = 0,
|
||||
.cs_density = 20,
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 2,
|
||||
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
|
||||
.walat = 0, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
.ddr_type = DDR_TYPE_DDR3,
|
||||
.refsel = 0, /* Refresh cycles at 64KHz */
|
||||
.refr = 1, /* 2 refresh commands per refresh cycle */
|
||||
};
|
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = {
|
||||
.mem_speed = 800,
|
||||
.density = 4,
|
||||
.width = 16,
|
||||
.banks = 8,
|
||||
.rowaddr = 15,
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1375,
|
||||
.trcmin = 4875,
|
||||
.trasmin = 3500,
|
||||
};
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0xFFFFFFFF, &ccm->CCGR0);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR1);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR2);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR3);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR4);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR5);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR6);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR7);
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
unsigned long ram_size;
|
||||
|
||||
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
|
||||
/*
|
||||
* Get actual RAM size, so we can adjust DDR row size for <512M
|
||||
* memories
|
||||
*/
|
||||
ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
|
||||
if (ram_size < SZ_512M) {
|
||||
mem_ddr.rowaddr = 14;
|
||||
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
}
|
||||
}
|
||||
|
||||
void litesom_init_f(void)
|
||||
{
|
||||
ccgr_init();
|
||||
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
board_early_init_f();
|
||||
#endif
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,87 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2014
|
||||
* Gabriel Huau <contact@huau-gabriel.fr>
|
||||
*
|
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define MAX_CPUS 4
|
||||
static struct src *src = (struct src *)SRC_BASE_ADDR;
|
||||
|
||||
static uint32_t cpu_reset_mask[MAX_CPUS] = {
|
||||
0, /* We don't really want to modify the cpu0 */
|
||||
SRC_SCR_CORE_1_RESET_MASK,
|
||||
SRC_SCR_CORE_2_RESET_MASK,
|
||||
SRC_SCR_CORE_3_RESET_MASK
|
||||
};
|
||||
|
||||
static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
|
||||
0, /* We don't really want to modify the cpu0 */
|
||||
SRC_SCR_CORE_1_ENABLE_MASK,
|
||||
SRC_SCR_CORE_2_ENABLE_MASK,
|
||||
SRC_SCR_CORE_3_ENABLE_MASK
|
||||
};
|
||||
|
||||
int cpu_reset(u32 nr)
|
||||
{
|
||||
/* Software reset of the CPU N */
|
||||
src->scr |= cpu_reset_mask[nr];
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cpu_status(u32 nr)
|
||||
{
|
||||
printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cpu_release(u32 nr, int argc, char *const argv[])
|
||||
{
|
||||
uint32_t boot_addr;
|
||||
|
||||
boot_addr = simple_strtoul(argv[0], NULL, 16);
|
||||
|
||||
switch (nr) {
|
||||
case 1:
|
||||
src->gpr3 = boot_addr;
|
||||
break;
|
||||
case 2:
|
||||
src->gpr5 = boot_addr;
|
||||
break;
|
||||
case 3:
|
||||
src->gpr7 = boot_addr;
|
||||
break;
|
||||
default:
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* CPU N is ready to start */
|
||||
src->scr |= cpu_ctrl_mask[nr];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int is_core_valid(unsigned int core)
|
||||
{
|
||||
uint32_t nr_cores = get_nr_cpus();
|
||||
|
||||
if (core > nr_cores)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int cpu_disable(u32 nr)
|
||||
{
|
||||
/* Disable the CPU N */
|
||||
src->scr &= ~cpu_ctrl_mask[nr];
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,212 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Armadeus Systems
|
||||
*/
|
||||
|
||||
#include <init.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
#include <miiphy.h>
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
|
||||
/* Use 50M anatop loopback REF_CLK1 for ENET1,
|
||||
* clear gpr1[13], set gpr1[17] */
|
||||
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
|
||||
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
|
||||
|
||||
return enable_fec_anatop_clock(0, ENET_50MHZ);
|
||||
}
|
||||
#endif /* CONFIG_FEC_MXC */
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __weak opos6ul_board_late_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
struct src *psrc = (struct src *)SRC_BASE_ADDR;
|
||||
unsigned reg = readl(&psrc->sbmr2);
|
||||
|
||||
/* In bootstrap don't use the env vars */
|
||||
if (((reg & 0x3000000) >> 24) == 0x1) {
|
||||
env_set_default(NULL, 0);
|
||||
env_set("preboot", "");
|
||||
}
|
||||
|
||||
return opos6ul_board_late_init();
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = imx_ddr_size();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <spl.h>
|
||||
|
||||
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_addds = 0x00000030,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_ctlds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_ddr_type = 0x000c0000,
|
||||
};
|
||||
|
||||
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
|
||||
.dram_dqm0 = 0x00000030,
|
||||
.dram_dqm1 = 0x00000030,
|
||||
.dram_ras = 0x00000030,
|
||||
.dram_cas = 0x00000030,
|
||||
.dram_odt0 = 0x00000030,
|
||||
.dram_odt1 = 0x00000030,
|
||||
.dram_sdba2 = 0x00000000,
|
||||
.dram_sdclk_0 = 0x00000008,
|
||||
.dram_sdqs0 = 0x00000038,
|
||||
.dram_sdqs1 = 0x00000030,
|
||||
.dram_reset = 0x00000030,
|
||||
};
|
||||
|
||||
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpwldectrl0 = 0x00070007,
|
||||
.p0_mpdgctrl0 = 0x41490145,
|
||||
.p0_mprddlctl = 0x40404546,
|
||||
.p0_mpwrdlctl = 0x4040524D,
|
||||
};
|
||||
|
||||
struct mx6_ddr_sysinfo ddr_sysinfo = {
|
||||
.dsize = 0,
|
||||
.cs_density = 20,
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 2,
|
||||
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
.ddr_type = DDR_TYPE_DDR3,
|
||||
.refsel = 1, /* Refresh cycles at 32KHz */
|
||||
.refr = 7, /* 8 refreshes commands per refresh cycle */
|
||||
};
|
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = {
|
||||
.mem_speed = 800,
|
||||
.density = 2,
|
||||
.width = 16,
|
||||
.banks = 8,
|
||||
.rowaddr = 14,
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1500,
|
||||
.trcmin = 5250,
|
||||
.trasmin = 3750,
|
||||
};
|
||||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
unsigned int bmode = readl(&src_base->sbmr2);
|
||||
|
||||
if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
|
||||
spl_boot_list[0] = BOOT_DEVICE_UART;
|
||||
else
|
||||
spl_boot_list[0] = spl_boot_device();
|
||||
}
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0xFFFFFFFF, &ccm->CCGR0);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR1);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR2);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR3);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR4);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR5);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR6);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR7);
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[4];
|
||||
struct fuse_bank4_regs *fuse =
|
||||
(struct fuse_bank4_regs *)bank->fuse_regs;
|
||||
int reg = readl(&fuse->gp1);
|
||||
|
||||
/* 512MB of RAM */
|
||||
if (reg & 0x1) {
|
||||
mem_ddr.density = 4;
|
||||
mem_ddr.rowaddr = 15;
|
||||
mem_ddr.trcd = 1375;
|
||||
mem_ddr.trcmin = 4875;
|
||||
mem_ddr.trasmin = 3500;
|
||||
}
|
||||
|
||||
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
preloader_console_init();
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
ccgr_init();
|
||||
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
}
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
@@ -0,0 +1,721 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2007
|
||||
* Sascha Hauer, Pengutronix
|
||||
*
|
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/bootm.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/dma.h>
|
||||
#include <asm/mach-imx/hab.h>
|
||||
#include <stdbool.h>
|
||||
#include <asm/arch/mxc_hdmi.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <dm.h>
|
||||
#include <imx_thermal.h>
|
||||
#include <mmc.h>
|
||||
|
||||
struct scu_regs {
|
||||
u32 ctrl;
|
||||
u32 config;
|
||||
u32 status;
|
||||
u32 invalidate;
|
||||
u32 fpga_rev;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_IMX_THERMAL)
|
||||
static const struct imx_thermal_plat imx6_thermal_plat = {
|
||||
.regs = (void *)ANATOP_BASE_ADDR,
|
||||
.fuse_bank = 1,
|
||||
.fuse_word = 6,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(imx6_thermal) = {
|
||||
.name = "imx_thermal",
|
||||
.platdata = &imx6_thermal_plat,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_IMX_HAB)
|
||||
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
|
||||
.bank = 0,
|
||||
.word = 6,
|
||||
};
|
||||
#endif
|
||||
|
||||
u32 get_nr_cpus(void)
|
||||
{
|
||||
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
|
||||
return readl(&scu->config) & 3;
|
||||
}
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
u32 reg = readl(&anatop->digprog_sololite);
|
||||
u32 type = ((reg >> 16) & 0xff);
|
||||
u32 major, cfg = 0;
|
||||
|
||||
if (type != MXC_CPU_MX6SL) {
|
||||
reg = readl(&anatop->digprog);
|
||||
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
|
||||
cfg = readl(&scu->config) & 3;
|
||||
type = ((reg >> 16) & 0xff);
|
||||
if (type == MXC_CPU_MX6DL) {
|
||||
if (!cfg)
|
||||
type = MXC_CPU_MX6SOLO;
|
||||
}
|
||||
|
||||
if (type == MXC_CPU_MX6Q) {
|
||||
if (cfg == 1)
|
||||
type = MXC_CPU_MX6D;
|
||||
}
|
||||
|
||||
if (type == MXC_CPU_MX6ULL) {
|
||||
if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
|
||||
type = MXC_CPU_MX6ULZ;
|
||||
}
|
||||
}
|
||||
major = ((reg >> 8) & 0xff);
|
||||
if ((major >= 1) &&
|
||||
((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
|
||||
major--;
|
||||
type = MXC_CPU_MX6QP;
|
||||
if (cfg == 1)
|
||||
type = MXC_CPU_MX6DP;
|
||||
}
|
||||
reg &= 0xff; /* mx6 silicon revision */
|
||||
|
||||
/* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
|
||||
if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
|
||||
reg = 0x3;
|
||||
|
||||
return (type << 12) | (reg + (0x10 * (major + 1)));
|
||||
}
|
||||
|
||||
/*
|
||||
* OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
|
||||
* defines a 2-bit SPEED_GRADING
|
||||
*/
|
||||
#define OCOTP_CFG3_SPEED_SHIFT 16
|
||||
#define OCOTP_CFG3_SPEED_800MHZ 0
|
||||
#define OCOTP_CFG3_SPEED_850MHZ 1
|
||||
#define OCOTP_CFG3_SPEED_1GHZ 2
|
||||
#define OCOTP_CFG3_SPEED_1P2GHZ 3
|
||||
|
||||
/*
|
||||
* For i.MX6UL
|
||||
*/
|
||||
#define OCOTP_CFG3_SPEED_528MHZ 1
|
||||
#define OCOTP_CFG3_SPEED_696MHZ 2
|
||||
|
||||
/*
|
||||
* For i.MX6ULL
|
||||
*/
|
||||
#define OCOTP_CFG3_SPEED_792MHZ 2
|
||||
#define OCOTP_CFG3_SPEED_900MHZ 3
|
||||
|
||||
u32 get_cpu_speed_grade_hz(void)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[0];
|
||||
struct fuse_bank0_regs *fuse =
|
||||
(struct fuse_bank0_regs *)bank->fuse_regs;
|
||||
uint32_t val;
|
||||
|
||||
val = readl(&fuse->cfg3);
|
||||
val >>= OCOTP_CFG3_SPEED_SHIFT;
|
||||
val &= 0x3;
|
||||
|
||||
if (is_mx6ul()) {
|
||||
if (val == OCOTP_CFG3_SPEED_528MHZ)
|
||||
return 528000000;
|
||||
else if (val == OCOTP_CFG3_SPEED_696MHZ)
|
||||
return 696000000;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (is_mx6ull()) {
|
||||
if (val == OCOTP_CFG3_SPEED_528MHZ)
|
||||
return 528000000;
|
||||
else if (val == OCOTP_CFG3_SPEED_792MHZ)
|
||||
return 792000000;
|
||||
else if (val == OCOTP_CFG3_SPEED_900MHZ)
|
||||
return 900000000;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (val) {
|
||||
/* Valid for IMX6DQ */
|
||||
case OCOTP_CFG3_SPEED_1P2GHZ:
|
||||
if (is_mx6dq() || is_mx6dqp())
|
||||
return 1200000000;
|
||||
/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
|
||||
case OCOTP_CFG3_SPEED_1GHZ:
|
||||
return 996000000;
|
||||
/* Valid for IMX6DQ */
|
||||
case OCOTP_CFG3_SPEED_850MHZ:
|
||||
if (is_mx6dq() || is_mx6dqp())
|
||||
return 852000000;
|
||||
/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
|
||||
case OCOTP_CFG3_SPEED_800MHZ:
|
||||
return 792000000;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
|
||||
* defines a 2-bit Temperature Grade
|
||||
*
|
||||
* return temperature grade and min/max temperature in Celsius
|
||||
*/
|
||||
#define OCOTP_MEM0_TEMP_SHIFT 6
|
||||
|
||||
u32 get_cpu_temp_grade(int *minc, int *maxc)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[1];
|
||||
struct fuse_bank1_regs *fuse =
|
||||
(struct fuse_bank1_regs *)bank->fuse_regs;
|
||||
uint32_t val;
|
||||
|
||||
val = readl(&fuse->mem0);
|
||||
val >>= OCOTP_MEM0_TEMP_SHIFT;
|
||||
val &= 0x3;
|
||||
|
||||
if (minc && maxc) {
|
||||
if (val == TEMP_AUTOMOTIVE) {
|
||||
*minc = -40;
|
||||
*maxc = 125;
|
||||
} else if (val == TEMP_INDUSTRIAL) {
|
||||
*minc = -40;
|
||||
*maxc = 105;
|
||||
} else if (val == TEMP_EXTCOMMERCIAL) {
|
||||
*minc = -20;
|
||||
*maxc = 105;
|
||||
} else {
|
||||
*minc = 0;
|
||||
*maxc = 95;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_REVISION_TAG
|
||||
u32 __weak get_board_rev(void)
|
||||
{
|
||||
u32 cpurev = get_cpu_rev();
|
||||
u32 type = ((cpurev >> 12) & 0xff);
|
||||
if (type == MXC_CPU_MX6SOLO)
|
||||
cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
|
||||
|
||||
if (type == MXC_CPU_MX6D)
|
||||
cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
|
||||
|
||||
return cpurev;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void clear_ldo_ramp(void)
|
||||
{
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
int reg;
|
||||
|
||||
/* ROM may modify LDO ramp up time according to fuse setting, so in
|
||||
* order to be in the safe side we neeed to reset these settings to
|
||||
* match the reset value: 0'b00
|
||||
*/
|
||||
reg = readl(&anatop->ana_misc2);
|
||||
reg &= ~(0x3f << 24);
|
||||
writel(reg, &anatop->ana_misc2);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the PMU_REG_CORE register
|
||||
*
|
||||
* Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
|
||||
* Possible values are from 0.725V to 1.450V in steps of
|
||||
* 0.025V (25mV).
|
||||
*/
|
||||
int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
|
||||
{
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
u32 val, step, old, reg = readl(&anatop->reg_core);
|
||||
u8 shift;
|
||||
|
||||
/* No LDO_SOC/PU/ARM */
|
||||
if (is_mx6sll())
|
||||
return 0;
|
||||
|
||||
if (mv < 725)
|
||||
val = 0x00; /* Power gated off */
|
||||
else if (mv > 1450)
|
||||
val = 0x1F; /* Power FET switched full on. No regulation */
|
||||
else
|
||||
val = (mv - 700) / 25;
|
||||
|
||||
clear_ldo_ramp();
|
||||
|
||||
switch (ldo) {
|
||||
case LDO_SOC:
|
||||
shift = 18;
|
||||
break;
|
||||
case LDO_PU:
|
||||
shift = 9;
|
||||
break;
|
||||
case LDO_ARM:
|
||||
shift = 0;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
old = (reg & (0x1F << shift)) >> shift;
|
||||
step = abs(val - old);
|
||||
if (step == 0)
|
||||
return 0;
|
||||
|
||||
reg = (reg & ~(0x1F << shift)) | (val << shift);
|
||||
writel(reg, &anatop->reg_core);
|
||||
|
||||
/*
|
||||
* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
|
||||
* step
|
||||
*/
|
||||
udelay(3 * step);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void set_ahb_rate(u32 val)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
u32 reg, div;
|
||||
|
||||
div = get_periph_clk() / val - 1;
|
||||
reg = readl(&mxc_ccm->cbcdr);
|
||||
|
||||
writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
|
||||
(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
|
||||
}
|
||||
|
||||
static void clear_mmdc_ch_mask(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
u32 reg;
|
||||
reg = readl(&mxc_ccm->ccdr);
|
||||
|
||||
/* Clear MMDC channel mask */
|
||||
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
|
||||
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
|
||||
else
|
||||
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
|
||||
writel(reg, &mxc_ccm->ccdr);
|
||||
}
|
||||
|
||||
#define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
|
||||
|
||||
static void init_bandgap(void)
|
||||
{
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[1];
|
||||
struct fuse_bank1_regs *fuse =
|
||||
(struct fuse_bank1_regs *)bank->fuse_regs;
|
||||
uint32_t val;
|
||||
|
||||
/*
|
||||
* Ensure the bandgap has stabilized.
|
||||
*/
|
||||
while (!(readl(&anatop->ana_misc0) & 0x80))
|
||||
;
|
||||
/*
|
||||
* For best noise performance of the analog blocks using the
|
||||
* outputs of the bandgap, the reftop_selfbiasoff bit should
|
||||
* be set.
|
||||
*/
|
||||
writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
|
||||
/*
|
||||
* On i.MX6ULL,we need to set VBGADJ bits according to the
|
||||
* REFTOP_TRIM[3:0] in fuse table
|
||||
* 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
|
||||
* 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
|
||||
* 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
|
||||
* 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
|
||||
* 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
|
||||
* 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
|
||||
* 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
|
||||
* 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
|
||||
*/
|
||||
if (is_mx6ull()) {
|
||||
val = readl(&fuse->mem0);
|
||||
val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
|
||||
val &= 0x7;
|
||||
|
||||
writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
|
||||
&anatop->ana_misc0_set);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
|
||||
static void noc_setup(void)
|
||||
{
|
||||
enable_ipu_clock();
|
||||
|
||||
writel(0x80000201, 0xbb0608);
|
||||
/* Bypass IPU1 QoS generator */
|
||||
writel(0x00000002, 0x00bb048c);
|
||||
/* Bypass IPU2 QoS generator */
|
||||
writel(0x00000002, 0x00bb050c);
|
||||
/* Bandwidth THR for of PRE0 */
|
||||
writel(0x00000200, 0x00bb0690);
|
||||
/* Bandwidth THR for of PRE1 */
|
||||
writel(0x00000200, 0x00bb0710);
|
||||
/* Bandwidth THR for of PRE2 */
|
||||
writel(0x00000200, 0x00bb0790);
|
||||
/* Bandwidth THR for of PRE3 */
|
||||
writel(0x00000200, 0x00bb0810);
|
||||
/* Saturation THR for of PRE0 */
|
||||
writel(0x00000010, 0x00bb0694);
|
||||
/* Saturation THR for of PRE1 */
|
||||
writel(0x00000010, 0x00bb0714);
|
||||
/* Saturation THR for of PRE2 */
|
||||
writel(0x00000010, 0x00bb0794);
|
||||
/* Saturation THR for of PRE */
|
||||
writel(0x00000010, 0x00bb0814);
|
||||
|
||||
disable_ipu_clock();
|
||||
}
|
||||
#endif
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
init_aips();
|
||||
|
||||
/* Need to clear MMDC_CHx_MASK to make warm reset work. */
|
||||
clear_mmdc_ch_mask();
|
||||
|
||||
/*
|
||||
* Disable self-bias circuit in the analog bandap.
|
||||
* The self-bias circuit is used by the bandgap during startup.
|
||||
* This bit should be set after the bandgap has initialized.
|
||||
*/
|
||||
init_bandgap();
|
||||
|
||||
if (!is_mx6ul() && !is_mx6ull()) {
|
||||
/*
|
||||
* When low freq boot is enabled, ROM will not set AHB
|
||||
* freq, so we need to ensure AHB freq is 132MHz in such
|
||||
* scenario.
|
||||
*
|
||||
* To i.MX6UL, when power up, default ARM core and
|
||||
* AHB rate is 396M and 132M.
|
||||
*/
|
||||
if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
|
||||
set_ahb_rate(132000000);
|
||||
}
|
||||
|
||||
if (is_mx6ul()) {
|
||||
if (is_soc_rev(CHIP_REV_1_0) == 0) {
|
||||
/*
|
||||
* According to the design team's requirement on
|
||||
* i.MX6UL,the PMIC_STBY_REQ PAD should be configured
|
||||
* as open drain 100K (0x0000b8a0).
|
||||
* Only exists on TO1.0
|
||||
*/
|
||||
writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
|
||||
} else {
|
||||
/*
|
||||
* From TO1.1, SNVS adds internal pull up control
|
||||
* for POR_B, the register filed is GPBIT[1:0],
|
||||
* after system boot up, it can be set to 2b'01
|
||||
* to disable internal pull up.It can save about
|
||||
* 30uA power in SNVS mode.
|
||||
*/
|
||||
writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
|
||||
(~0x1400)) | 0x400,
|
||||
MX6UL_SNVS_LP_BASE_ADDR + 0x10);
|
||||
}
|
||||
}
|
||||
|
||||
if (is_mx6ull()) {
|
||||
/*
|
||||
* GPBIT[1:0] is suggested to set to 2'b11:
|
||||
* 2'b00 : always PUP100K
|
||||
* 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
|
||||
* 2'b10 : always disable PUP100K
|
||||
* 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
|
||||
* register offset is different from i.MX6UL, since
|
||||
* i.MX6UL is fixed by ECO.
|
||||
*/
|
||||
writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
|
||||
0x3, MX6UL_SNVS_LP_BASE_ADDR);
|
||||
}
|
||||
|
||||
/* Set perclk to source from OSC 24MHz */
|
||||
if (is_mx6sl())
|
||||
setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
|
||||
|
||||
imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
|
||||
|
||||
if (is_mx6sx())
|
||||
setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
|
||||
|
||||
init_src();
|
||||
|
||||
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
|
||||
if (is_mx6dqp())
|
||||
noc_setup();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
__weak int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return CONFIG_SYS_MMC_ENV_DEV;
|
||||
}
|
||||
|
||||
static int mmc_get_boot_dev(void)
|
||||
{
|
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
||||
u32 soc_sbmr = readl(&src_regs->sbmr1);
|
||||
u32 bootsel;
|
||||
int devno;
|
||||
|
||||
/*
|
||||
* Refer to
|
||||
* "i.MX 6Dual/6Quad Applications Processor Reference Manual"
|
||||
* Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
|
||||
* i.MX6SL/SX/UL has same layout.
|
||||
*/
|
||||
bootsel = (soc_sbmr & 0x000000FF) >> 6;
|
||||
|
||||
/* No boot from sd/mmc */
|
||||
if (bootsel != 1)
|
||||
return -1;
|
||||
|
||||
/* BOOT_CFG2[3] and BOOT_CFG2[4] */
|
||||
devno = (soc_sbmr & 0x00001800) >> 11;
|
||||
|
||||
return devno;
|
||||
}
|
||||
|
||||
int mmc_get_env_dev(void)
|
||||
{
|
||||
int devno = mmc_get_boot_dev();
|
||||
|
||||
/* If not boot from sd/mmc, use default value */
|
||||
if (devno < 0)
|
||||
return CONFIG_SYS_MMC_ENV_DEV;
|
||||
|
||||
return board_mmc_get_env_dev(devno);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_MMC_ENV_PART
|
||||
__weak int board_mmc_get_env_part(int devno)
|
||||
{
|
||||
return CONFIG_SYS_MMC_ENV_PART;
|
||||
}
|
||||
|
||||
uint mmc_get_env_part(struct mmc *mmc)
|
||||
{
|
||||
int devno = mmc_get_boot_dev();
|
||||
|
||||
/* If not boot from sd/mmc, use default value */
|
||||
if (devno < 0)
|
||||
return CONFIG_SYS_MMC_ENV_PART;
|
||||
|
||||
return board_mmc_get_env_part(devno);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int board_postclk_init(void)
|
||||
{
|
||||
/* NO LDO SOC on i.MX6SLL */
|
||||
if (is_mx6sll())
|
||||
return 0;
|
||||
|
||||
set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/*
|
||||
* cfg_val will be used for
|
||||
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
|
||||
* After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
|
||||
* instead of SBMR1 to determine the boot device.
|
||||
*/
|
||||
const struct boot_mode soc_boot_modes[] = {
|
||||
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
|
||||
/* reserved value should start rom usb */
|
||||
#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
|
||||
{"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
|
||||
#else
|
||||
{"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
|
||||
#endif
|
||||
{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
|
||||
{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
|
||||
{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
|
||||
{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
|
||||
{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
|
||||
/* 4 bit bus width */
|
||||
{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
|
||||
{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
||||
{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
void reset_misc(void)
|
||||
{
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
|
||||
lcdif_power_down();
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
u32 mask480;
|
||||
u32 mask528;
|
||||
u32 reg, periph1, periph2;
|
||||
|
||||
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
|
||||
return;
|
||||
|
||||
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
|
||||
* to make sure PFD is working right, otherwise, PFDs may
|
||||
* not output clock after reset, MX6DL and MX6SL have added 396M pfd
|
||||
* workaround in ROM code, as bus clock need it
|
||||
*/
|
||||
|
||||
mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
|
||||
ANATOP_PFD_CLKGATE_MASK(1) |
|
||||
ANATOP_PFD_CLKGATE_MASK(2) |
|
||||
ANATOP_PFD_CLKGATE_MASK(3);
|
||||
mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
|
||||
ANATOP_PFD_CLKGATE_MASK(3);
|
||||
|
||||
reg = readl(&ccm->cbcmr);
|
||||
periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
|
||||
>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
|
||||
periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
|
||||
>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
|
||||
|
||||
/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
|
||||
if ((periph2 != 0x2) && (periph1 != 0x2))
|
||||
mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
|
||||
|
||||
if ((periph2 != 0x1) && (periph1 != 0x1) &&
|
||||
(periph2 != 0x3) && (periph1 != 0x3))
|
||||
mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
|
||||
|
||||
writel(mask480, &anatop->pfd_480_set);
|
||||
writel(mask528, &anatop->pfd_528_set);
|
||||
writel(mask480, &anatop->pfd_480_clr);
|
||||
writel(mask528, &anatop->pfd_528_clr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IMX_HDMI
|
||||
void imx_enable_hdmi_phy(void)
|
||||
{
|
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
|
||||
u8 reg;
|
||||
reg = readb(&hdmi->phy_conf0);
|
||||
reg |= HDMI_PHY_CONF0_PDZ_MASK;
|
||||
writeb(reg, &hdmi->phy_conf0);
|
||||
udelay(3000);
|
||||
reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
|
||||
writeb(reg, &hdmi->phy_conf0);
|
||||
udelay(3000);
|
||||
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
|
||||
writeb(reg, &hdmi->phy_conf0);
|
||||
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
|
||||
}
|
||||
|
||||
void imx_setup_hdmi(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
|
||||
int reg, count;
|
||||
u8 val;
|
||||
|
||||
/* Turn on HDMI PHY clock */
|
||||
reg = readl(&mxc_ccm->CCGR2);
|
||||
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
|
||||
MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
|
||||
writel(reg, &mxc_ccm->CCGR2);
|
||||
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
|
||||
reg = readl(&mxc_ccm->chsccdr);
|
||||
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
|
||||
MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
|
||||
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
|
||||
reg |= (CHSCCDR_PODF_DIVIDE_BY_3
|
||||
<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
|
||||
|(CHSCCDR_IPU_PRE_CLK_540M_PFD
|
||||
<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
|
||||
writel(reg, &mxc_ccm->chsccdr);
|
||||
|
||||
/* Clear the overflow condition */
|
||||
if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
|
||||
/* TMDS software reset */
|
||||
writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
|
||||
val = readb(&hdmi->fc_invidconf);
|
||||
/* Need minimum 3 times to write to clear the register */
|
||||
for (count = 0 ; count < 5 ; count++)
|
||||
writeb(val, &hdmi->fc_invidconf);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
|
||||
* MX6Q and MX6QP processors
|
||||
*/
|
||||
void gpr_init(void)
|
||||
{
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
|
||||
/*
|
||||
* If this function is used in a common MX6 spl implementation
|
||||
* we have to ensure that it is only called for suitable cpu types,
|
||||
* otherwise it breaks hardware parts like enet1, can1, can2, etc.
|
||||
*/
|
||||
if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
|
||||
return;
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
writel(0xF00000CF, &iomux->gpr[4]);
|
||||
if (is_mx6dqp()) {
|
||||
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
|
||||
writel(0x77177717, &iomux->gpr[6]);
|
||||
writel(0x77177717, &iomux->gpr[7]);
|
||||
} else {
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
writel(0x007F007F, &iomux->gpr[6]);
|
||||
writel(0x007F007F, &iomux->gpr[7]);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user