GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,84 @@
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if ARCH_MX7
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config MX7
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bool
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default y
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select ARCH_SUPPORT_PSCI
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ROM_UNIFIED_SECTIONS
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select SYSCOUNTER_TIMER
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imply CMD_FUSE
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config MX7D
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bool
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select HAS_CAAM
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select ROM_UNIFIED_SECTIONS
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imply CMD_FUSE
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choice
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prompt "MX7 board select"
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optional
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config TARGET_CL_SOM_IMX7
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bool "CL-SOM-iMX7"
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select DM
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select DM_THERMAL
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select MX7D
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_MEERKAT96
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bool "NovTech Meerkat96 board"
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select BOARD_LATE_INIT
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select DM
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select DM_SERIAL
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select DM_THERMAL
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select MX7D
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imply CMD_DM
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config TARGET_MX7DSABRESD
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bool "mx7dsabresd"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX7D
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imply CMD_DM
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config TARGET_PICO_IMX7D
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bool "pico-imx7d"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX7D
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_WARP7
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bool "warp7"
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select BOARD_LATE_INIT
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select DM
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select DM_THERMAL
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select MX7D
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imply CMD_DM
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config TARGET_COLIBRI_IMX7
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bool "Support Colibri iMX7S/iMX7D modules"
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select DM
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select DM_SERIAL
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select DM_THERMAL
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imply CMD_DM
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endchoice
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config SYS_SOC
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default "mx7"
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source "board/compulab/cl-som-imx7/Kconfig"
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source "board/freescale/mx7dsabresd/Kconfig"
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source "board/novtech/meerkat96/Kconfig"
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source "board/technexion/pico-imx7d/Kconfig"
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source "board/toradex/colibri_imx7/Kconfig"
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source "board/warp7/Kconfig"
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endif
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@@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2015 Freescale Semiconductor, Inc.
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#
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obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o
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obj-$(CONFIG_ARMV7_PSCI) += psci-mx7.o psci-suspend.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,756 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* Author:
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* Peng Fan <Peng.Fan@freescale.com>
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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static struct clk_root_map root_array[] = {
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{ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL,
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{OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK,
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PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK,
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PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
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},
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{ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK,
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PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
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},
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{ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK,
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PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
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},
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{MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK}
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},
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{DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK,
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PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
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},
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{ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK}
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},
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{NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK,
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PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
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},
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{AHB_CLK_ROOT, CCM_AHB_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
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PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
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},
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{DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL,
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{PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT}
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},
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{DRAM_CLK_ROOT, CCM_DRAM_CHANNEL,
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{PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT}
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},
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{DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
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PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK,
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PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
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},
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{DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
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PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK,
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PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK}
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},
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{USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK,
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PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK,
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PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
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},
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{PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK,
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PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK}
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},
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{PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK,
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EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
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EXT_CLK_4, PLL_SYS_PFD0_392M_CLK}
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},
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{EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK,
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PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK}
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},
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{LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK,
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EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
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PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
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},
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{MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK,
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PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
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},
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{MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK,
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PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
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},
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{MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2,
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PLL_VIDEO_MAIN_CLK, EXT_CLK_3}
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},
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{SAI1_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
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PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
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},
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{SAI2_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
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PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
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},
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{SAI3_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
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PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
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},
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{SPDIF_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
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PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
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},
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{ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
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PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
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},
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{ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
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EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
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EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
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},
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{ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
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PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
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},
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{ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
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EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
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EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
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},
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{ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK,
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PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
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PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK}
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},
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{EIM_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
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PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK,
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PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK}
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},
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{NAND_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
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PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK}
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},
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{QSPI_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK,
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PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
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},
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{USDHC1_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
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PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
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},
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{USDHC2_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
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PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
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},
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{USDHC3_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
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PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
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},
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{CAN1_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
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EXT_CLK_1, EXT_CLK_4}
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},
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{CAN2_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
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PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
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EXT_CLK_1, EXT_CLK_3}
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},
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{I2C1_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
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PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
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PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
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},
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{I2C2_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
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PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
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PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
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},
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{I2C3_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
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PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
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PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
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},
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{I2C4_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
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PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
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PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
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},
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{UART1_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
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PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
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EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
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},
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{UART2_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
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PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
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EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
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},
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{UART3_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
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PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
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EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
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},
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{UART4_CLK_ROOT, CCM_IP_CHANNEL,
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{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
|
||||
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
|
||||
EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{UART5_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
|
||||
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
|
||||
EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{UART6_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
|
||||
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
|
||||
EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{UART7_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
|
||||
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
|
||||
EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{ECSPI1_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
|
||||
PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
|
||||
PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{ECSPI2_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
|
||||
PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
|
||||
PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{ECSPI3_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
|
||||
PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
|
||||
PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{ECSPI4_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
|
||||
PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
|
||||
PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{PWM1_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
|
||||
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
|
||||
},
|
||||
{PWM2_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
|
||||
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
|
||||
},
|
||||
{PWM3_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
|
||||
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
|
||||
},
|
||||
{PWM4_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
|
||||
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
|
||||
},
|
||||
{FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
|
||||
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
|
||||
},
|
||||
{FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
|
||||
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
|
||||
},
|
||||
{SIM1_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK,
|
||||
PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
|
||||
},
|
||||
{SIM2_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK,
|
||||
PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
|
||||
},
|
||||
{GPT1_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
|
||||
PLL_AUDIO_MAIN_CLK, EXT_CLK_1}
|
||||
},
|
||||
{GPT2_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
|
||||
PLL_AUDIO_MAIN_CLK, EXT_CLK_2}
|
||||
},
|
||||
{GPT3_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
|
||||
PLL_AUDIO_MAIN_CLK, EXT_CLK_3}
|
||||
},
|
||||
{GPT4_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
|
||||
PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
|
||||
PLL_AUDIO_MAIN_CLK, EXT_CLK_4}
|
||||
},
|
||||
{TRACE_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
|
||||
EXT_CLK_1, EXT_CLK_3}
|
||||
},
|
||||
{WDOG_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
|
||||
REF_1M_CLK, PLL_SYS_PFD1_166M_CLK}
|
||||
},
|
||||
{CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
|
||||
PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
|
||||
PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
|
||||
PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
|
||||
},
|
||||
{WRCLK_CLK_ROOT, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK,
|
||||
PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK,
|
||||
PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK}
|
||||
},
|
||||
{IPP_DO_CLKO1, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK,
|
||||
PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
|
||||
PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK}
|
||||
},
|
||||
{IPP_DO_CLKO2, CCM_IP_CHANNEL,
|
||||
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK,
|
||||
PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK,
|
||||
PLL_VIDEO_MAIN_CLK, OSC_32K_CLK}
|
||||
},
|
||||
};
|
||||
|
||||
/* select which entry of root_array */
|
||||
static int select(enum clk_root_index clock_id)
|
||||
{
|
||||
int i, size;
|
||||
struct clk_root_map *p = root_array;
|
||||
|
||||
size = ARRAY_SIZE(root_array);
|
||||
|
||||
for (i = 0; i < size; i++, p++) {
|
||||
if (clock_id == p->entry)
|
||||
return i;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int src_supported(int entry, enum clk_root_src clock_src)
|
||||
{
|
||||
int i, size;
|
||||
struct clk_root_map *p = &root_array[entry];
|
||||
|
||||
if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL))
|
||||
size = 2;
|
||||
else
|
||||
size = 8;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (p->src_mux[i] == clock_src)
|
||||
return i;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Set src for clock root slice. */
|
||||
int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src)
|
||||
{
|
||||
int root_entry, src_entry;
|
||||
u32 reg;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
src_entry = src_supported(root_entry, clock_src);
|
||||
if (src_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
reg &= ~CLK_ROOT_MUX_MASK;
|
||||
reg |= src_entry << CLK_ROOT_MUX_SHIFT;
|
||||
__raw_writel(reg, &imx_ccm->root[clock_id].target_root);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Get src of a clock root slice. */
|
||||
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
|
||||
{
|
||||
u32 val;
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
val &= CLK_ROOT_MUX_MASK;
|
||||
val >>= CLK_ROOT_MUX_SHIFT;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
*p_clock_src = p->src_mux[val];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div)
|
||||
{
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
u32 reg;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
|
||||
if ((p->type == CCM_CORE_CHANNEL) ||
|
||||
(p->type == CCM_DRAM_PHYM_CHANNEL) ||
|
||||
(p->type == CCM_DRAM_CHANNEL)) {
|
||||
if (pre_div != CLK_ROOT_PRE_DIV1) {
|
||||
printf("Error pre div!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
reg &= ~CLK_ROOT_PRE_DIV_MASK;
|
||||
reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT;
|
||||
__raw_writel(reg, &imx_ccm->root[clock_id].target_root);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
|
||||
{
|
||||
u32 val;
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
|
||||
if ((p->type == CCM_CORE_CHANNEL) ||
|
||||
(p->type == CCM_DRAM_PHYM_CHANNEL) ||
|
||||
(p->type == CCM_DRAM_CHANNEL)) {
|
||||
*pre_div = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
val &= CLK_ROOT_PRE_DIV_MASK;
|
||||
val >>= CLK_ROOT_PRE_DIV_SHIFT;
|
||||
|
||||
*pre_div = val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
if (clock_id == DRAM_PHYM_CLK_ROOT) {
|
||||
if (div != CLK_ROOT_POST_DIV1) {
|
||||
printf("Error post div!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Only 3 bit post div. */
|
||||
if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) {
|
||||
printf("Error post div!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
reg &= ~CLK_ROOT_POST_DIV_MASK;
|
||||
reg |= div << CLK_ROOT_POST_DIV_SHIFT;
|
||||
__raw_writel(reg, &imx_ccm->root[clock_id].target_root);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
if (clock_id == DRAM_PHYM_CLK_ROOT) {
|
||||
*div = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
if (clock_id == DRAM_CLK_ROOT)
|
||||
val &= DRAM_CLK_ROOT_POST_DIV_MASK;
|
||||
else
|
||||
val &= CLK_ROOT_POST_DIV_MASK;
|
||||
val >>= CLK_ROOT_POST_DIV_SHIFT;
|
||||
|
||||
*div = val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
|
||||
int auto_en)
|
||||
{
|
||||
u32 val;
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
|
||||
if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
|
||||
printf("Auto postdiv not supported.!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Each time only one filed can be changed, no use target_root_set.
|
||||
*/
|
||||
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
val &= ~CLK_ROOT_AUTO_DIV_MASK;
|
||||
val |= (div << CLK_ROOT_AUTO_DIV_SHIFT);
|
||||
|
||||
if (auto_en)
|
||||
val |= CLK_ROOT_AUTO_EN;
|
||||
else
|
||||
val &= ~CLK_ROOT_AUTO_EN;
|
||||
|
||||
__raw_writel(val, &imx_ccm->root[clock_id].target_root);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
|
||||
int *auto_en)
|
||||
{
|
||||
u32 val;
|
||||
int root_entry;
|
||||
struct clk_root_map *p;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
|
||||
/*
|
||||
* Only bus/ahb channel supports auto div.
|
||||
* If unsupported, just set auto_en and div with 0.
|
||||
*/
|
||||
if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
|
||||
*auto_en = 0;
|
||||
*div = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
if ((val & CLK_ROOT_AUTO_EN_MASK) == 0)
|
||||
*auto_en = 0;
|
||||
else
|
||||
*auto_en = 1;
|
||||
|
||||
val &= CLK_ROOT_AUTO_DIV_MASK;
|
||||
val >>= CLK_ROOT_AUTO_DIV_SHIFT;
|
||||
|
||||
*div = val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
|
||||
{
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
*val = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_set_target_val(enum clk_root_index clock_id, u32 val)
|
||||
{
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
__raw_writel(val, &imx_ccm->root[clock_id].target_root);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Auto_div and auto_en is ignored, they are rarely used. */
|
||||
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
|
||||
enum root_post_div post_div, enum clk_root_src clock_src)
|
||||
{
|
||||
u32 val;
|
||||
int root_entry, src_entry;
|
||||
struct clk_root_map *p;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
root_entry = select(clock_id);
|
||||
if (root_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
p = &root_array[root_entry];
|
||||
|
||||
if ((p->type == CCM_CORE_CHANNEL) ||
|
||||
(p->type == CCM_DRAM_PHYM_CHANNEL) ||
|
||||
(p->type == CCM_DRAM_CHANNEL)) {
|
||||
if (pre_div != CLK_ROOT_PRE_DIV1) {
|
||||
printf("Error pre div!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Only 3 bit post div. */
|
||||
if (p->type == CCM_DRAM_CHANNEL) {
|
||||
if (post_div > CLK_ROOT_POST_DIV7) {
|
||||
printf("Error post div!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
if (p->type == CCM_DRAM_PHYM_CHANNEL) {
|
||||
if (post_div != CLK_ROOT_POST_DIV1) {
|
||||
printf("Error post div!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
src_entry = src_supported(root_entry, clock_src);
|
||||
if (src_entry < 0)
|
||||
return -EINVAL;
|
||||
|
||||
val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
|
||||
post_div << CLK_ROOT_POST_DIV_SHIFT |
|
||||
src_entry << CLK_ROOT_MUX_SHIFT;
|
||||
|
||||
__raw_writel(val, &imx_ccm->root[clock_id].target_root);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_root_enabled(enum clk_root_index clock_id)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (clock_id >= CLK_ROOT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* No enable bit for DRAM controller and PHY. Just return enabled.
|
||||
*/
|
||||
if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT))
|
||||
return 1;
|
||||
|
||||
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
|
||||
|
||||
return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0;
|
||||
}
|
||||
|
||||
/* CCGR gate operation */
|
||||
int clock_enable(enum clk_ccgr_index index, bool enable)
|
||||
{
|
||||
if (index >= CCGR_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
if (enable)
|
||||
__raw_writel(CCM_CLK_ON_MSK,
|
||||
&imx_ccm->ccgr_array[index].ccgr_set);
|
||||
else
|
||||
__raw_writel(CCM_CLK_ON_MSK,
|
||||
&imx_ccm->ccgr_array[index].ccgr_clr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,204 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* DDR controller configuration for the i.MX7 architecture
|
||||
*
|
||||
* (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
|
||||
*
|
||||
* Author: Uri Mashiach <uri.mashiach@compulab.co.il>
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/mx7-ddr.h>
|
||||
#include <common.h>
|
||||
|
||||
/*
|
||||
* Routine: mx7_dram_cfg
|
||||
* Description: DDR controller configuration
|
||||
*
|
||||
* @ddrc_regs_val: DDRC registers value
|
||||
* @ddrc_mp_val: DDRC_MP registers value
|
||||
* @ddr_phy_regs_val: DDR_PHY registers value
|
||||
* @calib_param: calibration parameters
|
||||
*
|
||||
*/
|
||||
void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
|
||||
struct ddr_phy *ddr_phy_regs_val,
|
||||
struct mx7_calibration *calib_param)
|
||||
{
|
||||
struct src *const src_regs = (struct src *)SRC_BASE_ADDR;
|
||||
struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
|
||||
struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;
|
||||
struct ddr_phy *const ddr_phy_regs =
|
||||
(struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
int i;
|
||||
|
||||
/* Assert DDR Controller preset and DDR PHY reset */
|
||||
writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr);
|
||||
|
||||
/* DDR controller configuration */
|
||||
writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
|
||||
writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);
|
||||
writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);
|
||||
writel(ddrc_regs_val->init1, &ddrc_regs->init1);
|
||||
writel(ddrc_regs_val->init0, &ddrc_regs->init0);
|
||||
writel(ddrc_regs_val->init3, &ddrc_regs->init3);
|
||||
writel(ddrc_regs_val->init4, &ddrc_regs->init4);
|
||||
writel(ddrc_regs_val->init5, &ddrc_regs->init5);
|
||||
writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);
|
||||
writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);
|
||||
writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);
|
||||
writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);
|
||||
writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);
|
||||
writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);
|
||||
writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
|
||||
writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
|
||||
writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
|
||||
writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
|
||||
writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
|
||||
writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
|
||||
writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);
|
||||
writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);
|
||||
writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);
|
||||
writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);
|
||||
writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);
|
||||
writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);
|
||||
writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);
|
||||
writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
|
||||
writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
|
||||
|
||||
/* De-assert DDR Controller preset and DDR PHY reset */
|
||||
clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
|
||||
|
||||
/* PHY configuration */
|
||||
writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);
|
||||
writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);
|
||||
writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);
|
||||
writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);
|
||||
writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);
|
||||
writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);
|
||||
writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);
|
||||
writel(ddr_phy_regs_val->cmd_sdll_con0 |
|
||||
DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
|
||||
&ddr_phy_regs->cmd_sdll_con0);
|
||||
writel(ddr_phy_regs_val->cmd_sdll_con0 &
|
||||
~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
|
||||
&ddr_phy_regs->cmd_sdll_con0);
|
||||
writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
|
||||
|
||||
/* calibration */
|
||||
for (i = 0; i < calib_param->num_val; i++)
|
||||
writel(calib_param->values[i], &ddr_phy_regs->zq_con0);
|
||||
|
||||
/* Wake_up DDR PHY */
|
||||
HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);
|
||||
writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |
|
||||
IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,
|
||||
&iomuxc_gpr_regs->gpr[8]);
|
||||
HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: imx_ddr_size
|
||||
* Description: extract the current DRAM size from the DDRC registers
|
||||
*
|
||||
* @return: DRAM size
|
||||
*/
|
||||
unsigned int imx_ddr_size(void)
|
||||
{
|
||||
struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
|
||||
u32 reg_val, field_val;
|
||||
int bits = 0;/* Number of address bits */
|
||||
|
||||
/* Count data bus width bits */
|
||||
reg_val = readl(&ddrc_regs->mstr);
|
||||
field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;
|
||||
bits += 2 - field_val;
|
||||
/* Count rank address bits */
|
||||
field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;
|
||||
if (field_val > 1)
|
||||
bits += field_val - 1;
|
||||
/* Count column address bits */
|
||||
bits += 2;/* Column address 0 and 1 are fixed mapped */
|
||||
reg_val = readl(&ddrc_regs->addrmap2);
|
||||
field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
reg_val = readl(&ddrc_regs->addrmap3);
|
||||
field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
reg_val = readl(&ddrc_regs->addrmap4);
|
||||
field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;
|
||||
if (field_val <= 7)
|
||||
bits++;
|
||||
/* Count row address bits */
|
||||
reg_val = readl(&ddrc_regs->addrmap5);
|
||||
field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;
|
||||
if (field_val <= 11)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;
|
||||
if (field_val <= 11)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;
|
||||
if (field_val <= 11)
|
||||
bits += 9;
|
||||
field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;
|
||||
if (field_val <= 11)
|
||||
bits++;
|
||||
reg_val = readl(&ddrc_regs->addrmap6);
|
||||
field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;
|
||||
if (field_val <= 11)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;
|
||||
if (field_val <= 11)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;
|
||||
if (field_val <= 11)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;
|
||||
if (field_val <= 11)
|
||||
bits++;
|
||||
/* Count bank bits */
|
||||
reg_val = readl(&ddrc_regs->addrmap1);
|
||||
field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;
|
||||
if (field_val <= 30)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;
|
||||
if (field_val <= 30)
|
||||
bits++;
|
||||
field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;
|
||||
if (field_val <= 29)
|
||||
bits++;
|
||||
|
||||
/* cap to max 2 GB */
|
||||
if (bits > 31)
|
||||
bits = 31;
|
||||
|
||||
return 1 << bits;
|
||||
}
|
||||
@@ -0,0 +1,689 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
#include <cpu_func.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/psci.h>
|
||||
#include <asm/secure.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/armv7.h>
|
||||
#include <asm/gic.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <common.h>
|
||||
#include <fsl_wdog.h>
|
||||
|
||||
#define GPC_LPCR_A7_BSC 0x0
|
||||
#define GPC_LPCR_A7_AD 0x4
|
||||
#define GPC_SLPCR 0x14
|
||||
#define GPC_PGC_ACK_SEL_A7 0x24
|
||||
#define GPC_IMR1_CORE0 0x30
|
||||
#define GPC_SLOT0_CFG 0xb0
|
||||
#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
|
||||
#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
|
||||
#define GPC_PGC_C0 0x800
|
||||
#define GPC_PGC_C0 0x800
|
||||
#define GPC_PGC_C1 0x840
|
||||
#define GPC_PGC_SCU 0x880
|
||||
|
||||
#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
|
||||
#define BM_LPCR_A7_BSC_LPM1 0xc
|
||||
#define BM_LPCR_A7_BSC_LPM0 0x3
|
||||
#define BP_LPCR_A7_BSC_LPM0 0
|
||||
#define BM_SLPCR_EN_DSM 0x80000000
|
||||
#define BM_SLPCR_RBC_EN 0x40000000
|
||||
#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
|
||||
#define BM_SLPCR_VSTBY 0x4
|
||||
#define BM_SLPCR_SBYOS 0x2
|
||||
#define BM_SLPCR_BYPASS_PMIC_READY 0x1
|
||||
#define BM_LPCR_A7_AD_L2PGE 0x10000
|
||||
#define BM_LPCR_A7_AD_EN_C1_PUP 0x800
|
||||
#define BM_LPCR_A7_AD_EN_C0_PUP 0x200
|
||||
#define BM_LPCR_A7_AD_EN_PLAT_PDN 0x10
|
||||
#define BM_LPCR_A7_AD_EN_C1_PDN 0x8
|
||||
#define BM_LPCR_A7_AD_EN_C0_PDN 0x2
|
||||
|
||||
#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7 0x1
|
||||
#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
|
||||
|
||||
#define BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK 0x8000
|
||||
#define BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK 0x80000000
|
||||
|
||||
#define MAX_SLOT_NUMBER 10
|
||||
#define A7_LPM_WAIT 0x5
|
||||
#define A7_LPM_STOP 0xa
|
||||
|
||||
#define BM_SYS_COUNTER_CNTCR_FCR1 0x200
|
||||
#define BM_SYS_COUNTER_CNTCR_FCR0 0x100
|
||||
|
||||
#define REG_SET 0x4
|
||||
#define REG_CLR 0x8
|
||||
|
||||
#define ANADIG_ARM_PLL 0x60
|
||||
#define ANADIG_DDR_PLL 0x70
|
||||
#define ANADIG_SYS_PLL 0xb0
|
||||
#define ANADIG_ENET_PLL 0xe0
|
||||
#define ANADIG_AUDIO_PLL 0xf0
|
||||
#define ANADIG_VIDEO_PLL 0x130
|
||||
#define BM_ANATOP_ARM_PLL_OVERRIDE BIT(20)
|
||||
#define BM_ANATOP_DDR_PLL_OVERRIDE BIT(19)
|
||||
#define BM_ANATOP_SYS_PLL_OVERRIDE (0x1ff << 17)
|
||||
#define BM_ANATOP_ENET_PLL_OVERRIDE BIT(13)
|
||||
#define BM_ANATOP_AUDIO_PLL_OVERRIDE BIT(24)
|
||||
#define BM_ANATOP_VIDEO_PLL_OVERRIDE BIT(24)
|
||||
|
||||
#define DDRC_STAT 0x4
|
||||
#define DDRC_PWRCTL 0x30
|
||||
#define DDRC_PSTAT 0x3fc
|
||||
|
||||
#define SRC_GPR1_MX7D 0x074
|
||||
#define SRC_GPR2_MX7D 0x078
|
||||
#define SRC_A7RCR0 0x004
|
||||
#define SRC_A7RCR1 0x008
|
||||
|
||||
#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
|
||||
#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
|
||||
|
||||
#define SNVS_LPCR 0x38
|
||||
#define BP_SNVS_LPCR_DP_EN 0x20
|
||||
#define BP_SNVS_LPCR_TOP 0x40
|
||||
|
||||
#define CCM_CCGR_SNVS 0x4250
|
||||
|
||||
#define CCM_ROOT_WDOG 0xbb80
|
||||
#define CCM_CCGR_WDOG1 0x49c0
|
||||
|
||||
#define MPIDR_AFF0 GENMASK(7, 0)
|
||||
|
||||
#define IMX7D_PSCI_NR_CPUS 2
|
||||
#if IMX7D_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
|
||||
#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
|
||||
#endif
|
||||
|
||||
#define imx_cpu_gpr_entry_offset(cpu) \
|
||||
(SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8)
|
||||
#define imx_cpu_gpr_para_offset(cpu) \
|
||||
(imx_cpu_gpr_entry_offset(cpu) + 4)
|
||||
|
||||
#define IMX_CPU_SYNC_OFF ~0
|
||||
#define IMX_CPU_SYNC_ON 0
|
||||
|
||||
u8 psci_state[IMX7D_PSCI_NR_CPUS] __secure_data = {
|
||||
PSCI_AFFINITY_LEVEL_ON,
|
||||
PSCI_AFFINITY_LEVEL_OFF};
|
||||
|
||||
enum imx_gpc_slot {
|
||||
CORE0_A7,
|
||||
CORE1_A7,
|
||||
SCU_A7,
|
||||
FAST_MEGA_MIX,
|
||||
MIPI_PHY,
|
||||
PCIE_PHY,
|
||||
USB_OTG1_PHY,
|
||||
USB_OTG2_PHY,
|
||||
USB_HSIC_PHY,
|
||||
CORE0_M4,
|
||||
};
|
||||
|
||||
enum mxc_cpu_pwr_mode {
|
||||
RUN,
|
||||
WAIT,
|
||||
STOP,
|
||||
};
|
||||
|
||||
extern void psci_system_resume(void);
|
||||
|
||||
static inline void psci_set_state(int cpu, u8 state)
|
||||
{
|
||||
psci_state[cpu] = state;
|
||||
dsb();
|
||||
isb();
|
||||
}
|
||||
|
||||
static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
|
||||
{
|
||||
writel(enable, GPC_IPS_BASE_ADDR + offset);
|
||||
}
|
||||
|
||||
__secure void imx_gpcv2_set_core_power(int cpu, bool pdn)
|
||||
{
|
||||
u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
|
||||
u32 pgc = cpu ? GPC_PGC_C1 : GPC_PGC_C0;
|
||||
u32 pdn_pup_req = cpu ? BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 :
|
||||
BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7;
|
||||
u32 val;
|
||||
|
||||
imx_gpcv2_set_m_core_pgc(true, pgc);
|
||||
|
||||
val = readl(GPC_IPS_BASE_ADDR + reg);
|
||||
val |= pdn_pup_req;
|
||||
writel(val, GPC_IPS_BASE_ADDR + reg);
|
||||
|
||||
while ((readl(GPC_IPS_BASE_ADDR + reg) & pdn_pup_req) != 0)
|
||||
;
|
||||
|
||||
imx_gpcv2_set_m_core_pgc(false, pgc);
|
||||
}
|
||||
|
||||
__secure void imx_enable_cpu_ca7(int cpu, bool enable)
|
||||
{
|
||||
u32 mask, val;
|
||||
|
||||
mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
|
||||
val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
|
||||
val = enable ? val | mask : val & ~mask;
|
||||
writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
|
||||
}
|
||||
|
||||
__secure void psci_arch_cpu_entry(void)
|
||||
{
|
||||
u32 cpu = psci_get_cpu_id();
|
||||
|
||||
psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
|
||||
}
|
||||
|
||||
__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep,
|
||||
u32 context_id)
|
||||
{
|
||||
u32 cpu = mpidr & MPIDR_AFF0;
|
||||
|
||||
if (mpidr & ~MPIDR_AFF0)
|
||||
return ARM_PSCI_RET_INVAL;
|
||||
|
||||
if (cpu >= IMX7D_PSCI_NR_CPUS)
|
||||
return ARM_PSCI_RET_INVAL;
|
||||
|
||||
if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
|
||||
return ARM_PSCI_RET_ALREADY_ON;
|
||||
|
||||
if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING)
|
||||
return ARM_PSCI_RET_ON_PENDING;
|
||||
|
||||
psci_save(cpu, ep, context_id);
|
||||
|
||||
writel((u32)psci_cpu_entry, imx_cpu_gpr_entry_offset(cpu));
|
||||
|
||||
psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
|
||||
|
||||
imx_gpcv2_set_core_power(cpu, true);
|
||||
imx_enable_cpu_ca7(cpu, true);
|
||||
|
||||
return ARM_PSCI_RET_SUCCESS;
|
||||
}
|
||||
|
||||
__secure s32 psci_cpu_off(void)
|
||||
{
|
||||
int cpu;
|
||||
|
||||
cpu = psci_get_cpu_id();
|
||||
|
||||
psci_cpu_off_common();
|
||||
psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
|
||||
|
||||
imx_enable_cpu_ca7(cpu, false);
|
||||
imx_gpcv2_set_core_power(cpu, false);
|
||||
/*
|
||||
* We use the cpu jumping argument register to sync with
|
||||
* psci_affinity_info() which is running on cpu0 to kill the cpu.
|
||||
*/
|
||||
writel(IMX_CPU_SYNC_OFF, imx_cpu_gpr_para_offset(cpu));
|
||||
|
||||
while (1)
|
||||
wfi();
|
||||
}
|
||||
|
||||
__secure void psci_system_reset(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
/* make sure WDOG1 clock is enabled */
|
||||
writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
|
||||
writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
|
||||
writew(WCR_WDE, &wdog->wcr);
|
||||
|
||||
while (1)
|
||||
wfi();
|
||||
}
|
||||
|
||||
__secure void psci_system_off(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* make sure SNVS clock is enabled */
|
||||
writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
|
||||
|
||||
val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
|
||||
val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
|
||||
writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
|
||||
|
||||
while (1)
|
||||
wfi();
|
||||
}
|
||||
|
||||
__secure u32 psci_version(void)
|
||||
{
|
||||
return ARM_PSCI_VER_1_0;
|
||||
}
|
||||
|
||||
__secure s32 psci_cpu_suspend(u32 __always_unused function_id, u32 power_state,
|
||||
u32 entry_point_address,
|
||||
u32 context_id)
|
||||
{
|
||||
return ARM_PSCI_RET_INVAL;
|
||||
}
|
||||
|
||||
__secure s32 psci_affinity_info(u32 __always_unused function_id,
|
||||
u32 target_affinity,
|
||||
u32 lowest_affinity_level)
|
||||
{
|
||||
u32 cpu = target_affinity & MPIDR_AFF0;
|
||||
|
||||
if (lowest_affinity_level > 0)
|
||||
return ARM_PSCI_RET_INVAL;
|
||||
|
||||
if (target_affinity & ~MPIDR_AFF0)
|
||||
return ARM_PSCI_RET_INVAL;
|
||||
|
||||
if (cpu >= IMX7D_PSCI_NR_CPUS)
|
||||
return ARM_PSCI_RET_INVAL;
|
||||
|
||||
/* CPU is waiting for killed */
|
||||
if (readl(imx_cpu_gpr_para_offset(cpu)) == IMX_CPU_SYNC_OFF) {
|
||||
imx_enable_cpu_ca7(cpu, false);
|
||||
imx_gpcv2_set_core_power(cpu, false);
|
||||
writel(IMX_CPU_SYNC_ON, imx_cpu_gpr_para_offset(cpu));
|
||||
}
|
||||
|
||||
return psci_state[cpu];
|
||||
}
|
||||
|
||||
__secure u32 psci_migrate_info_type(void)
|
||||
{
|
||||
/* Trusted OS is either not present or does not require migration */
|
||||
return 2;
|
||||
}
|
||||
|
||||
__secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid)
|
||||
{
|
||||
switch (psci_fid) {
|
||||
case ARM_PSCI_0_2_FN_PSCI_VERSION:
|
||||
case ARM_PSCI_0_2_FN_CPU_OFF:
|
||||
case ARM_PSCI_0_2_FN_CPU_ON:
|
||||
case ARM_PSCI_0_2_FN_AFFINITY_INFO:
|
||||
case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
|
||||
case ARM_PSCI_0_2_FN_SYSTEM_OFF:
|
||||
case ARM_PSCI_0_2_FN_SYSTEM_RESET:
|
||||
case ARM_PSCI_1_0_FN_PSCI_FEATURES:
|
||||
case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
|
||||
return 0x0;
|
||||
}
|
||||
return ARM_PSCI_RET_NI;
|
||||
}
|
||||
|
||||
static __secure void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode)
|
||||
{
|
||||
u32 val1, val2, val3;
|
||||
|
||||
val1 = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
|
||||
val2 = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
|
||||
/* all cores' LPM settings must be same */
|
||||
val1 &= ~(BM_LPCR_A7_BSC_LPM0 | BM_LPCR_A7_BSC_LPM1);
|
||||
val1 |= BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
|
||||
|
||||
val2 &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
|
||||
BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY);
|
||||
/*
|
||||
* GPC: When improper low-power sequence is used,
|
||||
* the SoC enters low power mode before the ARM core executes WFI.
|
||||
*
|
||||
* Software workaround:
|
||||
* 1) Software should trigger IRQ #32 (IOMUX) to be always pending
|
||||
* by setting IOMUX_GPR1_IRQ.
|
||||
* 2) Software should then unmask IRQ #32 in GPC before setting GPC
|
||||
* Low-Power mode.
|
||||
* 3) Software should mask IRQ #32 right after GPC Low-Power mode
|
||||
* is set.
|
||||
*/
|
||||
switch (mode) {
|
||||
case RUN:
|
||||
val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
|
||||
val3 &= ~0x1;
|
||||
writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
|
||||
break;
|
||||
case WAIT:
|
||||
val1 |= A7_LPM_WAIT << BP_LPCR_A7_BSC_LPM0;
|
||||
val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
|
||||
val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
|
||||
val3 &= ~0x1;
|
||||
writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
|
||||
break;
|
||||
case STOP:
|
||||
val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0;
|
||||
val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
|
||||
val2 |= BM_SLPCR_EN_DSM;
|
||||
val2 |= BM_SLPCR_SBYOS;
|
||||
val2 |= BM_SLPCR_VSTBY;
|
||||
val2 |= BM_SLPCR_BYPASS_PMIC_READY;
|
||||
val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
|
||||
val3 |= 0x1;
|
||||
writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
writel(val1, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
|
||||
writel(val2, GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
}
|
||||
|
||||
static __secure void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn)
|
||||
{
|
||||
u32 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
|
||||
|
||||
val &= ~(BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE);
|
||||
if (pdn)
|
||||
val |= BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE;
|
||||
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
|
||||
}
|
||||
|
||||
static __secure void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
|
||||
if (cpu == 0) {
|
||||
if (pdn)
|
||||
val |= BM_LPCR_A7_AD_EN_C0_PDN |
|
||||
BM_LPCR_A7_AD_EN_C0_PUP;
|
||||
else
|
||||
val &= ~(BM_LPCR_A7_AD_EN_C0_PDN |
|
||||
BM_LPCR_A7_AD_EN_C0_PUP);
|
||||
}
|
||||
if (cpu == 1) {
|
||||
if (pdn)
|
||||
val |= BM_LPCR_A7_AD_EN_C1_PDN |
|
||||
BM_LPCR_A7_AD_EN_C1_PUP;
|
||||
else
|
||||
val &= ~(BM_LPCR_A7_AD_EN_C1_PDN |
|
||||
BM_LPCR_A7_AD_EN_C1_PUP);
|
||||
}
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
|
||||
}
|
||||
|
||||
static __secure void imx_gpcv2_set_slot_ack(u32 index, enum imx_gpc_slot m_core,
|
||||
bool mode, bool ack)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (index >= MAX_SLOT_NUMBER)
|
||||
return;
|
||||
|
||||
/* set slot */
|
||||
writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) |
|
||||
((mode + 1) << (m_core * 2)),
|
||||
GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4);
|
||||
|
||||
if (ack) {
|
||||
/* set ack */
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
|
||||
/* clear dummy ack */
|
||||
val &= ~(mode ? BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK :
|
||||
BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK);
|
||||
val |= 1 << (m_core + (mode ? 16 : 0));
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
|
||||
}
|
||||
}
|
||||
|
||||
static __secure void imx_system_counter_resume(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(SYSCNT_CTRL_IPS_BASE_ADDR);
|
||||
val &= ~BM_SYS_COUNTER_CNTCR_FCR1;
|
||||
val |= BM_SYS_COUNTER_CNTCR_FCR0;
|
||||
writel(val, SYSCNT_CTRL_IPS_BASE_ADDR);
|
||||
}
|
||||
|
||||
static __secure void imx_system_counter_suspend(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(SYSCNT_CTRL_IPS_BASE_ADDR);
|
||||
val &= ~BM_SYS_COUNTER_CNTCR_FCR0;
|
||||
val |= BM_SYS_COUNTER_CNTCR_FCR1;
|
||||
writel(val, SYSCNT_CTRL_IPS_BASE_ADDR);
|
||||
}
|
||||
|
||||
static __secure void gic_resume(void)
|
||||
{
|
||||
u32 itlinesnr, i;
|
||||
u32 gic_dist_addr = GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET;
|
||||
|
||||
/* enable the GIC distributor */
|
||||
writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
|
||||
gic_dist_addr + GICD_CTLR);
|
||||
|
||||
/* TYPER[4:0] contains an encoded number of available interrupts */
|
||||
itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
|
||||
|
||||
/* set all bits in the GIC group registers to one to allow access
|
||||
* from non-secure state. The first 32 interrupts are private per
|
||||
* CPU and will be set later when enabling the GIC for each core
|
||||
*/
|
||||
for (i = 1; i <= itlinesnr; i++)
|
||||
writel((u32)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
|
||||
}
|
||||
|
||||
static inline void imx_pll_suspend(void)
|
||||
{
|
||||
writel(BM_ANATOP_ARM_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_ARM_PLL + REG_SET);
|
||||
writel(BM_ANATOP_DDR_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_SET);
|
||||
writel(BM_ANATOP_SYS_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_SYS_PLL + REG_SET);
|
||||
writel(BM_ANATOP_ENET_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_ENET_PLL + REG_SET);
|
||||
writel(BM_ANATOP_AUDIO_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_AUDIO_PLL + REG_SET);
|
||||
writel(BM_ANATOP_VIDEO_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_VIDEO_PLL + REG_SET);
|
||||
}
|
||||
|
||||
static inline void imx_pll_resume(void)
|
||||
{
|
||||
writel(BM_ANATOP_ARM_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_ARM_PLL + REG_CLR);
|
||||
writel(BM_ANATOP_DDR_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_CLR);
|
||||
writel(BM_ANATOP_SYS_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_SYS_PLL + REG_CLR);
|
||||
writel(BM_ANATOP_ENET_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_ENET_PLL + REG_CLR);
|
||||
writel(BM_ANATOP_AUDIO_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_AUDIO_PLL + REG_CLR);
|
||||
writel(BM_ANATOP_VIDEO_PLL_OVERRIDE,
|
||||
ANATOP_BASE_ADDR + ANADIG_VIDEO_PLL + REG_CLR);
|
||||
}
|
||||
|
||||
static inline void imx_udelay(u32 usec)
|
||||
{
|
||||
u32 freq;
|
||||
u64 start, end;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
|
||||
asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
|
||||
do {
|
||||
asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
|
||||
if ((end - start) > usec * (freq / 1000000))
|
||||
break;
|
||||
} while (1);
|
||||
}
|
||||
|
||||
static inline void imx_ddrc_enter_self_refresh(void)
|
||||
{
|
||||
writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
|
||||
while (readl(DDRC_IPS_BASE_ADDR + DDRC_PSTAT) & 0x10001)
|
||||
;
|
||||
|
||||
writel(0x20, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
|
||||
while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x23) != 0x23)
|
||||
;
|
||||
writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x8,
|
||||
DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
|
||||
}
|
||||
|
||||
static inline void imx_ddrc_exit_self_refresh(void)
|
||||
{
|
||||
writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
|
||||
while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x3) == 0x3)
|
||||
;
|
||||
writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x1,
|
||||
DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
|
||||
}
|
||||
|
||||
__secure void imx_system_resume(void)
|
||||
{
|
||||
unsigned int i, val, imr[4], entry;
|
||||
|
||||
entry = psci_get_target_pc(0);
|
||||
imx_ddrc_exit_self_refresh();
|
||||
imx_system_counter_resume();
|
||||
imx_gpcv2_set_lpm_mode(RUN);
|
||||
imx_gpcv2_set_cpu_power_gate_by_lpm(0, false);
|
||||
imx_gpcv2_set_plat_power_gate_by_lpm(false);
|
||||
imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0);
|
||||
imx_gpcv2_set_m_core_pgc(false, GPC_PGC_SCU);
|
||||
|
||||
/*
|
||||
* need to mask all interrupts in GPC before
|
||||
* operating RBC configurations
|
||||
*/
|
||||
for (i = 0; i < 4; i++) {
|
||||
imr[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
|
||||
writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
|
||||
}
|
||||
|
||||
/* configure RBC enable bit */
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
val &= ~BM_SLPCR_RBC_EN;
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
|
||||
/* configure RBC count */
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
val &= ~BM_SLPCR_REG_BYPASS_COUNT;
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
|
||||
/*
|
||||
* need to delay at least 2 cycles of CKIL(32K)
|
||||
* due to hardware design requirement, which is
|
||||
* ~61us, here we use 65us for safe
|
||||
*/
|
||||
imx_udelay(65);
|
||||
|
||||
/* restore GPC interrupt mask settings */
|
||||
for (i = 0; i < 4; i++)
|
||||
writel(imr[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
|
||||
|
||||
/* initialize gic distributor */
|
||||
gic_resume();
|
||||
_nonsec_init();
|
||||
|
||||
/* save cpu0 entry */
|
||||
psci_save(0, entry, 0);
|
||||
psci_cpu_entry();
|
||||
}
|
||||
|
||||
__secure void psci_system_suspend(u32 __always_unused function_id,
|
||||
u32 ep, u32 context_id)
|
||||
{
|
||||
u32 gpc_mask[4];
|
||||
u32 i, val;
|
||||
|
||||
psci_save(0, ep, context_id);
|
||||
/* overwrite PLL to be controlled by low power mode */
|
||||
imx_pll_suspend();
|
||||
imx_system_counter_suspend();
|
||||
/* set CA7 platform to enter STOP mode */
|
||||
imx_gpcv2_set_lpm_mode(STOP);
|
||||
/* enable core0/scu power down/up with low power mode */
|
||||
imx_gpcv2_set_cpu_power_gate_by_lpm(0, true);
|
||||
imx_gpcv2_set_plat_power_gate_by_lpm(true);
|
||||
/* time slot settings for core0 and scu */
|
||||
imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false);
|
||||
imx_gpcv2_set_slot_ack(1, SCU_A7, false, true);
|
||||
imx_gpcv2_set_slot_ack(5, SCU_A7, true, false);
|
||||
imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true);
|
||||
imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0);
|
||||
imx_gpcv2_set_m_core_pgc(true, GPC_PGC_SCU);
|
||||
psci_v7_flush_dcache_all();
|
||||
|
||||
imx_ddrc_enter_self_refresh();
|
||||
|
||||
/*
|
||||
* e10133: ARM: Boot failure after A7 enters into
|
||||
* low-power idle mode
|
||||
*
|
||||
* Workaround:
|
||||
* If both CPU0/CPU1 are IDLE, the last IDLE CPU should
|
||||
* disable GIC first, then REG_BYPASS_COUNTER is used
|
||||
* to mask wakeup INT, and then execute “wfi” is used to
|
||||
* bring the system into power down processing safely.
|
||||
* The counter must be enabled as close to the “wfi” state
|
||||
* as possible. The following equation can be used to
|
||||
* determine the RBC counter value:
|
||||
* RBC_COUNT * (1/32K RTC frequency) >=
|
||||
* (46 + PDNSCR_SW + PDNSCR_SW2ISO ) ( 1/IPG_CLK frequency ).
|
||||
*/
|
||||
|
||||
/* disable GIC distributor */
|
||||
writel(0, GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET);
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
gpc_mask[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
|
||||
|
||||
/*
|
||||
* enable the RBC bypass counter here
|
||||
* to hold off the interrupts. RBC counter
|
||||
* = 8 (240us). With this setting, the latency
|
||||
* from wakeup interrupt to ARM power up
|
||||
* is ~250uS.
|
||||
*/
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
val &= ~(0x3f << 24);
|
||||
val |= (0x8 << 24);
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
|
||||
/* enable the counter. */
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
val |= (1 << 30);
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
|
||||
/* unmask all the GPC interrupts. */
|
||||
for (i = 0; i < 4; i++)
|
||||
writel(gpc_mask[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
|
||||
|
||||
/*
|
||||
* now delay for a short while (3usec)
|
||||
* ARM is at 1GHz at this point
|
||||
* so a short loop should be enough.
|
||||
* this delay is required to ensure that
|
||||
* the RBC counter can start counting in
|
||||
* case an interrupt is already pending
|
||||
* or in case an interrupt arrives just
|
||||
* as ARM is about to assert DSM_request.
|
||||
*/
|
||||
imx_udelay(3);
|
||||
|
||||
/* save resume entry and sp in CPU0 GPR registers */
|
||||
asm volatile("mov %0, sp" : "=r" (val));
|
||||
writel((u32)psci_system_resume, SRC_BASE_ADDR + SRC_GPR1_MX7D);
|
||||
writel(val, SRC_BASE_ADDR + SRC_GPR2_MX7D);
|
||||
|
||||
/* sleep */
|
||||
while (1)
|
||||
wfi();
|
||||
}
|
||||
@@ -0,0 +1,67 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#include <asm/armv7.h>
|
||||
#include <asm/psci.h>
|
||||
|
||||
.pushsection ._secure.text, "ax"
|
||||
|
||||
.arch_extension sec
|
||||
|
||||
.globl v7_invalidate_l1
|
||||
v7_invalidate_l1:
|
||||
mov r0, #0
|
||||
mcr p15, 2, r0, c0, c0, 0
|
||||
mrc p15, 1, r0, c0, c0, 0
|
||||
|
||||
movw r1, #0x7fff
|
||||
and r2, r1, r0, lsr #13
|
||||
|
||||
movw r1, #0x3ff
|
||||
|
||||
and r3, r1, r0, lsr #3 @ NumWays - 1
|
||||
add r2, r2, #1 @ NumSets
|
||||
|
||||
and r0, r0, #0x7
|
||||
add r0, r0, #4 @ SetShift
|
||||
|
||||
clz r1, r3 @ WayShift
|
||||
add r4, r3, #1 @ NumWays
|
||||
1:
|
||||
sub r2, r2, #1 @ NumSets--
|
||||
mov r3, r4 @ Temp = NumWays
|
||||
2:
|
||||
subs r3, r3, #1 @ Temp--
|
||||
mov r5, r3, lsl r1
|
||||
mov r6, r2, lsl r0
|
||||
orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
|
||||
mcr p15, 0, r5, c7, c6, 2
|
||||
bgt 2b
|
||||
cmp r2, #0
|
||||
bgt 1b
|
||||
dsb st
|
||||
isb
|
||||
mov pc, lr
|
||||
|
||||
.globl psci_system_resume
|
||||
psci_system_resume:
|
||||
mov sp, r0
|
||||
|
||||
/* invalidate L1 I-cache first */
|
||||
mov r6, #0x0
|
||||
mcr p15, 0, r6, c7, c5, 0
|
||||
mcr p15, 0, r6, c7, c5, 6
|
||||
/* enable the Icache and branch prediction */
|
||||
mov r6, #0x1800
|
||||
mcr p15, 0, r6, c1, c0, 0
|
||||
isb
|
||||
|
||||
bl v7_invalidate_l1
|
||||
b imx_system_resume
|
||||
|
||||
.popsection
|
||||
@@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 Linaro
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#define SNVS_HPCOMR 0x04
|
||||
#define SNVS_HPCOMR_NPSWA_EN BIT(31)
|
||||
|
||||
void init_snvs(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Ensure SNVS HPCOMR sets NPSWA_EN to allow unpriv access to SNVS LP */
|
||||
val = readl(SNVS_BASE_ADDR + SNVS_HPCOMR);
|
||||
val |= SNVS_HPCOMR_NPSWA_EN;
|
||||
writel(val, SNVS_BASE_ADDR + SNVS_HPCOMR);
|
||||
}
|
||||
@@ -0,0 +1,391 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/dma.h>
|
||||
#include <asm/mach-imx/hab.h>
|
||||
#include <asm/mach-imx/rdc-sema.h>
|
||||
#include <asm/arch/imx-rdc.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <dm.h>
|
||||
#include <env.h>
|
||||
#include <imx_thermal.h>
|
||||
#include <fsl_sec.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#define IOMUXC_GPR1 0x4
|
||||
#define BM_IOMUXC_GPR1_IRQ 0x1000
|
||||
|
||||
#define GPC_LPCR_A7_BSC 0x0
|
||||
#define GPC_LPCR_M4 0x8
|
||||
#define GPC_SLPCR 0x14
|
||||
#define GPC_PGC_ACK_SEL_A7 0x24
|
||||
#define GPC_IMR1_CORE0 0x30
|
||||
#define GPC_IMR1_CORE1 0x40
|
||||
#define GPC_IMR1_M4 0x50
|
||||
#define GPC_PGC_CPU_MAPPING 0xec
|
||||
#define GPC_PGC_C0_PUPSCR 0x804
|
||||
#define GPC_PGC_SCU_TIMING 0x890
|
||||
#define GPC_PGC_C1_PUPSCR 0x844
|
||||
|
||||
#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
|
||||
#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
|
||||
#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
|
||||
#define BM_SLPCR_EN_DSM 0x80000000
|
||||
#define BM_SLPCR_RBC_EN 0x40000000
|
||||
#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
|
||||
#define BM_SLPCR_VSTBY 0x4
|
||||
#define BM_SLPCR_SBYOS 0x2
|
||||
#define BM_SLPCR_BYPASS_PMIC_READY 0x1
|
||||
#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
|
||||
|
||||
#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
|
||||
#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
|
||||
|
||||
#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
|
||||
|
||||
#if defined(CONFIG_IMX_THERMAL)
|
||||
static const struct imx_thermal_plat imx7_thermal_plat = {
|
||||
.regs = (void *)ANATOP_BASE_ADDR,
|
||||
.fuse_bank = 3,
|
||||
.fuse_word = 3,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(imx7_thermal) = {
|
||||
.name = "imx_thermal",
|
||||
.platdata = &imx7_thermal_plat,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(IMX_RDC)
|
||||
/*
|
||||
* In current design, if any peripheral was assigned to both A7 and M4,
|
||||
* it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
|
||||
* low power mode. So M4 sleep will cause some peripherals fail to work
|
||||
* at A7 core side. At default, all resources are in domain 0 - 3.
|
||||
*
|
||||
* There are 26 peripherals impacted by this IC issue:
|
||||
* SIM2(sim2/emvsim2)
|
||||
* SIM1(sim1/emvsim1)
|
||||
* UART1/UART2/UART3/UART4/UART5/UART6/UART7
|
||||
* SAI1/SAI2/SAI3
|
||||
* WDOG1/WDOG2/WDOG3/WDOG4
|
||||
* GPT1/GPT2/GPT3/GPT4
|
||||
* PWM1/PWM2/PWM3/PWM4
|
||||
* ENET1/ENET2
|
||||
* Software Workaround:
|
||||
* Here we setup some resources to domain 0 where M4 codes will move
|
||||
* the M4 out of this domain. Then M4 is not able to access them any longer.
|
||||
* This is a workaround for ic issue. So the peripherals are not shared
|
||||
* by them. This way requires the uboot implemented the RDC driver and
|
||||
* set the 26 IPs above to domain 0 only. M4 code will assign resource
|
||||
* to its own domain, if it want to use the resource.
|
||||
*/
|
||||
static rdc_peri_cfg_t const resources[] = {
|
||||
(RDC_PER_SIM1 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_SIM2 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_UART1 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_UART2 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_UART3 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_UART4 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_UART5 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_UART6 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_UART7 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_SAI1 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_SAI2 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_SAI3 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_WDOG1 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_WDOG2 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_WDOG3 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_WDOG4 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_GPT1 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_GPT2 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_GPT3 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_GPT4 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_PWM1 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_PWM2 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_PWM3 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_PWM4 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_ENET1 | RDC_DOMAIN(0)),
|
||||
(RDC_PER_ENET2 | RDC_DOMAIN(0)),
|
||||
};
|
||||
|
||||
static void isolate_resource(void)
|
||||
{
|
||||
imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_IMX_HAB)
|
||||
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
|
||||
.bank = 1,
|
||||
.word = 3,
|
||||
};
|
||||
#endif
|
||||
|
||||
static bool is_mx7d(void)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[1];
|
||||
struct fuse_bank1_regs *fuse =
|
||||
(struct fuse_bank1_regs *)bank->fuse_regs;
|
||||
int val;
|
||||
|
||||
val = readl(&fuse->tester4);
|
||||
if (val & 1)
|
||||
return false;
|
||||
else
|
||||
return true;
|
||||
}
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
|
||||
ANATOP_BASE_ADDR;
|
||||
u32 reg = readl(&ccm_anatop->digprog);
|
||||
u32 type = (reg >> 16) & 0xff;
|
||||
|
||||
if (!is_mx7d())
|
||||
type = MXC_CPU_MX7S;
|
||||
|
||||
reg &= 0xff;
|
||||
return (type << 12) | reg;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_REVISION_TAG
|
||||
u32 __weak get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
#endif
|
||||
|
||||
static void imx_enet_mdio_fixup(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr_regs =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/*
|
||||
* The management data input/output (MDIO) requires open-drain,
|
||||
* i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
|
||||
* this feature. So to TO1.1, need to enable open drain by setting
|
||||
* bits GPR0[8:7].
|
||||
*/
|
||||
|
||||
if (soc_rev() >= CHIP_REV_1_1) {
|
||||
setbits_le32(&gpr_regs->gpr[0],
|
||||
IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
static void init_cpu_basic(void)
|
||||
{
|
||||
imx_enet_mdio_fixup();
|
||||
|
||||
#ifdef CONFIG_APBH_DMA
|
||||
/* Start APBH DMA */
|
||||
mxs_dma_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
/* enable all periherial can be accessed in nosec mode */
|
||||
static void init_csu(void)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < CSU_NUM_REGS; i++)
|
||||
writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
|
||||
}
|
||||
|
||||
static void imx_gpcv2_init(void)
|
||||
{
|
||||
u32 val, i;
|
||||
|
||||
/*
|
||||
* Force IOMUXC irq pending, so that the interrupt to GPC can be
|
||||
* used to deassert dsm_request signal when the signal gets
|
||||
* asserted unexpectedly.
|
||||
*/
|
||||
val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
|
||||
val |= BM_IOMUXC_GPR1_IRQ;
|
||||
writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
|
||||
|
||||
/* Initially mask all interrupts */
|
||||
for (i = 0; i < 4; i++) {
|
||||
writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
|
||||
writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
|
||||
writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
|
||||
}
|
||||
|
||||
/* set SCU timing */
|
||||
writel((0x59 << 10) | 0x5B | (0x2 << 20),
|
||||
GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
|
||||
|
||||
/* only external IRQs to wake up LPM and core 0/1 */
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
|
||||
val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
|
||||
|
||||
/* set C0 power up timming per design requirement */
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
|
||||
val &= ~BM_GPC_PGC_CORE_PUPSCR;
|
||||
val |= (0x1A << 7);
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
|
||||
|
||||
/* set C1 power up timming per design requirement */
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
|
||||
val &= ~BM_GPC_PGC_CORE_PUPSCR;
|
||||
val |= (0x1A << 7);
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
|
||||
|
||||
/* dummy ack for time slot by default */
|
||||
writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
|
||||
BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
|
||||
GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
|
||||
|
||||
/* mask M4 DSM trigger */
|
||||
writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
|
||||
BM_LPCR_M4_MASK_DSM_TRIGGER,
|
||||
GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
|
||||
|
||||
/* set mega/fast mix in A7 domain */
|
||||
writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
|
||||
|
||||
/* DSM related settings */
|
||||
val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
|
||||
BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
|
||||
BM_SLPCR_REG_BYPASS_COUNT);
|
||||
val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
|
||||
writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
|
||||
|
||||
/*
|
||||
* disabling RBC need to delay at least 2 cycles of CKIL(32K)
|
||||
* due to hardware design requirement, which is
|
||||
* ~61us, here we use 65us for safe
|
||||
*/
|
||||
udelay(65);
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
init_aips();
|
||||
|
||||
init_csu();
|
||||
/* Disable PDE bit of WMCR register */
|
||||
imx_wdog_disable_powerdown();
|
||||
|
||||
init_cpu_basic();
|
||||
|
||||
#if CONFIG_IS_ENABLED(IMX_RDC)
|
||||
isolate_resource();
|
||||
#endif
|
||||
|
||||
init_snvs();
|
||||
|
||||
imx_gpcv2_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
init_cpu_basic();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_MISC_INIT
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
if (is_mx7d())
|
||||
env_set("soc", "imx7d");
|
||||
else
|
||||
env_set("soc", "imx7s");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_TAG
|
||||
/*
|
||||
* OCOTP_TESTER
|
||||
* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
|
||||
* OCOTP_TESTER describes a unique ID based on silicon wafer
|
||||
* and die X/Y position
|
||||
*
|
||||
* OCOTOP_TESTER offset 0x410
|
||||
* 31:0 fuse 0
|
||||
* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
|
||||
*
|
||||
* OCOTP_TESTER1 offset 0x420
|
||||
* 31:24 fuse 1
|
||||
* The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
|
||||
* 23:16 fuse 1
|
||||
* The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
|
||||
* 15:11 fuse 1
|
||||
* The wafer number of the wafer on which the device was fabricated/SJC
|
||||
* CHALLENGE/ Unique ID
|
||||
* 10:0 fuse 1
|
||||
* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
|
||||
*/
|
||||
void get_board_serial(struct tag_serialnr *serialnr)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[0];
|
||||
struct fuse_bank0_regs *fuse =
|
||||
(struct fuse_bank0_regs *)bank->fuse_regs;
|
||||
|
||||
serialnr->low = fuse->tester0;
|
||||
serialnr->high = fuse->tester1;
|
||||
}
|
||||
#endif
|
||||
|
||||
void set_wdog_reset(struct wdog_regs *wdog)
|
||||
{
|
||||
u32 reg = readw(&wdog->wcr);
|
||||
/*
|
||||
* Output WDOG_B signal to reset external pmic or POR_B decided by
|
||||
* the board desgin. Without external reset, the peripherals/DDR/
|
||||
* PMIC are not reset, that may cause system working abnormal.
|
||||
*/
|
||||
reg = readw(&wdog->wcr);
|
||||
reg |= 1 << 3;
|
||||
/*
|
||||
* WDZST bit is write-once only bit. Align this bit in kernel,
|
||||
* otherwise kernel code will have no chance to set this bit.
|
||||
*/
|
||||
reg |= 1 << 0;
|
||||
writew(reg, &wdog->wcr);
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
/* clock configuration. */
|
||||
clock_init();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void reset_misc(void)
|
||||
{
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
|
||||
lcdif_power_down();
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user