GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: AM6 SoC definitions, structures etc.
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*
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* (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef __ASM_ARCH_AM6_HARDWARE_H
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#define __ASM_ARCH_AM6_HARDWARE_H
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#include <config.h>
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#define CTRL_MMR0_BASE 0x00100000
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#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
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#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0)
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#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0
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#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4)
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#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 4
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#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK GENMASK(12, 12)
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#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT 12
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#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK GENMASK(14, 14)
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#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT 14
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#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK GENMASK(17, 17)
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#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 12
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define MCU_CTRL_MMR0_BASE 0x40f00000
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/*
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* The CTRL_MMR0 memory space is divided into several equally-spaced
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* partitions, so defining the partition size allows us to determine
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* register addresses common to those partitions.
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*/
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#define CTRL_MMR0_PARTITION_SIZE 0x4000
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/*
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* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
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* shared register definitions.
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*/
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#define CTRLMMR_LOCK_KICK0 0x01008
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#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
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#define CTRLMMR_LOCK_KICK1 0x0100c
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#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
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/* MCU SCRATCHPAD usage */
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
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#endif /* __ASM_ARCH_AM6_HARDWARE_H */
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#ifndef _ASM_ARCH_AM6_SPL_H_
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#define _ASM_ARCH_AM6_SPL_H_
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#define BOOT_DEVICE_RAM 0x00
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#define BOOT_DEVICE_OSPI 0x01
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#define BOOT_DEVICE_QSPI 0x02
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#define BOOT_DEVICE_HYPERFLASH 0x03
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#define BOOT_DEVICE_SPI 0x04
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#define BOOT_DEVICE_I2C 0x05
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#define BOOT_DEVICE_MMC2 0x06
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#define BOOT_DEVICE_ETHERNET 0x07
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#define BOOT_DEVICE_USB 0x08
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#define BOOT_DEVICE_PCIE 0x09
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#define BOOT_DEVICE_UART 0x0a
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#define BOOT_DEVICE_NAND 0x0c
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#define BOOT_DEVICE_MMC1 0x0d
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#define BOOT_DEVICE_MMC2_2 0x0e
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#define BACKUP_BOOT_DEVICE_RAM 0x0
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#define BACKUP_BOOT_DEVICE_USB 0x1
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#define BACKUP_BOOT_DEVICE_UART 0x2
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#define BACKUP_BOOT_DEVICE_ETHERNET 0x3
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#define BACKUP_BOOT_DEVICE_MMC2 0x4
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#define BACKUP_BOOT_DEVICE_SPI 0x5
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#define BACKUP_BOOT_DEVICE_HYPERFLASH 0x6
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#define BACKUP_BOOT_DEVICE_I2C 0x7
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#define K3_PRIMARY_BOOTMODE 0x0
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#define K3_BACKUP_BOOTMODE 0x1
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#endif
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: Common SoC clock definitions.
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*
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* (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef __ASM_ARCH_CLOCK_H
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#define __ASM_ARCH_CLOCK_H
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#include <config.h>
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/* Clock Defines */
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#define V_OSCK 24000000
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#define V_SCLK V_OSCK
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#endif /* __ASM_ARCH_CLOCK_H */
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#ifndef _ASM_ARCH_HARDWARE_H_
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#define _ASM_ARCH_HARDWARE_H_
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#ifdef CONFIG_SOC_K3_AM6
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#include "am6_hardware.h"
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#endif
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#ifdef CONFIG_SOC_K3_J721E
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#include "j721e_hardware.h"
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#endif
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/* Assuming these addresses and definitions stay common across K3 devices */
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#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018
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#define DEVICE_ID_FAMILY_SHIFT 26
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#define DEVICE_ID_FAMILY_MASK (0x3f << 26)
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#define DEVICE_ID_BASE_SHIFT 11
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#define DEVICE_ID_BASE_MASK (0x1fff << 11)
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#define DEVICE_ID_SPEED_SHIFT 6
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#define DEVICE_ID_SPEED_MASK (0x1f << 6)
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#define DEVICE_ID_TEMP_SHIFT 3
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#define DEVICE_ID_TEMP_MASK (0x7 << 3)
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#define CTRLMMR_WKUP_JTAG_ID 0x43000014
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#define JTAG_ID_VARIANT_SHIFT 28
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#define JTAG_ID_VARIANT_MASK (0xf << 28)
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#define JTAG_ID_PARTNO_SHIFT 12
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#define JTAG_ID_PARTNO_MASK (0x7ff << 1)
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#endif /* _ASM_ARCH_HARDWARE_H_ */
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: J721E SoC definitions, structures etc.
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*
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* (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef __ASM_ARCH_J721E_HARDWARE_H
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#define __ASM_ARCH_J721E_HARDWARE_H
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#include <config.h>
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#define CTRL_MMR0_BASE 0x00100000
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#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
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#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
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#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
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#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
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#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
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#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
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#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define MCU_CTRL_MMR0_BASE 0x40f00000
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#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
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#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
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#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
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#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
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/*
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* The CTRL_MMR0 memory space is divided into several equally-spaced
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* partitions, so defining the partition size allows us to determine
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* register addresses common to those partitions.
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*/
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#define CTRL_MMR0_PARTITION_SIZE 0x4000
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/*
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* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
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* shared register definitions.
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*/
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#define CTRLMMR_LOCK_KICK0 0x01008
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#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
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#define CTRLMMR_LOCK_KICK1 0x0100c
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#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
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#endif /* __ASM_ARCH_J721E_HARDWARE_H */
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#ifndef _ASM_ARCH_J721E_SPL_H_
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#define _ASM_ARCH_J721E_SPL_H_
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/* With BootMode B = 0 */
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#define BOOT_DEVICE_HYPERFLASH 0x00
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#define BOOT_DEVICE_OSPI 0x01
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#define BOOT_DEVICE_QSPI 0x02
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#define BOOT_DEVICE_SPI 0x03
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#define BOOT_DEVICE_ETHERNET 0x04
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#define BOOT_DEVICE_I2C 0x06
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#define BOOT_DEVICE_UART 0x07
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/* With BootMode B = 1 */
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#define BOOT_DEVICE_MMC2 0x10
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#define BOOT_DEVICE_MMC1 0x11
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#define BOOT_DEVICE_USB 0x12
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#define BOOT_DEVICE_UFS 0x13
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#define BOOT_DEVIE_GPMC 0x14
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#define BOOT_DEVICE_PCIE 0x15
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#define BOOT_DEVICE_MMC2_2 0x16
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#define BOOT_DEVICE_RAM 0x17
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#define BOOT_MODE_B_SHIFT 4
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#define BOOT_MODE_B_MASK BIT(4)
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#endif
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#ifndef _ASM_ARCH_SPL_H_
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#define _ASM_ARCH_SPL_H_
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#ifdef CONFIG_SOC_K3_AM6
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#include "am6_spl.h"
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#endif
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#ifdef CONFIG_SOC_K3_J721E
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#include "j721e_spl.h"
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#endif
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#endif /* _ASM_ARCH_SPL_H_ */
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Andreas Dannenberg <dannenberg@ti.com>
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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void sdelay(unsigned long loops);
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u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
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u32 bound);
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struct ti_sci_handle *get_ti_sci_handle(void);
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int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
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int do_board_detect(void);
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void release_resources_for_core_shutdown(void);
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int fdt_disable_node(void *blob, char *node_path);
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#endif
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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* Andreas Dannenberg <dannenberg@ti.com>
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*/
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#ifndef _SYSFW_LOADER_H_
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#define _SYSFW_LOADER_H_
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void k3_sysfw_loader(void (*config_pm_done_callback)(void));
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#endif
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