GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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# SPDX-License-Identifier: GPL-2.0
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obj-y += init.o
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obj-y += lowlevel_init.o
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <ram.h>
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#include <asm/arch/misc.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <linux/io.h>
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#include <dt-bindings/clock/mt7629-clk.h>
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#define L2_CFG_BASE 0x10200000
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#define L2_CFG_SIZE 0x1000
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#define L2_SHARE_CFG_MP0 0x7f0
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#define L2_SHARE_MODE_OFF BIT(8)
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DECLARE_GLOBAL_DATA_PTR;
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int mtk_pll_early_init(void)
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{
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unsigned long pll_rates[] = {
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[CLK_APMIXED_ARMPLL] = 1250000000,
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[CLK_APMIXED_MAINPLL] = 1120000000,
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[CLK_APMIXED_UNIV2PLL] = 1200000000,
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[CLK_APMIXED_ETH1PLL] = 500000000,
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[CLK_APMIXED_ETH2PLL] = 700000000,
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[CLK_APMIXED_SGMIPLL] = 650000000,
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};
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struct udevice *dev;
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int ret, i;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
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if (ret)
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return ret;
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/* configure default rate then enable apmixedsys */
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for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
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struct clk clk = { .id = i, .dev = dev };
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ret = clk_set_rate(&clk, pll_rates[i]);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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}
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/* setup mcu bus */
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ret = uclass_get_device_by_driver(UCLASS_SYSCON,
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DM_GET_DRIVER(mtk_mcucfg), &dev);
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if (ret)
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return ret;
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return 0;
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}
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int mtk_soc_early_init(void)
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{
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struct udevice *dev;
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int ret;
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/* initialize early clocks */
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ret = mtk_pll_early_init();
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if (ret)
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return ret;
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ret = uclass_first_device_err(UCLASS_RAM, &dev);
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if (ret)
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return ret;
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return 0;
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}
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int mach_cpu_init(void)
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{
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void __iomem *base;
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base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
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/* disable L2C shared mode */
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writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
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return 0;
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}
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int dram_init(void)
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{
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struct ram_info ram;
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struct udevice *dev;
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int ret;
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ret = uclass_first_device_err(UCLASS_RAM, &dev);
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if (ret)
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return ret;
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ret = ram_get_info(dev, &ram);
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if (ret)
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return ret;
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debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
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gd->ram_size = ram.size;
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return 0;
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}
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int print_cpuinfo(void)
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{
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void __iomem *chipid;
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u32 hwcode, swver;
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chipid = ioremap(VER_BASE, VER_SIZE);
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hwcode = readl(chipid + APHW_CODE);
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swver = readl(chipid + APSW_VER);
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printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
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return 0;
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}
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@@ -0,0 +1,99 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#include <linux/linkage.h>
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#include <asm/proc-armv/ptrace.h>
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#define WAIT_CODE_SRAM_BASE 0x0010ff00
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#define SLAVE_JUMP_REG 0x10202034
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#define SLAVE1_MAGIC_REG 0x10202038
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#define SLAVE1_MAGIC_NUM 0x534c4131
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#define GIC_CPU_BASE 0x10320000
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ENTRY(lowlevel_init)
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#ifndef CONFIG_SPL_BUILD
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/* Return to U-Boot via saved link register */
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mov pc, lr
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#else
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/*
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* Arch timer :
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* set CNTFRQ = 20Mhz, set CNTVOFF = 0
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*/
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movw r0, #0x2d00
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movt r0, #0x131
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mcr p15, 0, r0, c14, c0, 0
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cps #MON_MODE
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mrc p15, 0, r1, c1, c1, 0 @ Get Secure Config
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orr r0, r1, #1
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mcr p15, 0, r0, c1, c1, 0 @ Set Non Secure bit
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isb
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mov r0, #0
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mcrr p15, 4, r0, r0, c14 @ CNTVOFF = 0
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isb
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mcr p15, 0, r1, c1, c1, 0 @ Set Secure bit
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isb
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cps #SVC_MODE
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/* enable SMP bit */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #0x40
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mcr p15, 0, r0, c1, c0, 1
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/* if MP core, handle secondary cores */
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mrc p15, 0, r0, c0, c0, 5
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ands r1, r0, #0x40000000
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bne go @ Go if UP
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/* read slave CPU number */
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ands r0, r0, #0x0f
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beq go @ Go if core0 on primary core tile
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b secondary
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go:
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/* master CPU */
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mov pc, lr
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secondary:
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/* enable GIC as cores will be waken up by IPI */
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ldr r2, =GIC_CPU_BASE
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mov r1, #0xf0
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str r1, [r2, #4]
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mov r1, #1
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str r1, [r2, #0]
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ldr r1, [r2]
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orr r1, #1
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str r1, [r2]
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/* copy wait code into SRAM */
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ldr r0, =slave_cpu_wait
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ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns
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ldr r0, =WAIT_CODE_SRAM_BASE
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stm r0, {r1 - r8}
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/* pass args to slave_cpu_wait */
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ldr r0, =SLAVE1_MAGIC_REG
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ldr r1, =SLAVE1_MAGIC_NUM
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/* jump to wait code in SRAM */
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ldr pc, =WAIT_CODE_SRAM_BASE
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#endif
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ENDPROC(lowlevel_init)
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/* This function will be copied into SRAM */
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ENTRY(slave_cpu_wait)
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wfi
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ldr r2, [r0]
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cmp r2, r1
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bne slave_cpu_wait
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movw r0, #:lower16:SLAVE_JUMP_REG
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movt r0, #:upper16:SLAVE_JUMP_REG
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ldr r1, [r0]
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mov pc, r1
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ENDPROC(slave_cpu_wait)
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