GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,29 @@
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if OMAP44XX
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choice
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prompt "OMAP4 board select"
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optional
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config TARGET_DUOVERO
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bool "OMAP4430 Gumstix Duovero"
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config TARGET_OMAP4_PANDA
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bool "TI OMAP4 PandaBoard"
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config TARGET_OMAP4_SDP4430
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bool "TI OMAP4 SDP4430"
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config TARGET_KC1
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bool "Amazon Kindle Fire (first generation)"
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endchoice
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config SYS_SOC
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default "omap4"
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source "board/gumstix/duovero/Kconfig"
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source "board/ti/panda/Kconfig"
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source "board/ti/sdp4430/Kconfig"
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source "board/amazon/kc1/Kconfig"
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endif
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@@ -0,0 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2010
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += boot.o
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obj-y += sdram_elpida.o
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obj-y += hwinit.o
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obj-y += emif.o
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obj-y += prcm-regs.o
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obj-y += hw_data.o
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@@ -0,0 +1,104 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* OMAP4 boot
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*
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* Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/omap_common.h>
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#include <asm/arch/sys_proto.h>
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#include <spl.h>
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static u32 boot_devices[] = {
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BOOT_DEVICE_MMC2,
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BOOT_DEVICE_XIP,
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BOOT_DEVICE_XIPWAIT,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_XIPWAIT,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_MMC2,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_XIPWAIT,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_MMC2,
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BOOT_DEVICE_XIP,
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BOOT_DEVICE_XIPWAIT,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_MMC2,
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BOOT_DEVICE_XIP,
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BOOT_DEVICE_MMC2_2,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_MMC2_2,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_MMC2_2,
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BOOT_DEVICE_MMC2_2,
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BOOT_DEVICE_NONE,
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BOOT_DEVICE_XIPWAIT,
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};
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u32 omap_sys_boot_device(void)
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{
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u32 sys_boot;
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/* Grab the first 5 bits of the status register for SYS_BOOT. */
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sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1);
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if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
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return BOOT_DEVICE_NONE;
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return boot_devices[sys_boot];
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}
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int omap_reboot_mode(char *mode, unsigned int length)
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{
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unsigned int limit;
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unsigned int i;
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if (length < 2)
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return -1;
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if (!warm_reset())
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return -1;
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limit = (length < OMAP_REBOOT_REASON_SIZE) ? length :
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OMAP_REBOOT_REASON_SIZE;
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for (i = 0; i < (limit - 1); i++)
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mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE +
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OMAP_REBOOT_REASON_OFFSET + i));
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mode[i] = '\0';
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return 0;
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}
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int omap_reboot_mode_clear(void)
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{
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writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET));
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return 0;
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}
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int omap_reboot_mode_store(char *mode)
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{
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unsigned int i;
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for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++)
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writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE +
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OMAP_REBOOT_REASON_OFFSET + i));
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writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE +
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OMAP_REBOOT_REASON_OFFSET + i));
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return 0;
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}
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@@ -0,0 +1,110 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* EMIF programming
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*/
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#include <common.h>
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#include <asm/emif.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/utils.h>
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#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
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u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
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#endif
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#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
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static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
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.max_freq = 400000000,
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.RL = 6,
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.tRPab = 21,
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.tRCD = 18,
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.tWR = 15,
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.tRASmin = 42,
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.tRRD = 10,
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.tWTRx2 = 15,
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.tXSR = 140,
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.tXPx2 = 15,
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.tRFCab = 130,
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.tRTPx2 = 15,
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.tCKE = 3,
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.tCKESR = 15,
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.tZQCS = 90,
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.tZQCL = 360,
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.tZQINIT = 1000,
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.tDQSCKMAXx2 = 11,
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.tRASmax = 70,
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.tFAW = 50
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};
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/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
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static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
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.max_freq = 200000000,
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.RL = 3,
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.tRPab = 21,
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.tRCD = 18,
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.tWR = 15,
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.tRASmin = 42,
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.tRRD = 10,
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.tWTRx2 = 20,
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.tXSR = 140,
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.tXPx2 = 15,
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.tRFCab = 130,
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.tRTPx2 = 15,
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.tCKE = 3,
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.tCKESR = 15,
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.tZQCS = 90,
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.tZQCL = 360,
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.tZQINIT = 1000,
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.tDQSCKMAXx2 = 11,
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.tRASmax = 70,
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.tFAW = 50
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};
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/*
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* Min tCK values specified by JESD209-2
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* Min tCK specifies the minimum duration of some AC timing parameters in terms
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* of the number of cycles. If the calculated number of cycles based on the
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* absolute time value is less than the min tCK value, min tCK value should
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* be used instead. This typically happens at low frequencies.
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*/
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static const struct lpddr2_min_tck min_tck_jedec = {
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.tRL = 3,
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.tRP_AB = 3,
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.tRCD = 3,
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.tWR = 3,
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.tRAS_MIN = 3,
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.tRRD = 2,
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.tWTR = 2,
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.tXP = 2,
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.tRTP = 2,
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.tCKE = 3,
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.tCKESR = 3,
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.tFAW = 8
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};
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static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
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&timings_jedec_200_mhz,
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&timings_jedec_400_mhz
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};
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const struct lpddr2_device_timings jedec_default_timings = {
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.ac_timings = jedec_ac_timings,
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.min_tck = &min_tck_jedec
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};
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void emif_get_device_timings(u32 emif_nr,
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const struct lpddr2_device_timings **cs0_device_timings,
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const struct lpddr2_device_timings **cs1_device_timings)
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{
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/* Assume Identical devices on EMIF1 & EMIF2 */
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*cs0_device_timings = &jedec_default_timings;
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*cs1_device_timings = &jedec_default_timings;
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}
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#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
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@@ -0,0 +1,461 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* HW data initialization for OMAP4
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* Sricharan R <r.sricharan@ti.com>
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*/
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#include <common.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/omap_common.h>
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#include <asm/arch/clock.h>
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#include <asm/omap_gpio.h>
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#include <asm/io.h>
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struct prcm_regs const **prcm =
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(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
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struct dplls const **dplls_data =
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(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
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struct vcores_data const **omap_vcores =
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(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
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struct omap_sys_ctrl_regs const **ctrl =
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(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
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/*
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* The M & N values in the following tables are created using the
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* following tool:
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* tools/omap/clocks_get_m_n.c
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* Please use this tool for creating the table for any new frequency.
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*/
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/*
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* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
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* OMAP4460 OPP_NOM frequency
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*/
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static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
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{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/*
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* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
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* OMAP4430 OPP_TURBO frequency
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* OMAP4470 OPP_NOM frequency
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*/
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static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/*
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* dpll locked at 1200 MHz - MPU clk at 600 MHz
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* OMAP4430 OPP_NOM frequency
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*/
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static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
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{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* OMAP4460 OPP_NOM frequency */
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/* OMAP4470 OPP_NOM (Low Power) frequency */
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static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* OMAP4430 ES1 OPP_NOM frequency */
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static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
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{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
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{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
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{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* OMAP4430 ES2.X OPP_NOM frequency */
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static const struct dpll_params
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core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
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{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
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{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
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{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
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{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
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{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
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{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
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{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
/* ABE M & N values with sys_clk as source */
|
||||
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
static const struct dpll_params
|
||||
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
|
||||
{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
#else
|
||||
/* ABE M & N values with 32K clock as source */
|
||||
static const struct dpll_params abe_dpll_params_32k_196608khz = {
|
||||
750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
|
||||
{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
struct dplls omap4430_dplls_es1 = {
|
||||
.mpu = mpu_dpll_params_1200mhz,
|
||||
.core = core_dpll_params_es1_1524mhz,
|
||||
.per = per_dpll_params_1536mhz,
|
||||
.iva = iva_dpll_params_1862mhz,
|
||||
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
.abe = abe_dpll_params_sysclk_196608khz,
|
||||
#else
|
||||
.abe = &abe_dpll_params_32k_196608khz,
|
||||
#endif
|
||||
.usb = usb_dpll_params_1920mhz,
|
||||
.ddr = NULL
|
||||
};
|
||||
|
||||
struct dplls omap4430_dplls_es20 = {
|
||||
.mpu = mpu_dpll_params_1200mhz,
|
||||
.core = core_dpll_params_es2_1600mhz_ddr200mhz,
|
||||
.per = per_dpll_params_1536mhz,
|
||||
.iva = iva_dpll_params_1862mhz,
|
||||
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
.abe = abe_dpll_params_sysclk_196608khz,
|
||||
#else
|
||||
.abe = &abe_dpll_params_32k_196608khz,
|
||||
#endif
|
||||
.usb = usb_dpll_params_1920mhz,
|
||||
.ddr = NULL
|
||||
};
|
||||
|
||||
struct dplls omap4430_dplls = {
|
||||
.mpu = mpu_dpll_params_1200mhz,
|
||||
.core = core_dpll_params_1600mhz,
|
||||
.per = per_dpll_params_1536mhz,
|
||||
.iva = iva_dpll_params_1862mhz,
|
||||
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
.abe = abe_dpll_params_sysclk_196608khz,
|
||||
#else
|
||||
.abe = &abe_dpll_params_32k_196608khz,
|
||||
#endif
|
||||
.usb = usb_dpll_params_1920mhz,
|
||||
.ddr = NULL
|
||||
};
|
||||
|
||||
struct dplls omap4460_dplls = {
|
||||
.mpu = mpu_dpll_params_1400mhz,
|
||||
.core = core_dpll_params_1600mhz,
|
||||
.per = per_dpll_params_1536mhz,
|
||||
.iva = iva_dpll_params_1862mhz,
|
||||
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
.abe = abe_dpll_params_sysclk_196608khz,
|
||||
#else
|
||||
.abe = &abe_dpll_params_32k_196608khz,
|
||||
#endif
|
||||
.usb = usb_dpll_params_1920mhz,
|
||||
.ddr = NULL
|
||||
};
|
||||
|
||||
struct dplls omap4470_dplls = {
|
||||
.mpu = mpu_dpll_params_1600mhz,
|
||||
.core = core_dpll_params_1600mhz,
|
||||
.per = per_dpll_params_1536mhz,
|
||||
.iva = iva_dpll_params_1862mhz,
|
||||
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
.abe = abe_dpll_params_sysclk_196608khz,
|
||||
#else
|
||||
.abe = &abe_dpll_params_32k_196608khz,
|
||||
#endif
|
||||
.usb = usb_dpll_params_1920mhz,
|
||||
.ddr = NULL
|
||||
};
|
||||
|
||||
struct pmic_data twl6030_4430es1 = {
|
||||
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
|
||||
.step = 12660, /* 12.66 mV represented in uV */
|
||||
/* The code starts at 1 not 0 */
|
||||
.start_code = 1,
|
||||
.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
|
||||
.pmic_bus_init = sri2c_init,
|
||||
.pmic_write = omap_vc_bypass_send_value,
|
||||
};
|
||||
|
||||
/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
|
||||
struct pmic_data twl6030 = {
|
||||
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
|
||||
.step = 12660, /* 12.66 mV represented in uV */
|
||||
/* The code starts at 1 not 0 */
|
||||
.start_code = 1,
|
||||
.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
|
||||
.pmic_bus_init = sri2c_init,
|
||||
.pmic_write = omap_vc_bypass_send_value,
|
||||
};
|
||||
|
||||
struct pmic_data tps62361 = {
|
||||
.base_offset = TPS62361_BASE_VOLT_MV,
|
||||
.step = 10000, /* 10 mV represented in uV */
|
||||
.start_code = 0,
|
||||
.gpio = TPS62361_VSEL0_GPIO,
|
||||
.gpio_en = 1,
|
||||
.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
|
||||
.pmic_bus_init = sri2c_init,
|
||||
.pmic_write = omap_vc_bypass_send_value,
|
||||
};
|
||||
|
||||
struct vcores_data omap4430_volts_es1 = {
|
||||
.mpu.value[OPP_NOM] = 1325,
|
||||
.mpu.addr = SMPS_REG_ADDR_VCORE1,
|
||||
.mpu.pmic = &twl6030_4430es1,
|
||||
|
||||
.core.value[OPP_NOM] = 1200,
|
||||
.core.addr = SMPS_REG_ADDR_VCORE3,
|
||||
.core.pmic = &twl6030_4430es1,
|
||||
|
||||
.mm.value[OPP_NOM] = 1200,
|
||||
.mm.addr = SMPS_REG_ADDR_VCORE2,
|
||||
.mm.pmic = &twl6030_4430es1,
|
||||
};
|
||||
|
||||
struct vcores_data omap4430_volts = {
|
||||
.mpu.value[OPP_NOM] = 1325,
|
||||
.mpu.addr = SMPS_REG_ADDR_VCORE1,
|
||||
.mpu.pmic = &twl6030,
|
||||
|
||||
.core.value[OPP_NOM] = 1200,
|
||||
.core.addr = SMPS_REG_ADDR_VCORE3,
|
||||
.core.pmic = &twl6030,
|
||||
|
||||
.mm.value[OPP_NOM] = 1200,
|
||||
.mm.addr = SMPS_REG_ADDR_VCORE2,
|
||||
.mm.pmic = &twl6030,
|
||||
};
|
||||
|
||||
struct vcores_data omap4460_volts = {
|
||||
.mpu.value[OPP_NOM] = 1203,
|
||||
.mpu.addr = TPS62361_REG_ADDR_SET1,
|
||||
.mpu.pmic = &tps62361,
|
||||
|
||||
.core.value[OPP_NOM] = 1200,
|
||||
.core.addr = SMPS_REG_ADDR_VCORE1,
|
||||
.core.pmic = &twl6030,
|
||||
|
||||
.mm.value[OPP_NOM] = 1200,
|
||||
.mm.addr = SMPS_REG_ADDR_VCORE2,
|
||||
.mm.pmic = &twl6030,
|
||||
};
|
||||
|
||||
/*
|
||||
* Take closest integer part of the mV value corresponding to a TWL6032 SMPS
|
||||
* voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
|
||||
*/
|
||||
struct vcores_data omap4470_volts = {
|
||||
.mpu.value[OPP_NOM] = 1202,
|
||||
.mpu.addr = SMPS_REG_ADDR_SMPS1,
|
||||
.mpu.pmic = &twl6030,
|
||||
|
||||
.core.value[OPP_NOM] = 1126,
|
||||
.core.addr = SMPS_REG_ADDR_SMPS2,
|
||||
.core.pmic = &twl6030,
|
||||
|
||||
.mm.value[OPP_NOM] = 1139,
|
||||
.mm.addr = SMPS_REG_ADDR_SMPS5,
|
||||
.mm.pmic = &twl6030,
|
||||
};
|
||||
|
||||
/*
|
||||
* Enable essential clock domains, modules and
|
||||
* do some additional special settings needed
|
||||
*/
|
||||
void enable_basic_clocks(void)
|
||||
{
|
||||
u32 const clk_domains_essential[] = {
|
||||
(*prcm)->cm_l4per_clkstctrl,
|
||||
(*prcm)->cm_l3init_clkstctrl,
|
||||
(*prcm)->cm_memif_clkstctrl,
|
||||
(*prcm)->cm_l4cfg_clkstctrl,
|
||||
0
|
||||
};
|
||||
|
||||
u32 const clk_modules_hw_auto_essential[] = {
|
||||
(*prcm)->cm_l3_gpmc_clkctrl,
|
||||
(*prcm)->cm_memif_emif_1_clkctrl,
|
||||
(*prcm)->cm_memif_emif_2_clkctrl,
|
||||
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
|
||||
(*prcm)->cm_wkup_gpio1_clkctrl,
|
||||
(*prcm)->cm_l4per_gpio2_clkctrl,
|
||||
(*prcm)->cm_l4per_gpio3_clkctrl,
|
||||
(*prcm)->cm_l4per_gpio4_clkctrl,
|
||||
(*prcm)->cm_l4per_gpio5_clkctrl,
|
||||
(*prcm)->cm_l4per_gpio6_clkctrl,
|
||||
0
|
||||
};
|
||||
|
||||
u32 const clk_modules_explicit_en_essential[] = {
|
||||
(*prcm)->cm_wkup_gptimer1_clkctrl,
|
||||
(*prcm)->cm_l3init_hsmmc1_clkctrl,
|
||||
(*prcm)->cm_l3init_hsmmc2_clkctrl,
|
||||
(*prcm)->cm_l4per_gptimer2_clkctrl,
|
||||
(*prcm)->cm_wkup_wdtimer2_clkctrl,
|
||||
(*prcm)->cm_l4per_uart3_clkctrl,
|
||||
(*prcm)->cm_l4per_i2c1_clkctrl,
|
||||
(*prcm)->cm_l4per_i2c2_clkctrl,
|
||||
(*prcm)->cm_l4per_i2c3_clkctrl,
|
||||
(*prcm)->cm_l4per_i2c4_clkctrl,
|
||||
0
|
||||
};
|
||||
|
||||
/* Enable optional additional functional clock for GPIO4 */
|
||||
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
|
||||
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
|
||||
|
||||
/* Enable 96 MHz clock for MMC1 & MMC2 */
|
||||
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
|
||||
HSMMC_CLKCTRL_CLKSEL_MASK);
|
||||
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
|
||||
HSMMC_CLKCTRL_CLKSEL_MASK);
|
||||
|
||||
/* Select 32KHz clock as the source of GPTIMER1 */
|
||||
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
|
||||
GPTIMER1_CLKCTRL_CLKSEL_MASK);
|
||||
|
||||
/* Enable optional 48M functional clock for USB PHY */
|
||||
setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
|
||||
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
|
||||
|
||||
/* Enable 32 KHz clock for USB PHY */
|
||||
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
|
||||
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
|
||||
|
||||
do_enable_clocks(clk_domains_essential,
|
||||
clk_modules_hw_auto_essential,
|
||||
clk_modules_explicit_en_essential,
|
||||
1);
|
||||
}
|
||||
|
||||
void enable_basic_uboot_clocks(void)
|
||||
{
|
||||
u32 const clk_domains_essential[] = {
|
||||
0
|
||||
};
|
||||
|
||||
u32 const clk_modules_hw_auto_essential[] = {
|
||||
(*prcm)->cm_l3init_hsusbotg_clkctrl,
|
||||
(*prcm)->cm_l3init_usbphy_clkctrl,
|
||||
(*prcm)->cm_clksel_usb_60mhz,
|
||||
(*prcm)->cm_l3init_hsusbtll_clkctrl,
|
||||
0
|
||||
};
|
||||
|
||||
u32 const clk_modules_explicit_en_essential[] = {
|
||||
(*prcm)->cm_l4per_mcspi1_clkctrl,
|
||||
(*prcm)->cm_l3init_hsusbhost_clkctrl,
|
||||
0
|
||||
};
|
||||
|
||||
do_enable_clocks(clk_domains_essential,
|
||||
clk_modules_hw_auto_essential,
|
||||
clk_modules_explicit_en_essential,
|
||||
1);
|
||||
}
|
||||
|
||||
void hw_data_init(void)
|
||||
{
|
||||
u32 omap_rev = omap_revision();
|
||||
|
||||
(*prcm) = &omap4_prcm;
|
||||
|
||||
switch (omap_rev) {
|
||||
|
||||
case OMAP4430_ES1_0:
|
||||
*dplls_data = &omap4430_dplls_es1;
|
||||
*omap_vcores = &omap4430_volts_es1;
|
||||
break;
|
||||
|
||||
case OMAP4430_ES2_0:
|
||||
*dplls_data = &omap4430_dplls_es20;
|
||||
*omap_vcores = &omap4430_volts;
|
||||
break;
|
||||
|
||||
case OMAP4430_ES2_1:
|
||||
case OMAP4430_ES2_2:
|
||||
case OMAP4430_ES2_3:
|
||||
*dplls_data = &omap4430_dplls;
|
||||
*omap_vcores = &omap4430_volts;
|
||||
break;
|
||||
|
||||
case OMAP4460_ES1_0:
|
||||
case OMAP4460_ES1_1:
|
||||
*dplls_data = &omap4460_dplls;
|
||||
*omap_vcores = &omap4460_volts;
|
||||
break;
|
||||
|
||||
case OMAP4470_ES1_0:
|
||||
*dplls_data = &omap4470_dplls;
|
||||
*omap_vcores = &omap4470_volts;
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("\n INVALID OMAP REVISION ");
|
||||
}
|
||||
|
||||
*ctrl = &omap4_ctrl;
|
||||
}
|
||||
@@ -0,0 +1,187 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
*
|
||||
* Common functions for OMAP4 based boards
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
* Steve Sakoman <steve@sakoman.com>
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <palmas.h>
|
||||
#include <asm/armv7.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/emif.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/omap_common.h>
|
||||
|
||||
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
|
||||
|
||||
static const struct gpio_bank gpio_bank_44xx[6] = {
|
||||
{ (void *)OMAP44XX_GPIO1_BASE },
|
||||
{ (void *)OMAP44XX_GPIO2_BASE },
|
||||
{ (void *)OMAP44XX_GPIO3_BASE },
|
||||
{ (void *)OMAP44XX_GPIO4_BASE },
|
||||
{ (void *)OMAP44XX_GPIO5_BASE },
|
||||
{ (void *)OMAP44XX_GPIO6_BASE },
|
||||
};
|
||||
|
||||
const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/*
|
||||
* Some tuning of IOs for optimal power and performance
|
||||
*/
|
||||
void do_io_settings(void)
|
||||
{
|
||||
u32 lpddr2io;
|
||||
|
||||
u32 omap4_rev = omap_revision();
|
||||
|
||||
if (omap4_rev == OMAP4430_ES1_0)
|
||||
lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
|
||||
else if (omap4_rev == OMAP4430_ES2_0)
|
||||
lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
|
||||
else
|
||||
lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
|
||||
|
||||
/* EMIF1 */
|
||||
writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
|
||||
writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
|
||||
/* No pull for GR10 as per hw team's recommendation */
|
||||
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
|
||||
(*ctrl)->control_lpddr2io1_2);
|
||||
writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
|
||||
|
||||
/* EMIF2 */
|
||||
writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
|
||||
writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
|
||||
/* No pull for GR10 as per hw team's recommendation */
|
||||
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
|
||||
(*ctrl)->control_lpddr2io2_2);
|
||||
writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
|
||||
|
||||
/*
|
||||
* Some of these settings (TRIM values) come from eFuse and are
|
||||
* in turn programmed in the eFuse at manufacturing time after
|
||||
* calibration of the device. Do the software over-ride only if
|
||||
* the device is not correctly trimmed
|
||||
*/
|
||||
if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
|
||||
|
||||
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
|
||||
(*ctrl)->control_ldosram_iva_voltage_ctrl);
|
||||
|
||||
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
|
||||
(*ctrl)->control_ldosram_mpu_voltage_ctrl);
|
||||
|
||||
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
|
||||
(*ctrl)->control_ldosram_core_voltage_ctrl);
|
||||
}
|
||||
|
||||
/*
|
||||
* Over-ride the register
|
||||
* i. unconditionally for all 4430
|
||||
* ii. only if un-trimmed for 4460
|
||||
*/
|
||||
if (!readl((*ctrl)->control_efuse_1))
|
||||
writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
|
||||
|
||||
if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
|
||||
writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
|
||||
}
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
/* dummy fuction for omap4 */
|
||||
void config_data_eye_leveling_samples(u32 emif_base)
|
||||
{
|
||||
}
|
||||
|
||||
void init_omap_revision(void)
|
||||
{
|
||||
/*
|
||||
* For some of the ES2/ES1 boards ID_CODE is not reliable:
|
||||
* Also, ES1 and ES2 have different ARM revisions
|
||||
* So use ARM revision for identification
|
||||
*/
|
||||
unsigned int arm_rev = cortex_rev();
|
||||
|
||||
switch (arm_rev) {
|
||||
case MIDR_CORTEX_A9_R0P1:
|
||||
*omap_si_rev = OMAP4430_ES1_0;
|
||||
break;
|
||||
case MIDR_CORTEX_A9_R1P2:
|
||||
switch (readl(CONTROL_ID_CODE)) {
|
||||
case OMAP4_CONTROL_ID_CODE_ES2_0:
|
||||
*omap_si_rev = OMAP4430_ES2_0;
|
||||
break;
|
||||
case OMAP4_CONTROL_ID_CODE_ES2_1:
|
||||
*omap_si_rev = OMAP4430_ES2_1;
|
||||
break;
|
||||
case OMAP4_CONTROL_ID_CODE_ES2_2:
|
||||
*omap_si_rev = OMAP4430_ES2_2;
|
||||
break;
|
||||
default:
|
||||
*omap_si_rev = OMAP4430_ES2_0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MIDR_CORTEX_A9_R1P3:
|
||||
*omap_si_rev = OMAP4430_ES2_3;
|
||||
break;
|
||||
case MIDR_CORTEX_A9_R2P10:
|
||||
switch (readl(CONTROL_ID_CODE)) {
|
||||
case OMAP4470_CONTROL_ID_CODE_ES1_0:
|
||||
*omap_si_rev = OMAP4470_ES1_0;
|
||||
break;
|
||||
case OMAP4460_CONTROL_ID_CODE_ES1_1:
|
||||
*omap_si_rev = OMAP4460_ES1_1;
|
||||
break;
|
||||
case OMAP4460_CONTROL_ID_CODE_ES1_0:
|
||||
default:
|
||||
*omap_si_rev = OMAP4460_ES1_0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
*omap_si_rev = OMAP4430_SILICON_ID_INVALID;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void omap_die_id(unsigned int *die_id)
|
||||
{
|
||||
die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
|
||||
die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
|
||||
die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
|
||||
die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SYS_L2CACHE_OFF
|
||||
void v7_outer_cache_enable(void)
|
||||
{
|
||||
omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
|
||||
}
|
||||
|
||||
void v7_outer_cache_disable(void)
|
||||
{
|
||||
omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
|
||||
}
|
||||
#endif /* !CONFIG_SYS_L2CACHE_OFF */
|
||||
|
||||
void vmmc_pbias_config(uint voltage)
|
||||
{
|
||||
u32 value = 0;
|
||||
|
||||
value = readl((*ctrl)->control_pbiaslite);
|
||||
value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
|
||||
writel(value, (*ctrl)->control_pbiaslite);
|
||||
value = readl((*ctrl)->control_pbiaslite);
|
||||
value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
|
||||
writel(value, (*ctrl)->control_pbiaslite);
|
||||
}
|
||||
@@ -0,0 +1,306 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
*
|
||||
* HW regs data for OMAP4
|
||||
*
|
||||
* (C) Copyright 2013
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Sricharan R <r.sricharan@ti.com>
|
||||
*/
|
||||
|
||||
#include <asm/omap_common.h>
|
||||
|
||||
struct prcm_regs const omap4_prcm = {
|
||||
/* cm1.ckgen */
|
||||
.cm_clksel_core = 0x4a004100,
|
||||
.cm_clksel_abe = 0x4a004108,
|
||||
.cm_dll_ctrl = 0x4a004110,
|
||||
.cm_clkmode_dpll_core = 0x4a004120,
|
||||
.cm_idlest_dpll_core = 0x4a004124,
|
||||
.cm_autoidle_dpll_core = 0x4a004128,
|
||||
.cm_clksel_dpll_core = 0x4a00412c,
|
||||
.cm_div_m2_dpll_core = 0x4a004130,
|
||||
.cm_div_m3_dpll_core = 0x4a004134,
|
||||
.cm_div_m4_dpll_core = 0x4a004138,
|
||||
.cm_div_m5_dpll_core = 0x4a00413c,
|
||||
.cm_div_m6_dpll_core = 0x4a004140,
|
||||
.cm_div_m7_dpll_core = 0x4a004144,
|
||||
.cm_ssc_deltamstep_dpll_core = 0x4a004148,
|
||||
.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
|
||||
.cm_emu_override_dpll_core = 0x4a004150,
|
||||
.cm_clkmode_dpll_mpu = 0x4a004160,
|
||||
.cm_idlest_dpll_mpu = 0x4a004164,
|
||||
.cm_autoidle_dpll_mpu = 0x4a004168,
|
||||
.cm_clksel_dpll_mpu = 0x4a00416c,
|
||||
.cm_div_m2_dpll_mpu = 0x4a004170,
|
||||
.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
|
||||
.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
|
||||
.cm_bypclk_dpll_mpu = 0x4a00419c,
|
||||
.cm_clkmode_dpll_iva = 0x4a0041a0,
|
||||
.cm_idlest_dpll_iva = 0x4a0041a4,
|
||||
.cm_autoidle_dpll_iva = 0x4a0041a8,
|
||||
.cm_clksel_dpll_iva = 0x4a0041ac,
|
||||
.cm_div_m4_dpll_iva = 0x4a0041b8,
|
||||
.cm_div_m5_dpll_iva = 0x4a0041bc,
|
||||
.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
|
||||
.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
|
||||
.cm_bypclk_dpll_iva = 0x4a0041dc,
|
||||
.cm_clkmode_dpll_abe = 0x4a0041e0,
|
||||
.cm_idlest_dpll_abe = 0x4a0041e4,
|
||||
.cm_autoidle_dpll_abe = 0x4a0041e8,
|
||||
.cm_clksel_dpll_abe = 0x4a0041ec,
|
||||
.cm_div_m2_dpll_abe = 0x4a0041f0,
|
||||
.cm_div_m3_dpll_abe = 0x4a0041f4,
|
||||
.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
|
||||
.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
|
||||
.cm_clkmode_dpll_ddrphy = 0x4a004220,
|
||||
.cm_idlest_dpll_ddrphy = 0x4a004224,
|
||||
.cm_autoidle_dpll_ddrphy = 0x4a004228,
|
||||
.cm_clksel_dpll_ddrphy = 0x4a00422c,
|
||||
.cm_div_m2_dpll_ddrphy = 0x4a004230,
|
||||
.cm_div_m4_dpll_ddrphy = 0x4a004238,
|
||||
.cm_div_m5_dpll_ddrphy = 0x4a00423c,
|
||||
.cm_div_m6_dpll_ddrphy = 0x4a004240,
|
||||
.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
|
||||
.cm_shadow_freq_config1 = 0x4a004260,
|
||||
.cm_mpu_mpu_clkctrl = 0x4a004320,
|
||||
|
||||
/* cm1.dsp */
|
||||
.cm_dsp_clkstctrl = 0x4a004400,
|
||||
.cm_dsp_dsp_clkctrl = 0x4a004420,
|
||||
|
||||
/* cm1.abe */
|
||||
.cm1_abe_clkstctrl = 0x4a004500,
|
||||
.cm1_abe_l4abe_clkctrl = 0x4a004520,
|
||||
.cm1_abe_aess_clkctrl = 0x4a004528,
|
||||
.cm1_abe_pdm_clkctrl = 0x4a004530,
|
||||
.cm1_abe_dmic_clkctrl = 0x4a004538,
|
||||
.cm1_abe_mcasp_clkctrl = 0x4a004540,
|
||||
.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
|
||||
.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
|
||||
.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
|
||||
.cm1_abe_slimbus_clkctrl = 0x4a004560,
|
||||
.cm1_abe_timer5_clkctrl = 0x4a004568,
|
||||
.cm1_abe_timer6_clkctrl = 0x4a004570,
|
||||
.cm1_abe_timer7_clkctrl = 0x4a004578,
|
||||
.cm1_abe_timer8_clkctrl = 0x4a004580,
|
||||
.cm1_abe_wdt3_clkctrl = 0x4a004588,
|
||||
|
||||
/* cm2.ckgen */
|
||||
.cm_clksel_mpu_m3_iss_root = 0x4a008100,
|
||||
.cm_clksel_usb_60mhz = 0x4a008104,
|
||||
.cm_scale_fclk = 0x4a008108,
|
||||
.cm_core_dvfs_perf1 = 0x4a008110,
|
||||
.cm_core_dvfs_perf2 = 0x4a008114,
|
||||
.cm_core_dvfs_perf3 = 0x4a008118,
|
||||
.cm_core_dvfs_perf4 = 0x4a00811c,
|
||||
.cm_core_dvfs_current = 0x4a008124,
|
||||
.cm_iva_dvfs_perf_tesla = 0x4a008128,
|
||||
.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
|
||||
.cm_iva_dvfs_perf_abe = 0x4a008130,
|
||||
.cm_iva_dvfs_current = 0x4a008138,
|
||||
.cm_clkmode_dpll_per = 0x4a008140,
|
||||
.cm_idlest_dpll_per = 0x4a008144,
|
||||
.cm_autoidle_dpll_per = 0x4a008148,
|
||||
.cm_clksel_dpll_per = 0x4a00814c,
|
||||
.cm_div_m2_dpll_per = 0x4a008150,
|
||||
.cm_div_m3_dpll_per = 0x4a008154,
|
||||
.cm_div_m4_dpll_per = 0x4a008158,
|
||||
.cm_div_m5_dpll_per = 0x4a00815c,
|
||||
.cm_div_m6_dpll_per = 0x4a008160,
|
||||
.cm_div_m7_dpll_per = 0x4a008164,
|
||||
.cm_ssc_deltamstep_dpll_per = 0x4a008168,
|
||||
.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
|
||||
.cm_emu_override_dpll_per = 0x4a008170,
|
||||
.cm_clkmode_dpll_usb = 0x4a008180,
|
||||
.cm_idlest_dpll_usb = 0x4a008184,
|
||||
.cm_autoidle_dpll_usb = 0x4a008188,
|
||||
.cm_clksel_dpll_usb = 0x4a00818c,
|
||||
.cm_div_m2_dpll_usb = 0x4a008190,
|
||||
.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
|
||||
.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
|
||||
.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
|
||||
.cm_clkmode_dpll_unipro = 0x4a0081c0,
|
||||
.cm_idlest_dpll_unipro = 0x4a0081c4,
|
||||
.cm_autoidle_dpll_unipro = 0x4a0081c8,
|
||||
.cm_clksel_dpll_unipro = 0x4a0081cc,
|
||||
.cm_div_m2_dpll_unipro = 0x4a0081d0,
|
||||
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
|
||||
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
|
||||
.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
|
||||
|
||||
/* cm2.core */
|
||||
.cm_l3_1_clkstctrl = 0x4a008700,
|
||||
.cm_l3_1_dynamicdep = 0x4a008708,
|
||||
.cm_l3_1_l3_1_clkctrl = 0x4a008720,
|
||||
.cm_l3_2_clkstctrl = 0x4a008800,
|
||||
.cm_l3_2_dynamicdep = 0x4a008808,
|
||||
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
|
||||
.cm_l3_gpmc_clkctrl = 0x4a008828,
|
||||
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
|
||||
.cm_mpu_m3_clkstctrl = 0x4a008900,
|
||||
.cm_mpu_m3_staticdep = 0x4a008904,
|
||||
.cm_mpu_m3_dynamicdep = 0x4a008908,
|
||||
.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
|
||||
.cm_sdma_clkstctrl = 0x4a008a00,
|
||||
.cm_sdma_staticdep = 0x4a008a04,
|
||||
.cm_sdma_dynamicdep = 0x4a008a08,
|
||||
.cm_sdma_sdma_clkctrl = 0x4a008a20,
|
||||
.cm_memif_clkstctrl = 0x4a008b00,
|
||||
.cm_memif_dmm_clkctrl = 0x4a008b20,
|
||||
.cm_memif_emif_fw_clkctrl = 0x4a008b28,
|
||||
.cm_memif_emif_1_clkctrl = 0x4a008b30,
|
||||
.cm_memif_emif_2_clkctrl = 0x4a008b38,
|
||||
.cm_memif_dll_clkctrl = 0x4a008b40,
|
||||
.cm_memif_emif_h1_clkctrl = 0x4a008b50,
|
||||
.cm_memif_emif_h2_clkctrl = 0x4a008b58,
|
||||
.cm_memif_dll_h_clkctrl = 0x4a008b60,
|
||||
.cm_c2c_clkstctrl = 0x4a008c00,
|
||||
.cm_c2c_staticdep = 0x4a008c04,
|
||||
.cm_c2c_dynamicdep = 0x4a008c08,
|
||||
.cm_c2c_sad2d_clkctrl = 0x4a008c20,
|
||||
.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
|
||||
.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
|
||||
.cm_l4cfg_clkstctrl = 0x4a008d00,
|
||||
.cm_l4cfg_dynamicdep = 0x4a008d08,
|
||||
.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
|
||||
.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
|
||||
.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
|
||||
.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
|
||||
.cm_l3instr_clkstctrl = 0x4a008e00,
|
||||
.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
|
||||
.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
|
||||
.cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
|
||||
.cm_ivahd_clkstctrl = 0x4a008f00,
|
||||
|
||||
/* cm2.ivahd */
|
||||
.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
|
||||
.cm_ivahd_sl2_clkctrl = 0x4a008f28,
|
||||
|
||||
/* cm2.cam */
|
||||
.cm_cam_clkstctrl = 0x4a009000,
|
||||
.cm_cam_iss_clkctrl = 0x4a009020,
|
||||
.cm_cam_fdif_clkctrl = 0x4a009028,
|
||||
|
||||
/* cm2.dss */
|
||||
.cm_dss_clkstctrl = 0x4a009100,
|
||||
.cm_dss_dss_clkctrl = 0x4a009120,
|
||||
|
||||
/* cm2.sgx */
|
||||
.cm_sgx_clkstctrl = 0x4a009200,
|
||||
.cm_sgx_sgx_clkctrl = 0x4a009220,
|
||||
|
||||
/* cm2.l3init */
|
||||
.cm_l3init_clkstctrl = 0x4a009300,
|
||||
.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
|
||||
.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
|
||||
.cm_l3init_hsi_clkctrl = 0x4a009338,
|
||||
.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
|
||||
.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
|
||||
.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
|
||||
.cm_l3init_p1500_clkctrl = 0x4a009378,
|
||||
.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
|
||||
.cm_l3init_usbphy_clkctrl = 0x4a0093e0,
|
||||
|
||||
/* cm2.l4per */
|
||||
.cm_l4per_clkstctrl = 0x4a009400,
|
||||
.cm_l4per_dynamicdep = 0x4a009408,
|
||||
.cm_l4per_adc_clkctrl = 0x4a009420,
|
||||
.cm_l4per_gptimer10_clkctrl = 0x4a009428,
|
||||
.cm_l4per_gptimer11_clkctrl = 0x4a009430,
|
||||
.cm_l4per_gptimer2_clkctrl = 0x4a009438,
|
||||
.cm_l4per_gptimer3_clkctrl = 0x4a009440,
|
||||
.cm_l4per_gptimer4_clkctrl = 0x4a009448,
|
||||
.cm_l4per_gptimer9_clkctrl = 0x4a009450,
|
||||
.cm_l4per_elm_clkctrl = 0x4a009458,
|
||||
.cm_l4per_gpio2_clkctrl = 0x4a009460,
|
||||
.cm_l4per_gpio3_clkctrl = 0x4a009468,
|
||||
.cm_l4per_gpio4_clkctrl = 0x4a009470,
|
||||
.cm_l4per_gpio5_clkctrl = 0x4a009478,
|
||||
.cm_l4per_gpio6_clkctrl = 0x4a009480,
|
||||
.cm_l4per_hdq1w_clkctrl = 0x4a009488,
|
||||
.cm_l4per_hecc1_clkctrl = 0x4a009490,
|
||||
.cm_l4per_hecc2_clkctrl = 0x4a009498,
|
||||
.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
|
||||
.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
|
||||
.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
|
||||
.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
|
||||
.cm_l4per_l4per_clkctrl = 0x4a0094c0,
|
||||
.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
|
||||
.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
|
||||
.cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
|
||||
.cm_l4per_mgate_clkctrl = 0x4a0094e8,
|
||||
.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
|
||||
.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
|
||||
.cm_l4per_mcspi3_clkctrl = 0x4a009500,
|
||||
.cm_l4per_mcspi4_clkctrl = 0x4a009508,
|
||||
.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
|
||||
.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
|
||||
.cm_l4per_msprohg_clkctrl = 0x4a009530,
|
||||
.cm_l4per_slimbus2_clkctrl = 0x4a009538,
|
||||
.cm_l4per_uart1_clkctrl = 0x4a009540,
|
||||
.cm_l4per_uart2_clkctrl = 0x4a009548,
|
||||
.cm_l4per_uart3_clkctrl = 0x4a009550,
|
||||
.cm_l4per_uart4_clkctrl = 0x4a009558,
|
||||
.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
|
||||
.cm_l4per_i2c5_clkctrl = 0x4a009568,
|
||||
.cm_l4sec_clkstctrl = 0x4a009580,
|
||||
.cm_l4sec_staticdep = 0x4a009584,
|
||||
.cm_l4sec_dynamicdep = 0x4a009588,
|
||||
.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
|
||||
.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
|
||||
.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
|
||||
.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
|
||||
.cm_l4sec_rng_clkctrl = 0x4a0095c0,
|
||||
.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
|
||||
.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
|
||||
|
||||
/* l4 wkup regs */
|
||||
.cm_abe_pll_ref_clksel = 0x4a30610c,
|
||||
.cm_sys_clksel = 0x4a306110,
|
||||
.cm_wkup_clkstctrl = 0x4a307800,
|
||||
.cm_wkup_l4wkup_clkctrl = 0x4a307820,
|
||||
.cm_wkup_wdtimer1_clkctrl = 0x4a307828,
|
||||
.cm_wkup_wdtimer2_clkctrl = 0x4a307830,
|
||||
.cm_wkup_gpio1_clkctrl = 0x4a307838,
|
||||
.cm_wkup_gptimer1_clkctrl = 0x4a307840,
|
||||
.cm_wkup_gptimer12_clkctrl = 0x4a307848,
|
||||
.cm_wkup_synctimer_clkctrl = 0x4a307850,
|
||||
.cm_wkup_usim_clkctrl = 0x4a307858,
|
||||
.cm_wkup_sarram_clkctrl = 0x4a307860,
|
||||
.cm_wkup_keyboard_clkctrl = 0x4a307878,
|
||||
.cm_wkup_rtc_clkctrl = 0x4a307880,
|
||||
.cm_wkup_bandgap_clkctrl = 0x4a307888,
|
||||
.prm_vc_val_bypass = 0x4a307ba0,
|
||||
.prm_vc_cfg_channel = 0x4a307ba4,
|
||||
.prm_vc_cfg_i2c_mode = 0x4a307ba8,
|
||||
.prm_vc_cfg_i2c_clk = 0x4a307bac,
|
||||
};
|
||||
|
||||
struct omap_sys_ctrl_regs const omap4_ctrl = {
|
||||
.control_status = 0x4A0022C4,
|
||||
.control_std_fuse_die_id_0 = 0x4A002200,
|
||||
.control_std_fuse_die_id_1 = 0x4A002208,
|
||||
.control_std_fuse_die_id_2 = 0x4A00220C,
|
||||
.control_std_fuse_die_id_3 = 0x4A002210,
|
||||
.control_std_fuse_opp_bgap = 0x4a002260,
|
||||
.control_status = 0x4a0022c4,
|
||||
.control_ldosram_iva_voltage_ctrl = 0x4A002320,
|
||||
.control_ldosram_mpu_voltage_ctrl = 0x4A002324,
|
||||
.control_ldosram_core_voltage_ctrl = 0x4A002328,
|
||||
.control_usbotghs_ctrl = 0x4A00233C,
|
||||
.control_padconf_core_base = 0x4A100000,
|
||||
.control_pbiaslite = 0x4A100600,
|
||||
.control_lpddr2io1_0 = 0x4A100638,
|
||||
.control_lpddr2io1_1 = 0x4A10063C,
|
||||
.control_lpddr2io1_2 = 0x4A100640,
|
||||
.control_lpddr2io1_3 = 0x4A100644,
|
||||
.control_lpddr2io2_0 = 0x4A100648,
|
||||
.control_lpddr2io2_1 = 0x4A10064C,
|
||||
.control_lpddr2io2_2 = 0x4A100650,
|
||||
.control_lpddr2io2_3 = 0x4A100654,
|
||||
.control_efuse_1 = 0x4A100700,
|
||||
.control_efuse_2 = 0x4A100704,
|
||||
.control_padconf_wkup_base = 0x4A31E000,
|
||||
};
|
||||
@@ -0,0 +1,323 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Timing and Organization details of the Elpida parts used in OMAP4
|
||||
* SDPs and Panda
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*/
|
||||
|
||||
#include <asm/emif.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
/*
|
||||
* This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
|
||||
* SDP and Panda. Since the parts used and geometry are identical for
|
||||
* SDP and Panda for a given OMAP4 revision, this information is kept
|
||||
* here instead of being in board directory. However the key functions
|
||||
* exported are weakly linked so that they can be over-ridden in the board
|
||||
* directory if there is a OMAP4 board in the future that uses a different
|
||||
* memory device or geometry.
|
||||
*
|
||||
* For any new board with different memory devices over-ride one or more
|
||||
* of the following functions as per the CONFIG flags you intend to enable:
|
||||
* - emif_get_reg_dump()
|
||||
* - emif_get_dmm_regs()
|
||||
* - emif_get_device_details()
|
||||
* - emif_get_device_timings()
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
|
||||
|
||||
const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
|
||||
.sdram_config_init = 0x80000eb9,
|
||||
.sdram_config = 0x80001ab9,
|
||||
.ref_ctrl = 0x0000030c,
|
||||
.sdram_tim1 = 0x08648311,
|
||||
.sdram_tim2 = 0x101b06ca,
|
||||
.sdram_tim3 = 0x0048a19f,
|
||||
.read_idle_ctrl = 0x000501ff,
|
||||
.zq_config = 0x500b3214,
|
||||
.temp_alert_config = 0xd8016893,
|
||||
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
|
||||
.emif_ddr_phy_ctlr_1 = 0x049ff808
|
||||
};
|
||||
|
||||
const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
|
||||
.sdram_config_init = 0x80000eb1,
|
||||
.sdram_config = 0x80001ab1,
|
||||
.ref_ctrl = 0x000005cd,
|
||||
.sdram_tim1 = 0x10cb0622,
|
||||
.sdram_tim2 = 0x20350d52,
|
||||
.sdram_tim3 = 0x00b1431f,
|
||||
.read_idle_ctrl = 0x000501ff,
|
||||
.zq_config = 0x500b3214,
|
||||
.temp_alert_config = 0x58016893,
|
||||
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
|
||||
.emif_ddr_phy_ctlr_1 = 0x049ff418
|
||||
};
|
||||
|
||||
const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
|
||||
.sdram_config_init = 0x80800eb2,
|
||||
.sdram_config = 0x80801ab2,
|
||||
.ref_ctrl = 0x00000618,
|
||||
.sdram_tim1 = 0x10eb0662,
|
||||
.sdram_tim2 = 0x20370dd2,
|
||||
.sdram_tim3 = 0x00b1c33f,
|
||||
.read_idle_ctrl = 0x000501ff,
|
||||
.zq_config = 0x500b3215,
|
||||
.temp_alert_config = 0x58016893,
|
||||
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
|
||||
.emif_ddr_phy_ctlr_1 = 0x049ff418
|
||||
};
|
||||
|
||||
const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
|
||||
.sdram_config_init = 0x80000eb9,
|
||||
.sdram_config = 0x80001ab9,
|
||||
.ref_ctrl = 0x00000618,
|
||||
.sdram_tim1 = 0x10eb0662,
|
||||
.sdram_tim2 = 0x20370dd2,
|
||||
.sdram_tim3 = 0x00b1c33f,
|
||||
.read_idle_ctrl = 0x000501ff,
|
||||
.zq_config = 0xd00b3214,
|
||||
.temp_alert_config = 0xd8016893,
|
||||
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
|
||||
.emif_ddr_phy_ctlr_1 = 0x049ff418
|
||||
};
|
||||
|
||||
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
|
||||
.dmm_lisa_map_0 = 0xFF020100,
|
||||
.dmm_lisa_map_1 = 0,
|
||||
.dmm_lisa_map_2 = 0,
|
||||
.dmm_lisa_map_3 = 0x80540300,
|
||||
.is_ma_present = 0x0
|
||||
};
|
||||
|
||||
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
|
||||
.dmm_lisa_map_0 = 0xFF020100,
|
||||
.dmm_lisa_map_1 = 0,
|
||||
.dmm_lisa_map_2 = 0,
|
||||
.dmm_lisa_map_3 = 0x80640300,
|
||||
.is_ma_present = 0x0
|
||||
};
|
||||
|
||||
const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
|
||||
.dmm_lisa_map_0 = 0xFF020100,
|
||||
.dmm_lisa_map_1 = 0,
|
||||
.dmm_lisa_map_2 = 0,
|
||||
.dmm_lisa_map_3 = 0x80640300,
|
||||
.is_ma_present = 0x1
|
||||
};
|
||||
|
||||
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
|
||||
{
|
||||
u32 omap4_rev = omap_revision();
|
||||
|
||||
/* Same devices and geometry on both EMIFs */
|
||||
if (omap4_rev == OMAP4430_ES1_0)
|
||||
*regs = &emif_regs_elpida_380_mhz_1cs;
|
||||
else if (omap4_rev == OMAP4430_ES2_0)
|
||||
*regs = &emif_regs_elpida_200_mhz_2cs;
|
||||
else if (omap4_rev < OMAP4470_ES1_0)
|
||||
*regs = &emif_regs_elpida_400_mhz_2cs;
|
||||
else
|
||||
*regs = &emif_regs_elpida_400_mhz_1cs;
|
||||
}
|
||||
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
|
||||
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
|
||||
|
||||
static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
|
||||
**dmm_lisa_regs)
|
||||
{
|
||||
u32 omap_rev = omap_revision();
|
||||
|
||||
if (omap_rev == OMAP4430_ES1_0)
|
||||
*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
|
||||
else if (omap_rev < OMAP4460_ES1_0)
|
||||
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
|
||||
else
|
||||
*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
|
||||
}
|
||||
|
||||
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
|
||||
__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
|
||||
|
||||
#else
|
||||
|
||||
const struct lpddr2_device_details elpida_2G_S4_details = {
|
||||
.type = LPDDR2_TYPE_S4,
|
||||
.density = LPDDR2_DENSITY_2Gb,
|
||||
.io_width = LPDDR2_IO_WIDTH_32,
|
||||
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
|
||||
};
|
||||
|
||||
const struct lpddr2_device_details elpida_4G_S4_details = {
|
||||
.type = LPDDR2_TYPE_S4,
|
||||
.density = LPDDR2_DENSITY_4Gb,
|
||||
.io_width = LPDDR2_IO_WIDTH_32,
|
||||
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
|
||||
};
|
||||
|
||||
struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
|
||||
struct lpddr2_device_details *lpddr2_dev_details)
|
||||
{
|
||||
u32 omap_rev = omap_revision();
|
||||
|
||||
/* EMIF1 & EMIF2 have identical configuration */
|
||||
if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
|
||||
&& (cs == CS1)) {
|
||||
/* Nothing connected on CS1 for 4430/4470 ES1.0 */
|
||||
return NULL;
|
||||
} else if (omap_rev < OMAP4470_ES1_0) {
|
||||
/* In all other 4430/4460 cases Elpida 2G device */
|
||||
*lpddr2_dev_details = elpida_2G_S4_details;
|
||||
} else {
|
||||
/* 4470: 4G device */
|
||||
*lpddr2_dev_details = elpida_4G_S4_details;
|
||||
}
|
||||
return lpddr2_dev_details;
|
||||
}
|
||||
|
||||
struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
|
||||
struct lpddr2_device_details *lpddr2_dev_details)
|
||||
__attribute__((weak, alias("emif_get_device_details_sdp")));
|
||||
|
||||
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
|
||||
|
||||
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
|
||||
static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
|
||||
.max_freq = 400000000,
|
||||
.RL = 6,
|
||||
.tRPab = 21,
|
||||
.tRCD = 18,
|
||||
.tWR = 15,
|
||||
.tRASmin = 42,
|
||||
.tRRD = 10,
|
||||
.tWTRx2 = 15,
|
||||
.tXSR = 140,
|
||||
.tXPx2 = 15,
|
||||
.tRFCab = 130,
|
||||
.tRTPx2 = 15,
|
||||
.tCKE = 3,
|
||||
.tCKESR = 15,
|
||||
.tZQCS = 90,
|
||||
.tZQCL = 360,
|
||||
.tZQINIT = 1000,
|
||||
.tDQSCKMAXx2 = 11,
|
||||
.tRASmax = 70,
|
||||
.tFAW = 50
|
||||
};
|
||||
|
||||
static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
|
||||
.max_freq = 333000000,
|
||||
.RL = 5,
|
||||
.tRPab = 21,
|
||||
.tRCD = 18,
|
||||
.tWR = 15,
|
||||
.tRASmin = 42,
|
||||
.tRRD = 10,
|
||||
.tWTRx2 = 15,
|
||||
.tXSR = 140,
|
||||
.tXPx2 = 15,
|
||||
.tRFCab = 130,
|
||||
.tRTPx2 = 15,
|
||||
.tCKE = 3,
|
||||
.tCKESR = 15,
|
||||
.tZQCS = 90,
|
||||
.tZQCL = 360,
|
||||
.tZQINIT = 1000,
|
||||
.tDQSCKMAXx2 = 11,
|
||||
.tRASmax = 70,
|
||||
.tFAW = 50
|
||||
};
|
||||
|
||||
static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
|
||||
.max_freq = 200000000,
|
||||
.RL = 3,
|
||||
.tRPab = 21,
|
||||
.tRCD = 18,
|
||||
.tWR = 15,
|
||||
.tRASmin = 42,
|
||||
.tRRD = 10,
|
||||
.tWTRx2 = 20,
|
||||
.tXSR = 140,
|
||||
.tXPx2 = 15,
|
||||
.tRFCab = 130,
|
||||
.tRTPx2 = 15,
|
||||
.tCKE = 3,
|
||||
.tCKESR = 15,
|
||||
.tZQCS = 90,
|
||||
.tZQCL = 360,
|
||||
.tZQINIT = 1000,
|
||||
.tDQSCKMAXx2 = 11,
|
||||
.tRASmax = 70,
|
||||
.tFAW = 50
|
||||
};
|
||||
|
||||
static const struct lpddr2_min_tck min_tck_elpida = {
|
||||
.tRL = 3,
|
||||
.tRP_AB = 3,
|
||||
.tRCD = 3,
|
||||
.tWR = 3,
|
||||
.tRAS_MIN = 3,
|
||||
.tRRD = 2,
|
||||
.tWTR = 2,
|
||||
.tXP = 2,
|
||||
.tRTP = 2,
|
||||
.tCKE = 3,
|
||||
.tCKESR = 3,
|
||||
.tFAW = 8
|
||||
};
|
||||
|
||||
static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
|
||||
&timings_elpida_200_mhz,
|
||||
&timings_elpida_333_mhz,
|
||||
&timings_elpida_400_mhz
|
||||
};
|
||||
|
||||
const struct lpddr2_device_timings elpida_2G_S4_timings = {
|
||||
.ac_timings = elpida_ac_timings,
|
||||
.min_tck = &min_tck_elpida,
|
||||
};
|
||||
|
||||
void emif_get_device_timings_sdp(u32 emif_nr,
|
||||
const struct lpddr2_device_timings **cs0_device_timings,
|
||||
const struct lpddr2_device_timings **cs1_device_timings)
|
||||
{
|
||||
u32 omap_rev = omap_revision();
|
||||
|
||||
/* Identical devices on EMIF1 & EMIF2 */
|
||||
*cs0_device_timings = &elpida_2G_S4_timings;
|
||||
|
||||
if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
|
||||
*cs1_device_timings = NULL;
|
||||
else
|
||||
*cs1_device_timings = &elpida_2G_S4_timings;
|
||||
}
|
||||
|
||||
void emif_get_device_timings(u32 emif_nr,
|
||||
const struct lpddr2_device_timings **cs0_device_timings,
|
||||
const struct lpddr2_device_timings **cs1_device_timings)
|
||||
__attribute__((weak, alias("emif_get_device_timings_sdp")));
|
||||
|
||||
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
|
||||
|
||||
const struct lpddr2_mr_regs mr_regs = {
|
||||
.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
|
||||
.mr2 = 0x4,
|
||||
.mr3 = -1,
|
||||
.mr10 = MR10_ZQ_ZQINIT,
|
||||
.mr16 = MR16_REF_FULL_ARRAY
|
||||
};
|
||||
|
||||
void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
|
||||
{
|
||||
*regs = &mr_regs;
|
||||
}
|
||||
|
||||
__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user