GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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@@ -0,0 +1,38 @@
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if ROCKCHIP_RK3188
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config TARGET_ROCK
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bool "Radxa Rock"
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help
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Rock is a RK3188-based development board with 2 USB and 1 otg
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ports, HDMI, TV-out, micro-SD card, audio, WiFi and 100MBit
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Ethernet, It also includes on-board nand and 1GB of SDRAM.
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Expansion connectors provide access to display pins, I2C, SPI,
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UART and GPIOs.
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config ROCKCHIP_BOOT_MODE_REG
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default 0x20004040
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config SYS_SOC
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default "rk3188"
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config SYS_MALLOC_F_LEN
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default 0x0800
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config SPL_LIBCOMMON_SUPPORT
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default y
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config SPL_LIBGENERIC_SUPPORT
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default y
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config SPL_SERIAL_SUPPORT
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default y
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config TPL_LIBCOMMON_SUPPORT
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default y
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config TPL_LIBGENERIC_SUPPORT
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default y
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source "board/radxa/rock/Kconfig"
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endif
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@@ -0,0 +1,11 @@
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#
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# Copyright (c) 2015 Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifndef CONFIG_TPL_BUILD
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obj-y += clk_rk3188.o
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obj-y += rk3188.o
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obj-y += syscon_rk3188.o
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endif
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@@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <syscon.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3188.h>
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int rockchip_get_clk(struct udevice **devp)
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{
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return uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(rockchip_rk3188_cru), devp);
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}
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void *rockchip_get_cru(void)
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{
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struct rk3188_clk_priv *priv;
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struct udevice *dev;
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int ret;
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ret = rockchip_get_clk(&dev);
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if (ret)
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return ERR_PTR(ret);
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priv = dev_get_priv(dev);
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return priv->cru;
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}
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@@ -0,0 +1,120 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/grf_rk3188.h>
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#include <asm/arch-rockchip/hardware.h>
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#define GRF_BASE 0x20008000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@10214000",
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};
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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/* Enable early UART on the RK3188 */
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struct rk3188_grf * const grf = (void *)GRF_BASE;
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enum {
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = 3,
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GPIO1B1_GPIO = 0,
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GPIO1B1_UART2_SOUT,
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GPIO1B1_JTAG_TDO,
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GPIO1B0_SHIFT = 0,
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GPIO1B0_MASK = 3,
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GPIO1B0_GPIO = 0,
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GPIO1B0_UART2_SIN,
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GPIO1B0_JTAG_TDI,
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};
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK << GPIO1B1_SHIFT |
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GPIO1B0_MASK << GPIO1B0_SHIFT,
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GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
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GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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int arch_cpu_init(void)
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{
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struct rk3188_grf *grf;
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (IS_ERR(grf)) {
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pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
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return 0;
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}
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#ifdef CONFIG_ROCKCHIP_USB_UART
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rk_clrsetreg(&grf->uoc0_con[0],
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SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
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1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
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1 << COMMON_ON_N_SHIFT);
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rk_clrsetreg(&grf->uoc0_con[2],
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SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
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rk_clrsetreg(&grf->uoc0_con[3],
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OPMODE_MASK | XCVRSELECT_MASK |
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TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
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OPMODE_NODRIVING << OPMODE_SHIFT |
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XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
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1 << TERMSEL_FULLSPEED_SHIFT |
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1 << SUSPENDN_SHIFT);
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rk_clrsetreg(&grf->uoc0_con[0],
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BYPASSSEL_MASK | BYPASSDMEN_MASK,
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1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
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#endif
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/* enable noc remap to mimic legacy loaders */
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rk_clrsetreg(&grf->soc_con0,
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NOC_REMAP_MASK << NOC_REMAP_SHIFT,
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NOC_REMAP_MASK << NOC_REMAP_SHIFT);
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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static int setup_led(void)
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{
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#ifdef CONFIG_SPL_LED
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struct udevice *dev;
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char *led_name;
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int ret;
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led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
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if (!led_name)
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return 0;
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ret = led_get_by_label(led_name, &dev);
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if (ret) {
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debug("%s: get=%d\n", __func__, ret);
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return ret;
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}
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ret = led_set_on(dev, 1);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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void spl_board_init(void)
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{
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int ret;
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ret = setup_led();
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if (ret) {
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debug("LED ret=%d\n", ret);
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hang();
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}
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}
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#endif
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@@ -0,0 +1,54 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <syscon.h>
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#include <asm/arch-rockchip/clock.h>
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static const struct udevice_id rk3188_syscon_ids[] = {
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{ .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
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{ .compatible = "rockchip,rk3188-grf", .data = ROCKCHIP_SYSCON_GRF },
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{ .compatible = "rockchip,rk3188-pmu", .data = ROCKCHIP_SYSCON_PMU },
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{ }
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};
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U_BOOT_DRIVER(syscon_rk3188) = {
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.name = "rk3188_syscon",
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.id = UCLASS_SYSCON,
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.of_match = rk3188_syscon_ids,
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};
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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static int rk3188_syscon_bind_of_platdata(struct udevice *dev)
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{
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dev->driver_data = dev->driver->of_match->data;
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debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
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return 0;
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}
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U_BOOT_DRIVER(rockchip_rk3188_noc) = {
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.name = "rockchip_rk3188_noc",
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.id = UCLASS_SYSCON,
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.of_match = rk3188_syscon_ids,
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.bind = rk3188_syscon_bind_of_platdata,
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};
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U_BOOT_DRIVER(rockchip_rk3188_grf) = {
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.name = "rockchip_rk3188_grf",
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.id = UCLASS_SYSCON,
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.of_match = rk3188_syscon_ids + 1,
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.bind = rk3188_syscon_bind_of_platdata,
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};
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U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
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.name = "rockchip_rk3188_pmu",
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.id = UCLASS_SYSCON,
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.of_match = rk3188_syscon_ids + 2,
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.bind = rk3188_syscon_bind_of_platdata,
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};
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#endif
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