GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,196 @@
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if ROCKCHIP_RK3288
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choice
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prompt "RK3288 board select"
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config TARGET_CHROMEBOOK_JERRY
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bool "Google/Rockchip Veyron-Jerry Chromebook"
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select BOARD_LATE_INIT
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help
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Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
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HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
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WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
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the keyboard and battery functions.
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config TARGET_CHROMEBIT_MICKEY
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bool "Google/Rockchip Veyron-Mickey Chromebit"
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select BOARD_LATE_INIT
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help
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Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
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and WiFi. It has a separate power port and is designed to connect
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to the HDMI input of a monitor or TV. It has no internal battery.
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Typically a USB hub or wireless keyboard/touchpad is used to get
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keyboard and mouse access.
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config TARGET_CHROMEBOOK_MINNIE
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bool "Google/Rockchip Veyron-Minnie Chromebook"
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select BOARD_LATE_INIT
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help
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Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
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ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
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HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS
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EC (Cortex-M3) to provide access to the keyboard and battery
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functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
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internal MMC. The product name is ASUS Chromebook Flip.
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config TARGET_CHROMEBOOK_SPEEDY
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bool "Google/Rockchip Veyron-Speedy Chromebook"
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select BOARD_LATE_INIT
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help
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Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,
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micro HDMI, an 11.6 inch display, micro-SD card,
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HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS
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EC (Cortex-M3) to provide access to the keyboard and battery
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functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC.
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The product name is Asus Chromebook C201PA.
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config TARGET_EVB_RK3288
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bool "Evb-RK3288"
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select BOARD_LATE_INIT
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select TPL
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help
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EVB-RK3288 is a RK3288-based development board with 2 USB ports,
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HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
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also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
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provide access to display pins, I2C, SPI, UART and GPIOs.
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config TARGET_FENNEC_RK3288
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bool "Fennec-RK3288"
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select BOARD_LATE_INIT
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help
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Fennec is a RK3288-based development board with 2 USB ports,
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HDMI, micro-SD card, audio, WiFi and Gigabit Ethernet. It also
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includes on-board eMMC and 2GB of SDRAM. Expansion connectors
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provide access to display pins, I2C, SPI, UART and GPIOs.
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config TARGET_FIREFLY_RK3288
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bool "Firefly-RK3288"
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select BOARD_LATE_INIT
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select SPL_BOARD_INIT if SPL
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select TPL
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help
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Firefly is a RK3288-based development board with 2 USB ports,
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HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
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also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
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provide access to display pins, I2C, SPI, UART and GPIOs.
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config TARGET_MIQI_RK3288
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bool "MiQi-RK3288"
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select BOARD_LATE_INIT
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help
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MiQi-RK3288 is a RK3288-based development board with 4 USB 2.0
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ports, HDMI, micro-SD card, 16 GB eMMC and Gigabit Ethernet. It
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has 1 or 2 GiB SDRAM. Expansion connectors provide access to
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I2C, SPI, UART, GPIOs and fan control.
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config TARGET_PHYCORE_RK3288
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bool "phyCORE-RK3288"
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select BOARD_LATE_INIT
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select SPL_BOARD_INIT if SPL
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help
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Add basic support for the PCM-947 carrier board, a RK3288 based
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development board made by PHYTEC. This board works in a combination
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with the phyCORE-RK3288 System on Module.
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config TARGET_POPMETAL_RK3288
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bool "PopMetal-RK3288"
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select BOARD_LATE_INIT
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help
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PopMetal is a RK3288-based development board with 3 USB host ports,
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1 micro USB OTG port, HDMI, VGA, micro-SD card, audio, WiFi, Gigabit
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Ethernet and lots of sensors. It also includes on-board 8 GeMMC and
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2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
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GPIOs and display interface.
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config TARGET_VYASA_RK3288
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bool "Vyasa-RK3288"
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select BOARD_LATE_INIT
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select TPL
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help
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Vyasa is a RK3288-based development board with 2 USB ports,
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HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
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also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
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provide access to display pins, I2C, SPI, UART and GPIOs.
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config TARGET_ROCK2
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bool "Radxa Rock 2"
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select BOARD_LATE_INIT
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help
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Rock 2 is a SOM and base-board combination based on RK3288. It
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includes Ethernet, HDMI, 3 USB, micro-SD, audio, SATA, WiFi and
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space for a real-time-clock battery. There is also an expansion
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interface which provides access to many pins.
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config TARGET_TINKER_RK3288
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bool "Tinker-RK3288"
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select BOARD_LATE_INIT
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select TPL
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help
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Tinker is a RK3288-based development board with 2 USB ports, HDMI,
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micro-SD card, audio, Gigabit Ethernet. It also includes on-board
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8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
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I2C, SPI, UART, GPIOs.
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endchoice
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config ROCKCHIP_FAST_SPL
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bool "Change the CPU to full speed in SPL"
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depends on TARGET_CHROMEBOOK_JERRY
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help
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Some boards want to boot as fast as possible. We can increase the
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CPU frequency in SPL if the power supply is configured to the correct
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voltage. This option is only available on boards which support it
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and have the required PMIC code.
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config ROCKCHIP_BOOT_MODE_REG
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default 0xff730094
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config SYS_SOC
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default "rk3288"
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config SYS_MALLOC_F_LEN
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default 0x2000
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config SPL_DRIVERS_MISC_SUPPORT
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default y
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config SPL_LIBCOMMON_SUPPORT
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default y
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config SPL_LIBGENERIC_SUPPORT
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default y
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config SPL_SERIAL_SUPPORT
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default y
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config TPL_LDSCRIPT
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default "arch/arm/mach-rockchip/u-boot-tpl.lds"
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config TPL_MAX_SIZE
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default 32768
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config TPL_STACK
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default 0xff718000
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config TPL_TEXT_BASE
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default 0xff704000
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source "board/amarula/vyasa-rk3288/Kconfig"
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source "board/chipspark/popmetal_rk3288/Kconfig"
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source "board/firefly/firefly-rk3288/Kconfig"
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source "board/google/veyron/Kconfig"
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source "board/mqmaker/miqi_rk3288/Kconfig"
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source "board/phytec/phycore_rk3288/Kconfig"
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source "board/radxa/rock2/Kconfig"
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source "board/rockchip/evb_rk3288/Kconfig"
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source "board/rockchip/tinker_rk3288/Kconfig"
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endif
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@@ -0,0 +1,9 @@
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#
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# Copyright (c) 2015 Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += clk_rk3288.o
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obj-y += rk3288.o
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obj-y += syscon_rk3288.o
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@@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <syscon.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3288.h>
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int rockchip_get_clk(struct udevice **devp)
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{
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return uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(rockchip_rk3288_cru), devp);
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}
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void *rockchip_get_cru(void)
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{
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struct rk3288_clk_priv *priv;
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struct udevice *dev;
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int ret;
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ret = rockchip_get_clk(&dev);
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if (ret)
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return ERR_PTR(ret);
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priv = dev_get_priv(dev);
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return priv->cru;
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}
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@@ -0,0 +1,203 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <env.h>
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#include <clk.h>
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#include <init.h>
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#include <asm/armv7.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3288.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/grf_rk3288.h>
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#include <asm/arch-rockchip/pmu_rk3288.h>
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#include <asm/arch-rockchip/qos_rk3288.h>
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#include <asm/arch-rockchip/sdram.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_BASE 0xff770000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
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};
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#ifdef CONFIG_SPL_BUILD
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static void configure_l2ctlr(void)
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{
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u32 l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#endif
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int rk3288_qos_init(void)
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{
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int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
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/* set vop qos to higher priority */
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writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
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if (!fdt_node_check_compatible(gd->fdt_blob, 0,
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"rockchip,rk3288-tinker")) {
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/* set isp qos to higher priority */
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
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}
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return 0;
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}
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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configure_l2ctlr();
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#else
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/* We do some SoC one time setting here. */
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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/* Use rkpwm by default */
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rk_setreg(&grf->soc_con2, 1 << 0);
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/*
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* Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
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* cleared
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*/
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rk_clrreg(&grf->soc_con0, 1 << 12);
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rk3288_qos_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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/* Enable early UART on the RK3288 */
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
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GPIO7C6_MASK << GPIO7C6_SHIFT,
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GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
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GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
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}
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#endif
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static void rk3288_detect_reset_reason(void)
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{
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struct rk3288_cru *cru = rockchip_get_cru();
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const char *reason;
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if (IS_ERR(cru))
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return;
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switch (cru->cru_glb_rst_st) {
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case GLB_POR_RST:
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reason = "POR";
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break;
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case FST_GLB_RST_ST:
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case SND_GLB_RST_ST:
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reason = "RST";
|
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break;
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case FST_GLB_TSADC_RST_ST:
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case SND_GLB_TSADC_RST_ST:
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reason = "THERMAL";
|
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break;
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case FST_GLB_WDT_RST_ST:
|
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case SND_GLB_WDT_RST_ST:
|
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reason = "WDOG";
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break;
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default:
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reason = "unknown reset";
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}
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env_set("reset_reason", reason);
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/*
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* Clear cru_glb_rst_st, so we can determine the last reset cause
|
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* for following resets.
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*/
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rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
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}
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|
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__weak int rk3288_board_late_init(void)
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{
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return 0;
|
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}
|
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|
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int rk_board_late_init(void)
|
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{
|
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rk3288_detect_reset_reason();
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|
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return rk3288_board_late_init();
|
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}
|
||||
|
||||
static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
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{
|
||||
static const struct {
|
||||
char *name;
|
||||
int id;
|
||||
} clks[] = {
|
||||
{ "osc", CLK_OSC },
|
||||
{ "apll", CLK_ARM },
|
||||
{ "dpll", CLK_DDR },
|
||||
{ "cpll", CLK_CODEC },
|
||||
{ "gpll", CLK_GENERAL },
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||||
#ifdef CONFIG_ROCKCHIP_RK3036
|
||||
{ "mpll", CLK_NEW },
|
||||
#else
|
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{ "npll", CLK_NEW },
|
||||
#endif
|
||||
};
|
||||
int ret, i;
|
||||
struct udevice *dev;
|
||||
|
||||
ret = rockchip_get_clk(&dev);
|
||||
if (ret) {
|
||||
printf("clk-uclass not found\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++) {
|
||||
struct clk clk;
|
||||
ulong rate;
|
||||
|
||||
clk.id = clks[i].id;
|
||||
ret = clk_request(dev, &clk);
|
||||
if (ret < 0)
|
||||
continue;
|
||||
|
||||
rate = clk_get_rate(&clk);
|
||||
printf("%s: %lu\n", clks[i].name, rate);
|
||||
|
||||
clk_free(&clk);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
clock, 2, 1, do_clock,
|
||||
"display information about clocks",
|
||||
""
|
||||
);
|
||||
@@ -0,0 +1,62 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015 Google, Inc
|
||||
* Written by Simon Glass <sjg@chromium.org>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
|
||||
static const struct udevice_id rk3288_syscon_ids[] = {
|
||||
{ .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC },
|
||||
{ .compatible = "rockchip,rk3288-grf", .data = ROCKCHIP_SYSCON_GRF },
|
||||
{ .compatible = "rockchip,rk3288-sgrf", .data = ROCKCHIP_SYSCON_SGRF },
|
||||
{ .compatible = "rockchip,rk3288-pmu", .data = ROCKCHIP_SYSCON_PMU },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(syscon_rk3288) = {
|
||||
.name = "rk3288_syscon",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3288_syscon_ids,
|
||||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static int rk3288_syscon_bind_of_platdata(struct udevice *dev)
|
||||
{
|
||||
dev->driver_data = dev->driver->of_match->data;
|
||||
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3288_noc) = {
|
||||
.name = "rockchip_rk3288_noc",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3288_syscon_ids,
|
||||
.bind = rk3288_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3288_grf) = {
|
||||
.name = "rockchip_rk3288_grf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3288_syscon_ids + 1,
|
||||
.bind = rk3288_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
|
||||
.name = "rockchip_rk3288_sgrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3288_syscon_ids + 2,
|
||||
.bind = rk3288_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
|
||||
.name = "rockchip_rk3288_pmu",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3288_syscon_ids + 3,
|
||||
.bind = rk3288_syscon_bind_of_platdata,
|
||||
};
|
||||
#endif
|
||||
Reference in New Issue
Block a user