GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,77 @@
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if ROCKCHIP_RK3368
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choice
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prompt "RK3368 board"
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config TARGET_LION_RK3368
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bool "Theobroma Systems RK3368-uQ7 (Lion) module"
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help
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The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm,
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MXM-230 connector) system-on-module designed by Theobroma
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Systems for industrial applications.
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It provides the following features:
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- 8x Cortex-A53 (in 2 clusters of 4 cores each)
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- (on-module) up to 4GB of DDR3 memory
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- (on-module) SPI-NOR flash
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- (on-module) eMMC
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- Gigabit Ethernet (with an on-module KSZ9031 PHY)
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- USB
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- HDMI
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- MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
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- various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
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- on-module STM32 providing CAN, RTC and fan-control
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- (optional on-module) EAL4+-certified security module
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config TARGET_SHEEP
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bool "Sheep board"
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help
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Sheep board is designed by Rockchip as a EVB board
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for rk3368.
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config TARGET_GEEKBOX
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bool "GeekBox"
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config TARGET_EVB_PX5
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bool "Evb-PX5"
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help
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PX5 EVB is designed by Rockchip for automotive field
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with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
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HDMI video input/output interface, audio codec ES8396,
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WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity
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sensor STK3410.
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endchoice
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config ROCKCHIP_BOOT_MODE_REG
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default 0xff738200
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config SYS_SOC
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default "rk3368"
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config SYS_MALLOC_F_LEN
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default 0x2000
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config SPL_LIBCOMMON_SUPPORT
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default y
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config SPL_LIBGENERIC_SUPPORT
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default y
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source "board/theobroma-systems/lion_rk3368/Kconfig"
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source "board/rockchip/sheep_rk3368/Kconfig"
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source "board/geekbuying/geekbox/Kconfig"
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source "board/rockchip/evb_px5/Kconfig"
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config SPL_LDSCRIPT
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default "arch/arm/cpu/armv8/u-boot-spl.lds"
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config TPL_MAX_SIZE
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default 28672
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config TPL_STACK
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default 0xff8cffff
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config TPL_TEXT_BASE
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default 0xff8c1000
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endif
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2016 Andreas Färber
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obj-y += clk_rk3368.o
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obj-y += rk3368.o
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obj-y += syscon_rk3368.o
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@@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <syscon.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3368.h>
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int rockchip_get_clk(struct udevice **devp)
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{
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return uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(rockchip_rk3368_cru), devp);
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}
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void *rockchip_get_cru(void)
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{
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struct rk3368_clk_priv *priv;
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struct udevice *dev;
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int ret;
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ret = rockchip_get_clk(&dev);
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if (ret)
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return ERR_PTR(ret);
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priv = dev_get_priv(dev);
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return priv->cru;
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}
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@@ -0,0 +1,237 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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* Copyright (c) 2016 Andreas Färber
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*/
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#include <common.h>
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#include <syscon.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3368.h>
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#include <asm/arch-rockchip/grf_rk3368.h>
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#include <asm/arch-rockchip/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define IMEM_BASE 0xFF8C0000
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/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
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#define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4)
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#define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
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#define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
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/* exsram may using by mcu to accessing dram(0x0-0x20000000) */
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#define MCU_EXSRAM_BASE (0)
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#define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
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#define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
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/* experi no used, reserved value = 0 */
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#define MCU_EXPERI_BASE (0)
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#define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
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#define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
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static struct mm_region rk3368_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf0000000UL,
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.phys = 0xf0000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3368_mem_map;
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
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};
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#ifdef CONFIG_ARCH_EARLY_INIT_R
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static int mcu_init(void)
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{
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struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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struct rk3368_cru *cru = rockchip_get_cru();
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rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
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MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
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rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
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MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
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rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
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MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
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rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
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MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
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rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
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MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
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rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
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MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
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rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
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(MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
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(5 << MCU_CLK_DIV_SHIFT));
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/* mcu dereset, for start running */
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rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
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return 0;
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}
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int arch_early_init_r(void)
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{
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return mcu_init();
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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/*
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* The SPL (and also the full U-Boot stage on the RK3368) will run in
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* secure mode (i.e. EL3) and an ATF will eventually be booted before
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* starting up the operating system... so we can initialize the SGRF
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* here and rely on the ATF installing the final (secure) policy
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* later.
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*/
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static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
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{
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const uintptr_t SGRF_BASE =
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(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
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return SGRF_BASE + sizeof(u32) * no;
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}
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static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
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{
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const uintptr_t SGRF_BASE =
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(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
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const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
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const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
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return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
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}
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static void sgrf_init(void)
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{
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struct rk3368_cru * const cru =
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(struct rk3368_cru * const)rockchip_get_cru();
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const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
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const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
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const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
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/* Set all configurable IP to 'non secure'-mode */
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rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
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rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
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rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
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/*
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* From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
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* Original comment: "ddr space set no secure mode"
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*/
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rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
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rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
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rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
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/* Set 'secure dma' to 'non secure'-mode */
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rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
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rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
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dsb(); /* barrier */
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rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
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rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
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dsb(); /* barrier */
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udelay(10);
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rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
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rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
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}
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int arch_cpu_init(void)
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{
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/* Reset security, so we can use DMA in the MMC drivers */
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sgrf_init();
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return 0;
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}
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#endif
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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/*
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* N.B.: This is called before the device-model has been
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* initialised. For this reason, we can not access
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* the GRF address range using the syscon API.
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*/
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
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struct rk3368_grf * const grf =
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(struct rk3368_grf * const)0xff770000;
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enum {
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GPIO2D1_MASK = GENMASK(3, 2),
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GPIO2D1_GPIO = 0,
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GPIO2D1_UART0_SOUT = (1 << 2),
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GPIO2D0_MASK = GENMASK(1, 0),
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GPIO2D0_GPIO = 0,
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GPIO2D0_UART0_SIN = (1 << 0),
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};
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/* Enable early UART0 on the RK3368 */
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rk_clrsetreg(&grf->gpio2d_iomux,
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GPIO2D0_MASK, GPIO2D0_UART0_SIN);
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rk_clrsetreg(&grf->gpio2d_iomux,
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GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
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struct rk3368_pmu_grf * const pmugrf __maybe_unused =
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(struct rk3368_pmu_grf * const)0xff738000;
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enum {
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/* UART4 */
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GPIO0D2_MASK = GENMASK(5, 4),
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GPIO0D2_GPIO = 0,
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GPIO0D2_UART4_SOUT = (3 << 4),
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GPIO0D3_MASK = GENMASK(7, 6),
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GPIO0D3_GPIO = 0,
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GPIO0D3_UART4_SIN = (3 << 6),
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};
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/* Enable early UART4 on the PX5 */
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rk_clrsetreg(&pmugrf->gpio0d_iomux,
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GPIO0D2_MASK | GPIO0D3_MASK,
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GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
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struct rk3368_grf * const grf =
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(struct rk3368_grf * const)0xff770000;
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enum {
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GPIO2A6_SHIFT = 12,
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GPIO2A6_MASK = GENMASK(13, 12),
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GPIO2A6_GPIO = 0,
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GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
|
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|
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GPIO2A5_SHIFT = 10,
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GPIO2A5_MASK = GENMASK(11, 10),
|
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GPIO2A5_GPIO = 0,
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GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
|
||||
};
|
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|
||||
/* Enable early UART2 on the RK3368 */
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A6_MASK, GPIO2A6_UART2_SIN);
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
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#endif
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||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,67 @@
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||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
|
||||
* Author: Andy Yan <andy.yan@rock-chips.com>
|
||||
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <syscon.h>
|
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#include <asm/arch-rockchip/clock.h>
|
||||
|
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static const struct udevice_id rk3368_syscon_ids[] = {
|
||||
{ .compatible = "rockchip,rk3368-grf",
|
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.data = ROCKCHIP_SYSCON_GRF },
|
||||
{ .compatible = "rockchip,rk3368-pmugrf",
|
||||
.data = ROCKCHIP_SYSCON_PMUGRF },
|
||||
{ .compatible = "rockchip,rk3368-msch",
|
||||
.data = ROCKCHIP_SYSCON_MSCH },
|
||||
{ .compatible = "rockchip,rk3368-sgrf",
|
||||
.data = ROCKCHIP_SYSCON_SGRF },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(syscon_rk3368) = {
|
||||
.name = "rk3368_syscon",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3368_syscon_ids,
|
||||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
|
||||
{
|
||||
dev->driver_data = dev->driver->of_match->data;
|
||||
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3368_grf) = {
|
||||
.name = "rockchip_rk3368_grf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3368_syscon_ids,
|
||||
.bind = rk3368_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
|
||||
.name = "rockchip_rk3368_pmugrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3368_syscon_ids + 1,
|
||||
.bind = rk3368_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3368_msch) = {
|
||||
.name = "rockchip_rk3368_msch",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3368_syscon_ids + 2,
|
||||
.bind = rk3368_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
|
||||
.name = "rockchip_rk3368_sgrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3368_syscon_ids + 3,
|
||||
.bind = rk3368_syscon_bind_of_platdata,
|
||||
};
|
||||
#endif
|
||||
Reference in New Issue
Block a user