GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,122 @@
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if ROCKCHIP_RK3399
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choice
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prompt "RK3399 board select"
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config TARGET_EVB_RK3399
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bool "RK3399 evaluation board"
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help
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RK3399evb is a evaluation board for Rockchip RK3399,
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with full function and physical connectors support like Type-C ports,
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USB.0 host ports, LVDS, JTAG, MAC, SD card, HDMI, USB-to-serial...
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config TARGET_PUMA_RK3399
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bool "Theobroma Systems RK3399-Q7 (Puma)"
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help
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The RK3399-Q7 (Puma) is a system-on-module (designed and
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marketed by Theobroma Systems) featuring the Rockchip RK3399
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in a Qseven-compatible form-factor (running of a single 5V
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supply and exposing its external interfaces on a MXM-230
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connector).
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Key features of the RK3399-Q7 include:
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* on-module USB 3.0 hub (2x USB 3.0 host + 1x USB 2.0 host)
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* USB 3.0 dual-role
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* on-module Micrel KSZ9031 GbE PHY
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* on-module eMMC (up to 256GB configurations available)
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* on-module DDR3 (1GB, 2GB and 4GB configurations available)
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* HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI
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* SPI, I2C, I2S, UART, GPIO, ...
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config TARGET_ROCK960_RK3399
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bool "Vamrs Limited Rock960 board family"
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help
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Support for Rock960 board family by Vamrs Limited. This board
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family consists of Rock960 (Consumer Edition) and Ficus
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(Enterprise Edition) 96Boards.
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Common features implemented on both boards:
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* Rockchip RK3399 SoC (2xCortex A72, 4xCortex A53, ARM Mali T860MP4)
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* 16/32GB eMMC, uSD slot
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* HDMI/DP/MIPI
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* 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons
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Additional features of Rock960:
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* 2GiB/4GiB LPDDR3 RAM
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* 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only),
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1x USB 3.0 type C OTG
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Additional features of Ficus:
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* 2GiB/4GiB DDR3 RAM
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* Ethernet
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* Dual SATA
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* 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only),
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1x USB 3.0 type C OTG
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config TARGET_CHROMEBOOK_BOB
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bool "Asus Flip C101PA Chromebook (RK3399)"
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help
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Bob is a small RK3299-based device similar in apperance to Minnie.
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It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1",
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1280x800 display. It uses its USB ports for both power and external
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display. It includes a Chrome OS EC (Cortex-M3) to provide access to
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the keyboard and battery functions.
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config TARGET_ROCKPRO64_RK3399
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bool "Pine64 Rockpro64 board"
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help
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Rockro64 is SBC produced by Pine64. Key features:
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* Rockchip RK3399
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* 2/4GB Dual-Channel LPDDR3
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* SD card slot
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* eMMC socket
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* 128Mb SPI Flash
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* Gigabit ethernet
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* PCIe 4X slot
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* WiFI/BT module socket
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* HDMI In/Out, DP, MIPI DSI/CSI, eDP
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* USB 3.0, 2.0
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* USB Type C power and data
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* GPIO expansion ports
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* DC 12V/2A
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endchoice
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config ROCKCHIP_BOOT_MODE_REG
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default 0xff320300
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config SYS_SOC
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default "rk3399"
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config SYS_MALLOC_F_LEN
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default 0x4000
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config SPL_LIBCOMMON_SUPPORT
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default y
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config SPL_LIBGENERIC_SUPPORT
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default y
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config TPL_LDSCRIPT
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default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
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config TPL_MAX_SIZE
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default 188416
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config TPL_STACK
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default 0xff8effff
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config TPL_TEXT_BASE
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default 0xff8c2000
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config SPL_STACK_R_ADDR
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default 0x04000000
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source "board/rockchip/evb_rk3399/Kconfig"
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source "board/theobroma-systems/puma_rk3399/Kconfig"
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source "board/vamrs/rock960_rk3399/Kconfig"
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source "board/google/gru/Kconfig"
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source "board/pine64/rockpro64_rk3399/Kconfig"
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endif
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@@ -0,0 +1,9 @@
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#
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# (C) Copyright 2016 Rockchip Electronics Co., Ltd
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += clk_rk3399.o
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obj-y += rk3399.o
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obj-y += syscon_rk3399.o
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@@ -0,0 +1,53 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <syscon.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3399.h>
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static int rockchip_get_cruclk(struct udevice **devp)
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{
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return uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(clk_rk3399), devp);
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}
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void *rockchip_get_cru(void)
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{
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struct rk3399_clk_priv *priv;
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struct udevice *dev;
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int ret;
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ret = rockchip_get_cruclk(&dev);
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if (ret)
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return ERR_PTR(ret);
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priv = dev_get_priv(dev);
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return priv->cru;
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}
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static int rockchip_get_pmucruclk(struct udevice **devp)
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{
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return uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp);
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}
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void *rockchip_get_pmucru(void)
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{
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struct rk3399_pmuclk_priv *priv;
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struct udevice *dev;
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int ret;
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ret = rockchip_get_pmucruclk(&dev);
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if (ret)
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return ERR_PTR(ret);
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priv = dev_get_priv(dev);
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return priv->pmucru;
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}
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@@ -0,0 +1,273 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <spl.h>
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#include <spl_gpio.h>
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#include <syscon.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/gpio.h>
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#include <asm/arch-rockchip/grf_rk3399.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_EMMCCORE_CON11 0xff77f02c
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#define GRF_BASE 0xff770000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
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[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
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};
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static struct mm_region rk3399_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xf8000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf8000000UL,
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.phys = 0xf8000000UL,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3399_mem_map;
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#ifdef CONFIG_SPL_BUILD
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#define TIMER_END_COUNT_L 0x00
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#define TIMER_END_COUNT_H 0x04
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#define TIMER_INIT_COUNT_L 0x10
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#define TIMER_INIT_COUNT_H 0x14
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#define TIMER_CONTROL_REG 0x1c
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#define TIMER_EN 0x1
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#define TIMER_FMODE BIT(0)
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#define TIMER_RMODE BIT(1)
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void rockchip_stimer_init(void)
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{
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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if (reg & TIMER_EN)
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return;
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
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writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
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TIMER_CONTROL_REG);
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}
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#endif
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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struct rk3399_pmusgrf_regs *sgrf;
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struct rk3399_grf_regs *grf;
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/*
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* Disable DDR and SRAM security regions.
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*
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* As we are entered from the BootROM, the region from
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* 0x0 through 0xfffff (i.e. the first MB of memory) will
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* be protected. This will cause issues with the DW_MMC
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* driver, which tries to DMA from/to the stack (likely)
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* located in this range.
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*/
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sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
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rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
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rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
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/* eMMC clock generator: disable the clock multipilier */
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrreg(&grf->emmccore_con[11], 0x0ff);
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#endif
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return 0;
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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#define GRF_BASE 0xff770000
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#define GPIO0_BASE 0xff720000
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#define PMUGRF_BASE 0xff320000
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struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
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#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
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struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
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struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
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#endif
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
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/* Enable early UART0 on the RK3399 */
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rk_clrsetreg(&grf->gpio2c_iomux,
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GRF_GPIO2C0_SEL_MASK,
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GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio2c_iomux,
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GRF_GPIO2C1_SEL_MASK,
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GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
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/* Enable early UART3 on the RK3399 */
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rk_clrsetreg(&grf->gpio3b_iomux,
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GRF_GPIO3B6_SEL_MASK,
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GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio3b_iomux,
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GRF_GPIO3B7_SEL_MASK,
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GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
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#else
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# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
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rk_setreg(&grf->io_vsel, 1 << 0);
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/*
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* Let's enable these power rails here, we are already running the SPI
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* Flash based code.
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*/
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spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
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spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
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spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
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spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
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#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
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/* Enable early UART2 channel C on the RK3399 */
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rk_clrsetreg(&grf->gpio4c_iomux,
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GRF_GPIO4C3_SEL_MASK,
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GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio4c_iomux,
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GRF_GPIO4C4_SEL_MASK,
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GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
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/* Set channel C as UART2 input */
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rk_clrsetreg(&grf->soc_con7,
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GRF_UART_DBG_SEL_MASK,
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GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
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#endif
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}
|
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#endif
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|
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#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
|
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const char *spl_decode_boot_device(u32 boot_device)
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{
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int i;
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static const struct {
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u32 boot_device;
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const char *ofpath;
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} spl_boot_devices_tbl[] = {
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{ BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
|
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{ BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
|
||||
{ BOOT_DEVICE_SPI, "/spi@ff1d0000" },
|
||||
};
|
||||
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||||
for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
|
||||
if (spl_boot_devices_tbl[i].boot_device == boot_device)
|
||||
return spl_boot_devices_tbl[i].ofpath;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void spl_perform_fixups(struct spl_image_info *spl_image)
|
||||
{
|
||||
void *blob = spl_image->fdt_addr;
|
||||
const char *boot_ofpath;
|
||||
int chosen;
|
||||
|
||||
/*
|
||||
* Inject the ofpath of the device the full U-Boot (or Linux in
|
||||
* Falcon-mode) was booted from into the FDT, if a FDT has been
|
||||
* loaded at the same time.
|
||||
*/
|
||||
if (!blob)
|
||||
return;
|
||||
|
||||
boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
|
||||
if (!boot_ofpath) {
|
||||
pr_err("%s: could not map boot_device to ofpath\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
|
||||
if (chosen < 0) {
|
||||
pr_err("%s: could not find/create '/chosen'\n", __func__);
|
||||
return;
|
||||
}
|
||||
fdt_setprop_string(blob, chosen,
|
||||
"u-boot,spl-boot-device", boot_ofpath);
|
||||
}
|
||||
|
||||
#if defined(SPL_GPIO_SUPPORT)
|
||||
static void rk3399_force_power_on_reset(void)
|
||||
{
|
||||
ofnode node;
|
||||
struct gpio_desc sysreset_gpio;
|
||||
|
||||
debug("%s: trying to force a power-on reset\n", __func__);
|
||||
|
||||
node = ofnode_path("/config");
|
||||
if (!ofnode_valid(node)) {
|
||||
debug("%s: no /config node?\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
|
||||
&sysreset_gpio, GPIOD_IS_OUT)) {
|
||||
debug("%s: could not find a /config/sysreset-gpio\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
dm_gpio_set_value(&sysreset_gpio, 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
#if defined(SPL_GPIO_SUPPORT)
|
||||
struct rk3399_cru *cru = rockchip_get_cru();
|
||||
|
||||
/*
|
||||
* The RK3399 resets only 'almost all logic' (see also in the TRM
|
||||
* "3.9.4 Global software reset"), when issuing a software reset.
|
||||
* This may cause issues during boot-up for some configurations of
|
||||
* the application software stack.
|
||||
*
|
||||
* To work around this, we test whether the last reset reason was
|
||||
* a power-on reset and (if not) issue an overtemp-reset to reset
|
||||
* the entire module.
|
||||
*
|
||||
* While this was previously fixed by modifying the various places
|
||||
* that could generate a software reset (e.g. U-Boot's sysreset
|
||||
* driver, the ATF or Linux), we now have it here to ensure that
|
||||
* we no longer have to track this through the various components.
|
||||
*/
|
||||
if (cru->glb_rst_st != 0)
|
||||
rk3399_force_power_on_reset();
|
||||
#endif
|
||||
|
||||
#if defined(SPL_DM_REGULATOR)
|
||||
/*
|
||||
* Turning the eMMC and SPI back on (if disabled via the Qseven
|
||||
* BIOS_ENABLE) signal is done through a always-on regulator).
|
||||
*/
|
||||
if (regulators_enable_boot_on(false))
|
||||
debug("%s: Cannot enable boot on regulator\n", __func__);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,69 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
|
||||
static const struct udevice_id rk3399_syscon_ids[] = {
|
||||
{ .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF },
|
||||
{ .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
|
||||
{ .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF },
|
||||
{ .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
|
||||
{ .compatible = "rockchip,rk3399-pmu", .data = ROCKCHIP_SYSCON_PMU },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(syscon_rk3399) = {
|
||||
.name = "rk3399_syscon",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids,
|
||||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static int rk3399_syscon_bind_of_platdata(struct udevice *dev)
|
||||
{
|
||||
dev->driver_data = dev->driver->of_match->data;
|
||||
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3399_grf) = {
|
||||
.name = "rockchip_rk3399_grf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = {
|
||||
.name = "rockchip_rk3399_pmugrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids + 1,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = {
|
||||
.name = "rockchip_rk3399_pmusgrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids + 2,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3399_cic) = {
|
||||
.name = "rockchip_rk3399_cic",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids + 3,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
|
||||
.name = "rockchip_rk3399_pmu",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids + 4,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
};
|
||||
#endif
|
||||
Reference in New Issue
Block a user