GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,5 @@
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obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o
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obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o
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obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o
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obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o
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obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o
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@@ -0,0 +1,84 @@
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#include <common.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/cpu.h>
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void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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u8 tccd = 1;
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u8 tfaw = ns_to_t(50);
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u8 trrd = max(ns_to_t(10), 2);
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u8 trcd = ns_to_t(20);
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u8 trc = ns_to_t(65);
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u8 txp = 2;
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u8 twtr = max(ns_to_t(8), 2);
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u8 trtp = max(ns_to_t(8), 2);
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u8 twr = max(ns_to_t(15), 3);
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u8 trp = ns_to_t(15);
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u8 tras = ns_to_t(45);
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u16 trefi = ns_to_t(7800) / 32;
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u16 trfc = ns_to_t(328);
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u8 tmrw = 0;
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u8 tmrd = 2;
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u8 tmod = 12;
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u8 tcke = 3;
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u8 tcksrx = 5;
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u8 tcksre = 5;
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u8 tckesr = 4;
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u8 trasmax = 27;
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u8 tcl = 3; /* CL 6 */
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u8 tcwl = 3; /* CWL 6 */
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u8 t_rdata_en = 1;
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u8 wr_latency = 1;
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u32 tdinit0 = (400 * CONFIG_DRAM_CLK) + 1; /* 400us */
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u32 tdinit1 = (500 * CONFIG_DRAM_CLK) / 1000 + 1; /* 500ns */
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u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
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u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
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u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
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u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
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u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
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/* set mode register */
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writel(0x263, &mctl_ctl->mr[0]);
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writel(0x4, &mctl_ctl->mr[1]);
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writel(0x0, &mctl_ctl->mr[2]);
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writel(0x0, &mctl_ctl->mr[3]);
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/* set DRAM timing */
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writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
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DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
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&mctl_ctl->dramtmg[0]);
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writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
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&mctl_ctl->dramtmg[1]);
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writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
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DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
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&mctl_ctl->dramtmg[2]);
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writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
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&mctl_ctl->dramtmg[3]);
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writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
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DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
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writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
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DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
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&mctl_ctl->dramtmg[5]);
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/* set two rank timing */
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clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
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(0x66 << 8) | (0x10 << 0));
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/* set PHY interface timing, write latency and read latency configure */
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writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
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(wr_latency << 0), &mctl_ctl->pitmg[0]);
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/* set PHY timing, PTR0-2 use default */
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writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
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writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
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/* set refresh timing */
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writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
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}
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@@ -0,0 +1,87 @@
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#include <common.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/cpu.h>
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void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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u8 tccd = 2;
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u8 tfaw = ns_to_t(50);
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u8 trrd = max(ns_to_t(10), 4);
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u8 trcd = ns_to_t(15);
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u8 trc = ns_to_t(53);
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u8 txp = max(ns_to_t(8), 3);
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u8 twtr = max(ns_to_t(8), 4);
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u8 trtp = max(ns_to_t(8), 4);
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u8 twr = max(ns_to_t(15), 3);
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u8 trp = ns_to_t(15);
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u8 tras = ns_to_t(38);
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u16 trefi = ns_to_t(7800) / 32;
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u16 trfc = ns_to_t(350);
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u8 tmrw = 0;
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u8 tmrd = 4;
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u8 tmod = 12;
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u8 tcke = 3;
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u8 tcksrx = 5;
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u8 tcksre = 5;
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u8 tckesr = 4;
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u8 trasmax = 24;
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u8 tcl = 6; /* CL 12 */
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u8 tcwl = 4; /* CWL 8 */
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u8 t_rdata_en = 4;
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u8 wr_latency = 2;
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u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
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u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
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u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
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u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
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u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
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u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
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u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
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/* set mode register */
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writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
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writel(0x40, &mctl_ctl->mr[1]);
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writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
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writel(0x0, &mctl_ctl->mr[3]);
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if (socid == SOCID_R40)
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writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */
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/* set DRAM timing */
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writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
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DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
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&mctl_ctl->dramtmg[0]);
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writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
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&mctl_ctl->dramtmg[1]);
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writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
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DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
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&mctl_ctl->dramtmg[2]);
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writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
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&mctl_ctl->dramtmg[3]);
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writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
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DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
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writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
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DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
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&mctl_ctl->dramtmg[5]);
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/* set two rank timing */
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clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
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((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
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/* set PHY interface timing, write latency and read latency configure */
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writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
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(wr_latency << 0), &mctl_ctl->pitmg[0]);
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/* set PHY timing, PTR0-2 use default */
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writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
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writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
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/* set refresh timing */
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writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
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}
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@@ -0,0 +1,144 @@
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/*
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* sun50i H6 DDR3-1333 timings, as programmed by Allwinner's boot0
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* for some TV boxes with the H6 and DDR3 memory.
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*
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* The chips are probably able to be driven by a faster clock, but boot0
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* uses a more conservative timing (as usual).
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*
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* (C) Copyright 2018,2019 Arm Ltd.
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* based on previous work by:
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* References used:
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* - JEDEC DDR3 SDRAM standard: JESD79-3F.pdf
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* - Samsung K4B2G0446D datasheet
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* - ZynqMP UG1087 register DDRC/PHY documentation
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*
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* Many thanks to Jernej Skrabec for contributing some fixes!
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/cpu.h>
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/*
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* Only the first four are used for DDR3(?)
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* MR0: BL8, seq. read burst, no test, fast exit (DLL on), no DLL reset,
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* CAS latency (CL): 11, write recovery (WR): 12
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* MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2,
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* write levelling disabled, TDQS disabled, output buffer enabled
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* MR2: manual full array self refresh, dynamic ODT off,
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* CAS write latency (CWL): 8
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*/
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static u32 mr_ddr3[7] = {
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0x00001c70, 0x00000040, 0x00000018, 0x00000000,
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0x00000000, 0x00000400, 0x00000848,
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};
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/* TODO: flexible timing */
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void mctl_set_timing_params(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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struct sunxi_mctl_phy_reg * const mctl_phy =
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(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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int i;
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u8 tccd = 2; /* JEDEC: 4nCK */
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u8 tfaw = ns_to_t(50); /* JEDEC: 30 ns w/ 1K pages */
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u8 trrd = max(ns_to_t(6), 4); /* JEDEC: max(6 ns, 4nCK) */
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u8 trcd = ns_to_t(15); /* JEDEC: 13.5 ns */
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u8 trc = ns_to_t(53); /* JEDEC: 49.5 ns */
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u8 txp = max(ns_to_t(6), 3); /* JEDEC: max(6 ns, 3nCK) */
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u8 twtr = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */
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u8 trtp = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */
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u8 twr = ns_to_t(15); /* JEDEC: 15 ns */
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u8 trp = ns_to_t(15); /* JEDEC: >= 13.75 ns */
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u8 tras = ns_to_t(38); /* JEDEC >= 36 ns, <= 9*trefi */
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u8 twtr_sa = 2; /* ? */
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u8 tcksrea = 4; /* ? */
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u16 trefi = ns_to_t(7800) / 32; /* JEDEC: 7.8us@Tcase <= 85C */
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u16 trfc = ns_to_t(350); /* JEDEC: 160 ns for 2Gb */
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u16 txsr = 4; /* ? */
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u8 tmrw = 0; /* ? */
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u8 tmrd = 4; /* JEDEC: 4nCK */
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u8 tmod = max(ns_to_t(15), 12); /* JEDEC: max(15 ns, 12nCK) */
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u8 tcke = max(ns_to_t(6), 3); /* JEDEC: max(5.625 ns, 3nCK) */
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u8 tcksrx = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */
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u8 tcksre = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */
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u8 tckesr = tcke + 1; /* JEDEC: tCKE(min) + 1nCK */
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u8 trasmax = 24; /* JEDEC: tREFI * 9 */
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u8 txs = ns_to_t(360) / 32; /* JEDEC: max(5nCK,tRFC+10ns) */
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u8 txsdll = 4; /* JEDEC: 512 nCK */
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u8 txsabort = 4; /* ? */
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u8 txsfast = 4; /* ? */
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u8 tcl = 6; /* JEDEC: CL / 2 => 6 */
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u8 tcwl = 4; /* JEDEC: 8 */
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u8 t_rdata_en = 7; /* ? */
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u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
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u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1;
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u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1;
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u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
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u8 twtp = tcwl + 2 + twr; /* (WL + BL / 2 + tWR) / 2 */
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u8 twr2rd = tcwl + 2 + twtr; /* (WL + BL / 2 + tWTR) / 2 */
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u8 trd2wr = 5; /* (RL + BL / 2 + 2 - WL) / 2 */
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if (tcl + 1 >= trtp + trp)
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trtp = tcl + 2 - trp;
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/* set mode registers */
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for (i = 0; i < ARRAY_SIZE(mr_ddr3); i++)
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writel(mr_ddr3[i], &mctl_phy->mr[i]);
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/* set DRAM timing */
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writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
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&mctl_ctl->dramtmg[0]);
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writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
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writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
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&mctl_ctl->dramtmg[2]);
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writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
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writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
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&mctl_ctl->dramtmg[4]);
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writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
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&mctl_ctl->dramtmg[5]);
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/* Value suggested by ZynqMP manual and used by libdram */
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writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
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writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
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&mctl_ctl->dramtmg[8]);
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writel(txsr, &mctl_ctl->dramtmg[14]);
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clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
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writel(0, &mctl_ctl->dfimisc);
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clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
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/*
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* Set timing registers of the PHY.
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* Note: the PHY is clocked 2x from the DRAM frequency.
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*/
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writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
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&mctl_phy->dtpr[0]);
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writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
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writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
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writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
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&mctl_phy->dtpr[3]);
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writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
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writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
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writel(0x0505, &mctl_phy->dtpr[6]);
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/* Configure DFI timing */
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writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
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&mctl_ctl->dfitmg0);
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writel(0x040201, &mctl_ctl->dfitmg1);
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/* Configure PHY timing. Zynq uses different registers. */
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writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
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writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
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/* set refresh timing */
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writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
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}
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@@ -0,0 +1,132 @@
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/*
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* sun50i H6 LPDDR3 timings
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*
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/cpu.h>
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static u32 mr_lpddr3[12] = {
|
||||
0x00000000, 0x00000043, 0x0000001a, 0x00000001,
|
||||
0x00000000, 0x00000000, 0x00000048, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000003,
|
||||
};
|
||||
|
||||
/* TODO: flexible timing */
|
||||
void mctl_set_timing_params(struct dram_para *para)
|
||||
{
|
||||
struct sunxi_mctl_ctl_reg * const mctl_ctl =
|
||||
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
|
||||
struct sunxi_mctl_phy_reg * const mctl_phy =
|
||||
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
|
||||
int i;
|
||||
|
||||
u8 tccd = 2;
|
||||
u8 tfaw = max(ns_to_t(50), 4);
|
||||
u8 trrd = max(ns_to_t(10), 2);
|
||||
u8 trcd = max(ns_to_t(24), 2);
|
||||
u8 trc = ns_to_t(70);
|
||||
u8 txp = max(ns_to_t(8), 2);
|
||||
u8 twtr = max(ns_to_t(8), 2);
|
||||
u8 trtp = max(ns_to_t(8), 2);
|
||||
u8 twr = max(ns_to_t(15), 2);
|
||||
u8 trp = ns_to_t(18);
|
||||
u8 tras = ns_to_t(42);
|
||||
u8 twtr_sa = ns_to_t(5);
|
||||
u8 tcksrea = ns_to_t(11);
|
||||
u16 trefi = ns_to_t(3900) / 32;
|
||||
u16 trfc = ns_to_t(210);
|
||||
u16 txsr = ns_to_t(220);
|
||||
|
||||
if (CONFIG_DRAM_CLK % 400 == 0) {
|
||||
/* Round up these parameters */
|
||||
twtr_sa++;
|
||||
tcksrea++;
|
||||
}
|
||||
|
||||
u8 tmrw = 5;
|
||||
u8 tmrd = 5;
|
||||
u8 tmod = 12;
|
||||
u8 tcke = 3;
|
||||
u8 tcksrx = 5;
|
||||
u8 tcksre = 5;
|
||||
u8 tckesr = 5;
|
||||
u8 trasmax = CONFIG_DRAM_CLK / 60;
|
||||
u8 txs = 4;
|
||||
u8 txsdll = 4;
|
||||
u8 txsabort = 4;
|
||||
u8 txsfast = 4;
|
||||
|
||||
u8 tcl = 5; /* CL 10 */
|
||||
u8 tcwl = 3; /* CWL 6 */
|
||||
u8 t_rdata_en = twtr_sa + 8;
|
||||
|
||||
u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
|
||||
u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
|
||||
u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
|
||||
u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
|
||||
|
||||
u8 twtp = tcwl + 4 + twr + 1;
|
||||
/*
|
||||
* The code below for twr2rd and trd2wr follows the IP core's
|
||||
* document from ZynqMP and i.MX7. The BSP has both number
|
||||
* substracted by 2.
|
||||
*/
|
||||
u8 twr2rd = tcwl + 4 + 1 + twtr;
|
||||
u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1;
|
||||
|
||||
/* set mode registers */
|
||||
for (i = 0; i < ARRAY_SIZE(mr_lpddr3); i++)
|
||||
writel(mr_lpddr3[i], &mctl_phy->mr[i]);
|
||||
|
||||
/* set DRAM timing */
|
||||
writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
|
||||
&mctl_ctl->dramtmg[0]);
|
||||
writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
|
||||
writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
|
||||
&mctl_ctl->dramtmg[2]);
|
||||
writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
|
||||
writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
|
||||
&mctl_ctl->dramtmg[4]);
|
||||
writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
|
||||
&mctl_ctl->dramtmg[5]);
|
||||
/* Value suggested by ZynqMP manual and used by libdram */
|
||||
writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
|
||||
writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
|
||||
&mctl_ctl->dramtmg[8]);
|
||||
writel(txsr, &mctl_ctl->dramtmg[14]);
|
||||
|
||||
clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
|
||||
writel(0, &mctl_ctl->dfimisc);
|
||||
clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
|
||||
|
||||
/*
|
||||
* Set timing registers of the PHY.
|
||||
* Note: the PHY is clocked 2x from the DRAM frequency.
|
||||
*/
|
||||
writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
|
||||
&mctl_phy->dtpr[0]);
|
||||
writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
|
||||
writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
|
||||
writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
|
||||
&mctl_phy->dtpr[3]);
|
||||
writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
|
||||
writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
|
||||
writel(0x0505, &mctl_phy->dtpr[6]);
|
||||
|
||||
/* Configure DFI timing */
|
||||
writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
|
||||
&mctl_ctl->dfitmg0);
|
||||
writel(0x040201, &mctl_ctl->dfitmg1);
|
||||
|
||||
/* Configure PHY timing */
|
||||
writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
|
||||
writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
|
||||
|
||||
/* set refresh timing */
|
||||
writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
|
||||
}
|
||||
@@ -0,0 +1,83 @@
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
|
||||
{
|
||||
struct sunxi_mctl_ctl_reg * const mctl_ctl =
|
||||
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
|
||||
|
||||
u8 tccd = 2;
|
||||
u8 tfaw = max(ns_to_t(50), 4);
|
||||
u8 trrd = max(ns_to_t(10), 2);
|
||||
u8 trcd = max(ns_to_t(24), 2);
|
||||
u8 trc = ns_to_t(70);
|
||||
u8 txp = max(ns_to_t(8), 2);
|
||||
u8 twtr = max(ns_to_t(8), 2);
|
||||
u8 trtp = max(ns_to_t(8), 2);
|
||||
u8 twr = max(ns_to_t(15), 3);
|
||||
u8 trp = max(ns_to_t(27), 2);
|
||||
u8 tras = ns_to_t(42);
|
||||
u16 trefi = ns_to_t(3900) / 32;
|
||||
u16 trfc = ns_to_t(210);
|
||||
|
||||
u8 tmrw = 5;
|
||||
u8 tmrd = 5;
|
||||
u8 tmod = 12;
|
||||
u8 tcke = 3;
|
||||
u8 tcksrx = 5;
|
||||
u8 tcksre = 5;
|
||||
u8 tckesr = 5;
|
||||
u8 trasmax = 24;
|
||||
|
||||
u8 tcl = 6; /* CL 12 */
|
||||
u8 tcwl = 3; /* CWL 6 */
|
||||
u8 t_rdata_en = 5;
|
||||
u8 wr_latency = 2;
|
||||
|
||||
u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
|
||||
u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
|
||||
u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
|
||||
u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
|
||||
|
||||
u8 twtp = tcwl + 4 + twr + 1;
|
||||
u8 twr2rd = tcwl + 4 + 1 + twtr;
|
||||
u8 trd2wr = tcl + 4 + 5 - tcwl + 1;
|
||||
|
||||
/* set mode register */
|
||||
writel(0xc3, &mctl_ctl->mr[1]); /* nWR=8, BL8 */
|
||||
writel(0xa, &mctl_ctl->mr[2]); /* RL=12, WL=6 */
|
||||
writel(0x2, &mctl_ctl->mr[3]); /* 40 0hms PD/PU */
|
||||
|
||||
/* set DRAM timing */
|
||||
writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
|
||||
DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
|
||||
&mctl_ctl->dramtmg[0]);
|
||||
writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
|
||||
&mctl_ctl->dramtmg[1]);
|
||||
writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
|
||||
DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
|
||||
&mctl_ctl->dramtmg[2]);
|
||||
writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
|
||||
&mctl_ctl->dramtmg[3]);
|
||||
writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
|
||||
DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
|
||||
writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
|
||||
DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
|
||||
&mctl_ctl->dramtmg[5]);
|
||||
|
||||
/* set two rank timing */
|
||||
clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
|
||||
(0x66 << 8) | (0x10 << 0));
|
||||
|
||||
/* set PHY interface timing, write latency and read latency configure */
|
||||
writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
|
||||
(wr_latency << 0), &mctl_ctl->pitmg[0]);
|
||||
|
||||
/* set PHY timing, PTR0-2 use default */
|
||||
writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
|
||||
writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
|
||||
|
||||
/* set refresh timing */
|
||||
writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
|
||||
}
|
||||
Reference in New Issue
Block a user