GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= bcu-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= bcu-ld4.o
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
+
+#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
+
+void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd)
+{
+	int shift;
+
+	writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
+	writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
+
+	/* Specify DDR channel */
+	shift = bd->dram_ch[0].size / 0x04000000 * 4;
+	writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
+
+	shift -= 32;
+	writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
+
+	shift -= 32;
+	writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+}
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * UniPhier BCU (Bus Control Unit) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ */
+
+#ifndef ARCH_BCU_REGS_H
+#define ARCH_BCU_REGS_H
+
+#define	BCU_BASE		0x50080000
+
+#define	BCSCR(x)                (BCU_BASE + 0x180 + (x) * 4)
+#define	BCSCR0			(BCSCR(0))
+#define	BCSCR1			(BCSCR(1))
+#define	BCSCR2			(BCSCR(2))
+#define	BCSCR3			(BCSCR(3))
+#define	BCSCR4			(BCSCR(4))
+#define	BCSCR5			(BCSCR(5))
+
+#define	BCIPPCCHR(x)		(BCU_BASE + 0x0280 + (x) * 4)
+#define	BCIPPCCHR0		(BCIPPCCHR(0))
+#define	BCIPPCCHR1		(BCIPPCCHR(1))
+#define	BCIPPCCHR2		(BCIPPCCHR(2))
+#define	BCIPPCCHR3		(BCIPPCCHR(3))
+#define	BCIPPCCHR4		(BCIPPCCHR(4))
+#define	BCIPPCCHR5		(BCIPPCCHR(5))
+
+#endif  /* ARCH_BCU_REGS_H */