GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/Makefile

@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+ifdef CONFIG_SPL_BUILD
+
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
+
+else
+
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= clk-ld4.o pll-ld4.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= clk-pro4.o pll-pro4.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o pll-ld4.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o pll-base-ld20.o pll-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o pll-base-ld20.o pll-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS3)	+= clk-pxs3.o pll-base-ld20.o pll-pxs3.o
+
+endif

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-dram-ld4.c

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_ld4_dram_clk_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(sc_base + SC_RSTCTRL);
+	tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
+	writel(tmp, sc_base + SC_RSTCTRL);
+	readl(sc_base + SC_RSTCTRL); /* dummy read */
+
+	/* provide clocks */
+	tmp = readl(sc_base + SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CEN_UMC;
+	writel(tmp, sc_base + SC_CLKCTRL);
+	readl(sc_base + SC_CLKCTRL); /* dummy read */
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-dram-pro5.c

@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2017 Socionext Inc.
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_pro5_dram_clk_init(void)
+{
+	u32 tmp;
+
+	/*
+	 * deassert reset
+	 * UMCA2: Ch1 (DDR3)
+	 * UMCA1, UMC31: Ch0 (WIO1)
+	 * UMCA0, UMC30: Ch0 (WIO0)
+	 */
+	tmp = readl(sc_base + SC_RSTCTRL4);
+	tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+	       SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+	       SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
+	writel(tmp, sc_base + SC_RSTCTRL4);
+	readl(sc_base + SC_RSTCTRL4); /* dummy read */
+
+	/* provide clocks */
+	tmp = readl(sc_base + SC_CLKCTRL4);
+	tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
+	       SC_CLKCTRL4_CEN_UMC0;
+	writel(tmp, sc_base + SC_CLKCTRL4);
+	readl(sc_base + SC_CLKCTRL4); /* dummy read */
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_pxs2_dram_clk_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(sc_base + SC_RSTCTRL4);
+	tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+	       SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+	       SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
+	       SC_RSTCTRL4_NRST_UMC30;
+	writel(tmp, sc_base + SC_RSTCTRL4);
+	readl(sc_base + SC_RSTCTRL4); /* dummy read */
+
+	/* provide clocks */
+	tmp = readl(sc_base + SC_CLKCTRL4);
+	tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
+	       SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
+	writel(tmp, sc_base + SC_CLKCTRL4);
+	readl(sc_base + SC_CLKCTRL4); /* dummy read */
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-early-ld4.c

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_ld4_early_clk_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	if (spl_boot_device() != BOOT_DEVICE_NAND) {
+		tmp = readl(sc_base + SC_RSTCTRL);
+		tmp &= ~SC_RSTCTRL_NRST_NAND;
+		writel(tmp, sc_base + SC_RSTCTRL);
+	};
+
+	/* provide clocks */
+	tmp = readl(sc_base + SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+	writel(tmp, sc_base + SC_CLKCTRL);
+	readl(sc_base + SC_CLKCTRL); /* dummy read */
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-ld11.c

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "../sg-regs.h"
+
+#define SDCTRL_EMMC_HW_RESET	0x59810280
+
+void uniphier_ld11_clk_init(void)
+{
+	/* if booted from a device other than USB, without stand-by MPU */
+	if ((readl(sg_base + SG_PINMON0) & BIT(27)) &&
+	    uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
+		writel(1, sg_base + SG_ETPHYPSHUT);
+		writel(1, sg_base + SG_ETPHYCNT);
+
+		udelay(1); /* wait for regulator level 1.1V -> 2.5V */
+
+		writel(3, sg_base + SG_ETPHYCNT);
+		writel(3, sg_base + SG_ETPHYPSHUT);
+		writel(7, sg_base + SG_ETPHYCNT);
+	}
+
+	/* TODO: use "mmc-pwrseq-emmc" */
+	writel(1, SDCTRL_EMMC_HW_RESET);
+
+#ifdef CONFIG_USB_EHCI_HCD
+	{
+		int ch;
+
+		for (ch = 0; ch < 3; ch++) {
+			void __iomem *phyctrl = sg_base + SG_USBPHYCTRL;
+
+			writel(0x82280600, phyctrl + 8 * ch);
+			writel(0x00000106, phyctrl + 8 * ch + 4);
+		}
+	}
+#endif
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-ld20.c

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+#define SDCTRL_EMMC_HW_RESET	0x59810280
+
+void uniphier_ld20_clk_init(void)
+{
+	u32 tmp;
+
+	tmp = readl(sc_base + SC_RSTCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, sc_base + SC_RSTCTRL6);
+
+	tmp = readl(sc_base + SC_CLKCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, sc_base + SC_CLKCTRL6);
+
+	/* TODO: use "mmc-pwrseq-emmc" */
+	writel(1, SDCTRL_EMMC_HW_RESET);
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-ld4.c

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_ld4_clk_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(sc_base + SC_RSTCTRL);
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+	writel(tmp, sc_base + SC_RSTCTRL);
+	readl(sc_base + SC_RSTCTRL); /* dummy read */
+
+	/* provide clocks */
+	tmp = readl(sc_base + SC_CLKCTRL);
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+	writel(tmp, sc_base + SC_CLKCTRL);
+	readl(sc_base + SC_CLKCTRL); /* dummy read */
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-pro4.c

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_pro4_clk_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(sc_base + SC_RSTCTRL);
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+	tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
+		SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+	writel(tmp, sc_base + SC_RSTCTRL);
+	readl(sc_base + SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+	tmp = readl(sc_base + SC_RSTCTRL2);
+	tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
+	writel(tmp, sc_base + SC_RSTCTRL2);
+	readl(sc_base + SC_RSTCTRL2); /* dummy read */
+#endif
+
+	/* provide clocks */
+	tmp = readl(sc_base + SC_CLKCTRL);
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+	tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+		SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+	writel(tmp, sc_base + SC_CLKCTRL);
+	readl(sc_base + SC_CLKCTRL); /* dummy read */
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-pro5.c

@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_pro5_clk_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(sc_base + SC_RSTCTRL);
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+	tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+	writel(tmp, sc_base + SC_RSTCTRL);
+	readl(sc_base + SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+	tmp = readl(sc_base + SC_RSTCTRL2);
+	tmp |= SC_RSTCTRL2_NRST_USB3B1;
+	writel(tmp, sc_base + SC_RSTCTRL2);
+	readl(sc_base + SC_RSTCTRL2); /* dummy read */
+#endif
+
+	/* provide clocks */
+	tmp = readl(sc_base + SC_CLKCTRL);
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+	tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+		SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+	writel(tmp, sc_base + SC_CLKCTRL);
+	readl(sc_base + SC_CLKCTRL); /* dummy read */
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-pxs2.c

@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_pxs2_clk_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(sc_base + SC_RSTCTRL);
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+	tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+	writel(tmp, sc_base + SC_RSTCTRL);
+	readl(sc_base + SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+	tmp = readl(sc_base + SC_RSTCTRL2);
+	tmp |= SC_RSTCTRL2_NRST_USB3B1;
+	writel(tmp, sc_base + SC_RSTCTRL2);
+	readl(sc_base + SC_RSTCTRL2); /* dummy read */
+
+	tmp = readl(sc_base + SC_RSTCTRL6);
+	tmp |= 0x37;
+	writel(tmp, sc_base + SC_RSTCTRL6);
+#endif
+
+	/* provide clocks */
+	tmp = readl(sc_base + SC_CLKCTRL);
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+	tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+		SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+	writel(tmp, sc_base + SC_CLKCTRL);
+	readl(sc_base + SC_CLKCTRL); /* dummy read */
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/clk-pxs3.c

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+#define SDCTRL_EMMC_HW_RESET	0x59810280
+
+void uniphier_pxs3_clk_init(void)
+{
+	u32 tmp;
+
+	tmp = readl(sc_base + SC_RSTCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, sc_base + SC_RSTCTRL6);
+
+	tmp = readl(sc_base + SC_CLKCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, sc_base + SC_CLKCTRL6);
+
+	/* TODO: use "mmc-pwrseq-emmc" */
+	writel(1, SDCTRL_EMMC_HW_RESET);
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/dpll-ld4.c

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+#undef DPLL_SSC_RATE_1PER
+
+int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
+{
+	unsigned int dram_freq = bd->dram_freq;
+	u32 tmp;
+
+	/*
+	 * Set Frequency
+	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+	 * to FOUT (DPLLCTRL.bit[29:20])
+	 */
+	tmp = readl(sc_base + SC_DPLLCTRL);
+	tmp &= ~0x000f0000;
+	switch (dram_freq) {
+	case 1333:
+		tmp |= 0x000d0000;
+		break;
+	case 1600:
+		tmp |= 0x000c0000;
+		break;
+	default:
+		pr_err("Unsupported frequency");
+		return -EINVAL;
+	}
+
+#if defined(DPLL_SSC_RATE_1PER)
+	tmp &= ~SC_DPLLCTRL_SSC_RATE;
+#else
+	tmp |= SC_DPLLCTRL_SSC_RATE;
+#endif
+	writel(tmp, sc_base + SC_DPLLCTRL);
+
+	tmp = readl(sc_base + SC_DPLLCTRL2);
+	tmp |= SC_DPLLCTRL2_NRSTDS;
+	writel(tmp, sc_base + SC_DPLLCTRL2);
+
+	/* Wait 500 usec until dpll gets stable */
+	udelay(500);
+
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/dpll-pro4.c

@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+#undef DPLL_SSC_RATE_1PER
+
+int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
+{
+	unsigned int dram_freq = bd->dram_freq;
+	u32 tmp;
+
+	/*
+	 * Set Frequency
+	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+	 * to FOUT ( DPLLCTRL.bit[29:20] )
+	 */
+	tmp = readl(sc_base + SC_DPLLCTRL);
+	tmp &= ~(0x000f0000);
+	switch (dram_freq) {
+	case 1333:
+		tmp |= 0x000d0000;
+		break;
+	case 1600:
+		tmp |= 0x000c0000;
+		break;
+	default:
+		pr_err("Unsupported frequency");
+		return -EINVAL;
+	}
+
+	/*
+	 * Set Moduration rate
+	 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
+	 */
+#if defined(DPLL_SSC_RATE_1PER)
+	tmp &= ~0x00008000;
+#else
+	tmp |= 0x00008000;
+#endif
+	writel(tmp, sc_base + SC_DPLLCTRL);
+
+	tmp = readl(sc_base + SC_DPLLCTRL2);
+	tmp |= SC_DPLLCTRL2_NRSTDS;
+	writel(tmp, sc_base + SC_DPLLCTRL2);
+
+	/* Wait until dpll gets stable */
+	udelay(500);
+
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/dpll-pro5.c

@@ -0,0 +1,6 @@
+#include "../init.h"
+
+int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd)
+{
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/dpll-pxs2.c

@@ -0,0 +1,6 @@
+#include "../init.h"
+
+int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd)
+{
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/dpll-sld8.c

@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+	/*
+	 * Set DPLL SSC parameters for DPLLCTRL3
+	 * [23]    DIVN_TEST    0x1
+	 * [22:16] DIVN         0x50
+	 * [10]    FREFSEL_TEST 0x1
+	 * [9:8]   FREFSEL      0x2
+	 * [4]     ICPD_TEST    0x1
+	 * [3:0]   ICPD         0xb
+	 */
+	tmp = readl(sc_base + SC_DPLLCTRL3);
+	tmp &= ~0x00ff0717;
+	tmp |= 0x00d0061b;
+	writel(tmp, sc_base + SC_DPLLCTRL3);
+
+	/*
+	 * Set DPLL SSC parameters for DPLLCTRL
+	 *                    <-1%>          <-2%>
+	 * [29:20] SSC_UPCNT 132 (0x084)    132  (0x084)
+	 * [14:0]  SSC_dK    6335(0x18bf)   12710(0x31a6)
+	 */
+	tmp = readl(sc_base + SC_DPLLCTRL);
+	tmp &= ~0x3ff07fff;
+#ifdef DPLL_SSC_RATE_1PER
+	tmp |= 0x084018bf;
+#else
+	tmp |= 0x084031a6;
+#endif
+	writel(tmp, sc_base + SC_DPLLCTRL);
+
+	/*
+	 * Set DPLL SSC parameters for DPLLCTRL2
+	 * [31:29]  SSC_STEP     0
+	 * [27]     SSC_REG_REF  1
+	 * [26:20]  SSC_M        79     (0x4f)
+	 * [19:0]   SSC_K        964689 (0xeb851)
+	 */
+	tmp = readl(sc_base + SC_DPLLCTRL2);
+	tmp &= ~0xefffffff;
+	tmp |= 0x0cfeb851;
+	writel(tmp, sc_base + SC_DPLLCTRL2);
+
+	/* Wait 500 usec until dpll gets stable */
+	udelay(500);
+
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/dpll-tail.c

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/io.h>
+
+#include "../sc-regs.h"
+#include "pll.h"
+
+void uniphier_ld4_dpll_ssc_en(void)
+{
+	u32 tmp;
+
+	tmp = readl(sc_base + SC_DPLLCTRL);
+	tmp |= SC_DPLLCTRL_SSC_EN;
+	writel(tmp, sc_base + SC_DPLLCTRL);
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/pll-base-ld20.c

@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "../sc64-regs.h"
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_PLLCTRL_SSC_DK_MASK		GENMASK(14, 0)
+#define SC_PLLCTRL_SSC_EN		BIT(31)
+#define SC_PLLCTRL2_NRSTDS		BIT(28)
+#define SC_PLLCTRL2_SSC_JK_MASK		GENMASK(26, 0)
+#define SC_PLLCTRL3_REGI_MASK		GENMASK(19, 16)
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27CTRL_WP		BIT(0)
+#define SC_VPLL27CTRL3_K_LD		BIT(28)
+
+/* PLL type: DSPLL */
+#define SC_DSPLLCTRL2_K_LD		BIT(28)
+
+int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
+			      unsigned int ssc_rate, unsigned int divn)
+{
+	void __iomem *base = sc_base + reg_base;
+	u32 tmp;
+
+	if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
+		tmp = readl(base);	/* SSCPLLCTRL */
+		tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
+		tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK,
+				  DIV_ROUND_CLOSEST(487UL * freq * ssc_rate,
+						    divn * 512));
+		writel(tmp, base);
+
+		tmp = readl(base + 4);
+		tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
+		tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK,
+				  DIV_ROUND_CLOSEST(21431887UL * freq,
+						    divn * 512));
+		writel(tmp, base + 4);
+
+		udelay(50);
+	}
+
+	tmp = readl(base + 4);		/* SSCPLLCTRL2 */
+	tmp |= SC_PLLCTRL2_NRSTDS;
+	writel(tmp, base + 4);
+
+	return 0;
+}
+
+int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
+{
+	void __iomem *base = sc_base + reg_base;
+	u32 tmp;
+
+	tmp = readl(base);	/* SSCPLLCTRL */
+	tmp |= SC_PLLCTRL_SSC_EN;
+	writel(tmp, base);
+
+	return 0;
+}
+
+int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
+{
+	void __iomem *base = sc_base + reg_base;
+	u32 tmp;
+
+	tmp = readl(base + 8);	/* SSCPLLCTRL3 */
+	tmp &= ~SC_PLLCTRL3_REGI_MASK;
+	tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
+	writel(tmp, base + 8);
+
+	return 0;
+}
+
+int uniphier_ld20_vpll27_init(unsigned long reg_base)
+{
+	void __iomem *base = sc_base + reg_base;
+	u32 tmp;
+
+	tmp = readl(base);		/* VPLL27CTRL */
+	tmp |= SC_VPLL27CTRL_WP;	/* write protect off */
+	writel(tmp, base);
+
+	tmp = readl(base + 8);		/* VPLL27CTRL3 */
+	tmp |= SC_VPLL27CTRL3_K_LD;
+	writel(tmp, base + 8);
+
+	tmp = readl(base);		/* VPLL27CTRL */
+	tmp &= ~SC_VPLL27CTRL_WP;	/* write protect on */
+	writel(tmp, base);
+
+	return 0;
+}
+
+int uniphier_ld20_dspll_init(unsigned long reg_base)
+{
+	void __iomem *base = sc_base + reg_base;
+	u32 tmp;
+
+	tmp = readl(base + 4);		/* DSPLLCTRL2 */
+	tmp |= SC_DSPLLCTRL2_K_LD;
+	writel(tmp, base + 4);
+
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/pll-ld11.c

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_CPLLCTRL	0x1400	/* CPU/ARM */
+#define SC_SPLLCTRL	0x1410	/* misc */
+#define SC_MPLLCTRL	0x1430	/* DSP */
+#define SC_VSPLLCTRL	0x1440	/* Video codec, VPE etc. */
+#define SC_DPLLCTRL	0x1460	/* DDR memory */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL	0x1500
+#define SC_VPLL27ACTRL	0x1520
+
+void uniphier_ld11_pll_init(void)
+{
+	uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2);	/* 2000MHz -> 1960MHz */
+	/* do nothing for SPLL */
+	uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2);	/* 1500MHz -> 1600MHz */
+	uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+	uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5);
+
+	mdelay(1);
+
+	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLLCTRL);
+
+	uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+	uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+	writel(0, sc_base + SC_CA53_GEARSET);	/* Gear0: CPLL/2 */
+	writel(SC_CA_GEARUPD, sc_base + SC_CA53_GEARUPD);
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/pll-ld20.c

@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/delay.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_CPLLCTRL	0x1400	/* CPU/ARM */
+#define SC_SPLLCTRL	0x1410	/* misc */
+#define SC_SPLL2CTRL	0x1420	/* DSP */
+#define SC_MPLLCTRL	0x1430	/* Video codec */
+#define SC_VPPLLCTRL	0x1440	/* VPE etc. */
+#define SC_GPPLLCTRL	0x1450	/* GPU/Mali */
+#define SC_DPLL0CTRL	0x1460	/* DDR memory 0 */
+#define SC_DPLL1CTRL	0x1470	/* DDR memory 1 */
+#define SC_DPLL2CTRL	0x1480	/* DDR memory 2 */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL	0x1500
+#define SC_VPLL27ACTRL	0x1520
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL	0x1540
+#define SC_A2PLLCTRL	0x15C0
+
+void uniphier_ld20_pll_init(void)
+{
+	uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+	/* do nothing for SPLL */
+	uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+	uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+	uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+	mdelay(1);
+
+	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
+
+	uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+	uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+	uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
+	uniphier_ld20_dspll_init(SC_A2PLLCTRL);
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/pll-ld4.c

@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "pll.h"
+
+static void upll_init(void)
+{
+	u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+	tmp = readl(sg_base + SG_PINMON0);
+	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+	tmp = readl(sc_base + SC_UPLLCTRL);
+	tmp &= ~0x18000000;
+	writel(tmp, sc_base + SC_UPLLCTRL);
+
+	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+			/* AXO: 25MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x0228f5c0;
+		} else {
+			/* AXO: default 24.576MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x02328000;
+		}
+	}
+
+	writel(tmp, sc_base + SC_UPLLCTRL);
+
+	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
+	tmp |= 0x08000000;
+	writel(tmp, sc_base + SC_UPLLCTRL);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
+	tmp |= 0x10000000;
+	writel(tmp, sc_base + SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+	u32 tmp, clk_mode_axosel;
+
+	tmp = readl(sg_base + SG_PINMON0);
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 1 to VPLA27WP and VPLA27WP */
+	tmp = readl(sc_base + SC_VPLL27ACTRL);
+	tmp |= 0x00000001;
+	writel(tmp, sc_base + SC_VPLL27ACTRL);
+	tmp = readl(sc_base + SC_VPLL27BCTRL);
+	tmp |= 0x00000001;
+	writel(tmp, sc_base + SC_VPLL27BCTRL);
+
+	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(sc_base + SC_VPLL27ACTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, sc_base + SC_VPLL27ACTRL3);
+	tmp = readl(sc_base + SC_VPLL27BCTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, sc_base + SC_VPLL27BCTRL3);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(sc_base + SC_VPLL27ACTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, sc_base + SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27BCTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, sc_base + SC_VPLL27BCTRL2);
+
+	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(sc_base + SC_VPLL27ACTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, sc_base + SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27BCTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, sc_base + SC_VPLL27BCTRL2);
+
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+		/* AXO: 25MHz */
+		tmp = readl(sc_base + SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, sc_base + SC_VPLL27ACTRL3);
+		tmp = readl(sc_base + SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, sc_base + SC_VPLL27BCTRL3);
+	} else {
+		/* AXO: default 24.576MHz */
+		tmp = readl(sc_base + SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, sc_base + SC_VPLL27ACTRL3);
+		tmp = readl(sc_base + SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, sc_base + SC_VPLL27BCTRL3);
+	}
+
+	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(sc_base + SC_VPLL27ACTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, sc_base + SC_VPLL27ACTRL3);
+	tmp = readl(sc_base + SC_VPLL27BCTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, sc_base + SC_VPLL27BCTRL3);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(sc_base + SC_VPLL27ACTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, sc_base + SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27BCTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, sc_base + SC_VPLL27BCTRL2);
+
+	/* set 0 to VPLA27WP and VPLA27WP */
+	tmp = readl(sc_base + SC_VPLL27ACTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, sc_base + SC_VPLL27ACTRL);
+	tmp = readl(sc_base + SC_VPLL27BCTRL);
+	tmp |= ~0x00000001;
+	writel(tmp, sc_base + SC_VPLL27BCTRL);
+}
+
+void uniphier_ld4_pll_init(void)
+{
+	upll_init();
+	vpll_init();
+	uniphier_ld4_dpll_ssc_en();
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/pll-pro4.c

@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "pll.h"
+
+static void vpll_init(void)
+{
+	u32 tmp, clk_mode_axosel;
+
+	/* Set VPLL27A &  VPLL27B */
+	tmp = readl(sg_base + SG_PINMON0);
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
+		return;
+
+	/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+	tmp = readl(sc_base + SC_VPLL27ACTRL);
+	tmp |= 0x00000001;
+	writel(tmp, sc_base + SC_VPLL27ACTRL);
+	tmp = readl(sc_base + SC_VPLL27BCTRL);
+	tmp |= 0x00000001;
+	writel(tmp, sc_base + SC_VPLL27BCTRL);
+
+	/* Unset VPLA_K_LD and VPLB_K_LD bit */
+	tmp = readl(sc_base + SC_VPLL27ACTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, sc_base + SC_VPLL27ACTRL3);
+	tmp = readl(sc_base + SC_VPLL27BCTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, sc_base + SC_VPLL27BCTRL3);
+
+	/* Set VPLA_M and VPLB_M to 0x20 */
+	tmp = readl(sc_base + SC_VPLL27ACTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, sc_base + SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27BCTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, sc_base + SC_VPLL27BCTRL2);
+
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
+		/* Set VPLA_K and VPLB_K for AXO: 25MHz */
+		tmp = readl(sc_base + SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066666;
+		writel(tmp, sc_base + SC_VPLL27ACTRL3);
+		tmp = readl(sc_base + SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066666;
+		writel(tmp, sc_base + SC_VPLL27BCTRL3);
+	} else {
+		/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
+		tmp = readl(sc_base + SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, sc_base + SC_VPLL27ACTRL3);
+		tmp = readl(sc_base + SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, sc_base + SC_VPLL27BCTRL3);
+	}
+
+	/* wait 1 usec */
+	udelay(1);
+
+	/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
+	tmp = readl(sc_base + SC_VPLL27ACTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, sc_base + SC_VPLL27ACTRL3);
+	tmp = readl(sc_base + SC_VPLL27BCTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, sc_base + SC_VPLL27BCTRL3);
+
+	/* Unset VPLA_SNRST and VPLB_SNRST bit */
+	tmp = readl(sc_base + SC_VPLL27ACTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, sc_base + SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27BCTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, sc_base + SC_VPLL27BCTRL2);
+
+	/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+	tmp = readl(sc_base + SC_VPLL27ACTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, sc_base + SC_VPLL27ACTRL);
+	tmp = readl(sc_base + SC_VPLL27BCTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, sc_base + SC_VPLL27BCTRL);
+}
+
+void uniphier_pro4_pll_init(void)
+{
+	vpll_init();
+	uniphier_ld4_dpll_ssc_en();
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/pll-pxs3.c

@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ */
+
+#include <linux/delay.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_CPLLCTRL	0x1400	/* CPU/ARM */
+#define SC_SPLLCTRL	0x1410	/* misc */
+#define SC_SPLL2CTRL	0x1420	/* DSP */
+#define SC_VPPLLCTRL	0x1430	/* VPE */
+#define SC_VGPLLCTRL	0x1440
+#define SC_DECPLLCTRL	0x1450
+#define SC_ENCPLLCTRL	0x1460
+#define SC_PXFPLLCTRL	0x1470
+#define SC_DPLL0CTRL	0x1480	/* DDR memory 0 */
+#define SC_DPLL1CTRL	0x1490	/* DDR memory 1 */
+#define SC_DPLL2CTRL	0x14a0	/* DDR memory 2 */
+#define SC_VSPLLCTRL	0x14c0
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL	0x1500
+#define SC_VPLL27ACTRL	0x1520
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL	0x1540
+
+void uniphier_pxs3_pll_init(void)
+{
+	uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+	/* do nothing for SPLL */
+	uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+	uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+	uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+	mdelay(1);
+
+	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+
+	uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+	uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+	uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
+}

source/bootloader/u-boot-2020.01/arch/arm/mach-uniphier/clk/pll.h

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#ifndef MACH_PLL_H
+#define MACH_PLL_H
+
+#define UNIPHIER_PLL_FREQ_DEFAULT	(0)
+
+void uniphier_ld4_dpll_ssc_en(void);
+
+int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
+			      unsigned int ssc_rate, unsigned int divn);
+int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
+int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
+int uniphier_ld20_vpll27_init(unsigned long reg_base);
+int uniphier_ld20_dspll_init(unsigned long reg_base);
+
+#endif /* MACH_PLL_H */