GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/arch/arm/mach-versal/Kconfig

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+# SPDX-License-Identifier: GPL-2.0+
+
+if ARCH_VERSAL
+
+config SYS_BOARD
+	string "Board name"
+	default "versal"
+
+config SYS_VENDOR
+	string "Vendor name"
+	default "xilinx"
+
+config SYS_SOC
+	default "versal"
+
+config SYS_CONFIG_NAME
+	string "Board configuration name"
+	default "xilinx_versal"
+	help
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
+
+config GICV3
+	def_bool y
+
+config SYS_MALLOC_LEN
+	default 0x2000000
+
+config COUNTER_FREQUENCY
+	int "Timer clock frequency"
+	default 0
+	help
+	  Setup time clock frequency for certain platform
+
+config ZYNQ_SDHCI_MAX_FREQ
+	default 200000000
+
+config IOU_SWITCH_DIVISOR0
+	hex "IOU switch divisor0"
+	default 0x20
+	help
+	  Setup time clock divisor for input clock.
+
+config SYS_MEM_RSVD_FOR_MMU
+	bool "Reserve memory for MMU Table"
+	help
+	  If defined this option is used to setup different space for
+	  MMU table than the one which will be allocated during
+	  relocation.
+
+config DEFINE_TCM_OCM_MMAP
+	bool "Define TCM and OCM memory in MMU Table"
+	default y if MP
+	help
+	  This option if enabled defines the TCM and OCM memory and its
+	  memory attributes in MMU table entry.
+
+endif

source/bootloader/u-boot-2020.01/arch/arm/mach-versal/Makefile

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+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 - 2018 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+
+obj-y	+= clk.o
+obj-y	+= cpu.o
+obj-$(CONFIG_SYS_MEM_RSVD_FOR_MMU)	+= mp.o

source/bootloader/u-boot-2020.01/arch/arm/mach-versal/clk.c

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+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 - 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CLOCKS
+/**
+ * set_cpu_clk_info - Initialize clock framework
+ *
+ * Return: 0 always.
+ *
+ * This function is called from common code after relocation and sets up the
+ * clock framework. The framework must not be used before this function had been
+ * called.
+ */
+int set_cpu_clk_info(void)
+{
+	gd->cpu_clk = get_tbclk();
+
+	gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+	gd->bd->bi_dsp_freq = 0;
+
+	return 0;
+}
+#endif

source/bootloader/u-boot-2020.01/arch/arm/mach-versal/cpu.c

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+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 - 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define VERSAL_MEM_MAP_USED	5
+
+#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+#define TCM_MAP 1
+#else
+#define TCM_MAP 0
+#endif
+
+/* +1 is end of list which needs to be empty */
+#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
+
+static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
+	{
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x70000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0xf0000000UL,
+		.phys = 0xf0000000UL,
+		.size = 0x0fe00000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x400000000UL,
+		.phys = 0x400000000UL,
+		.size = 0x200000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x600000000UL,
+		.phys = 0x600000000UL,
+		.size = 0x800000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xe00000000UL,
+		.phys = 0xe00000000UL,
+		.size = 0xf200000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}
+};
+
+void mem_map_fill(void)
+{
+	int banks = VERSAL_MEM_MAP_USED;
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+	versal_mem_map[banks].virt = 0xffe00000UL;
+	versal_mem_map[banks].phys = 0xffe00000UL;
+	versal_mem_map[banks].size = 0x00200000UL;
+	versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				      PTE_BLOCK_INNER_SHARE;
+	banks = banks + 1;
+#endif
+
+	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* Zero size means no more DDR that's this is end */
+		if (!gd->bd->bi_dram[i].size)
+			break;
+
+		versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
+		versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
+		versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+		versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+					      PTE_BLOCK_INNER_SHARE;
+		banks = banks + 1;
+	}
+}
+
+struct mm_region *mem_map = versal_mem_map;
+
+u64 get_page_table_size(void)
+{
+	return 0x14000;
+}
+
+#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
+int reserve_mmu(void)
+{
+	tcm_init(TCM_LOCK);
+	gd->arch.tlb_size = PGTABLE_SIZE;
+	gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
+
+	return 0;
+}
+#endif

source/bootloader/u-boot-2020.01/arch/arm/mach-versal/include/mach/gpio.h

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+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - 2018 Xilinx, Inc.
+ */
+
+/* Empty file - for compilation */

source/bootloader/u-boot-2020.01/arch/arm/mach-versal/include/mach/hardware.h

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+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - 2018 Xilinx, Inc.
+ */
+
+#define VERSAL_CRL_APB_BASEADDR	0xFF5E0000
+
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	BIT(25)
+
+#define IOU_SWITCH_CTRL_CLKACT_BIT	BIT(25)
+#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT	8
+
+struct crlapb_regs {
+	u32 reserved0[67];
+	u32 cpu_r5_ctrl;
+	u32 reserved;
+	u32 iou_switch_ctrl; /* 0x114 */
+	u32 reserved1[13];
+	u32 timestamp_ref_ctrl; /* 0x14c */
+	u32 reserved3[108];
+	u32 rst_cpu_r5;
+	u32 reserved2[17];
+	u32 rst_timestamp; /* 0x348 */
+};
+
+#define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR)
+
+#define VERSAL_IOU_SCNTR_SECURE	0xFF140000
+
+#define IOU_SCNTRS_CONTROL_EN	1
+
+struct iou_scntrs_regs {
+	u32 counter_control_register; /* 0x0 */
+	u32 reserved0[7];
+	u32 base_frequency_id_register; /* 0x20 */
+};
+
+#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE)
+
+#define VERSAL_TCM_BASE_ADDR	0xFFE00000
+#define VERSAL_TCM_SIZE		0x40000
+
+#define VERSAL_RPU_BASEADDR	0xFF9A0000
+
+struct rpu_regs {
+	u32 rpu_glbl_ctrl;
+	u32 reserved0[63];
+	u32 rpu0_cfg; /* 0x100 */
+	u32 reserved1[63];
+	u32 rpu1_cfg; /* 0x200 */
+};
+
+#define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR)
+
+#define VERSAL_CRP_BASEADDR	0xF1260000
+
+struct crp_regs {
+	u32 reserved0[128];
+	u32 boot_mode_usr;
+};
+
+#define crp_base ((struct crp_regs *)VERSAL_CRP_BASEADDR)
+
+/* Bootmode setting values */
+#define BOOT_MODES_MASK	0x0000000F
+#define QSPI_MODE_24BIT	0x00000001
+#define QSPI_MODE_32BIT	0x00000002
+#define SD_MODE		0x00000003 /* sd 0 */
+#define SD_MODE1	0x00000005 /* sd 1 */
+#define EMMC_MODE	0x00000006
+#define USB_MODE	0x00000007
+#define OSPI_MODE	0x00000008
+#define SD1_LSHFT_MODE	0x0000000E /* SD1 Level shifter */
+#define JTAG_MODE	0x00000000
+#define BOOT_MODE_USE_ALT	0x100
+#define BOOT_MODE_ALT_SHIFT	12

source/bootloader/u-boot-2020.01/arch/arm/mach-versal/include/mach/sys_proto.h

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+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - 2018 Xilinx, Inc.
+ */
+
+enum {
+	TCM_LOCK,
+	TCM_SPLIT,
+};
+
+#define PAYLOAD_ARG_CNT	4U
+
+void tcm_init(u8 mode);
+void mem_map_fill(void);

source/bootloader/u-boot-2020.01/arch/arm/mach-versal/mp.c

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+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 Xilinx, Inc.
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HALT		0
+#define RELEASE		1
+
+#define VERSAL_RPU_CFG_CPU_HALT_MASK		0x01
+#define VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK	0x08
+#define VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK	0x40
+#define VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK	0x10
+
+#define VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK	0x04
+#define VERSAL_CRLAPB_RST_LPD_R50_RST_MASK	0x01
+#define VERSAL_CRLAPB_RST_LPD_R51_RST_MASK	0x02
+#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK	0x10
+#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK	0x1000000
+
+void set_r5_halt_mode(u8 halt, u8 mode)
+{
+	u32 tmp;
+
+	tmp = readl(&rpu_base->rpu0_cfg);
+	if (halt == HALT)
+		tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
+	else
+		tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
+	writel(tmp, &rpu_base->rpu0_cfg);
+
+	if (mode == TCM_LOCK) {
+		tmp = readl(&rpu_base->rpu1_cfg);
+		if (halt == HALT)
+			tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
+		else
+			tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
+		writel(tmp, &rpu_base->rpu1_cfg);
+	}
+}
+
+void set_r5_tcm_mode(u8 mode)
+{
+	u32 tmp;
+
+	tmp = readl(&rpu_base->rpu_glbl_ctrl);
+	if (mode == TCM_LOCK) {
+		tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
+		tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
+		       VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK;
+	} else {
+		tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
+		tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
+		       VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK);
+	}
+
+	writel(tmp, &rpu_base->rpu_glbl_ctrl);
+}
+
+void release_r5_reset(u8 mode)
+{
+	u32 tmp;
+
+	tmp = readl(&crlapb_base->rst_cpu_r5);
+	tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK |
+	       VERSAL_CRLAPB_RST_LPD_R50_RST_MASK |
+	       VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK);
+
+	if (mode == TCM_LOCK)
+		tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK;
+
+	writel(tmp, &crlapb_base->rst_cpu_r5);
+}
+
+void enable_clock_r5(void)
+{
+	u32 tmp;
+
+	tmp = readl(&crlapb_base->cpu_r5_ctrl);
+	tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
+	writel(tmp, &crlapb_base->cpu_r5_ctrl);
+}
+
+void initialize_tcm(bool mode)
+{
+	if (!mode) {
+		set_r5_tcm_mode(TCM_LOCK);
+		set_r5_halt_mode(HALT, TCM_LOCK);
+		enable_clock_r5();
+		release_r5_reset(TCM_LOCK);
+	} else {
+		set_r5_tcm_mode(TCM_SPLIT);
+		set_r5_halt_mode(HALT, TCM_SPLIT);
+		enable_clock_r5();
+		release_r5_reset(TCM_SPLIT);
+	}
+}
+
+void tcm_init(u8 mode)
+{
+	puts("WARNING: Initializing TCM overwrites TCM content\n");
+	initialize_tcm(mode);
+	memset((void *)VERSAL_TCM_BASE_ADDR, 0, VERSAL_TCM_SIZE);
+}