GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ */
+
+#ifndef _ZYNQ_CLK_H_
+#define _ZYNQ_CLK_H_
+
+enum zynq_clk {
+	armpll_clk, ddrpll_clk, iopll_clk,
+	cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
+	ddr2x_clk, ddr3x_clk, dci_clk,
+	lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
+	fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
+	sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
+	usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
+	sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
+	can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
+	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
+	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
+
+#endif
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Xilinx, Inc.
+ * Copyright (c) 2015 DAVE Embedded Systems
+ */
+
+#ifndef _ZYNQ_GPIO_H
+#define _ZYNQ_GPIO_H
+
+#endif /* _ZYNQ_GPIO_H */
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define ZYNQ_SYS_CTRL_BASEADDR		0xF8000000
+#define ZYNQ_DEV_CFG_APB_BASEADDR	0xF8007000
+#define ZYNQ_SCU_BASEADDR		0xF8F00000
+#define ZYNQ_QSPI_BASEADDR		0xE000D000
+#define ZYNQ_SMC_BASEADDR		0xE000E000
+#define ZYNQ_NAND_BASEADDR		0xE1000000
+#define ZYNQ_DDRC_BASEADDR		0xF8006000
+#define ZYNQ_EFUSE_BASEADDR		0xF800D000
+#define ZYNQ_USB_BASEADDR0		0xE0002000
+#define ZYNQ_USB_BASEADDR1		0xE0003000
+#define ZYNQ_OCM_BASEADDR		0xFFFC0000
+
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK		0x7
+#define ZYNQ_BM_QSPI		0x1
+#define ZYNQ_BM_NOR		0x2
+#define ZYNQ_BM_NAND		0x4
+#define ZYNQ_BM_SD		0x5
+#define ZYNQ_BM_JTAG		0x0
+
+/* Reflect slcr offsets */
+struct slcr_regs {
+	u32 scl; /* 0x0 */
+	u32 slcr_lock; /* 0x4 */
+	u32 slcr_unlock; /* 0x8 */
+	u32 reserved0_1[61];
+	u32 arm_pll_ctrl; /* 0x100 */
+	u32 ddr_pll_ctrl; /* 0x104 */
+	u32 io_pll_ctrl; /* 0x108 */
+	u32 reserved0_2[5];
+	u32 arm_clk_ctrl; /* 0x120 */
+	u32 ddr_clk_ctrl; /* 0x124 */
+	u32 dci_clk_ctrl; /* 0x128 */
+	u32 aper_clk_ctrl; /* 0x12c */
+	u32 reserved0_3[2];
+	u32 gem0_rclk_ctrl; /* 0x138 */
+	u32 gem1_rclk_ctrl; /* 0x13c */
+	u32 gem0_clk_ctrl; /* 0x140 */
+	u32 gem1_clk_ctrl; /* 0x144 */
+	u32 smc_clk_ctrl; /* 0x148 */
+	u32 lqspi_clk_ctrl; /* 0x14c */
+	u32 sdio_clk_ctrl; /* 0x150 */
+	u32 uart_clk_ctrl; /* 0x154 */
+	u32 spi_clk_ctrl; /* 0x158 */
+	u32 can_clk_ctrl; /* 0x15c */
+	u32 can_mioclk_ctrl; /* 0x160 */
+	u32 dbg_clk_ctrl; /* 0x164 */
+	u32 pcap_clk_ctrl; /* 0x168 */
+	u32 reserved0_4[1];
+	u32 fpga0_clk_ctrl; /* 0x170 */
+	u32 reserved0_5[3];
+	u32 fpga1_clk_ctrl; /* 0x180 */
+	u32 reserved0_6[3];
+	u32 fpga2_clk_ctrl; /* 0x190 */
+	u32 reserved0_7[3];
+	u32 fpga3_clk_ctrl; /* 0x1a0 */
+	u32 reserved0_8[8];
+	u32 clk_621_true; /* 0x1c4 */
+	u32 reserved1[14];
+	u32 pss_rst_ctrl; /* 0x200 */
+	u32 reserved2[15];
+	u32 fpga_rst_ctrl; /* 0x240 */
+	u32 reserved3[5];
+	u32 reboot_status; /* 0x258 */
+	u32 boot_mode; /* 0x25c */
+	u32 reserved4[116];
+	u32 trust_zone; /* 0x430 */ /* FIXME */
+	u32 reserved5_1[63];
+	u32 pss_idcode; /* 0x530 */
+	u32 reserved5_2[51];
+	u32 ddr_urgent; /* 0x600 */
+	u32 reserved6[6];
+	u32 ddr_urgent_sel; /* 0x61c */
+	u32 reserved7[56];
+	u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+	u32 reserved8[74];
+	u32 lvl_shftr_en; /* 0x900 */
+	u32 reserved9[3];
+	u32 ocm_cfg; /* 0x910 */
+};
+
+#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
+
+struct devcfg_regs {
+	u32 ctrl; /* 0x0 */
+	u32 lock; /* 0x4 */
+	u32 cfg; /* 0x8 */
+	u32 int_sts; /* 0xc */
+	u32 int_mask; /* 0x10 */
+	u32 status; /* 0x14 */
+	u32 dma_src_addr; /* 0x18 */
+	u32 dma_dst_addr; /* 0x1c */
+	u32 dma_src_len; /* 0x20 */
+	u32 dma_dst_len; /* 0x24 */
+	u32 rom_shadow; /* 0x28 */
+	u32 reserved1[2];
+	u32 unlock; /* 0x34 */
+	u32 reserved2[18];
+	u32 mctrl; /* 0x80 */
+	u32 reserved3;
+	u32 write_count; /* 0x88 */
+	u32 read_count; /* 0x8c */
+};
+
+#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
+
+struct scu_regs {
+	u32 reserved1[16];
+	u32 filter_start; /* 0x40 */
+	u32 filter_end; /* 0x44 */
+};
+
+#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
+
+struct ddrc_regs {
+	u32 ddrc_ctrl; /* 0x0 */
+	u32 reserved[60];
+	u32 ecc_scrub; /* 0xF4 */
+};
+#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
+
+struct efuse_reg {
+	u32 reserved1[4];
+	u32 status;
+	u32 reserved2[3];
+};
+
+#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
+
+#endif /* _ASM_ARCH_HARDWARE_H */
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ */
+
+#ifndef _ASM_ARCH_PS7_INIT_GPL_H
+#define _ASM_ARCH_PS7_INIT_GPL_H
+
+/* Opcode exit is 0 all the time */
+#define OPCODE_EXIT		0U
+#define OPCODE_MASKWRITE	0U
+#define OPCODE_MASKPOLL		1U
+#define OPCODE_MASKDELAY	2U
+#define OPCODE_WRITE		3U
+#define OPCODE_ADDRESS_MASK	(~3U)
+
+/* Sentinel */
+#define EMIT_EXIT()			OPCODE_EXIT
+/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
+#define EMIT_MASKWRITE(addr, mask, val)	OPCODE_MASKWRITE | addr, mask, val
+#define EMIT_MASKPOLL(addr, mask)	OPCODE_MASKPOLL | addr, mask
+#define EMIT_MASKDELAY(addr, mask)	OPCODE_MASKDELAY | addr, mask
+#define EMIT_WRITE(addr, val)		OPCODE_WRITE | addr, val
+
+/* Returns codes of ps7_init* */
+#define PS7_INIT_SUCCESS		(0)
+#define PS7_INIT_CORRUPT		(1)
+#define PS7_INIT_TIMEOUT		(2)
+#define PS7_POLL_FAILED_DDR_INIT	(3)
+#define PS7_POLL_FAILED_DMA		(4)
+#define PS7_POLL_FAILED_PLL		(5)
+
+#define PCW_SILICON_VERSION_1	0
+#define PCW_SILICON_VERSION_2	1
+#define PCW_SILICON_VERSION_3	2
+
+/* Called by spl.c */
+int ps7_init(void);
+int ps7_post_config(void);
+
+/* Defined in ps7_init_common.c */
+int ps7_config(unsigned long *ps7_config_init);
+
+unsigned long ps7GetSiliconVersion(void);
+
+#endif /* _ASM_ARCH_PS7_INIT_GPL_H */
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+extern void zynq_slcr_lock(void);
+extern void zynq_slcr_unlock(void);
+extern void zynq_slcr_cpu_reset(void);
+extern void zynq_slcr_devcfg_disable(void);
+extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_boot_mode(void);
+extern u32 zynq_slcr_get_idcode(void);
+extern int zynq_slcr_get_mio_pin_status(const char *periph);
+extern void zynq_ddrc_init(void);
+extern unsigned int zynq_get_silicon_version(void);
+
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
+
+#endif /* _SYS_PROTO_H_ */