GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/arch/m68k/Kconfig

@@ -0,0 +1,260 @@
+menu "M68000 architecture"
+	depends on M68K
+
+config SYS_ARCH
+	default "m68k"
+
+# processor family
+config MCF520x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF52x2
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF523x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF530x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF5301x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF532x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF537x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF5441x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF5445x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF5227x
+	select OF_CONTROL
+	select DM
+        select DM_SERIAL
+	bool
+
+config MCF547x_8x
+	select OF_CONTROL
+        select DM
+        select DM_SERIAL
+	bool
+
+# processor type
+config M5208
+	bool
+	select MCF520x
+
+config M5235
+	bool
+	select MCF523x
+
+config M5249
+	bool
+	select MCF52x2
+
+config M5253
+	bool
+	select MCF52x2
+
+config M5271
+	bool
+	select MCF52x2
+
+config M5272
+	bool
+	select MCF52x2
+
+config M5275
+	bool
+	select MCF52x2
+
+config M5282
+	bool
+	select MCF52x2
+
+config M5307
+	bool
+	select MCF530x
+
+config M53015
+	bool
+	select MCF5301x
+
+config M5329
+	bool
+	select MCF532x
+
+config M5373
+	bool
+	select MCF532x
+	select MCF537x
+
+config M54418
+	bool
+	select MCF5441x
+
+config M54451
+	bool
+	select MCF5445x
+
+config M54455
+	bool
+	select MCF5445x
+
+config M52277
+	bool
+	select MCF5227x
+
+config M547x
+	bool
+	select MCF547x_8x
+
+config M548x
+	bool
+	select MCF547x_8x
+
+choice
+	prompt "Target select"
+	optional
+
+config TARGET_M52277EVB
+	bool "Support M52277EVB"
+	select M52277
+
+config TARGET_M5235EVB
+	bool "Support M5235EVB"
+	select M5235
+
+config TARGET_COBRA5272
+	bool "Support cobra5272"
+	select M5272
+
+config TARGET_EB_CPU5282
+	bool "Support eb_cpu5282"
+	select M5282
+
+config TARGET_M5208EVBE
+	bool "Support M5208EVBE"
+	select M5208
+
+config TARGET_M5249EVB
+	bool "Support M5249EVB"
+	select M5249
+
+config TARGET_M5253DEMO
+	bool "Support M5253DEMO"
+	select M5253
+
+config TARGET_M5272C3
+	bool "Support M5272C3"
+	select M5272
+
+config TARGET_M5275EVB
+	bool "Support M5275EVB"
+	select M5275
+
+config TARGET_M5282EVB
+	bool "Support M5282EVB"
+	select M5282
+
+config TARGET_ASTRO_MCF5373L
+	bool "Support astro_mcf5373l"
+	select M5373
+
+config TARGET_M53017EVB
+	bool "Support M53017EVB"
+	select M53015
+
+config TARGET_M5329EVB
+	bool "Support M5329EVB"
+	select M5329
+
+config TARGET_M5373EVB
+	bool "Support M5373EVB"
+	select M5373
+
+config TARGET_M54418TWR
+	bool "Support M54418TWR"
+	select M54418
+
+config TARGET_M54451EVB
+	bool "Support M54451EVB"
+	select M54451
+
+config TARGET_M54455EVB
+	bool "Support M54455EVB"
+	select M54455
+
+config TARGET_M5475EVB
+	bool "Support M5475EVB"
+	select M547x
+
+config TARGET_M5485EVB
+	bool "Support M5485EVB"
+	select M548x
+
+config TARGET_AMCORE
+	bool "Support AMCORE"
+	select M5307
+
+config TARGET_STMARK2
+        bool "Support stmark2"
+        select M54418
+
+endchoice
+
+source "board/BuS/eb_cpu5282/Kconfig"
+source "board/astro/mcf5373l/Kconfig"
+source "board/cobra5272/Kconfig"
+source "board/freescale/m5208evbe/Kconfig"
+source "board/freescale/m52277evb/Kconfig"
+source "board/freescale/m5235evb/Kconfig"
+source "board/freescale/m5249evb/Kconfig"
+source "board/freescale/m5253demo/Kconfig"
+source "board/freescale/m5272c3/Kconfig"
+source "board/freescale/m5275evb/Kconfig"
+source "board/freescale/m5282evb/Kconfig"
+source "board/freescale/m53017evb/Kconfig"
+source "board/freescale/m5329evb/Kconfig"
+source "board/freescale/m5373evb/Kconfig"
+source "board/freescale/m54418twr/Kconfig"
+source "board/freescale/m54451evb/Kconfig"
+source "board/freescale/m54455evb/Kconfig"
+source "board/freescale/m547xevb/Kconfig"
+source "board/freescale/m548xevb/Kconfig"
+source "board/sysam/amcore/Kconfig"
+source "board/sysam/stmark2/Kconfig"
+
+endmenu

source/bootloader/u-boot-2020.01/arch/m68k/Makefile

@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+head-y := arch/m68k/cpu/$(CPU)/start.o
+
+libs-y += arch/m68k/cpu/$(CPU)/
+libs-y += arch/m68k/lib/
+
+cpuflags-$(CONFIG_M5208)	:= -mcpu=5208
+cpuflags-$(CONFIG_M5235)	:= -mcpu=5235 -fPIC
+cpuflags-$(CONFIG_M52277)	:= -mcpu=52277 -fPIC
+cpuflags-$(CONFIG_M5249)	:= -mcpu=5249
+cpuflags-$(CONFIG_M5253)	:= -mcpu=5253
+cpuflags-$(CONFIG_M5271)	:= -mcpu=5271
+cpuflags-$(CONFIG_M5272)	:= -mcpu=5272
+cpuflags-$(CONFIG_M5275)	:= -mcpu=5275
+cpuflags-$(CONFIG_M5282)	:= -mcpu=5282
+cpuflags-$(CONFIG_M5307)	:= -mcpu=5307
+cpuflags-$(CONFIG_MCF5301x)	:= -mcpu=53015 -fPIC
+cpuflags-$(CONFIG_MCF532x)	:= -mcpu=5329 -fPIC
+cpuflags-$(CONFIG_MCF5441x)	:= -mcpu=54418 -fPIC
+cpuflags-$(CONFIG_MCF5445x)	:= -mcpu=54455 -fPIC
+cpuflags-$(CONFIG_MCF547x_8x)	:= -mcpu=5485 -fPIC
+
+PLATFORM_CPPFLAGS += $(cpuflags-y)
+
+
+ldflags-$(CONFIG_MCF5441x)	:= --got=single
+ldflags-$(CONFIG_MCF5445x)	:= --got=single
+ldflags-$(CONFIG_MCF547x_8x)	:= --got=single
+
+ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
+ifneq (,$(findstring GOT,$(shell $(LD) --help)))
+PLATFORM_LDFLAGS += $(ldflags-y)
+endif
+endif

source/bootloader/u-boot-2020.01/arch/m68k/config.mk

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := m68k-elf-
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
+
+PLATFORM_CPPFLAGS += -D__M68K__
+PLATFORM_LDFLAGS  += -n
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+LDFLAGS_FINAL                  += --gc-sections

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5227x/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+# ccflags-y += -DET_DEBUG
+
+extra-y	= start.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o dspi.o

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5227x/cpu.c

@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <watchdog.h>
+#include <command.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+	udelay(1000);
+	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
+
+	/* we don't return! */
+	return 0;
+};
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	u16 msk;
+	u16 id = 0;
+	u8 ver;
+
+	puts("CPU:   ");
+	msk = (in_be16(&ccm->cir) >> 6);
+	ver = (in_be16(&ccm->cir) & 0x003f);
+	switch (msk) {
+	case 0x6c:
+		id = 52277;
+		break;
+	}
+
+	if (id) {
+		char buf1[32], buf2[32], buf3[32];
+
+		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
+		       ver);
+		printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
+		       strmhz(buf1, gd->cpu_clk),
+		       strmhz(buf2, gd->bus_clk),
+		       strmhz(buf3, gd->arch.flb_clk));
+		printf("       INP CLK %s MHz VCO CLK %s MHz\n",
+		       strmhz(buf1, gd->arch.inp_clk),
+		       strmhz(buf2, gd->arch.vco_clk));
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5227x/cpu_init.c

@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <watchdog.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <asm/rtc.h>
+#include <linux/compiler.h>
+
+void cfspi_port_conf(void)
+{
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+	out_8(&gpio->par_dspi,
+	      GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	      GPIO_PAR_DSPI_SCK_SCK);
+}
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
+
+#if !defined(CONFIG_CF_SBF)
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	pll_t *pll = (pll_t *)MMAP_PLL;
+
+	/* Workaround, must place before fbcs */
+	out_be32(&pll->psr, 0x12);
+
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
+	out_be32(&scm1->pacrg, 0);
+	out_be32(&scm1->pacri, 0);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#endif
+#endif				/* CONFIG_CF_SBF */
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
+#endif
+
+#ifdef CONFIG_SYS_I2C_FSL
+	out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
+#endif
+
+	icache_enable();
+
+	cfspi_port_conf();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+#ifdef CONFIG_MCFRTC
+	rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+	rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
+
+	out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
+#endif
+
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		clrbits_be16(&gpio->par_uart,
+			~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		break;
+	case 1:
+		clrbits_be16(&gpio->par_uart,
+			~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+		break;
+	case 2:
+		clrbits_8(&gpio->par_dspi,
+			~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
+		out_8(&gpio->par_dspi,
+			GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
+		break;
+	}
+}

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5227x/dspi.c

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Angelo Dureghello <angleo@sysam.it>
+ *
+ * CPU specific dspi routines
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CF_DSPI
+void dspi_chip_select(int cs)
+{
+	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		break;
+	case 2:
+		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+		setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
+		break;
+	}
+}
+
+void dspi_chip_unselect(int cs)
+{
+	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		break;
+	case 2:
+		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+		break;
+	}
+}
+#endif /* CONFIG_CF_DSPI */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5227x/interrupts.c

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <irq_func.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+int interrupt_init(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	/* Make sure all interrupts are disabled */
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
+
+	enable_interrupts();
+	return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5227x/speed.c

@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Low Power Divider specifications
+ */
+#define CLOCK_LPD_MIN		(1 << 0)	/* Divider (decoded) */
+#define CLOCK_LPD_MAX		(1 << 15)	/* Divider (decoded) */
+
+#define CLOCK_PLL_FVCO_MAX	540000000
+#define CLOCK_PLL_FVCO_MIN	300000000
+
+#define CLOCK_PLL_FSYS_MAX	266666666
+#define CLOCK_PLL_FSYS_MIN	100000000
+#define MHZ			1000000
+
+void clock_enter_limp(int lpdiv)
+{
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	int i, j;
+
+	/* Check bounds of divider */
+	if (lpdiv < CLOCK_LPD_MIN)
+		lpdiv = CLOCK_LPD_MIN;
+	if (lpdiv > CLOCK_LPD_MAX)
+		lpdiv = CLOCK_LPD_MAX;
+
+	/* Round divider down to nearest power of two */
+	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
+
+	/* Apply the divider to the system clock */
+	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
+
+	/* Enable Limp Mode */
+	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
+}
+
+/*
+ * brief   Exit Limp mode
+ * warning The PLL should be set and locked prior to exiting Limp mode
+ */
+void clock_exit_limp(void)
+{
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
+
+	/* Exit Limp mode */
+	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
+
+	/* Wait for the PLL to lock */
+	while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
+		;
+}
+
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
+	int vco, temp, pcrvalue, pfdr;
+	u8 bootmode;
+
+	pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
+	pfdr = pcrvalue >> 24;
+
+	if (pfdr == 0x1E)
+		bootmode = 0;	/* Normal Mode */
+
+#ifdef CONFIG_CF_SBF
+	bootmode = 3;		/* Serial Mode */
+#endif
+
+	if (bootmode == 0) {
+		/* Normal mode */
+		vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
+			/* Default value */
+			pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
+			pcrvalue |= 0x1E << 24;
+			out_be32(&pll->pcr, pcrvalue);
+			vco =
+			    ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
+			    CONFIG_SYS_INPUT_CLKSRC;
+		}
+		gd->arch.vco_clk = vco;	/* Vco clock */
+	} else if (bootmode == 3) {
+		/* serial mode */
+		vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		gd->arch.vco_clk = vco;	/* Vco clock */
+	}
+
+	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+		/* Limp mode */
+	} else {
+		gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
+
+		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
+		gd->cpu_clk = vco / temp;	/* cpu clock */
+
+		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+		gd->arch.flb_clk = vco / temp;	/* flexbus clock */
+		gd->bus_clk = gd->arch.flb_clk;
+	}
+
+#ifdef CONFIG_SYS_I2C_FSL
+	gd->arch.i2c1_clk = gd->bus_clk;
+#endif
+
+	return (0);
+}

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5227x/start.S

@@ -0,0 +1,495 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#define _START	_start
+#define _FAULT	_fault
+
+#define SAVE_ALL						\
+	move.w	#0x2700,%sr;		/* disable intrs */	\
+	subl	#60,%sp;		/* space for 15 regs */ \
+	moveml	%d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL						\
+	moveml	%sp@,%d0-%d7/%a0-%a6;				\
+	addl	#60,%sp;		/* space for 15 regs */ \
+	rte;
+
+#if defined(CONFIG_CF_SBF)
+#define ASM_DRAMINIT	(asm_dram_init - CONFIG_SYS_TEXT_BASE + \
+	CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
+	CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+
+.text
+
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+#if defined(CONFIG_CF_SBF)
+INITSP:	.long	0			/* Initial SP	*/
+INITPC:	.long	ASM_DRAMINIT		/* Initial PC 	*/
+#else
+INITSP:	.long	0			/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC 	*/
+#endif
+
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved */
+vector10_17:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+#if !defined(CONFIG_CF_SBF)
+/* TRAP #0 - #15 */
+vector20_2F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved	*/
+vector30_3F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+#endif
+
+#if defined(CONFIG_CF_SBF)
+	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
+asm_sbf_img_hdr:
+	.long	0x00000000		/* checksum, not yet implemented */
+	.long	0x00020000		/* image length */
+	.long	CONFIG_SYS_TEXT_BASE	/* image to be relocated at */
+
+asm_dram_init:
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1		/* init Rambar */
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	clr.l	%sp@-
+
+	/* Must disable global address */
+	move.l	#0xFC008000, %a1
+	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#0xFC008008, %a1
+	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#0xFC008004, %a1
+	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+
+	/*
+	 * Dram Initialization
+	 * a1, a2, and d0
+	 */
+	move.l	#0xFC0A4074, %a1
+	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
+	nop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#0xFC0B8110, %a1
+	move.l	#0xFC0B8114, %a2
+
+	/* calculate the size */
+	move.l	#0x13, %d1
+	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	lsr.l	#1, %d2
+#endif
+
+dramsz_loop:
+	lsr.l	#1, %d2
+	add.l	#1, %d1
+	cmp.l	#1, %d2
+	bne	dramsz_loop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
+	or.l	%d1, (%a1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
+	or.l	%d1, (%a2)
+#endif
+	nop
+
+	/* dram cfg1 and cfg2 */
+	move.l	#0xFC0B8008, %a1
+	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
+	nop
+	move.l	#0xFC0B800C, %a2
+	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
+	nop
+
+	move.l	#0xFC0B8000, %a1	/* Mode */
+	move.l	#0xFC0B8004, %a2	/* Ctrl */
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Issue LEMR */
+	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
+	nop
+	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
+	nop
+
+	move.l	#1000, %d0
+wait1000:
+	nop
+	subq.l	#1, %d0
+	bne	wait1000
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Perform two refresh cycles */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
+	nop
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a2)
+	nop
+
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d0
+	and.l	#0x7FFFFFFF, %d0
+	or.l	#0x10000c00, %d0
+	move.l	%d0, (%a2)
+	nop
+
+	/*
+	 * DSPI Initialization
+	 * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
+	 * a1 - dspi status
+	 * a2 - dtfr
+	 * a3 - drfr
+	 * a4 - Dst addr
+	 */
+
+	/* Enable pins for DSPI mode - chip-selects are enabled later */
+	move.l	#0xFC0A4036, %a0
+	move.b	#0x3F, %d0
+	move.b	%d0, (%a0)
+
+	/* DSPI CS */
+#ifdef CONFIG_SYS_DSPI_CS0
+	move.b	(%a0), %d0
+	or.l	#0xC0, %d0
+	move.b	%d0, (%a0)
+#endif
+#ifdef CONFIG_SYS_DSPI_CS2
+	move.l	#0xFC0A4037, %a0
+	move.b	(%a0), %d0
+	or.l	#0x10, %d0
+	move.b	%d0, (%a0)
+#endif
+	nop
+
+	/* Configure DSPI module */
+	move.l	#0xFC05C000, %a0
+	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
+
+	move.l	#0xFC05C00C, %a0
+	move.l	#0x3E000011, (%a0)
+
+	move.l	#0xFC05C034, %a2	/* dtfr */
+	move.l	#0xFC05C03B, %a3	/* drfr */
+
+	move.l	#(ASM_SBF_IMG_HDR + 4), %a1
+	move.l	(%a1)+, %d5
+	move.l	(%a1), %a4
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
+	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
+
+	move.l	#0xFC05C02C, %a1	/* dspi status */
+
+	/* Issue commands and address */
+	move.l	#0x8004000B, %d2	/* Fast Read Cmd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 2 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 1 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 0 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Dummy Wr and Rd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* Transfer serial boot header to sram */
+asm_dspi_rd_loop1:
+	move.l	#0x80040000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a0)		/* read, copy to dst */
+
+	add.l	#1, %a0			/* inc dst by 1 */
+	sub.l	#1, %d4			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop1
+
+	/* Transfer u-boot from serial flash to memory */
+asm_dspi_rd_loop2:
+	move.l	#0x80040000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a4)		/* read, copy to dst */
+
+	add.l	#1, %a4			/* inc dst by 1 */
+	sub.l	#1, %d5			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop2
+
+	move.l	#0x00040000, %d2	/* Terminate */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* jump to memory and execute */
+	move.l	#(CONFIG_SYS_TEXT_BASE + 0x400), %a0
+	move.l	%a0, (%a1)
+	jmp	(%a0)
+
+asm_dspi_wr_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x0000F000, %d0
+	cmp.l	#0x00003000, %d0
+	bgt	asm_dspi_wr_status
+
+	move.l	%d2, (%a2)
+	rts
+
+asm_dspi_rd_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x000000F0, %d0
+	lsr.l	#4, %d0
+	cmp.l	#0, %d0
+	beq	asm_dspi_rd_status
+
+	move.b	(%a3), %d1
+	rts
+#endif /* CONFIG_CF_SBF */
+
+.text
+	. = 0x400
+.globl _start
+_start:
+	nop
+	nop
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
+
+	/* Set vector base register at the beginning of the Flash */
+#if defined(CONFIG_CF_SBF)
+	move.l	#CONFIG_SYS_TEXT_BASE, %d0
+	movec	%d0, %VBR
+#else
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	movec	%d0, %VBR
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+#endif
+
+	/* invalidate and disable cache */
+	move.l	#CF_CACR_CINV, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+
+	/* initialize general use internal ram */
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+
+	/* put relocation table address to a5 */
+	move.l	#__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	bsr	board_init_f_alloc_reserve
+
+	/* update stack and frame-pointers */
+	move.l	%d0, %sp
+	move.l	%sp, %fp
+
+	/* initialize reserved area */
+	move.l	%d0, -(%sp)
+	bsr	board_init_f_init_reserve
+
+	/* run low-level CPU init code (from flash) */
+	bsr	cpu_init_f
+	clr.l	%sp@-
+
+	/* run low-level board init code (from flash) */
+	move.l	#board_init_f, %a1
+	jsr	(%a1)
+
+	/* board_init_f() does not return */
+
+/******************************************************************************/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+.globl relocate_code
+relocate_code:
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
+
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
+
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
+
+	/* copy the code to RAM */
+1:
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a1,%a5			/* fix got pointer register a5 */
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start,%d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
+	jsr	(%a1)
+
+/******************************************************************************/
+
+/* exception code */
+.globl _fault
+_fault:
+	bra	_fault
+
+.globl _exc_handler
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+.globl _int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/******************************************************************************/
+
+.globl version_string
+version_string:
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf523x/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+# ccflags-y += -DET_DEBUG
+
+extra-y	= start.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf523x/cpu.c

@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <watchdog.h>
+#include <command.h>
+#include <netdev.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
+
+	out_8(&ccm->rcr, CCM_RCR_SOFTRST);
+	/* we don't return! */
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	u16 msk;
+	u16 id = 0;
+	u8 ver;
+
+	puts("CPU:   ");
+	msk = (in_be16(&ccm->cir) >> 6);
+	ver = (in_be16(&ccm->cir) & 0x003f);
+	switch (msk) {
+	case 0x31:
+		id = 5235;
+		break;
+	}
+
+	if (id) {
+		char buf1[32], buf2[32];
+
+		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
+		       ver);
+		printf("       CPU CLK %s MHz BUS CLK %s MHz\n",
+		       strmhz(buf1, gd->cpu_clk),
+		       strmhz(buf2, gd->bus_clk));
+	}
+
+	return 0;
+};
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+	/* Count register */
+	out_be16(&wdp->sr, 0x5555);
+	asm("nop");
+	out_be16(&wdp->sr, 0xaaaa);
+}
+
+int watchdog_disable(void)
+{
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
+	/* halted watchdog timer */
+	setbits_be16(&wdp->cr, WTM_WCR_HALTED);
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	u32 wdog_module = 0;
+
+	/* set timeout and enable watchdog */
+	wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
+	wdog_module |= (wdog_module / 8192);
+	out_be16(&wdp->mr, wdog_module);
+
+	out_be16(&wdp->cr, WTM_WCR_EN);
+	puts("WATCHDOG:enabled\n");
+
+	return (0);
+}
+#endif				/* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers.  To override,
+ * create a board-specific function called:
+ * 	int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+	return mcffec_initialize(bis);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf523x/cpu_init.c

@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <watchdog.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
+/* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
+#ifdef CONFIG_M5235
+#define out_be_fbcs_reg		out_be16
+#else
+#define out_be_fbcs_reg		out_be32
+#endif
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+	scm_t *scm = (scm_t *) MMAP_SCM;
+
+	/* watchdog is enabled by default - disable the watchdog */
+#ifndef CONFIG_WATCHDOG
+	out_be16(&wdog->cr, 0);
+#endif
+
+	out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+
+	/* Port configuration */
+	out_8(&gpio->par_cs, 0);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+	out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
+	out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
+	out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
+	out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
+	out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
+	out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
+	out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+	out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
+	out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+	out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
+#endif
+
+#ifdef CONFIG_SYS_I2C_FSL
+	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
+	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+#endif
+
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+		break;
+	case 1:
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
+		break;
+	case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
+		clrbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
+#endif
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_EMDC_FECEMDC |
+			GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+	} else {
+		clrbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_EMDC_MASK |
+			GPIO_PAR_FECI2C_EMDIO_MASK);
+	}
+
+	return 0;
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf523x/interrupts.c

@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <irq_func.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+int interrupt_init(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	/* Make sure all interrupts are disabled */
+	setbits_be32(&intp->imrl0, 0x1);
+
+	enable_interrupts();
+	return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
+	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf523x/speed.c

@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+	pll_t *pll = (pll_t *)(MMAP_PLL);
+
+	out_be32(&pll->syncr, PLL_SYNCR_MFD(1));
+
+	while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
+		;
+
+	gd->bus_clk = CONFIG_SYS_CLK;
+	gd->cpu_clk = (gd->bus_clk * 2);
+
+#ifdef CONFIG_SYS_I2C_FSL
+	gd->arch.i2c1_clk = gd->bus_clk;
+#endif
+
+	return (0);
+}

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf523x/start.S

@@ -0,0 +1,259 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#define _START	_start
+#define _FAULT	_fault
+
+#define SAVE_ALL						\
+	move.w	#0x2700,%sr;		/* disable intrs */	\
+	subl	#60,%sp;		/* space for 15 regs */ \
+	moveml	%d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL						\
+	moveml	%sp@,%d0-%d7/%a0-%a6;				\
+	addl	#60,%sp;		/* space for 15 regs */ \
+	rte;
+
+.text
+
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+INITSP:	.long	0x00000000		/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC	*/
+
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved */
+vector10_17:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved	*/
+vector30_3F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.text
+
+.globl _start
+_start:
+	nop
+	nop
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
+
+	/* Set vector base register at the beginning of the Flash */
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	movec	%d0, %VBR
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	/* invalidate and disable cache */
+	move.l	#CF_CACR_CINV, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	nop
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+
+	/* initialize general use internal ram */
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+
+	/* put relocation table address to a5 */
+	move.l	#__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l	%d0, %sp
+	move.l	%sp, %fp
+
+	/* initialize reserved area */
+	move.l	%d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
+
+	/* run low-level CPU init code (from flash) */
+	move.l	#cpu_init_f, %a1
+	jsr	(%a1)
+
+	/* run low-level board init code (from flash) */
+	clr.l	%sp@-
+	move.l	#board_init_f, %a1
+	jsr	(%a1)
+
+	/* board_init_f() does not return */
+
+/******************************************************************************/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+.globl relocate_code
+relocate_code:
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
+
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
+
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
+
+	/* copy the code to RAM */
+1:
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a1,%a5		/* * fix got pointer register a5 */
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start,%d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
+	jsr	(%a1)
+
+/******************************************************************************/
+
+/* exception code */
+.globl _fault
+_fault:
+	bra	_fault
+
+.globl _exc_handler
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+.globl _int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/******************************************************************************/
+
+.globl version_string
+version_string:
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf52x2/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+# ccflags-y += -DET_DEBUG
+
+extra-y	= start.o
+obj-y	= interrupts.o cpu.o speed.o cpu_init.o

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf52x2/cpu.c

@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2003
+ * Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * MCF5282 additionals
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
+ *
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef	CONFIG_M5208
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+	udelay(1000);
+
+	out_8(&rcm->rcr, RCM_RCR_SOFTRST);
+
+	/* we don't return! */
+	return 0;
+};
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf1[32], buf2[32];
+
+	printf("CPU:   Freescale Coldfire MCF5208\n"
+	       "       CPU CLK %s MHz BUS CLK %s MHz\n",
+	       strmhz(buf1, gd->cpu_clk),
+	       strmhz(buf2, gd->bus_clk));
+	return 0;
+};
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	out_be16(&wdt->sr, 0x5555);
+	out_be16(&wdt->sr, 0xaaaa);
+}
+
+int watchdog_disable(void)
+{
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->sr, 0x5555);
+	out_be16(&wdt->sr, 0xaaaa);
+	/* disable watchdog timer */
+	out_be16(&wdt->cr, 0);
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	/* disable watchdog */
+	out_be16(&wdt->cr, 0);
+
+	/* set timeout and enable watchdog */
+	out_be16(&wdt->mr,
+		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->sr, 0x5555);
+	out_be16(&wdt->sr, 0xaaaa);
+
+	puts("WATCHDOG:enabled\n");
+	return (0);
+}
+#endif				/* #ifdef CONFIG_WATCHDOG */
+#endif				/* #ifdef CONFIG_M5208 */
+
+#ifdef  CONFIG_M5271
+#if defined(CONFIG_DISPLAY_CPUINFO)
+/*
+ * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
+ * determine which one we are running on, based on the Chip Identification
+ * Register (CIR).
+ */
+int print_cpuinfo(void)
+{
+	char buf[32];
+	unsigned short cir;	/* Chip Identification Register */
+	unsigned short pin;	/* Part identification number */
+	unsigned char prn;	/* Part revision number */
+	char *cpu_model;
+
+	cir = mbar_readShort(MCF_CCM_CIR);
+	pin = cir >> MCF_CCM_CIR_PIN_LEN;
+	prn = cir & MCF_CCM_CIR_PRN_MASK;
+
+	switch (pin) {
+	case MCF_CCM_CIR_PIN_MCF5270:
+		cpu_model = "5270";
+		break;
+	case MCF_CCM_CIR_PIN_MCF5271:
+		cpu_model = "5271";
+		break;
+	default:
+		cpu_model = NULL;
+		break;
+	}
+
+	if (cpu_model)
+		printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
+		       cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
+	else
+		printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
+		       " (PIN: 0x%x) rev. %hu, at %s MHz\n",
+		       pin, prn, strmhz(buf, CONFIG_SYS_CLK));
+
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	/* Call the board specific reset actions first. */
+	if(board_reset) {
+		board_reset();
+	}
+
+	mbar_writeByte(MCF_RCM_RCR,
+		       MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
+	return 0;
+};
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset(void)
+{
+	mbar_writeShort(MCF_WTM_WSR, 0x5555);
+	mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
+}
+
+int watchdog_disable(void)
+{
+	mbar_writeShort(MCF_WTM_WCR, 0);
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
+	return (0);
+}
+#endif				/* #ifdef CONFIG_WATCHDOG */
+
+#endif
+
+#ifdef	CONFIG_M5272
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+	out_be16(&wdp->wdog_wrrr, 0);
+	udelay(1000);
+
+	/* enable watchdog, set timeout to 0 and wait */
+	out_be16(&wdp->wdog_wrrr, 1);
+	while (1) ;
+
+	/* we don't return! */
+	return 0;
+};
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
+	uchar msk;
+	char *suf;
+
+	puts("CPU:   ");
+	msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
+	switch (msk) {
+	case 0x2:
+		suf = "1K75N";
+		break;
+	case 0x4:
+		suf = "3K75N";
+		break;
+	default:
+		suf = NULL;
+		printf("Freescale MCF5272 (Mask:%01x)\n", msk);
+		break;
+	}
+
+	if (suf)
+		printf("Freescale MCF5272 %s\n", suf);
+	return 0;
+};
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	out_be16(&wdt->wdog_wcr, 0);
+}
+
+int watchdog_disable(void)
+{
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->wdog_wcr, 0);
+	/* disable watchdog interrupt */
+	out_be16(&wdt->wdog_wirr, 0);
+	/* disable watchdog timer */
+	out_be16(&wdt->wdog_wrrr, 0);
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	/* disable watchdog interrupt */
+	out_be16(&wdt->wdog_wirr, 0);
+
+	/* set timeout and enable watchdog */
+	out_be16(&wdt->wdog_wrrr,
+		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->wdog_wcr, 0);
+
+	puts("WATCHDOG:enabled\n");
+	return (0);
+}
+#endif				/* #ifdef CONFIG_WATCHDOG */
+
+#endif				/* #ifdef CONFIG_M5272 */
+
+#ifdef	CONFIG_M5275
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+	udelay(1000);
+
+	out_8(&rcm->rcr, RCM_RCR_SOFTRST);
+
+	/* we don't return! */
+	return 0;
+};
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
+			strmhz(buf, CONFIG_SYS_CLK));
+	return 0;
+};
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	out_be16(&wdt->wsr, 0x5555);
+	out_be16(&wdt->wsr, 0xaaaa);
+}
+
+int watchdog_disable(void)
+{
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->wsr, 0x5555);
+	out_be16(&wdt->wsr, 0xaaaa);
+
+	/* disable watchdog timer */
+	out_be16(&wdt->wcr, 0);
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	/* disable watchdog */
+	out_be16(&wdt->wcr, 0);
+
+	/* set timeout and enable watchdog */
+	out_be16(&wdt->wmr,
+		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->wsr, 0x5555);
+	out_be16(&wdt->wsr, 0xaaaa);
+
+	puts("WATCHDOG:enabled\n");
+	return (0);
+}
+#endif				/* #ifdef CONFIG_WATCHDOG */
+
+#endif				/* #ifdef CONFIG_M5275 */
+
+#ifdef	CONFIG_M5282
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	unsigned char resetsource = MCFRESET_RSR;
+
+	printf("CPU:   Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
+	       MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
+	printf("Reset:%s%s%s%s%s%s%s\n",
+	       (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
+	       (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
+	       (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
+	       (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
+	       (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
+	       (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
+	       (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
+	return 0;
+};
+#endif
+
+#ifdef CONFIG_M5249
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
+	       strmhz(buf, CONFIG_SYS_CLK));
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	/* enable watchdog, set timeout to 0 and wait */
+	mbar_writeByte(MCFSIM_SYPCR, 0xc0);
+	while (1) ;
+
+	/* we don't return! */
+	return 0;
+};
+#endif
+
+#ifdef CONFIG_M5253
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	unsigned char resetsource = mbar_readLong(SIM_RSR);
+	printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
+	       strmhz(buf, CONFIG_SYS_CLK));
+
+	if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
+		printf("Reset:%s%s\n",
+		       (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
+		       : "",
+		       (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
+		       "");
+	}
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	/* enable watchdog, set timeout to 0 and wait */
+	mbar_writeByte(SIM_SYPCR, 0xc0);
+	while (1) ;
+
+	/* we don't return! */
+	return 0;
+};
+#endif
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers.  To override,
+ * create a board-specific function called:
+ * 	int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+	return mcffec_initialize(bis);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf52x2/cpu.h

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  cpu.h
+ *
+ *  Copyright (c) 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+/* Use this to create board specific reset functions */
+void board_reset(void) __attribute__((__weak__));
+
+#endif /* _CPU_H_ */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf52x2/cpu_init.c

@@ -0,0 +1,738 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2003
+ * Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * MCF5282 additionals
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
+ * (c) Copyright 2010
+ * Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <watchdog.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
+#ifndef CONFIG_M5272
+/* Only 5272 Flexbus chipselect is different from the rest */
+void init_fbcs(void)
+{
+	fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
+     && defined(CONFIG_SYS_CS6_CTRL))
+	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
+     && defined(CONFIG_SYS_CS7_CTRL))
+	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
+#endif
+}
+#endif
+
+#if defined(CONFIG_M5208)
+void cpu_init_f(void)
+{
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+#ifndef CONFIG_WATCHDOG
+	wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+
+	/* Disable the watchdog if we aren't using it */
+	out_be16(&wdg->cr, 0);
+#endif
+
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+	icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		break;
+	case 1:
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+		break;
+	case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+		clrbits_8(&gpio->par_feci2c,
+			~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+		clrbits_8(&gpio->par_feci2c,
+			~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		setbits_8(&gpio->par_fec,
+			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
+	} else {
+		clrbits_8(&gpio->par_fec,
+			~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
+		clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
+	}
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
+#endif				/* CONFIG_M5208 */
+
+#if defined(CONFIG_M5253)
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	mbar_writeByte(MCFSIM_MPARK, 0x40);	/* 5249 Internal Core takes priority over DMA */
+	mbar_writeByte(MCFSIM_SYPCR, 0x00);
+	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
+	mbar_writeByte(MCFSIM_SWSR, 0x00);
+	mbar_writeByte(MCFSIM_SWDICR, 0x00);
+	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
+	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
+	mbar_writeByte(MCFSIM_I2CICR, 0x00);
+	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
+	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
+	mbar_writeByte(MCFSIM_ICR6, 0x00);
+	mbar_writeByte(MCFSIM_ICR7, 0x00);
+	mbar_writeByte(MCFSIM_ICR8, 0x00);
+	mbar_writeByte(MCFSIM_ICR9, 0x00);
+	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
+
+	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
+	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
+	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
+
+	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+#ifdef CONFIG_SYS_I2C_FSL
+	CONFIG_SYS_I2C_PINMUX_REG =
+	    CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
+	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+#ifdef CONFIG_SYS_I2C2_OFFSET
+	CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
+	CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
+#endif
+#endif
+
+	/* enable instruction cache now */
+	icache_enable();
+}
+
+/*initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	u32 *par = (u32 *) MMAP_PAR;
+
+	/* Setup Ports: */
+	switch (port) {
+	case 1:
+		clrbits_be32(par, 0x00180000);
+		setbits_be32(par, 0x00180000);
+		break;
+	case 2:
+		clrbits_be32(par, 0x00000003);
+		clrbits_be32(par, 0xFFFFFFFC);
+		break;
+	}
+}
+#endif				/* #if defined(CONFIG_M5253) */
+
+#if defined(CONFIG_M5271)
+void cpu_init_f(void)
+{
+#ifndef CONFIG_WATCHDOG
+	/* Disable the watchdog if we aren't using it */
+	mbar_writeShort(MCF_WTM_WCR, 0);
+#endif
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+#ifdef CONFIG_SYS_MCF_SYNCR
+	/* Set clockspeed according to board header file */
+	mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
+#else
+	/* Set clockspeed to 100MHz */
+	mbar_writeLong(MCF_FMPLL_SYNCR,
+			MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
+#endif
+	while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	u16 temp;
+
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
+		temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
+		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
+		break;
+	case 1:
+		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
+		temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
+		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
+		break;
+	case 2:
+		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
+		temp |= (0x3000);
+		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	if (setclear) {
+		/* Enable Ethernet pins */
+		mbar_writeByte(MCF_GPIO_PAR_FECI2C,
+			       (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
+	} else {
+	}
+
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
+
+#endif				/* CONFIG_M5271 */
+
+#if defined(CONFIG_M5272)
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	/* if we come from RAM we assume the CPU is
+	 * already initialized.
+	 */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+	sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+	gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+	csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
+
+	out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
+	out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
+
+	/* Setup Ports: */
+	out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
+	out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
+	out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
+	out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
+	out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
+	out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
+	out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
+
+	/* Memory Controller: */
+	out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
+	out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
+
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+	out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
+	out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+	out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
+	out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+	out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
+	out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
+	out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
+	out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
+	out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
+	out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
+	out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
+	out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
+	out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
+	out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
+#endif
+
+#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+
+	/* enable instruction cache now */
+	icache_enable();
+
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		clrbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+		setbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+		break;
+	case 1:
+		clrbits_be32(&gpio->gpio_pdcnt,
+			GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+		setbits_be32(&gpio->gpio_pdcnt,
+			GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		setbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+			GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+			GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+			GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
+	} else {
+	}
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
+#endif				/* #if defined(CONFIG_M5272) */
+
+#if defined(CONFIG_M5275)
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	/*
+	 * if we come from RAM we assume the CPU is
+	 * already initialized.
+	 */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+	wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+	gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
+
+	/* Kill watchdog so we can initialize the PLL */
+	out_be16(&wdog_reg->wcr, 0);
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+
+#ifdef CONFIG_SYS_I2C_FSL
+	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
+	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+#endif
+
+	/* enable instruction cache now */
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
+		break;
+	case 1:
+		clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
+		break;
+	case 2:
+		clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	struct fec_info_s *info = (struct fec_info_s *) dev->priv;
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+	if (setclear) {
+		/* Enable Ethernet pins */
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+			setbits_be16(&gpio->par_feci2c, 0x0f00);
+			setbits_8(&gpio->par_fec0hl, 0xc0);
+		} else {
+			setbits_be16(&gpio->par_feci2c, 0x00a0);
+			setbits_8(&gpio->par_fec1hl, 0xc0);
+		}
+	} else {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+			clrbits_be16(&gpio->par_feci2c, 0x0f00);
+			clrbits_8(&gpio->par_fec0hl, 0xc0);
+		} else {
+			clrbits_be16(&gpio->par_feci2c, 0x00a0);
+			clrbits_8(&gpio->par_fec1hl, 0xc0);
+		}
+	}
+
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
+#endif				/* #if defined(CONFIG_M5275) */
+
+#if defined(CONFIG_M5282)
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+#ifndef CONFIG_WATCHDOG
+	/* disable watchdog if we aren't using it */
+	MCFWTM_WCR = 0;
+#endif
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+	/* Set speed /PLL */
+	MCFCLOCK_SYNCR =
+	    MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
+	    MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+	while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
+
+	MCFGPIO_PBCDPAR = 0xc0;
+
+	/* Set up the GPIO ports */
+#ifdef CONFIG_SYS_PEPAR
+	MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
+#endif
+#ifdef	CONFIG_SYS_PFPAR
+	MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
+#endif
+#ifdef CONFIG_SYS_PJPAR
+	MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
+#endif
+#ifdef CONFIG_SYS_PSDPAR
+	MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
+#endif
+#ifdef CONFIG_SYS_PASPAR
+	MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
+#endif
+#ifdef CONFIG_SYS_PEHLPAR
+	MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+#endif
+#ifdef CONFIG_SYS_PQSPAR
+	MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
+#endif
+#ifdef CONFIG_SYS_PTCPAR
+	MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
+#endif
+#if defined(CONFIG_SYS_PORTTC)
+	MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
+#endif
+#if defined(CONFIG_SYS_DDRTC)
+	MCFGPIO_DDRTC  = CONFIG_SYS_DDRTC;
+#endif
+#ifdef CONFIG_SYS_PTDPAR
+	MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
+#endif
+#ifdef CONFIG_SYS_PUAPAR
+	MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
+#endif
+
+#if defined(CONFIG_SYS_DDRD)
+	MCFGPIO_DDRD = CONFIG_SYS_DDRD;
+#endif
+#ifdef CONFIG_SYS_DDRUA
+	MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
+#endif
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+#endif				/* CONFIG_MONITOR_IS_IN_RAM */
+
+	/* defer enabling cache until boot (see do_go) */
+	/* icache_enable(); */
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		MCFGPIO_PUAPAR &= 0xFc;
+		MCFGPIO_PUAPAR |= 0x03;
+		break;
+	case 1:
+		MCFGPIO_PUAPAR &= 0xF3;
+		MCFGPIO_PUAPAR |= 0x0C;
+		break;
+	case 2:
+		MCFGPIO_PASPAR &= 0xFF0F;
+		MCFGPIO_PASPAR |= 0x00A0;
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	if (setclear) {
+		MCFGPIO_PASPAR |= 0x0F00;
+		MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+	} else {
+		MCFGPIO_PASPAR &= 0xF0FF;
+		MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+	}
+	return 0;
+}
+#endif			/* CONFIG_CMD_NET */
+#endif
+
+#if defined(CONFIG_M5249)
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	/*
+	 *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
+	 *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
+	 *        which is their primary function.
+	 *        ~Jeremy
+	 */
+	mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
+	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
+	mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
+	mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
+	mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
+	mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
+
+	/*
+	 *  dBug Compliance:
+	 *    You can verify these values by using dBug's 'ird'
+	 *    (Internal Register Display) command
+	 *    ~Jeremy
+	 *
+	 */
+	mbar_writeByte(MCFSIM_MPARK, 0x30);	/* 5249 Internal Core takes priority over DMA */
+	mbar_writeByte(MCFSIM_SYPCR, 0x00);
+	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
+	mbar_writeByte(MCFSIM_SWSR, 0x00);
+	mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
+	mbar_writeByte(MCFSIM_SWDICR, 0x00);
+	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
+	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
+	mbar_writeByte(MCFSIM_I2CICR, 0x00);
+	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
+	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
+	mbar_writeByte(MCFSIM_ICR6, 0x00);
+	mbar_writeByte(MCFSIM_ICR7, 0x00);
+	mbar_writeByte(MCFSIM_ICR8, 0x00);
+	mbar_writeByte(MCFSIM_ICR9, 0x00);
+	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
+
+	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
+	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
+	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
+	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);	/* Enable a 1 cycle pre-drive cycle on CS1 */
+
+	/* Setup interrupt priorities for gpio7 */
+	/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
+
+	/* IDE Config registers */
+	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
+	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+	/* enable instruction cache now */
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+}
+#endif				/* #if defined(CONFIG_M5249) */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf52x2/interrupts.c

@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <irq_func.h>
+#include <watchdog.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef	CONFIG_M5272
+int interrupt_init(void)
+{
+	intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
+
+	/* disable all external interrupts */
+	out_be32(&intp->int_icr1, 0x88888888);
+	out_be32(&intp->int_icr2, 0x88888888);
+	out_be32(&intp->int_icr3, 0x88888888);
+	out_be32(&intp->int_icr4, 0x88888888);
+	out_be32(&intp->int_pitr, 0x00000000);
+
+	/* initialize vector register */
+	out_8(&intp->int_pivr, 0x40);
+
+	enable_interrupts();
+
+	return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+	intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+
+	clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
+	setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
+}
+#endif				/* CONFIG_MCFTMR */
+#endif				/* CONFIG_M5272 */
+
+#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
+    defined(CONFIG_M5271) || defined(CONFIG_M5275)
+int interrupt_init(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	/* Make sure all interrupts are disabled */
+#if defined(CONFIG_M5208)
+	out_be32(&intp->imrl0, 0xffffffff);
+	out_be32(&intp->imrh0, 0xffffffff);
+#else
+	setbits_be32(&intp->imrl0, 0x1);
+#endif
+
+	enable_interrupts();
+	return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrl0, 0x00000001);
+	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
+}
+#endif				/* CONFIG_MCFTMR */
+#endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
+
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+int interrupt_init(void)
+{
+	enable_interrupts();
+
+	return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
+	mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
+}
+#endif				/* CONFIG_MCFTMR */
+#endif				/* CONFIG_M5249 || CONFIG_M5253 */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf52x2/speed.c

@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2003
+ * Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks (void)
+{
+#if defined(CONFIG_M5208)
+	pll_t *pll = (pll_t *) MMAP_PLL;
+
+	out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
+	out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
+#endif
+
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
+	unsigned long pllcr;
+
+#ifndef CONFIG_SYS_PLL_BYPASS
+
+#ifdef CONFIG_M5249
+	/* Setup the PLL to run at the specified speed */
+#ifdef CONFIG_SYS_FAST_CLK
+	pllcr = 0x925a3100;	/* ~140MHz clock (PLL bypass = 0) */
+#else
+	pllcr = 0x135a4140;	/* ~72MHz clock (PLL bypass = 0) */
+#endif
+#endif				/* CONFIG_M5249 */
+
+#ifdef CONFIG_M5253
+	pllcr = CONFIG_SYS_PLLCR;
+#endif				/* CONFIG_M5253 */
+
+	cpll = cpll & 0xfffffffe;	/* Set PLL bypass mode = 0 (PSTCLK = crystal) */
+	mbar2_writeLong(MCFSIM_PLLCR, cpll);	/* Set the PLL to bypass mode (PSTCLK = crystal) */
+	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* set the clock speed */
+	pllcr ^= 0x00000001;	/* Set pll bypass to 1 */
+	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* Start locking (pll bypass = 1) */
+	udelay(0x20);		/* Wait for a lock ... */
+#endif				/* #ifndef CONFIG_SYS_PLL_BYPASS */
+
+#endif				/* CONFIG_M5249 || CONFIG_M5253 */
+
+#if defined(CONFIG_M5275)
+	pll_t *pll = (pll_t *)(MMAP_PLL);
+
+	/* Setup PLL */
+	out_be32(&pll->syncr, 0x01080000);
+	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
+		;
+	out_be32(&pll->syncr, 0x01000000);
+	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
+		;
+#endif
+
+	gd->cpu_clk = CONFIG_SYS_CLK;
+#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+    defined(CONFIG_M5271) || defined(CONFIG_M5275)
+	gd->bus_clk = gd->cpu_clk / 2;
+#else
+	gd->bus_clk = gd->cpu_clk;
+#endif
+
+#ifdef CONFIG_SYS_I2C_FSL
+	gd->arch.i2c1_clk = gd->bus_clk;
+#ifdef CONFIG_SYS_I2C2_FSL_OFFSET
+	gd->arch.i2c2_clk = gd->bus_clk;
+#endif
+#endif
+
+	return (0);
+}

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf52x2/start.S

@@ -0,0 +1,341 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#define _START	_start
+#define _FAULT	_fault
+
+
+#define SAVE_ALL						\
+	move.w	#0x2700,%sr;		/* disable intrs */	\
+	subl	#60,%sp;		/* space for 15 regs */ \
+	moveml	%d0-%d7/%a0-%a6,%sp@;				\
+
+#define RESTORE_ALL						\
+	moveml	%sp@,%d0-%d7/%a0-%a6;				\
+	addl	#60,%sp;		/* space for 15 regs */ \
+	rte
+
+/* If we come from a pre-loader we don't need an initial exception
+ * table.
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+
+.text
+
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+.long	0x00000000		/* Flash offset is 0 until we setup CS0 */
+#if defined(CONFIG_M5282) && (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+.long	_start - CONFIG_SYS_TEXT_BASE
+#else
+.long	_START
+#endif
+
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+#endif
+
+.text
+
+#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
+    (defined(CONFIG_M5282) || defined(CONFIG_M5281))
+#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+.long	0x55AA55AA,0xAA55AA55		/* CFM Backdoorkey */
+.long	0xFFFFFFFF			/* all sectors protected */
+.long	0x00000000			/* supervisor/User restriction */
+.long	0x00000000			/* programm/data space restriction */
+.long	0x00000000			/* Flash security */
+#endif
+#endif
+
+.globl _start
+_start:
+	nop
+	nop
+	move.w	#0x2700,%sr
+
+#if defined(CONFIG_M5208)
+	/* Initialize RAMBAR: locate SRAM and validate it */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+#endif
+
+#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
+	/* set MBAR address + valid flag */
+	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.c	%d0, %MBAR
+
+	/*** The 5249 has MBAR2 as well ***/
+#ifdef CONFIG_SYS_MBAR2
+	/* Get MBAR2 address */
+	move.l	#(CONFIG_SYS_MBAR2 + 1), %d0
+	 /* Set MBAR2 */
+	movec	%d0, #0xc0e
+#endif
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+	movec	%d0, %RAMBAR0
+#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
+
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+	/* set MBAR address + valid flag */
+	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	%d0, 0x40000000
+
+	/* Initialize RAMBAR1: locate SRAM and validate it */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+	movec	%d0, %RAMBAR1
+
+#if defined(CONFIG_M5282)
+#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+	/*
+	 * Setup code in SRAM to initialize FLASHBAR,
+	 * if start from internal Flash
+	 */
+	move.l	#(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
+	move.l	#(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR), %a2
+_copy_flash:
+	move.l	(%a0)+, (%a2)+
+	cmp.l	%a0, %a1
+	bgt.s	_copy_flash
+	jmp	CONFIG_SYS_INIT_RAM_ADDR
+
+_flashbar_setup:
+	/* Initialize FLASHBAR: locate internal Flash and validate it */
+	move.l	#(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+	movec	%d0, %FLASHBAR
+	jmp	_after_flashbar_copy.L	/* Force jump to absolute address */
+_flashbar_setup_end:
+	nop
+_after_flashbar_copy:
+#else
+	/* Setup code to initialize FLASHBAR, if start from external Memory */
+	move.l	#(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+	movec	%d0, %FLASHBAR
+#endif /* (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
+
+#endif
+#endif
+	/*
+	 * if we come from a pre-loader we have no exception table and
+	 * therefore no VBR to set
+	 */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+#if defined(CONFIG_M5282) && (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+	move.l	#CONFIG_SYS_INT_FLASH_BASE, %d0
+#else
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+#endif
+	movec	%d0, %VBR
+#endif
+
+#ifdef CONFIG_M5275
+	/* set MBAR address + valid flag */
+	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	%d0, 0x40000000
+/*	movec	%d0, %MBAR */
+
+	/* Initialize RAMBAR: locate SRAM and validate it */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+	movec	%d0, %RAMBAR1
+#endif
+
+	/* initialize general use internal ram */
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+
+	/* put relocation table address to a5 */
+	move.l	#__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l	%d0, %sp
+	move.l	%sp, %fp
+
+	/* initialize reserved area */
+	move.l	%d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
+
+	/* run low-level CPU init code (from flash) */
+	move.l	#cpu_init_f, %a1
+	jsr	(%a1)
+
+	/* run low-level board init code (from flash) */
+	clr.l	%sp@-
+	move.l	#board_init_f, %a1
+	jsr	(%a1)
+
+	/* board_init_f() does not return */
+
+/******************************************************************************/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+.globl relocate_code
+relocate_code:
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
+
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
+
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
+	/* copy the code to RAM */
+1:
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a1,%a5			/* fix got pointer register a5 */
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start,%d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
+#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
+    defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
+	halt
+#endif
+	jsr	(%a1)
+
+/******************************************************************************/
+
+/* exception code */
+.globl _fault
+_fault:
+	bra	_fault
+
+.globl _exc_handler
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+.globl _int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/******************************************************************************/
+
+.globl version_string
+version_string:
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf530x/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+
+extra-y	= start.o
+obj-y	= interrupts.o cpu.o speed.o cpu_init.o
+

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf530x/cpu.c

@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+ *
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_M5307
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	sim_t *sim = (sim_t *)(MMAP_SIM);
+
+	/* enable watchdog/reset, set timeout to 0 and wait */
+	out_8(&sim->sypcr, SYPCR_SWE | SYPCR_SWRI);
+
+	/* wait for watchdog reset */
+	for (;;)
+		;
+
+	/* we don't return! */
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	printf("CPU:   Freescale Coldfire MCF5307 at %s MHz\n",
+	       strmhz(buf, CONFIG_SYS_CPU_CLK));
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf530x/cpu_init.c

@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+ *
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <watchdog.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_M5307)
+/*
+ * Simple mcf5307 chip select module init.
+ *
+ * Note: this chip has an issue reported in the device "errata":
+ * MCF5307ER Rev 4.2 reports @ section 35:
+ * Corrupted Return PC in Exception Stack Frame
+ * When processing an autovectored interrupt an error can occur that
+ * causes 0xFFFFFFFF to be written as the return PC value in the
+ * exception stack frame. The problem is caused by a conflict between
+ * an internal autovector access and a chip select mapped to the IACK
+ * address space (0xFFFFXXXX).
+ * Workaround:
+ * Set the C/I bit in the chip select mask register (CSMR) for the
+ * chip select that is mapped to 0xFFFFXXXX.
+ * This will prevent the chip select from asserting for IACK accesses.
+ */
+
+#define MCF5307_SP_ERR_FIX(cs_base, mask)				\
+	do {								\
+		if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >=	\
+			0xffff0000)					\
+			setbits_be32(&mask, CSMR_CI);			\
+	} while (0)
+
+void init_csm(void)
+{
+	csm_t *csm = (csm_t *)(MMAP_CSM);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
+	defined(CONFIG_SYS_CS0_CTRL))
+	out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
+	out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
+	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
+	defined(CONFIG_SYS_CS1_CTRL))
+	out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
+	out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
+	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
+	defined(CONFIG_SYS_CS2_CTRL))
+	out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
+	out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
+	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
+	defined(CONFIG_SYS_CS3_CTRL))
+	out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
+	out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
+	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
+	defined(CONFIG_SYS_CS4_CTRL))
+	out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
+	out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
+	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
+	defined(CONFIG_SYS_CS5_CTRL))
+	out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
+	out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
+	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
+	defined(CONFIG_SYS_CS6_CTRL))
+	out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
+	out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
+	out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
+	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
+	defined(CONFIG_SYS_CS7_CTRL))
+	out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
+	out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
+	out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
+	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
+#endif
+}
+
+/*
+ * Set up the memory map and initialize registers
+ */
+void cpu_init_f(void)
+{
+	sim_t *sim = (sim_t *)(MMAP_SIM);
+
+	out_8(&sim->sypcr, 0x00);
+	out_8(&sim->swivr, 0x0f);
+	out_8(&sim->swsr,  0x00);
+	out_8(&sim->mpark, 0x00);
+
+	intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+	/* timer 2 not masked */
+	out_be32(&icr->imr, 0xfffffbff);
+
+	out_8(&icr->icr0, 0x00); /* sw watchdog */
+	out_8(&icr->icr1, 0x00); /* timer 1     */
+	out_8(&icr->icr2, 0x88); /* timer 2     */
+	out_8(&icr->icr3, 0x00); /* i2c         */
+	out_8(&icr->icr4, 0x00); /* uart 0      */
+	out_8(&icr->icr5, 0x00); /* uart 1      */
+	out_8(&icr->icr6, 0x00); /* dma  0      */
+	out_8(&icr->icr7, 0x00); /* dma  1      */
+	out_8(&icr->icr8, 0x00); /* dma  2      */
+	out_8(&icr->icr9, 0x00); /* dma  3      */
+
+	/* Chipselect Init */
+	init_csm();
+
+	/* enable data/instruction cache now */
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return 0;
+}
+
+void uart_port_conf(int port)
+{
+}
+
+void arch_preboot_os(void)
+{
+	/*
+	 * OS can change interrupt offsets and are about to boot the OS so
+	 * we need to make sure we disable all async interrupts.
+	 */
+	intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+	out_8(&icr->icr1, 0x00); /* timer 1     */
+	out_8(&icr->icr2, 0x00); /* timer 2     */
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf530x/interrupts.c

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+ *
+ */
+
+#include <common.h>
+#include <irq_func.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_M5307
+int interrupt_init(void)
+{
+	enable_interrupts();
+
+	return 0;
+}
+
+void dtimer_intr_setup(void)
+{
+	intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
+
+	/* clearing TIMER2 mask, so enabling the related interrupt */
+	out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400);
+	/* set TIMER2 interrupt priority */
+	out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf530x/speed.c

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#if defined(CONFIG_M5307)
+	gd->bus_clk = CONFIG_SYS_CLK;
+	gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+#endif
+
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf530x/start.S

@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015  Angelo Dureghello <angelo@sysam.it>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#define _START	_start
+#define _FAULT	_fault
+
+
+.macro  SAVE_ALL
+	move.w	#0x2700,%sr;		/* disable intrs */
+	subl	#60,%sp;		/* space for 15 regs */
+	moveml	%d0-%d7/%a0-%a6,%sp@
+.endm
+
+.macro  RESTORE_ALL
+	moveml	%sp@,%d0-%d7/%a0-%a6;
+	addl	#60,%sp;		/* space for 15 regs */
+	rte
+.endm
+
+/* If we come from a pre-loader we don't need an initial exception
+ * table.
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+
+.text
+
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+/* Flash offset is 0 until we setup CS0 */
+.long	0x00000000
+#if defined(CONFIG_M5307) && \
+	   (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+.long	_start - CONFIG_SYS_TEXT_BASE
+#else
+.long	_START
+#endif
+
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+#endif
+
+.text
+
+.globl _start
+_start:
+	nop
+	nop
+	move.w	#0x2700,%sr
+
+	/* set MBAR address + valid flag */
+	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.c	%d0, %MBAR
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+	move.c	%d0, %RAMBAR
+
+	/* DS 4.8.2 (Cache Organization) invalidate and disable cache */
+        move.l	#CF_CACR_CINVA, %d0
+        movec	%d0, %CACR
+        move.l	#0, %d0
+        movec	%d0, %ACR0
+        movec	%d0, %ACR1
+
+	/*
+	 * if we come from a pre-loader we have no exception table and
+	 * therefore no VBR to set
+	 */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	movec	%d0, %VBR
+#endif
+
+	/* initialize general use internal ram */
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* dcache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+
+	/* put relocation table address to a5 */
+	move.l	#__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	bsr	board_init_f_alloc_reserve
+
+	/* update stack and frame-pointers */
+	move.l	%d0, %sp
+	move.l	%sp, %fp
+
+	/* initialize reserved area */
+	move.l	%d0, -(%sp)
+	bsr	board_init_f_init_reserve
+
+	/* run low-level CPU init code (from flash) */
+	bsr	cpu_init_f
+
+	/* run low-level board init code (from flash) */
+	clr.l	%sp@-
+	bsr	board_init_f
+
+	/* board_init_f() does not return */
+
+/******************************************************************************/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl relocate_code
+relocate_code:
+	link.w	%a6,#0
+	move.l	8(%a6), %sp	/* set new stack pointer */
+	move.l	12(%a6), %d0	/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0	/* Save copy of Destination Address */
+
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
+	/* copy the code to RAM */
+1:
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE), %a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE), %d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE), %a1
+
+	/* fix got pointer register a5 */
+	move.l	%a1,%a5
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE), %a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start, %d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l	%a0,-(%sp)	/* dest_addr */
+	move.l	%d0,-(%sp)	/* gd */
+#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \
+    defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
+	halt
+#endif
+	jsr	(%a1)
+
+/******************************************************************************/
+
+/* exception code */
+.globl _fault
+_fault:
+	bra	_fault
+
+.globl _exc_handler
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+.globl _int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/******************************************************************************/
+
+.globl version_string
+version_string:
+.ascii	U_BOOT_VERSION
+.ascii	" (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
+.ascii	CONFIG_IDENT_STRING, "\0"
+.align	4

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf532x/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+# ccflags-y += -DET_DEBUG
+
+extra-y := start.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf532x/cpu.c

@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <watchdog.h>
+#include <command.h>
+#include <netdev.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+
+	udelay(1000);
+	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
+
+	/* we don't return! */
+	return 0;
+};
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	u16 msk;
+	u16 id = 0;
+	u8 ver;
+
+	puts("CPU:   ");
+	msk = (in_be16(&ccm->cir) >> 6);
+	ver = (in_be16(&ccm->cir) & 0x003f);
+	switch (msk) {
+#ifdef CONFIG_MCF5301x
+	case 0x78:
+		id = 53010;
+		break;
+	case 0x77:
+		id = 53012;
+		break;
+	case 0x76:
+		id = 53015;
+		break;
+	case 0x74:
+		id = 53011;
+		break;
+	case 0x73:
+		id = 53013;
+		break;
+#endif
+#ifdef CONFIG_MCF532x
+	case 0x54:
+		id = 5329;
+		break;
+	case 0x59:
+		id = 5328;
+		break;
+	case 0x61:
+		id = 5327;
+		break;
+	case 0x65:
+		id = 5373;
+		break;
+	case 0x68:
+		id = 53721;
+		break;
+	case 0x69:
+		id = 5372;
+		break;
+	case 0x6B:
+		id = 5372;
+		break;
+#endif
+	}
+
+	if (id) {
+		char buf1[32], buf2[32];
+
+		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
+		       ver);
+		printf("       CPU CLK %s MHz BUS CLK %s MHz\n",
+		       strmhz(buf1, gd->cpu_clk),
+		       strmhz(buf2, gd->bus_clk));
+	}
+
+	return 0;
+};
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+	/* Count register */
+	out_be16(&wdp->sr, 0x5555);
+	out_be16(&wdp->sr, 0xaaaa);
+}
+
+int watchdog_disable(void)
+{
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
+	/* halted watchdog timer */
+	setbits_be16(&wdp->cr, WTM_WCR_HALTED);
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	u32 wdog_module = 0;
+
+	/* set timeout and enable watchdog */
+	wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
+#ifdef CONFIG_M5329
+	out_be16(&wdp->mr, wdog_module / 8192);
+#else
+	out_be16(&wdp->mr, wdog_module / 4096);
+#endif
+
+	out_be16(&wdp->cr, WTM_WCR_EN);
+	puts("WATCHDOG:enabled\n");
+
+	return (0);
+}
+#endif				/* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers.  To override,
+ * create a board-specific function called:
+ * 	int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+	return mcffec_initialize(bis);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf532x/cpu_init.c

@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <watchdog.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
+#ifdef CONFIG_MCF5301x
+void cpu_init_f(void)
+{
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
+	out_be32(&scm1->pacrg, 0);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
+#endif
+
+#ifdef CONFIG_SYS_I2C_FSL
+	out_8(&gpio->par_feci2c,
+		GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
+#endif
+
+	icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+#ifdef CONFIG_MCFFEC
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
+#endif
+#ifdef CONFIG_MCFRTC
+	rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
+	rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
+
+	out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
+	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
+
+#endif
+#ifdef CONFIG_MCFFEC
+	if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
+		setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
+	else
+		clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
+#endif
+
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		clrbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		break;
+	case 1:
+#ifdef CONFIG_SYS_UART1_ALT1_GPIO
+		clrbits_8(&gpio->par_simp1h,
+			GPIO_PAR_SIMP1H_DATA1_UNMASK |
+			GPIO_PAR_SIMP1H_VEN1_UNMASK);
+		setbits_8(&gpio->par_simp1h,
+			GPIO_PAR_SIMP1H_DATA1_U1TXD |
+			GPIO_PAR_SIMP1H_VEN1_U1RXD);
+#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
+		clrbits_8(&gpio->par_ssih,
+			GPIO_PAR_SSIH_RXD_UNMASK |
+			GPIO_PAR_SSIH_TXD_UNMASK);
+		setbits_8(&gpio->par_ssih,
+			GPIO_PAR_SSIH_RXD_U1RXD |
+			GPIO_PAR_SSIH_TXD_U1TXD);
+#endif
+		break;
+	case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U2TXD |
+			GPIO_PAR_UART_U2RXD);
+#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
+		clrbits_8(&gpio->par_dspih,
+			GPIO_PAR_DSPIH_SIN_UNMASK |
+			GPIO_PAR_DSPIH_SOUT_UNMASK);
+		setbits_8(&gpio->par_dspih,
+			GPIO_PAR_DSPIH_SIN_U2RXD |
+			GPIO_PAR_DSPIH_SOUT_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+		clrbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SDA_UNMASK |
+			GPIO_PAR_FECI2C_SCL_UNMASK);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SDA_U2TXD |
+			GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+	if (setclear) {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+			setbits_8(&gpio->par_fec,
+				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+			setbits_8(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0);
+		} else {
+			setbits_8(&gpio->par_fec,
+				GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+			setbits_8(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
+		}
+	} else {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+			clrbits_8(&gpio->par_fec,
+				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+			clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
+		} else {
+			clrbits_8(&gpio->par_fec,
+				GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+			clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK);
+		}
+	}
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
+#endif				/* CONFIG_MCF5301x */
+
+#ifdef CONFIG_MCF532x
+void cpu_init_f(void)
+{
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+#ifndef CONFIG_WATCHDOG
+	wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+
+	/* watchdog is enabled by default - disable the watchdog */
+	out_be16(&wdog->cr, 0);
+#endif
+
+	out_be32(&scm1->mpr0, 0x77777777);
+	out_be32(&scm2->pacra, 0);
+	out_be32(&scm2->pacrb, 0);
+	out_be32(&scm2->pacrc, 0);
+	out_be32(&scm2->pacrd, 0);
+	out_be32(&scm2->pacre, 0);
+	out_be32(&scm2->pacrf, 0);
+	out_be32(&scm2->pacrg, 0);
+	out_be32(&scm1->pacrh, 0);
+
+	/* Port configuration */
+	out_8(&gpio->par_cs, 0);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
+	/* Latch chipselect */
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
+#endif
+
+#ifdef CONFIG_SYS_I2C_FSL
+	out_8(&gpio->par_feci2c,
+		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
+#endif
+
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+		break;
+	case 1:
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+		break;
+	case 2:
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+		clrbits_8(&gpio->par_timer, 0xf0);
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+		clrbits_8(&gpio->par_feci2c, 0x00ff);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
+#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
+		clrbits_be16(&gpio->par_ssi, 0x0f00);
+		setbits_be16(&gpio->par_ssi,
+			GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
+#endif
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		setbits_8(&gpio->par_fec,
+			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+	} else {
+		clrbits_8(&gpio->par_fec,
+			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		clrbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+	}
+	return 0;
+}
+#endif
+#endif				/* CONFIG_MCF532x */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf532x/interrupts.c

@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <irq_func.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+int interrupt_init(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	/* Make sure all interrupts are disabled */
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
+
+	enable_interrupts();
+	return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf532x/speed.c

@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PLL min/max specifications */
+#define MAX_FVCO	500000	/* KHz */
+#define MAX_FSYS	80000	/* KHz */
+#define MIN_FSYS	58333	/* KHz */
+
+#ifdef CONFIG_MCF5301x
+#define FREF		20000	/* KHz */
+#define MAX_MFD		63	/* Multiplier */
+#define MIN_MFD		0	/* Multiplier */
+#define USBDIV		8
+
+/* Low Power Divider specifications */
+#define MIN_LPD		(0)	/* Divider (not encoded) */
+#define MAX_LPD		(15)	/* Divider (not encoded) */
+#define DEFAULT_LPD	(0)	/* Divider (not encoded) */
+#endif
+
+#ifdef CONFIG_MCF532x
+#define FREF		16000	/* KHz */
+#define MAX_MFD		135	/* Multiplier */
+#define MIN_MFD		88	/* Multiplier */
+
+/* Low Power Divider specifications */
+#define MIN_LPD		(1 << 0)	/* Divider (not encoded) */
+#define MAX_LPD		(1 << 15)	/* Divider (not encoded) */
+#define DEFAULT_LPD	(1 << 1)	/* Divider (not encoded) */
+#endif
+
+#define BUSDIV		6	/* Divider */
+
+/* Get the value of the current system clock */
+int get_sys_clock(void)
+{
+	ccm_t *ccm = (ccm_t *)(MMAP_CCM);
+	pll_t *pll = (pll_t *)(MMAP_PLL);
+	int divider;
+
+	/* Test to see if device is in LIMP mode */
+	if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
+		divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
+#ifdef CONFIG_MCF5301x
+		return (FREF / (3 * (1 << divider)));
+#endif
+#ifdef CONFIG_MCF532x
+		return (FREF / (2 << divider));
+#endif
+	} else {
+#ifdef CONFIG_MCF5301x
+		u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
+		u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
+		u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
+
+		return (((FREF * pfdr) / refdiv) / busdiv);
+#endif
+#ifdef CONFIG_MCF532x
+		return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
+#endif
+	}
+}
+
+/*
+ * Initialize the Low Power Divider circuit
+ *
+ * Parameters:
+ *  div     Desired system frequency divider
+ *
+ * Return Value:
+ *  The resulting output system frequency
+ */
+int clock_limp(int div)
+{
+	ccm_t *ccm = (ccm_t *)(MMAP_CCM);
+	u32 temp;
+
+	/* Check bounds of divider */
+	if (div < MIN_LPD)
+		div = MIN_LPD;
+	if (div > MAX_LPD)
+		div = MAX_LPD;
+
+	/* Save of the current value of the SSIDIV so we don't overwrite the value */
+	temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
+
+	/* Apply the divider to the system clock */
+	out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
+
+	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
+
+	return (FREF / (3 * (1 << div)));
+}
+
+/* Exit low power LIMP mode */
+int clock_exit_limp(void)
+{
+	ccm_t *ccm = (ccm_t *)(MMAP_CCM);
+	int fout;
+
+	/* Exit LIMP mode */
+	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
+
+	/* Wait for PLL to lock */
+	while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
+		;
+
+	fout = get_sys_clock();
+
+	return fout;
+}
+
+/* Initialize the PLL
+ *
+ * Parameters:
+ *  fref    PLL reference clock frequency in KHz
+ *  fsys    Desired PLL output frequency in KHz
+ *  flags   Operating parameters
+ *
+ * Return Value:
+ *  The resulting output system frequency
+ */
+int clock_pll(int fsys, int flags)
+{
+#ifdef CONFIG_MCF532x
+	u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
+#endif
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	pll_t *pll = (pll_t *)(MMAP_PLL);
+	int fref, temp, fout, mfd;
+	u32 i;
+
+	fref = FREF;
+
+	if (fsys == 0) {
+		/* Return current PLL output */
+#ifdef CONFIG_MCF5301x
+		u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
+		mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
+
+		return (fref * mfd) / busdiv;
+#endif
+#ifdef CONFIG_MCF532x
+		mfd = in_8(&pll->pfdr);
+
+		return (fref * mfd / (BUSDIV * 4));
+#endif
+	}
+
+	/* Check bounds of requested system clock */
+	if (fsys > MAX_FSYS)
+		fsys = MAX_FSYS;
+
+	if (fsys < MIN_FSYS)
+		fsys = MIN_FSYS;
+
+	/*
+	 * Multiplying by 100 when calculating the temp value,
+	 * and then dividing by 100 to calculate the mfd allows
+	 * for exact values without needing to include floating
+	 * point libraries.
+	 */
+	temp = (100 * fsys) / fref;
+#ifdef CONFIG_MCF5301x
+	mfd = (BUSDIV * temp) / 100;
+
+	/* Determine the output frequency for selected values */
+	fout = ((fref * mfd) / BUSDIV);
+#endif
+#ifdef CONFIG_MCF532x
+	mfd = (4 * BUSDIV * temp) / 100;
+
+	/* Determine the output frequency for selected values */
+	fout = ((fref * mfd) / (BUSDIV * 4));
+#endif
+
+/* must not tamper with SDRAMC if running from SDRAM */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+	/*
+	 * Check to see if the SDRAM has already been initialized.
+	 * If it has then the SDRAM needs to be put into self refresh
+	 * mode before reprogramming the PLL.
+	 */
+	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
+		clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
+
+	/*
+	 * Initialize the PLL to generate the new system clock frequency.
+	 * The device must be put into LIMP mode to reprogram the PLL.
+	 */
+
+	/* Enter LIMP mode */
+	clock_limp(DEFAULT_LPD);
+
+#ifdef CONFIG_MCF5301x
+	out_be32(&pll->pdr,
+		PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
+		PLL_PDR_OUTDIV2(BUSDIV - 1)	|
+		PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
+		PLL_PDR_OUTDIV4(USBDIV - 1));
+
+	clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
+	setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
+#endif
+#ifdef CONFIG_MCF532x
+	/* Reprogram PLL for desired fsys */
+	out_8(&pll->podr,
+		PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
+
+	out_8(&pll->pfdr, mfd);
+#endif
+
+	/* Exit LIMP mode */
+	clock_exit_limp();
+
+	/* Return the SDRAM to normal operation if it is in use. */
+	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
+		setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
+
+#ifdef CONFIG_MCF532x
+	/*
+	 * software workaround for SDRAM opeartion after exiting LIMP
+	 * mode errata
+	 */
+	out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
+#endif
+
+	/* wait for DQS logic to relock */
+	for (i = 0; i < 0x200; i++) ;
+#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
+
+	return fout;
+}
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+	gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
+	gd->cpu_clk = (gd->bus_clk * 3);
+
+#ifdef CONFIG_SYS_I2C_FSL
+	gd->arch.i2c1_clk = gd->bus_clk;
+#endif
+
+	return (0);
+}

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf532x/start.S

@@ -0,0 +1,274 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#define _START	_start
+#define _FAULT	_fault
+
+#define SAVE_ALL						\
+	move.w	#0x2700,%sr;		/* disable intrs */	\
+	subl	#60,%sp;		/* space for 15 regs */ \
+	moveml	%d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL						\
+	moveml	%sp@,%d0-%d7/%a0-%a6;				\
+	addl	#60,%sp;		/* space for 15 regs */ \
+	rte;
+
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+
+.text
+
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+INITSP:	.long	0x00000000		/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC		*/
+
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved */
+vector10_17:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved	*/
+vector30_3F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
+
+.text
+
+.globl _start
+_start:
+	nop
+	nop
+	move.w	#0x2700,%sr	/* Mask off Interrupt */
+
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+	/* Set vector base register at the beginning of the Flash */
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	movec	%d0, %VBR
+#endif
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	/* invalidate and disable cache */
+	move.l	#CF_CACR_CINVA, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+
+#ifdef CONFIG_MCF5301x
+	move.l	#(0xFC0a0010), %a0
+	move.w	(%a0), %d0
+	and.l	%d0, 0xEFFF
+
+	move.w	%d0, (%a0)
+#endif
+
+	/* initialize general use internal ram */
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+
+	/* put relocation table address to a5 */
+	move.l	#__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l	%d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
+
+	/* run low-level CPU init code (from flash) */
+	move.l	#cpu_init_f, %a1
+	jsr	(%a1)
+
+	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
+	move.l #board_init_f, %a1
+	jsr (%a1)
+
+	/* board_init_f() does not return */
+
+/******************************************************************************/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+.globl relocate_code
+relocate_code:
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
+
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
+
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
+
+	/* copy the code to RAM */
+1:
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a1,%a5			/* fix got pointer register a5 */
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start,%d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
+	jsr	(%a1)
+
+/******************************************************************************/
+
+/* exception code */
+.globl _fault
+_fault:
+	bra _fault
+
+.globl _exc_handler
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+.globl _int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/******************************************************************************/
+
+.globl version_string
+version_string:
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5445x/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+# ccflags-y += -DET_DEBUG
+
+extra-y	= start.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5445x/cpu.c

@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <watchdog.h>
+#include <command.h>
+#include <netdev.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+	udelay(1000);
+	out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
+	udelay(10000);
+	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
+
+	/* we don't return! */
+	return 0;
+};
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	u16 msk;
+	u16 id = 0;
+	u8 ver;
+
+	puts("CPU:   ");
+	msk = (in_be16(&ccm->cir) >> 6);
+	ver = (in_be16(&ccm->cir) & 0x003f);
+	switch (msk) {
+	case 0x48:
+		id = 54455;
+		break;
+	case 0x49:
+		id = 54454;
+		break;
+	case 0x4a:
+		id = 54453;
+		break;
+	case 0x4b:
+		id = 54452;
+		break;
+	case 0x4d:
+		id = 54451;
+		break;
+	case 0x4f:
+		id = 54450;
+		break;
+	case 0x9F:
+		id = 54410;
+		break;
+	case 0xA0:
+		id = 54415;
+		break;
+	case 0xA1:
+		id = 54416;
+		break;
+	case 0xA2:
+		id = 54417;
+		break;
+	case 0xA3:
+		id = 54418;
+		break;
+	}
+
+	if (id) {
+		char buf1[32], buf2[32], buf3[32];
+
+		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
+		       ver);
+		printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
+		       strmhz(buf1, gd->cpu_clk),
+		       strmhz(buf2, gd->bus_clk),
+		       strmhz(buf3, gd->arch.flb_clk));
+#ifdef CONFIG_PCI
+		printf("       PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
+		       strmhz(buf1, gd->pci_clk),
+		       strmhz(buf2, gd->arch.inp_clk),
+		       strmhz(buf3, gd->arch.vco_clk));
+#else
+		printf("       INP CLK %s MHz VCO CLK %s MHz\n",
+		       strmhz(buf1, gd->arch.inp_clk),
+		       strmhz(buf2, gd->arch.vco_clk));
+#endif
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers.  To override,
+ * create a board-specific function called:
+ * 	int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+	return mcffec_initialize(bis);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5445x/cpu_init.c

@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <watchdog.h>
+#include <asm/immap.h>
+#include <asm/processor.h>
+#include <asm/rtc.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
+void init_fbcs(void)
+{
+	fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
+
+#if !defined(CONFIG_SERIAL_BOOT)
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#endif
+#endif
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+	/* Latch chipselect */
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
+#endif
+}
+
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+	out_8(&gpio->par_dspi,
+	      GPIO_PAR_DSPI_SIN_SIN |
+	      GPIO_PAR_DSPI_SOUT_SOUT |
+	      GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+	pm_t *pm = (pm_t *)MMAP_PM;
+
+	out_8(&gpio->par_dspi0,
+	      GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+	      GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+	out_8(&gpio->srcr_dspiow, 3);
+
+	/* DSPI0 */
+	out_8(&pm->pmcr0, 23);
+#endif
+}
+#endif
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+#ifdef CONFIG_MCF5441x
+	scm_t *scm = (scm_t *) MMAP_SCM;
+	pm_t *pm = (pm_t *) MMAP_PM;
+
+	/* Disable Switch */
+	*(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
+
+	/* Disable core watchdog */
+	out_be16(&scm->cwcr, 0);
+	out_8(&gpio->par_fbctl,
+		GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
+		GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
+		GPIO_PAR_FBCTL_TA_TA);
+	out_8(&gpio->par_be,
+		GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+		GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+
+	/* eDMA */
+	out_8(&pm->pmcr0, 17);
+
+	/* INTR0 - INTR2 */
+	out_8(&pm->pmcr0, 18);
+	out_8(&pm->pmcr0, 19);
+	out_8(&pm->pmcr0, 20);
+
+	/* I2C */
+	out_8(&pm->pmcr0, 22);
+	out_8(&pm->pmcr1, 4);
+	out_8(&pm->pmcr1, 7);
+
+	/* DTMR0 - DTMR3*/
+	out_8(&pm->pmcr0, 28);
+	out_8(&pm->pmcr0, 29);
+	out_8(&pm->pmcr0, 30);
+	out_8(&pm->pmcr0, 31);
+
+	/* PIT0 - PIT3 */
+	out_8(&pm->pmcr0, 32);
+	out_8(&pm->pmcr0, 33);
+	out_8(&pm->pmcr0, 34);
+	out_8(&pm->pmcr0, 35);
+
+	/* Edge Port */
+	out_8(&pm->pmcr0, 36);
+	out_8(&pm->pmcr0, 37);
+
+	/* USB OTG */
+	out_8(&pm->pmcr0, 44);
+	/* USB Host */
+	out_8(&pm->pmcr0, 45);
+
+	/* ESDHC */
+	out_8(&pm->pmcr0, 51);
+
+	/* ENET0 - ENET1 */
+	out_8(&pm->pmcr0, 53);
+	out_8(&pm->pmcr0, 54);
+
+	/* NAND */
+	out_8(&pm->pmcr0, 63);
+
+#ifdef CONFIG_SYS_I2C_0
+	out_8(&gpio->par_cani2c, 0xF0);
+	/* I2C0 pull up */
+	out_be16(&gpio->pcr_b, 0x003C);
+	/* I2C0 max speed */
+	out_8(&gpio->srcr_cani2c, 0x03);
+#endif
+#ifdef CONFIG_SYS_I2C_2
+	/* I2C2 */
+	out_8(&gpio->par_ssi0h, 0xA0);
+	/* I2C2, UART7 */
+	out_8(&gpio->par_ssi0h, 0xA8);
+	/* UART7 */
+	out_8(&gpio->par_ssi0l, 0x2);
+	/* UART8, UART9 */
+	out_8(&gpio->par_cani2c, 0xAA);
+	/* UART4, UART0 */
+	out_8(&gpio->par_uart0, 0xAF);
+	/* UART5, UART1 */
+	out_8(&gpio->par_uart1, 0xAF);
+	/* UART6, UART2 */
+	out_8(&gpio->par_uart2, 0xAF);
+	/* I2C2 pull up */
+	out_be16(&gpio->pcr_h, 0xF000);
+#endif
+#ifdef CONFIG_SYS_I2C_5
+	/* I2C5 */
+	out_8(&gpio->par_uart1, 0x0A);
+	/* I2C5 pull up */
+	out_be16(&gpio->pcr_e, 0x0003);
+	out_be16(&gpio->pcr_f, 0xC000);
+#endif
+
+	/* Lowest slew rate for UART0,1,2 */
+	out_8(&gpio->srcr_uart, 0x00);
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+	/* eSDHC pin as faster speed */
+	out_8(&gpio->srcr_sdhc, 0x03);
+
+	/* All esdhc pins as SD */
+	out_8(&gpio->par_sdhch, 0xff);
+	out_8(&gpio->par_sdhcl, 0xff);
+#endif
+#endif		/* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
+	out_be32(&scm1->pacrg, 0);
+
+	/* FlexBus */
+	out_8(&gpio->par_be,
+		GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+		GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+	out_8(&gpio->par_fbctl,
+		GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+		GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+
+#ifdef CONFIG_CF_SPI
+	cfspi_port_conf();
+#endif
+
+#ifdef CONFIG_SYS_FSL_I2C
+	out_be16(&gpio->par_feci2c,
+		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
+#endif
+#endif		/* CONFIG_MCF5445x */
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+#ifdef CONFIG_SYS_CS0_BASE
+	/*
+	 * now the flash base address is no longer at 0 (Newer ColdFire family
+	 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
+	 * also move to the new location.
+	 */
+	if (CONFIG_SYS_CS0_BASE != 0)
+		setvbr(CONFIG_SYS_CS0_BASE);
+#endif
+
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+#ifdef CONFIG_MCFRTC
+	rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+	rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
+
+	out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
+#endif
+
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5441x
+	pm_t *pm = (pm_t *) MMAP_PM;
+#endif
+
+	/* Setup Ports: */
+	switch (port) {
+#ifdef CONFIG_MCF5441x
+	case 0:
+		/* UART0 */
+		out_8(&pm->pmcr0, 24);
+		clrbits_8(&gpio->par_uart0,
+			~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
+		setbits_8(&gpio->par_uart0,
+			GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
+		break;
+	case 1:
+		/* UART1 */
+		out_8(&pm->pmcr0, 25);
+		clrbits_8(&gpio->par_uart1,
+			~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
+		setbits_8(&gpio->par_uart1,
+			GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
+		break;
+	case 2:
+		/* UART2 */
+		out_8(&pm->pmcr0, 26);
+		clrbits_8(&gpio->par_uart2,
+			~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
+		setbits_8(&gpio->par_uart2,
+			GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
+		break;
+	case 3:
+		/* UART3 */
+		out_8(&pm->pmcr0, 27);
+		clrbits_8(&gpio->par_dspi0,
+			~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
+		setbits_8(&gpio->par_dspi0,
+			GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
+		break;
+	case 4:
+		/* UART4 */
+		out_8(&pm->pmcr1, 24);
+		clrbits_8(&gpio->par_uart0,
+			~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
+		setbits_8(&gpio->par_uart0,
+			GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
+		break;
+	case 5:
+		/* UART5 */
+		out_8(&pm->pmcr1, 25);
+		clrbits_8(&gpio->par_uart1,
+			~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
+		setbits_8(&gpio->par_uart1,
+			GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
+		break;
+	case 6:
+		/* UART6 */
+		out_8(&pm->pmcr1, 26);
+		clrbits_8(&gpio->par_uart2,
+			~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
+		setbits_8(&gpio->par_uart2,
+			GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
+		break;
+	case 7:
+		/* UART7 */
+		out_8(&pm->pmcr1, 27);
+		clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
+		clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
+		setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
+		setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
+		break;
+	case 8:
+		/* UART8 */
+		out_8(&pm->pmcr0, 28);
+		clrbits_8(&gpio->par_cani2c,
+			~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
+		setbits_8(&gpio->par_cani2c,
+			GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
+		break;
+	case 9:
+		/* UART9 */
+		out_8(&pm->pmcr1, 29);
+		clrbits_8(&gpio->par_cani2c,
+			~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
+		setbits_8(&gpio->par_cani2c,
+			GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
+		break;
+#endif
+#ifdef CONFIG_MCF5445x
+	case 0:
+		clrbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		break;
+	case 1:
+#ifdef CONFIG_SYS_UART1_PRI_GPIO
+		clrbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
+		clrbits_be16(&gpio->par_ssi,
+			~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
+		setbits_be16(&gpio->par_ssi,
+			GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
+#endif
+		break;
+	case 2:
+#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
+#endif
+		break;
+#endif	/* CONFIG_MCF5445x */
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5445x
+	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+	if (setclear) {
+#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+			setbits_be16(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC0_MDC0 |
+				GPIO_PAR_FECI2C_MDIO0_MDIO0);
+		else
+			setbits_be16(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC1_MDC1 |
+				GPIO_PAR_FECI2C_MDIO1_MDIO1);
+#else
+		setbits_be16(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+#endif
+
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
+		else
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
+	} else {
+		clrbits_be16(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+#ifdef CONFIG_SYS_FEC_FULL_MII
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
+#else
+			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
+#endif
+		} else {
+#ifdef CONFIG_SYS_FEC_FULL_MII
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
+#else
+			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
+#endif
+		}
+	}
+#endif	/* CONFIG_MCF5445x */
+
+#ifdef CONFIG_MCF5441x
+	if (setclear) {
+		out_8(&gpio->par_fec, 0x03);
+		out_8(&gpio->srcr_fec, 0x0F);
+		clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
+			GPIO_PAR_SIMP0H_DAT_GPIO);
+		clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
+			GPIO_PDDR_G4_OUTPUT);
+		clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
+
+	} else
+		clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
+#endif
+	return 0;
+}
+#endif
+

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5445x/dspi.c

@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Angelo Dureghello <angleo@sysam.it>
+ *
+ * CPU specific dspi routines
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CF_DSPI
+void dspi_chip_select(int cs)
+{
+	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		break;
+	case 1:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+		break;
+	case 2:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+		break;
+	case 3:
+		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+		setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
+		break;
+	case 5:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+		break;
+	}
+#endif
+#ifdef CONFIG_MCF5441x
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi0,
+			  ~GPIO_PAR_DSPI0_PCS0_MASK);
+		setbits_8(&gpio->par_dspi0,
+			  GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+		break;
+	case 1:
+		clrbits_8(&gpio->par_dspiow,
+			  GPIO_PAR_DSPIOW_DSPI0PSC1);
+		setbits_8(&gpio->par_dspiow,
+			  GPIO_PAR_DSPIOW_DSPI0PSC1);
+		break;
+	}
+#endif
+}
+
+void dspi_chip_unselect(int cs)
+{
+	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		break;
+	case 1:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+		break;
+	case 2:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+		break;
+	case 3:
+		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+		break;
+	case 5:
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+		break;
+	}
+#endif
+#ifdef CONFIG_MCF5441x
+	if (cs == 1)
+		clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
+}
+#endif /* CONFIG_CF_DSPI */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5445x/interrupts.c

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <irq_func.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+int interrupt_init(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	/* Make sure all interrupts are disabled */
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
+
+	enable_interrupts();
+	return 0;
+}
+
+#if defined(CONFIG_MCFTMR)
+void dtimer_intr_setup(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5445x/pci.c

@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * PCI Configuration space access support
+ */
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+#if defined(CONFIG_PCI)
+/* System RAM mapped over PCI */
+#define CONFIG_SYS_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define cfg_read(val, addr, type, op)		*val = op((type)(addr));
+#define cfg_write(val, addr, type, op)		op((type *)(addr), (val));
+
+#define PCI_OP(rw, size, type, op, mask)				\
+int pci_##rw##_cfg_##size(struct pci_controller *hose,			\
+	pci_dev_t dev, int offset, type val)				\
+{									\
+	u32 addr = 0;							\
+	u16 cfg_type = 0;						\
+	addr = ((offset & 0xfc) | cfg_type | (dev)  | 0x80000000);	\
+	out_be32(hose->cfg_addr, addr);					\
+	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	\
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);			\
+	return 0;							\
+}
+
+PCI_OP(read, byte, u8 *, in_8, 3)
+PCI_OP(read, word, u16 *, in_le16, 2)
+PCI_OP(read, dword, u32 *, in_le32, 0)
+PCI_OP(write, byte, u8, out_8, 3)
+PCI_OP(write, word, u16, out_le16, 2)
+PCI_OP(write, dword, u32, out_le32, 0)
+
+void pci_mcf5445x_init(struct pci_controller *hose)
+{
+	pci_t *pci = (pci_t *)MMAP_PCI;
+	pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	u32 barEn = 0;
+
+	out_be32(&pciarb->acr, 0x001f001f);
+
+	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
+	   PCIREQ2, PCIGNT2 */
+	out_be16(&gpio->par_pci,
+		GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
+		GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
+		GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
+		GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
+
+	/* Assert reset bit */
+	setbits_be32(&pci->gscr, PCI_GSCR_PR);
+
+	setbits_be32(&pci->tcr1, PCI_TCR1_P);
+
+	/* Initiator windows */
+	out_be32(&pci->iw0btar,
+		CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
+	out_be32(&pci->iw1btar,
+		CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
+	out_be32(&pci->iw2btar,
+		CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
+
+	out_be32(&pci->iwcr,
+		PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+		PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
+
+	out_be32(&pci->icr, 0);
+
+	/* Enable bus master and mem access */
+	out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
+
+	/* Cache line size and master latency */
+	out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
+	out_be32(&pci->cr2, 0);
+
+#ifdef CONFIG_SYS_PCI_BAR0
+	out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
+	out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
+	barEn |= PCI_TCR2_B0E;
+#endif
+#ifdef CONFIG_SYS_PCI_BAR1
+	out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
+	out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
+	barEn |= PCI_TCR2_B1E;
+#endif
+#ifdef CONFIG_SYS_PCI_BAR2
+	out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
+	out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
+	barEn |= PCI_TCR2_B2E;
+#endif
+#ifdef CONFIG_SYS_PCI_BAR3
+	out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
+	out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
+	barEn |= PCI_TCR2_B3E;
+#endif
+#ifdef CONFIG_SYS_PCI_BAR4
+	out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
+	out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
+	barEn |= PCI_TCR2_B4E;
+#endif
+#ifdef CONFIG_SYS_PCI_BAR5
+	out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
+	out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
+	barEn |= PCI_TCR2_B5E;
+#endif
+
+	out_be32(&pci->tcr2, barEn);
+
+	/* Deassert reset bit */
+	clrbits_be32(&pci->gscr, PCI_GSCR_PR);
+	udelay(1000);
+
+	/* Enable PCI bus master support */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
+
+	pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
+		       CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
+		       CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 3;
+
+	hose->cfg_addr = &(pci->car);
+	hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
+
+	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
+		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
+		    pci_write_cfg_dword);
+
+	/* Hose scan */
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
+}
+#endif				/* CONFIG_PCI */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5445x/speed.c

@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Low Power Divider specifications
+ */
+#define CLOCK_LPD_MIN		(1 << 0)	/* Divider (decoded) */
+#define CLOCK_LPD_MAX		(1 << 15)	/* Divider (decoded) */
+
+#define CLOCK_PLL_FVCO_MAX	540000000
+#define CLOCK_PLL_FVCO_MIN	300000000
+
+#define CLOCK_PLL_FSYS_MAX	266666666
+#define CLOCK_PLL_FSYS_MIN	100000000
+#define MHZ			1000000
+
+void clock_enter_limp(int lpdiv)
+{
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	int i, j;
+
+	/* Check bounds of divider */
+	if (lpdiv < CLOCK_LPD_MIN)
+		lpdiv = CLOCK_LPD_MIN;
+	if (lpdiv > CLOCK_LPD_MAX)
+		lpdiv = CLOCK_LPD_MAX;
+
+	/* Round divider down to nearest power of two */
+	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
+
+#ifdef CONFIG_MCF5445x
+	/* Apply the divider to the system clock */
+	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
+#endif
+
+	/* Enable Limp Mode */
+	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
+}
+
+/*
+ * brief   Exit Limp mode
+ * warning The PLL should be set and locked prior to exiting Limp mode
+ */
+void clock_exit_limp(void)
+{
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
+
+	/* Exit Limp mode */
+	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
+
+	/* Wait for the PLL to lock */
+	while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
+		;
+}
+
+#ifdef CONFIG_MCF5441x
+void setup_5441x_clocks(void)
+{
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
+	int temp, vco = 0, bootmod_ccr, pdr;
+
+	bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
+
+	switch (bootmod_ccr) {
+	case 0:
+		out_be32(&pll->pcr, 0x00000013);
+		out_be32(&pll->pdr, 0x00e70c61);
+		clock_exit_limp();
+		break;
+	case 2:
+		break;
+	case 3:
+		break;
+	}
+
+	/*Change frequency for Modelo SER1 USB host*/
+#ifdef CONFIG_LOW_MCFCLK
+	temp = in_be32(&pll->pcr);
+	temp &= ~0x3f;
+	temp |= 5;
+	out_be32(&pll->pcr, temp);
+
+	temp = in_be32(&pll->pdr);
+	temp &= ~0x001f0000;
+	temp |= 0x00040000;
+	out_be32(&pll->pdr, temp);
+	__asm__("tpf");
+#endif
+
+	setbits_be16(&ccm->misccr2, 0x02);
+
+	vco =  ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
+		CONFIG_SYS_INPUT_CLKSRC;
+	gd->arch.vco_clk = vco;
+
+	gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
+
+	pdr = in_be32(&pll->pdr);
+	temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
+	gd->cpu_clk = vco / temp;	/* cpu clock */
+	gd->arch.flb_clk = vco / temp;	/* FlexBus clock */
+	gd->arch.flb_clk >>= 1;
+	if (in_be16(&ccm->misccr2) & 2)		/* fsys/4 */
+		gd->arch.flb_clk >>= 1;
+
+	temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
+	gd->bus_clk = vco / temp;	/* bus clock */
+
+	temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1;
+	gd->arch.sdhc_clk = vco / temp;
+}
+#endif
+
+#ifdef CONFIG_MCF5445x
+void setup_5445x_clocks(void)
+{
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
+	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
+	int pllmult_pci[] = { 12, 6, 16, 8 };
+	int vco = 0, temp, fbtemp, pcrvalue;
+	int *pPllmult = NULL;
+	u16 fbpll_mask;
+#ifdef CONFIG_PCI
+	int bPci;
+#endif
+
+#ifdef CONFIG_M54455EVB
+	u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
+#endif
+	u8 bootmode;
+
+	/* To determine PCI is present or not */
+	if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
+	    ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
+		pPllmult = &pllmult_pci[0];
+		fbpll_mask = 3;		/* 11b */
+#ifdef CONFIG_PCI
+		bPci = 1;
+#endif
+	} else {
+		pPllmult = &pllmult_nopci[0];
+		fbpll_mask = 7;		/* 111b */
+#ifdef CONFIG_PCI
+		gd->pci_clk = 0;
+		bPci = 0;
+#endif
+	}
+
+#ifdef CONFIG_M54455EVB
+	bootmode = (in_8(cpld) & 0x03);
+
+	if (bootmode != 3) {
+		/* Temporary read from CCR- fixed fb issue, must be the same clock
+		   as pci or input clock, causing cpld/fpga read inconsistancy */
+		fbtemp = pPllmult[ccm->ccr & fbpll_mask];
+
+		/* Break down into small pieces, code still in flex bus */
+		pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
+		temp = fbtemp - 1;
+		pcrvalue |= PLL_PCR_OUTDIV3(temp);
+
+		out_be32(&pll->pcr, pcrvalue);
+	}
+#endif
+#ifdef CONFIG_M54451EVB
+	/* No external logic to read the bootmode, hard coded from built */
+#ifdef CONFIG_CF_SBF
+	bootmode = 3;
+#else
+	bootmode = 2;
+
+	/* default value is 16 mul, set to 20 mul */
+	pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
+	out_be32(&pll->pcr, pcrvalue);
+	while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
+		;
+#endif
+#endif
+
+	if (bootmode == 0) {
+		/* RCON mode */
+		vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
+
+		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
+			/* invaild range, re-set in PCR */
+			int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+			int i, j, bus;
+
+			j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
+			for (i = j; i < 0xFF; i++) {
+				vco = i * CONFIG_SYS_INPUT_CLKSRC;
+				if (vco >= CLOCK_PLL_FVCO_MIN) {
+					bus = vco / temp;
+					if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
+						continue;
+					else
+						break;
+				}
+			}
+			pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
+			fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
+			pcrvalue |= ((i << 24) | fbtemp);
+
+			out_be32(&pll->pcr, pcrvalue);
+		}
+		gd->arch.vco_clk = vco;	/* Vco clock */
+	} else if (bootmode == 2) {
+		/* Normal mode */
+		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
+			/* Default value */
+			pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
+			pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
+			out_be32(&pll->pcr, pcrvalue);
+			vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		}
+		gd->arch.vco_clk = vco;	/* Vco clock */
+	} else if (bootmode == 3) {
+		/* serial mode */
+		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		gd->arch.vco_clk = vco;	/* Vco clock */
+	}
+
+	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+		/* Limp mode */
+	} else {
+		gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
+
+		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
+		gd->cpu_clk = vco / temp;	/* cpu clock */
+
+		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+		gd->bus_clk = vco / temp;	/* bus clock */
+
+		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
+		gd->arch.flb_clk = vco / temp;	/* FlexBus clock */
+
+#ifdef CONFIG_PCI
+		if (bPci) {
+			temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
+			gd->pci_clk = vco / temp;	/* PCI clock */
+		}
+#endif
+	}
+
+#ifdef CONFIG_SYS_I2C_FSL
+	gd->arch.i2c1_clk = gd->bus_clk;
+#endif
+}
+#endif
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#ifdef CONFIG_MCF5441x
+	setup_5441x_clocks();
+#endif
+#ifdef CONFIG_MCF5445x
+	setup_5445x_clocks();
+#endif
+
+#ifdef CONFIG_SYS_FSL_I2C
+	gd->arch.i2c1_clk = gd->bus_clk;
+#endif
+
+	return (0);
+}

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf5445x/start.S

@@ -0,0 +1,623 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <asm-offsets.h>
+#include <config.h>
+#include <timestamp.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#define _START	_start
+#define _FAULT	_fault
+
+#define SAVE_ALL						\
+	move.w	#0x2700,%sr;		/* disable intrs */	\
+	subl	#60,%sp;		/* space for 15 regs */ \
+	moveml	%d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL						\
+	moveml	%sp@,%d0-%d7/%a0-%a6;				\
+	addl	#60,%sp;		/* space for 15 regs */ \
+	rte;
+
+#if defined(CONFIG_SERIAL_BOOT)
+#define ASM_DRAMINIT	(asm_dram_init - CONFIG_SYS_TEXT_BASE + \
+	CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT_N	(asm_dram_init - CONFIG_SYS_TEXT_BASE)
+#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
+	CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+
+.text
+
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+#if defined(CONFIG_SERIAL_BOOT)
+
+INITSP:	.long	0			/* Initial SP	*/
+#ifdef CONFIG_CF_SBF
+INITPC:	.long	ASM_DRAMINIT		/* Initial PC 	*/
+#endif
+#ifdef CONFIG_SYS_NAND_BOOT
+INITPC:	.long	ASM_DRAMINIT_N		/* Initial PC 	*/
+#endif
+
+#else
+
+INITSP:	.long	0			/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC 	*/
+
+#endif
+
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved */
+vector10_17:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+#if !defined(CONFIG_SERIAL_BOOT)
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved	*/
+vector30_3F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+#endif
+
+#if defined(CONFIG_SERIAL_BOOT)
+	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
+asm_sbf_img_hdr:
+	.long	0x00000000		/* checksum, not yet implemented */
+	.long	0x00040000		/* image length */
+	.long	CONFIG_SYS_TEXT_BASE	/* image to be relocated at */
+
+asm_dram_init:
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
+
+#ifdef CONFIG_SYS_NAND_BOOT
+	/* for assembly stack */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	clr.l	%sp@-
+#endif
+
+#ifdef CONFIG_CF_SBF
+	move.l	#CONFIG_SYS_INIT_RAM_ADDR, %d0
+	movec	%d0, %VBR
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	/* initialize general use internal ram */
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* dcache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+
+	/* invalidate and disable cache */
+	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	clr.l	%sp@-
+
+#ifdef CONFIG_SYS_CS0_BASE
+	/* Must disable global address */
+	move.l	#0xFC008000, %a1
+	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#0xFC008008, %a1
+	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#0xFC008004, %a1
+	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+#endif
+#endif /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_MCF5441x
+	/* TC: enable all peripherals,
+	in the future only enable certain peripherals */
+	move.l	#0xFC04002D, %a1
+
+#if defined(CONFIG_CF_SBF)
+	move.b	#23, (%a1)		/* dspi */
+#endif
+#endif	/* CONFIG_MCF5441x */
+
+	/* mandatory board level ddr-sdram init,
+	 * for both 5441x and 5445x
+	 */
+	bsr	sbf_dram_init
+
+#ifdef CONFIG_CF_SBF
+	/*
+	 * DSPI Initialization
+	 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
+	 * a1 - dspi status
+	 * a2 - dtfr
+	 * a3 - drfr
+	 * a4 - Dst addr
+	 */
+	/* Enable pins for DSPI mode - chip-selects are enabled later */
+asm_dspi_init:
+#ifdef CONFIG_MCF5441x
+	move.l	#0xEC09404E, %a1
+	move.l	#0xEC09404F, %a2
+	move.b	#0xFF, (%a1)
+	move.b	#0x80, (%a2)
+#endif
+
+#ifdef CONFIG_MCF5445x
+	move.l	#0xFC0A4063, %a0
+	move.b	#0x7F, (%a0)
+#endif
+	/* Configure DSPI module */
+	move.l	#0xFC05C000, %a0
+	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
+
+	move.l	#0xFC05C00C, %a0
+#ifdef CONFIG_MCF5441x
+	move.l	#0x3E000016, (%a0)
+#endif
+#ifdef CONFIG_MCF5445x
+	move.l	#0x3E000011, (%a0)
+#endif
+
+	move.l	#0xFC05C034, %a2	/* dtfr */
+	move.l	#0xFC05C03B, %a3	/* drfr */
+
+	move.l	#(ASM_SBF_IMG_HDR + 4), %a1
+	move.l	(%a1)+, %d5
+	move.l	(%a1), %a4
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
+	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
+
+	move.l	#0xFC05C02C, %a1	/* dspi status */
+
+	/* Issue commands and address */
+	move.l	#0x8002000B, %d2	/* Fast Read Cmd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80020000, %d2	/* Address byte 2 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80020000, %d2	/* Address byte 1 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80020000, %d2	/* Address byte 0 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80020000, %d2	/* Dummy Wr and Rd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* Transfer serial boot header to sram */
+asm_dspi_rd_loop1:
+	move.l	#0x80020000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a0)		/* read, copy to dst */
+
+	add.l	#1, %a0			/* inc dst by 1 */
+	sub.l	#1, %d4			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop1
+
+	/* Transfer u-boot from serial flash to memory */
+asm_dspi_rd_loop2:
+	move.l	#0x80020000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a4)		/* read, copy to dst */
+
+	add.l	#1, %a4			/* inc dst by 1 */
+	sub.l	#1, %d5			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop2
+
+	move.l	#0x00020000, %d2	/* Terminate */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* jump to memory and execute */
+	move.l	#(CONFIG_SYS_TEXT_BASE + 0x400), %a0
+	jmp	(%a0)
+
+asm_dspi_wr_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x0000F000, %d0
+	cmp.l	#0x00003000, %d0
+	bgt	asm_dspi_wr_status
+
+	move.l	%d2, (%a2)
+	rts
+
+asm_dspi_rd_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x000000F0, %d0
+	lsr.l	#4, %d0
+	cmp.l	#0, %d0
+	beq	asm_dspi_rd_status
+
+	move.b	(%a3), %d1
+	rts
+#endif /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_SYS_NAND_BOOT
+	/* copy 4 boot pages to dram as soon as possible */
+	/* each page is 996 bytes (1056 total with 60 ECC bytes */
+	move.l  #0x00000000, %a1	/* src */
+	move.l	#CONFIG_SYS_TEXT_BASE, %a2		/* dst */
+	move.l	#0x3E0, %d0		/* sz in long */
+
+asm_boot_nand_copy:
+	move.l	(%a1)+, (%a2)+
+	subq.l	#1, %d0
+	bne	asm_boot_nand_copy
+
+	/* jump to memory and execute */
+	move.l	#(asm_nand_init), %a0
+	jmp	(%a0)
+
+asm_nand_init:
+	/* exit nand boot-mode */
+	move.l	#0xFC0FFF30, %a1
+	or.l	#0x00000040, %d1
+	move.l	%d1, (%a1)
+
+	/* initialize general use internal ram */
+	move.l	#0, %d0
+	move.l	#(CACR_STATUS), %a1	/* CACR */
+	move.l	#(ICACHE_STATUS), %a2	/* icache */
+	move.l	#(DCACHE_STATUS), %a3	/* dcache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a3)
+
+	/* invalidate and disable cache */
+	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+
+#ifdef CONFIG_SYS_CS0_BASE
+	/* Must disable global address */
+	move.l	#0xFC008000, %a1
+	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#0xFC008008, %a1
+	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#0xFC008004, %a1
+	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+#endif
+
+	/* NAND port configuration */
+	move.l	#0xEC094048, %a1
+	move.b	#0xFD, (%a1)+
+	move.b	#0x5F, (%a1)+
+	move.b	#0x04, (%a1)+
+
+	/* reset nand */
+	move.l  #0xFC0FFF38, %a1	/* isr */
+	move.l  #0x000e0000, (%a1)
+	move.l	#0xFC0FFF08, %a2
+	move.l	#0x00000000, (%a2)+	/* car */
+	move.l	#0x11000000, (%a2)+	/* rar */
+	move.l	#0x00000000, (%a2)+	/* rpt */
+	move.l	#0x00000000, (%a2)+	/* rai */
+	move.l  #0xFC0FFF2c, %a2	/* cfg */
+	move.l  #0x00000000, (%a2)+	/* secsz */
+	move.l  #0x000e0681, (%a2)+
+	move.l  #0xFC0FFF04, %a2	/* cmd2 */
+	move.l  #0xFF404001, (%a2)
+	move.l  #0x000e0000, (%a1)
+
+	move.l	#0x2000, %d1
+	bsr	asm_delay
+
+	/* setup nand */
+	move.l  #0xFC0FFF00, %a1
+	move.l  #0x30700000, (%a1)+	/* cmd1 */
+	move.l  #0x007EF000, (%a1)+	/* cmd2 */
+
+	move.l  #0xFC0FFF2C, %a1
+	move.l  #0x00000841, (%a1)+	/* secsz */
+	move.l  #0x000e0681, (%a1)+	/* cfg */
+
+	move.l	#100, %d4		/* 100 pages ~200KB */
+	move.l	#4, %d2			/* start at 4 */
+	move.l  #0xFC0FFF04, %a0	/* cmd2 */
+	move.l  #0xFC0FFF0C, %a1	/* rar */
+	move.l	#(CONFIG_SYS_TEXT_BASE + 0xF80), %a2
+
+asm_nand_read:
+	move.l	#0x11000000, %d0	/* rar */
+	or.l	%d2, %d0
+	move.l	%d0, (%a1)
+	add.l	#1, %d2
+
+	move.l	(%a0), %d0		/* cmd2 */
+	or.l	#1, %d0
+	move.l	%d0, (%a0)
+
+	move.l	#0x200, %d1
+	bsr	asm_delay
+
+asm_nand_chk_status:
+	move.l  #0xFC0FFF38, %a4	/* isr */
+	move.l	(%a4), %d0
+	and.l	#0x40000000, %d0
+	tst.l	%d0
+	beq	asm_nand_chk_status
+
+	move.l  #0xFC0FFF38, %a4	/* isr */
+	move.l	(%a4), %d0
+	or.l	#0x000E0000, %d0
+	move.l	%d0, (%a4)
+
+	move.l	#0x200, %d3
+	move.l	#0xFC0FC000, %a3	/* buf 1 */
+asm_nand_copy:
+	move.l	(%a3)+, (%a2)+
+	subq.l	#1, %d3
+	bgt	asm_nand_copy
+
+	subq.l	#1, %d4
+	bgt	asm_nand_read
+
+	/* jump to memory and execute */
+	move.l	#(CONFIG_SYS_TEXT_BASE + 0x400), %a0
+	jmp	(%a0)
+
+#endif			/* CONFIG_SYS_NAND_BOOT */
+
+.globl asm_delay
+asm_delay:
+	nop
+	subq.l	#1, %d1
+	bne	asm_delay
+	rts
+#endif			/* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
+
+.text
+	. = 0x400
+.globl _start
+_start:
+#if !defined(CONFIG_SERIAL_BOOT)
+	nop
+	nop
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
+
+	/* Set vector base register at the beginning of the Flash */
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	movec	%d0, %VBR
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	/* initialize general use internal ram */
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* dcache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+
+	/* invalidate and disable cache */
+	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+#else
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+#endif
+
+	/* put relocation table address to a5 */
+	move.l	#__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l	%d0, %sp
+	move.l	%sp, %fp
+
+	/* initialize reserved area */
+	move.l	%d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
+
+	/* run low-level CPU init code (from flash) */
+	move.l	#cpu_init_f, %a1
+	jsr	(%a1)
+
+	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
+	move.l	#board_init_f, %a1
+	jsr	(%a1)
+
+	/* board_init_f() does not return */
+
+/******************************************************************************/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+.globl relocate_code
+relocate_code:
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
+
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
+
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
+
+	/* copy the code to RAM */
+1:
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a1,%a5			/* fix got pointer register a5 */
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start,%d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
+	jsr	(%a1)
+
+/******************************************************************************/
+
+/* exception code */
+.globl _fault
+_fault:
+	bra	_fault
+
+.globl _exc_handler
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+.globl _int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/******************************************************************************/
+
+.globl version_string
+version_string:
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf547x_8x/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+# ccflags-y += -DET_DEBUG
+
+extra-y = start.o
+obj-y	= cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf547x_8x/cpu.c

@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <watchdog.h>
+#include <command.h>
+#include <netdev.h>
+
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+
+	out_be16(&gptmr->pre, 10);
+	out_be16(&gptmr->cnt, 1);
+
+	/* enable watchdog, set timeout to 0 and wait */
+	out_8(&gptmr->mode, GPT_TMS_SGPIO);
+	out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
+
+	/* we don't return! */
+	return 1;
+};
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	siu_t *siu = (siu_t *) MMAP_SIU;
+	u16 id = 0;
+
+	puts("CPU:   ");
+
+	switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
+	case 0x0C:
+		id = 5485;
+		break;
+	case 0x0D:
+		id = 5484;
+		break;
+	case 0x0E:
+		id = 5483;
+		break;
+	case 0x0F:
+		id = 5482;
+		break;
+	case 0x10:
+		id = 5481;
+		break;
+	case 0x11:
+		id = 5480;
+		break;
+	case 0x12:
+		id = 5475;
+		break;
+	case 0x13:
+		id = 5474;
+		break;
+	case 0x14:
+		id = 5473;
+		break;
+	case 0x15:
+		id = 5472;
+		break;
+	case 0x16:
+		id = 5471;
+		break;
+	case 0x17:
+		id = 5470;
+		break;
+	}
+
+	if (id) {
+		char buf1[32], buf2[32];
+
+		printf("Freescale MCF%d\n", id);
+		printf("       CPU CLK %s MHz BUS CLK %s MHz\n",
+		       strmhz(buf1, gd->cpu_clk),
+		       strmhz(buf2, gd->bus_clk));
+	}
+
+	return 0;
+};
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#if defined(CONFIG_HW_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void hw_watchdog_reset(void)
+{
+	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+
+	out_8(&gptmr->ocpw, 0xa5);
+}
+
+int watchdog_disable(void)
+{
+	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+
+	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
+	out_8(&gptmr->mode, 0);
+	out_8(&gptmr->ctrl, 0);
+
+	puts("WATCHDOG:disabled\n");
+
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+
+	out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
+	out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
+
+	out_8(&gptmr->mode, GPT_TMS_SGPIO);
+	out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
+	puts("WATCHDOG:enabled\n");
+
+	return (0);
+}
+#endif				/* CONFIG_HW_WATCHDOG */
+
+#if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers.  To override,
+ * create a board-specific function called:
+ * 	int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSLDMAFEC)
+	mcdmafec_initialize(bis);
+#endif
+#if defined(CONFIG_MCFFEC)
+	mcffec_initialize(bis);
+#endif
+	return 0;
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf547x_8x/cpu_init.c

@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <MCD_dma.h>
+#include <cpu_func.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fsl_mcdmafec.h>
+#endif
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
+
+	out_be32(&xlbarb->adrto, 0x2000);
+	out_be32(&xlbarb->datto, 0x2500);
+	out_be32(&xlbarb->busto, 0x3000);
+
+	out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
+
+	/* Master Priority Enable */
+	out_be32(&xlbarb->prien, 0xff);
+	out_be32(&xlbarb->pri, 0);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
+#endif
+
+#ifdef CONFIG_SYS_I2C_FSL
+	out_be16(&gpio->par_feci2cirq,
+		GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
+#endif
+
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
+	MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
+		    MCD_RELOC_TASKS);
+#endif
+	return (0);
+}
+
+void uart_port_conf(int port)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
+
+	/* Setup Ports: */
+	switch (port) {
+	case 0:
+		out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
+		break;
+	case 1:
+		out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
+		break;
+	case 2:
+		out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
+		break;
+	case 3:
+		out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
+		break;
+	}
+
+	clrbits_8(pscsicr, 0x07);
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
+
+	if (setclear) {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+			setbits_be16(&gpio->par_feci2cirq, 0xf000);
+		else
+			setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
+	} else {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+			clrbits_be16(&gpio->par_feci2cirq, 0xf000);
+		else
+			clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
+	}
+	return 0;
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf547x_8x/interrupts.c

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/* CPU specific interrupt routine */
+#include <common.h>
+#include <irq_func.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+int interrupt_init(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	/* Make sure all interrupts are disabled */
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
+
+	enable_interrupts();
+
+	return 0;
+}
+
+#if defined(CONFIG_SLTTMR)
+void dtimer_intr_setup(void)
+{
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+}
+#endif

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf547x_8x/pci.c

@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * PCI Configuration space access support
+ */
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+#if defined(CONFIG_PCI)
+/* System RAM mapped over PCI */
+#define CONFIG_SYS_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define cfg_read(val, addr, type, op)		*val = op((type)(addr));
+#define cfg_write(val, addr, type, op)		op((type *)(addr), (val));
+
+#define PCI_OP(rw, size, type, op, mask)				\
+int pci_##rw##_cfg_##size(struct pci_controller *hose,			\
+	pci_dev_t dev, int offset, type val)				\
+{									\
+	u32 addr = 0;							\
+	u16 cfg_type = 0;						\
+	addr = ((offset & 0xfc) | cfg_type | (dev)  | 0x80000000);	\
+	out_be32(hose->cfg_addr, addr);					\
+	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	\
+	__asm__ __volatile__("nop");					\
+	__asm__ __volatile__("nop");					\
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);			\
+	return 0;							\
+}
+
+PCI_OP(read, byte, u8 *, in_8, 3)
+PCI_OP(read, word, u16 *, in_le16, 2)
+PCI_OP(write, byte, u8, out_8, 3)
+PCI_OP(write, word, u16, out_le16, 2)
+PCI_OP(write, dword, u32, out_le32, 0)
+
+int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
+		       int offset, u32 * val)
+{
+	u32 addr;
+	u32 tmpv;
+	u32 mask = 2;		/* word access */
+	/* Read lower 16 bits */
+	addr = ((offset & 0xfc) | (dev) | 0x80000000);
+	out_be32(hose->cfg_addr, addr);
+	*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+	__asm__ __volatile__("nop");
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);
+
+	/* Read upper 16 bits */
+	offset += 2;
+	addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
+	out_be32(hose->cfg_addr, addr);
+	tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+	__asm__ __volatile__("nop");
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);
+
+	/* combine results into dword value */
+	*val = (tmpv << 16) | *val;
+
+	return 0;
+}
+
+void pci_mcf547x_8x_init(struct pci_controller *hose)
+{
+	pci_t *pci = (pci_t *) MMAP_PCI;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Port configuration */
+	out_be16(&gpio->par_pcibg,
+		GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
+		GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
+		GPIO_PAR_PCIBG_PCIBG4(3));
+	out_be16(&gpio->par_pcibr,
+		GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
+		GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
+		GPIO_PAR_PCIBR_PCIBR4(3));
+
+	/* Assert reset bit */
+	setbits_be32(&pci->gscr, PCI_GSCR_PR);
+
+	out_be32(&pci->tcr1, PCI_TCR1_P);
+
+	/* Initiator windows */
+	out_be32(&pci->iw0btar,
+		CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
+	out_be32(&pci->iw1btar,
+		CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
+	out_be32(&pci->iw2btar,
+		CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
+
+	out_be32(&pci->iwcr,
+		PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+		PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
+
+	out_be32(&pci->icr, 0);
+
+	/* Enable bus master and mem access */
+	out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
+
+	/* Cache line size and master latency */
+	out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
+	out_be32(&pci->cr2, 0);
+
+#ifdef CONFIG_SYS_PCI_BAR0
+	out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
+	out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
+#endif
+#ifdef CONFIG_SYS_PCI_BAR1
+	out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
+	out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
+#endif
+
+	/* Deassert reset bit */
+	clrbits_be32(&pci->gscr, PCI_GSCR_PR);
+	udelay(1000);
+
+	/* Enable PCI bus master support */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
+
+	pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
+		       CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
+		       CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 3;
+
+	hose->cfg_addr = &(pci->car);
+	hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
+
+	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
+		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
+		    pci_write_cfg_dword);
+
+	/* Hose scan */
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
+}
+#endif				/* CONFIG_PCI */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf547x_8x/slicetimer.c

@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <irq_func.h>
+
+#include <asm/timer.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong timestamp;
+
+#if defined(CONFIG_SLTTMR)
+#ifndef CONFIG_SYS_UDELAY_BASE
+#	error	"uDelay base not defined!"
+#endif
+
+#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
+#	error	"TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
+#endif
+extern void dtimer_intr_setup(void);
+
+void __udelay(unsigned long usec)
+{
+	slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
+	u32 now, freq;
+
+	/* 1 us period */
+	freq = CONFIG_SYS_TIMER_PRESCALER;
+
+	/* Disable */
+	out_be32(&timerp->cr, 0);
+	out_be32(&timerp->tcnt, usec * freq);
+	out_be32(&timerp->cr, SLT_CR_TEN);
+
+	now = in_be32(&timerp->cnt);
+	while (now != 0)
+		now = in_be32(&timerp->cnt);
+
+	setbits_be32(&timerp->sr, SLT_SR_ST);
+	out_be32(&timerp->cr, 0);
+}
+
+void dtimer_interrupt(void *not_used)
+{
+	slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
+
+	/* check for timer interrupt asserted */
+	if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
+		setbits_be32(&timerp->sr, SLT_SR_ST);
+		timestamp++;
+		return;
+	}
+}
+
+int timer_init(void)
+{
+	slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
+
+	timestamp = 0;
+
+	/* disable timer */
+	out_be32(&timerp->cr, 0);
+	out_be32(&timerp->tcnt, 0);
+	/* clear status */
+	out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
+
+	/* initialize and enable timer interrupt */
+	irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
+
+	/* Interrupt every ms */
+	out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
+
+	dtimer_intr_setup();
+
+	/* set a period of 1us, set timer mode to restart and
+	   enable timer and interrupt */
+	out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
+	return 0;
+}
+
+ulong get_timer(ulong base)
+{
+	return (timestamp - base);
+}
+
+#endif				/* CONFIG_SLTTMR */

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf547x_8x/speed.c

@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+	gd->bus_clk = CONFIG_SYS_CLK;
+	gd->cpu_clk = (gd->bus_clk * 2);
+
+#ifdef CONFIG_SYS_I2C_FSL
+	gd->arch.i2c1_clk = gd->bus_clk;
+#endif
+
+	return (0);
+}

source/bootloader/u-boot-2020.01/arch/m68k/cpu/mcf547x_8x/start.S

@@ -0,0 +1,264 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include "version.h"
+#include <asm/cache.h>
+
+#define _START	_start
+#define _FAULT	_fault
+
+#define SAVE_ALL						\
+	move.w	#0x2700,%sr;		/* disable intrs */	\
+	subl	#60,%sp;		/* space for 15 regs */ \
+	moveml	%d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL						\
+	moveml	%sp@,%d0-%d7/%a0-%a6;				\
+	addl	#60,%sp;		/* space for 15 regs */ \
+	rte;
+
+.text
+
+/*
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
+ */
+_vectors:
+INITSP:	.long	0x00000000		/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC	*/
+
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved */
+vector10_17:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved	*/
+vector30_3F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+.text
+
+.globl _start
+_start:
+	nop
+	nop
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
+
+	/* Set vector base register at the beginning of the Flash */
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	movec	%d0, %VBR
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR0
+
+	move.l	#(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	move.l	#CONFIG_SYS_MBAR, %d0	/* set MBAR address */
+	move.c	%d0, %MBAR
+
+	/* invalidate and disable cache */
+	move.l	#0x01040100, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+
+	/* initialize general use internal ram */
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+
+	/* put relocation table address to a5 */
+	move.l	#__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l	%d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
+
+	/* run low-level CPU init code (from flash) */
+	jbsr	cpu_init_f
+
+	/* run low-level board init code (from flash) */
+	clr.l	%sp@-
+	jbsr	board_init_f
+
+	/* board_init_f() does not return */
+
+/******************************************************************************/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+.globl relocate_code
+relocate_code:
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
+
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
+
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
+
+	/* copy the code to RAM */
+1:
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
+	move.l	%a1,%a5			/* fix got pointer register a5 */
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start,%d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
+	jsr	(%a1)
+
+/******************************************************************************/
+
+/* exception code */
+.globl _fault
+_fault:
+	bra	_fault
+
+.globl _exc_handler
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+.globl _int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr	int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/******************************************************************************/
+
+.globl version_string
+version_string:
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4

source/bootloader/u-boot-2020.01/arch/m68k/cpu/u-boot.lds

@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2015
+ * Angelo Dureghello, Sysam Firmware, angelo@sysam.it
+ */
+
+#include <config.h>
+
+OUTPUT_ARCH(m68k)
+
+#ifndef LDS_BOARD_TEXT
+#define LDS_BOARD_TEXT
+#endif
+
+SECTIONS
+{
+	.text :
+	{
+		CPUDIR/start.o (.text*)
+		LDS_BOARD_TEXT
+
+		*(.text*)
+	}
+	_etext = .;
+	PROVIDE (etext = .);
+	.rodata :
+	{
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	/* Read-write section, merged into data segment: */
+	. = (. + 0x00FF) & 0xFFFFFF00;
+	_erotext = .;
+	PROVIDE (erotext = .);
+
+	.reloc :
+	{
+		__got_start = .;
+		KEEP(*(.got))
+		__got_end = .;
+		_GOT2_TABLE_ = .;
+		KEEP(*(.got2))
+		_FIXUP_TABLE_ = .;
+		KEEP(*(.fixup))
+	}
+	__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+	__fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+	.data :
+	{
+		*(.data*)
+		*(.sdata*)
+	}
+	_edata = .;
+	PROVIDE (edata = .);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = .;
+	__start___ex_table = .;
+	__ex_table : { *(__ex_table) }
+	__stop___ex_table = .;
+
+	. = ALIGN(4);
+	__init_begin = .;
+	.text.init : { *(.text.init) }
+	.data.init : { *(.data.init) }
+	. = ALIGN(4);
+	__init_end = .;
+
+	_end = .;
+
+	__bss_start = .;
+	.bss (NOLOAD)       :
+	{
+		_sbss = .;
+		*(.bss*)
+		*(.sbss*)
+		*(COMMON)
+		. = ALIGN(4);
+		_ebss = .;
+	}
+	__bss_end = . ;
+	PROVIDE (end = .);
+}

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5208EVBE.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5208.dtsi"
+
+/ {
+	model = "Freescale M5208EVBE";
+	compatible = "fsl,M5208EVBE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M52277EVB.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+	model = "Freescale M52277EVB";
+	compatible = "fsl,M52277EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M52277EVB_stmicro.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+	model = "Freescale M52277_stmicro";
+	compatible = "fsl,M52277_stmicro";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5235EVB.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+	model = "Freescale M5235EVB";
+	compatible = "fsl,M5235EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5235EVB_Flash32.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+	model = "Freescale M5235EVB_Flash32";
+	compatible = "fsl,M5235EVB_Flash32";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5249EVB.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5249.dtsi"
+
+/ {
+	model = "Freescale M5249EVB";
+	compatible = "fsl,M5249EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5253DEMO.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5253.dtsi"
+
+/ {
+	model = "Freescale M5253DEMO";
+	compatible = "fsl,M5253DEMO";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5272C3.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+	model = "Freescale M5272C3";
+	compatible = "fsl,M5272C3";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5275EVB.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5275.dtsi"
+
+/ {
+	model = "Freescale M5275EVB";
+	compatible = "fsl,M5275EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5282EVB.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+	model = "Freescale M5282EVB";
+	compatible = "fsl,M5282EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M53017EVB.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5301x.dtsi"
+
+/ {
+	model = "Freescale M53017EVB";
+	compatible = "fsl,M53017EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5329AFEE.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+	model = "Freescale M5329AFEE";
+	compatible = "fsl,M5329AFEE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5329BFEE.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+	model = "Freescale M5329BFEE";
+	compatible = "fsl,M5329BFEE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5373EVB.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+	model = "Freescale M5373EVB";
+	compatible = "fsl,M5373EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54418TWR.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR";
+	compatible = "fsl,M54418TWR";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54418TWR_nand_mii.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_nand_mii";
+	compatible = "fsl,M54418TWR_nand_mii";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54418TWR_nand_rmii.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_nand_rmii";
+	compatible = "fsl,M54418TWR_nand_rmii";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_nand_rmii_lowfreq";
+	compatible = "fsl,M54418TWR_nand_rmii_lowfreq";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54418TWR_serial_mii.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_serial_mii";
+	compatible = "fsl,M54418TWR_serial_mii";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54418TWR_serial_rmii.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+	model = "Freescale M54418TWR_serial_rmii";
+	compatible = "fsl,M54418TWR_serial_rmii";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54451EVB.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54451EVB";
+	compatible = "fsl,M54451EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54451EVB_stmicro.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54451EVB_stmicro";
+	compatible = "fsl,M54451EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54455EVB.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB";
+	compatible = "fsl,M54455EVB";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54455EVB_a66.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB_a66";
+	compatible = "fsl,M54455EVB_a66";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54455EVB_i66.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB_i66";
+	compatible = "fsl,M54455EVB_i66";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54455EVB_intel.dts

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB_intel";
+	compatible = "fsl,M5275EVB_intel";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M54455EVB_stm33.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+	model = "Freescale M54455EVB_stm33";
+	compatible = "fsl,M5275EVB_stm33";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+};

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5475AFE.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475AFE";
+	compatible = "fsl,M5475AFE";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5475BFE.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475BFE";
+	compatible = "fsl,M5475BFE";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5475CFE.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475CFE";
+	compatible = "fsl,M5475CFE";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5475DFE.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475DFE";
+	compatible = "fsl,M5475DFE";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5475EFE.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475EFE";
+	compatible = "fsl,M5475EFE";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5475FFE.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475FFE";
+	compatible = "fsl,M5475FFE";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5475GFE.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5475GFE";
+	compatible = "fsl,M5475GFE";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5485AFE.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485AFE";
+	compatible = "fsl,M5485AFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5485BFE.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485BFE";
+	compatible = "fsl,M5485BFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5485CFE.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485CFE";
+	compatible = "fsl,M5485CFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5485DFE.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485DFE";
+	compatible = "fsl,M5485DFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5485EFE.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485EFE";
+	compatible = "fsl,M5485EFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5485FFE.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485FFE";
+	compatible = "fsl,M5485FFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5485GFE.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485GFE";
+	compatible = "fsl,M5485GFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/M5485HFE.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+	model = "Freescale M5485HFE";
+	compatible = "fsl,M5485HFE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/Makefile

@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \
+	M52277EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \
+	M5235EVB_Flash32.dtb
+dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb
+dtb-$(CONFIG_TARGET_EB_CPU5282) += eb_cpu5282.dtb \
+	eb_cpu5282_internal.dtb
+dtb-$(CONFIG_TARGET_M5208EVBE) += M5208EVBE.dtb
+dtb-$(CONFIG_TARGET_M5249EVB) += M5249EVB.dtb
+dtb-$(CONFIG_TARGET_M5253DEMO) += M5253DEMO.dtb
+dtb-$(CONFIG_TARGET_M5272C3) += M5272C3.dtb
+dtb-$(CONFIG_TARGET_M5275EVB) += M5275EVB.dtb
+dtb-$(CONFIG_TARGET_M5282EVB) += M5282EVB.dtb
+dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb
+dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb
+dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb
+dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb
+dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \
+	M54418TWR_nand_mii.dtb \
+	M54418TWR_nand_rmii.dtb \
+	M54418TWR_serial_mii.dtb \
+	M54418TWR_serial_rmii.dtb \
+	M54418TWR_nand_rmii_lowfreq.dtb
+dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \
+	M54451EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
+	M54455EVB_intel.dtb \
+	M54455EVB_stm33.dtb \
+	M54455EVB_a66.dtb \
+	M54455EVB_i66.dtb
+dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
+dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
+dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
+	M5475BFE.dtb \
+	M5475CFE.dtb \
+	M5475DFE.dtb \
+	M5475EFE.dtb \
+	M5475FFE.dtb \
+	M5475GFE.dtb
+dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \
+	M5485BFE.dtb \
+	M5485CFE.dtb \
+	M5485DFE.dtb \
+	M5485EFE.dtb \
+	M5485FFE.dtb \
+	M5485GFE.dtb \
+	M5485HFE.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb

source/bootloader/u-boot-2020.01/arch/m68k/dts/amcore.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5307.dtsi"
+
+/ {
+	model = "Sysam AMCORE";
+	compatible = "sysam,AMCORE";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/astro_mcf5373l.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+	model = "Astro mcf5373l";
+	compatible = "astro,mcf5373l";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/cobra5272.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+	model = "Cobra 5272";
+	compatible = "cobra,M5272";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/eb_cpu5282.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+	model = "BuS eb_cpuM5282";
+	compatible = "bus,eb_cpuM5282";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+

source/bootloader/u-boot-2020.01/arch/m68k/dts/eb_cpu5282_internal.dts

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+	model = "BuS eb_cpu5282_internals";
+	compatible = "bus,eb_cpu5282_internals";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+