GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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menu "MIPS architecture"
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depends on MIPS
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config SYS_ARCH
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default "mips"
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config SYS_CPU
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default "mips32" if CPU_MIPS32
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default "mips64" if CPU_MIPS64
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choice
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prompt "Target select"
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optional
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config TARGET_QEMU_MIPS
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bool "Support qemu-mips"
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
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select SUPPORTS_LITTLE_ENDIAN
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config TARGET_MALTA
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bool "Support malta"
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select DM
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select DM_SERIAL
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select DYNAMIC_IO_PORT_BASE
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select MIPS_CM
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select MIPS_INSERT_BOOT_CONFIG
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select MIPS_L1_CACHE_SHIFT_6
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select MIPS_L2_CACHE
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select OF_CONTROL
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select OF_ISA_BUS
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_CPU_MIPS32_R6
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
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select SUPPORTS_CPU_MIPS64_R6
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select SUPPORTS_LITTLE_ENDIAN
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select SWAP_IO_SPACE
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imply CMD_DM
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config TARGET_VCT
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bool "Support vct"
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SYS_MIPS_CACHE_INIT_RAM_LOAD
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config ARCH_ATH79
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bool "Support QCA/Atheros ath79"
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select DM
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select OF_CONTROL
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imply CMD_DM
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config ARCH_MSCC
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bool "Support MSCC VCore-III"
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select OF_CONTROL
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select DM
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config ARCH_BMIPS
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bool "Support BMIPS SoCs"
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select CLK
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select CPU
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select DM
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select OF_CONTROL
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select RAM
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select SYSRESET
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imply CMD_DM
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config ARCH_MTMIPS
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bool "Support MediaTek MIPS platforms"
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select CLK
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imply CMD_DM
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select DISPLAY_CPUINFO
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select DM
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imply DM_ETH
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imply DM_GPIO
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select DM_RESET
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select DM_SERIAL
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select PINCTRL
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select PINMUX
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select PINCONF
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select RESET_MTMIPS
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imply DM_SPI
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imply DM_SPI_FLASH
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select LAST_STAGE_INIT
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select MIPS_TUNE_24KC
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select OF_CONTROL
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_LITTLE_ENDIAN
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select SYSRESET
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config ARCH_JZ47XX
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bool "Support Ingenic JZ47xx"
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select SUPPORT_SPL
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select OF_CONTROL
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select DM
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config MACH_PIC32
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bool "Support Microchip PIC32"
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select DM
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select OF_CONTROL
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imply CMD_DM
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config TARGET_BOSTON
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bool "Support Boston"
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select DM
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select DM_SERIAL
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select MIPS_CM
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select MIPS_L1_CACHE_SHIFT_6
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select MIPS_L2_CACHE
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select OF_BOARD_SETUP
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select OF_CONTROL
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_CPU_MIPS32_R6
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
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select SUPPORTS_CPU_MIPS64_R6
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select SUPPORTS_LITTLE_ENDIAN
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imply CMD_DM
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config TARGET_XILFPGA
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bool "Support Imagination Xilfpga"
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_SERIAL
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select MIPS_L1_CACHE_SHIFT_4
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select OF_CONTROL
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_LITTLE_ENDIAN
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imply CMD_DM
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help
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This supports IMGTEC MIPSfpga platform
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endchoice
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source "board/imgtec/boston/Kconfig"
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source "board/imgtec/malta/Kconfig"
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source "board/imgtec/xilfpga/Kconfig"
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source "board/qemu-mips/Kconfig"
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source "arch/mips/mach-ath79/Kconfig"
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source "arch/mips/mach-mscc/Kconfig"
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source "arch/mips/mach-bmips/Kconfig"
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source "arch/mips/mach-jz47xx/Kconfig"
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source "arch/mips/mach-pic32/Kconfig"
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source "arch/mips/mach-mtmips/Kconfig"
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if MIPS
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choice
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prompt "Endianness selection"
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help
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Some MIPS boards can be configured for either little or big endian
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byte order. These modes require different U-Boot images. In general there
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is one preferred byteorder for a particular system but some systems are
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just as commonly used in the one or the other endianness.
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config SYS_BIG_ENDIAN
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bool "Big endian"
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depends on SUPPORTS_BIG_ENDIAN
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config SYS_LITTLE_ENDIAN
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bool "Little endian"
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depends on SUPPORTS_LITTLE_ENDIAN
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endchoice
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choice
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prompt "CPU selection"
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default CPU_MIPS32_R2
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config CPU_MIPS32_R1
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bool "MIPS32 Release 1"
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depends on SUPPORTS_CPU_MIPS32_R1
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select 32BIT
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help
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Choose this option to build an U-Boot for release 1 through 5 of the
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MIPS32 architecture.
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config CPU_MIPS32_R2
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bool "MIPS32 Release 2"
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depends on SUPPORTS_CPU_MIPS32_R2
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select 32BIT
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help
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Choose this option to build an U-Boot for release 2 through 5 of the
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MIPS32 architecture.
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config CPU_MIPS32_R6
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bool "MIPS32 Release 6"
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depends on SUPPORTS_CPU_MIPS32_R6
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select 32BIT
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help
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Choose this option to build an U-Boot for release 6 or later of the
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MIPS32 architecture.
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config CPU_MIPS64_R1
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bool "MIPS64 Release 1"
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depends on SUPPORTS_CPU_MIPS64_R1
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select 64BIT
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help
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Choose this option to build a kernel for release 1 through 5 of the
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MIPS64 architecture.
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config CPU_MIPS64_R2
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bool "MIPS64 Release 2"
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depends on SUPPORTS_CPU_MIPS64_R2
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select 64BIT
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help
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Choose this option to build a kernel for release 2 through 5 of the
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MIPS64 architecture.
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config CPU_MIPS64_R6
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bool "MIPS64 Release 6"
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depends on SUPPORTS_CPU_MIPS64_R6
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select 64BIT
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help
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Choose this option to build a kernel for release 6 or later of the
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MIPS64 architecture.
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endchoice
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menu "General setup"
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config ROM_EXCEPTION_VECTORS
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bool "Build U-Boot image with exception vectors"
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help
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Enable this to include exception vectors in the U-Boot image. This is
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required if the U-Boot entry point is equal to the address of the
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CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
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U-Boot booted from parallel NOR flash).
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Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
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In that case the image size will be reduced by 0x500 bytes.
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config MIPS_CM_BASE
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hex "MIPS CM GCR Base Address"
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depends on MIPS_CM
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default 0x16100000 if TARGET_BOSTON
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default 0x1fbf8000
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help
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The physical base address at which to map the MIPS Coherence Manager
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Global Configuration Registers (GCRs). This should be set such that
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the GCRs occupy a region of the physical address space which is
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otherwise unused, or at minimum that software doesn't need to access.
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config MIPS_CACHE_INDEX_BASE
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hex "Index base address for cache initialisation"
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default 0x80000000 if CPU_MIPS32
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default 0xffffffff80000000 if CPU_MIPS64
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help
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This is the base address for a memory block, which is used for
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initialising the cache lines. This is also the base address of a memory
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block which is used for loading and filling cache lines when
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SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
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Normally this is CKSEG0. If the MIPS system needs to move this block
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to some SRAM or ScratchPad RAM, adapt this option accordingly.
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config MIPS_RELOCATION_TABLE_SIZE
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hex "Relocation table size"
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range 0x100 0x10000
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default "0x8000"
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---help---
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A table of relocation data will be appended to the U-Boot binary
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and parsed in relocate_code() to fix up all offsets in the relocated
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U-Boot.
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This option allows the amount of space reserved for the table to be
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adjusted in a range from 256 up to 64k. The default is 32k and should
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be ok in most cases. Reduce this value to shrink the size of U-Boot
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binary.
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The build will fail and a valid size suggested if this is too small.
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If unsure, leave at the default value.
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endmenu
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menu "OS boot interface"
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config MIPS_BOOT_CMDLINE_LEGACY
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bool "Hand over legacy command line to Linux kernel"
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default y
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help
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Enable this option if you want U-Boot to hand over the Yamon-style
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command line to the kernel. All bootargs will be prepared as argc/argv
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compatible list. The argument count (argc) is stored in register $a0.
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The address of the argument list (argv) is stored in register $a1.
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config MIPS_BOOT_ENV_LEGACY
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bool "Hand over legacy environment to Linux kernel"
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default y
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help
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Enable this option if you want U-Boot to hand over the Yamon-style
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environment to the kernel. Information like memory size, initrd
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address and size will be prepared as zero-terminated key/value list.
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The address of the environment is stored in register $a2.
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config MIPS_BOOT_FDT
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bool "Hand over a flattened device tree to Linux kernel"
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default n
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help
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Enable this option if you want U-Boot to hand over a flattened
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device tree to the kernel. According to UHI register $a0 will be set
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to -2 and the FDT address is stored in $a1.
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endmenu
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config SUPPORTS_BIG_ENDIAN
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bool
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config SUPPORTS_LITTLE_ENDIAN
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bool
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config SUPPORTS_CPU_MIPS32_R1
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bool
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config SUPPORTS_CPU_MIPS32_R2
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bool
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config SUPPORTS_CPU_MIPS32_R6
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bool
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config SUPPORTS_CPU_MIPS64_R1
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bool
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config SUPPORTS_CPU_MIPS64_R2
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bool
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config SUPPORTS_CPU_MIPS64_R6
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bool
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config CPU_MIPS32
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bool
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default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
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config CPU_MIPS64
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bool
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default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
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config MIPS_TUNE_4KC
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bool
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config MIPS_TUNE_14KC
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bool
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config MIPS_TUNE_24KC
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bool
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config MIPS_TUNE_34KC
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bool
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config MIPS_TUNE_74KC
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bool
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config 32BIT
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bool
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config 64BIT
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bool
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config SWAP_IO_SPACE
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bool
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config SYS_MIPS_CACHE_INIT_RAM_LOAD
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bool
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config MIPS_INIT_STACK_IN_SRAM
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bool
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default n
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help
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Select this if the initial stack frame could be setup in SRAM.
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Normally the initial stack frame is set up in DRAM which is often
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only available after lowlevel_init. With this option the initial
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stack frame and the early C environment is set up before
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lowlevel_init. Thus lowlevel_init does not need to be implemented
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in assembler.
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config SYS_DCACHE_SIZE
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int
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default 0
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help
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The total size of the L1 Dcache, if known at compile time.
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config SYS_DCACHE_LINE_SIZE
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int
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default 0
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help
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The size of L1 Dcache lines, if known at compile time.
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config SYS_ICACHE_SIZE
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int
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default 0
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help
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The total size of the L1 ICache, if known at compile time.
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config SYS_ICACHE_LINE_SIZE
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int
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default 0
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help
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The size of L1 Icache lines, if known at compile time.
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config SYS_SCACHE_LINE_SIZE
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int
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default 0
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help
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The size of L2 cache lines, if known at compile time.
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config SYS_CACHE_SIZE_AUTO
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def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
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SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
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SYS_SCACHE_LINE_SIZE = 0
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help
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Select this (or let it be auto-selected by not defining any cache
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sizes) in order to allow U-Boot to automatically detect the sizes
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of caches at runtime. This has a small cost in code size & runtime
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so if you know the cache configuration for your system at compile
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time it would be beneficial to configure it.
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config MIPS_L1_CACHE_SHIFT_4
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bool
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config MIPS_L1_CACHE_SHIFT_5
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bool
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config MIPS_L1_CACHE_SHIFT_6
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bool
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||||
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||||
config MIPS_L1_CACHE_SHIFT_7
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bool
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||||
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config MIPS_L1_CACHE_SHIFT
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int
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default "7" if MIPS_L1_CACHE_SHIFT_7
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default "6" if MIPS_L1_CACHE_SHIFT_6
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default "5" if MIPS_L1_CACHE_SHIFT_5
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default "4" if MIPS_L1_CACHE_SHIFT_4
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||||
default "5"
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config MIPS_L2_CACHE
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bool
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help
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||||
Select this if your system includes an L2 cache and you want U-Boot
|
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to initialise & maintain it.
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||||
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config DYNAMIC_IO_PORT_BASE
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bool
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|
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config MIPS_CM
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bool
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help
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||||
Select this if your system contains a MIPS Coherence Manager and you
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wish U-Boot to configure it or make use of it to retrieve system
|
||||
information such as cache configuration.
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config MIPS_INSERT_BOOT_CONFIG
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bool
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||||
default n
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||||
help
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||||
Enable this to insert some board-specific boot configuration in
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the U-Boot binary at offset 0x10.
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||||
|
||||
config MIPS_BOOT_CONFIG_WORD0
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||||
hex
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||||
depends on MIPS_INSERT_BOOT_CONFIG
|
||||
default 0x420 if TARGET_MALTA
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default 0x0
|
||||
help
|
||||
Value which is inserted as boot config word 0.
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||||
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||||
config MIPS_BOOT_CONFIG_WORD1
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hex
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||||
depends on MIPS_INSERT_BOOT_CONFIG
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default 0x0
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||||
help
|
||||
Value which is inserted as boot config word 1.
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||||
|
||||
endif
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||||
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||||
endmenu
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||||
@@ -0,0 +1,44 @@
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# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
head-y := arch/mips/cpu/start.o
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||||
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||||
ifeq ($(CONFIG_SPL_BUILD),y)
|
||||
ifneq ($(CONFIG_SPL_START_S_PATH),)
|
||||
head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
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||||
endif
|
||||
endif
|
||||
|
||||
libs-y += arch/mips/cpu/
|
||||
libs-y += arch/mips/lib/
|
||||
|
||||
machine-$(CONFIG_ARCH_ATH79) += ath79
|
||||
machine-$(CONFIG_ARCH_BMIPS) += bmips
|
||||
machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
|
||||
machine-$(CONFIG_MACH_PIC32) += pic32
|
||||
machine-$(CONFIG_ARCH_MTMIPS) += mtmips
|
||||
machine-$(CONFIG_ARCH_MSCC) += mscc
|
||||
|
||||
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
|
||||
libs-y += $(machdirs)
|
||||
|
||||
PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
|
||||
|
||||
# Optimize for MIPS architectures
|
||||
arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
|
||||
arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
|
||||
arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
|
||||
arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
|
||||
arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
|
||||
arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
|
||||
|
||||
# Allow extra optimization for specific CPUs/SoCs
|
||||
tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
|
||||
tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
|
||||
tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
|
||||
tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
|
||||
tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
|
||||
|
||||
# Include default header files
|
||||
cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
|
||||
|
||||
PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) $(cflags-y)
|
||||
@@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (c) 2017 Imagination Technologies Ltd.
|
||||
|
||||
PHONY := __archpost
|
||||
__archpost:
|
||||
|
||||
-include include/config/auto.conf
|
||||
include scripts/Kbuild.include
|
||||
|
||||
CMD_RELOCS = tools/mips-relocs
|
||||
quiet_cmd_relocs = RELOCS $@
|
||||
cmd_relocs = $(CMD_RELOCS) $@
|
||||
|
||||
u-boot: FORCE
|
||||
@true
|
||||
$(call if_changed,relocs)
|
||||
|
||||
.PHONY: FORCE
|
||||
|
||||
FORCE:
|
||||
@@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
ifdef CONFIG_SYS_BIG_ENDIAN
|
||||
32bit-emul := elf32btsmip
|
||||
64bit-emul := elf64btsmip
|
||||
32bit-bfd := elf32-tradbigmips
|
||||
64bit-bfd := elf64-tradbigmips
|
||||
PLATFORM_CPPFLAGS += -EB
|
||||
PLATFORM_LDFLAGS += -EB
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SYS_LITTLE_ENDIAN
|
||||
32bit-emul := elf32ltsmip
|
||||
64bit-emul := elf64ltsmip
|
||||
32bit-bfd := elf32-tradlittlemips
|
||||
64bit-bfd := elf64-tradlittlemips
|
||||
PLATFORM_CPPFLAGS += -EL
|
||||
PLATFORM_LDFLAGS += -EL
|
||||
endif
|
||||
|
||||
ifdef CONFIG_32BIT
|
||||
PLATFORM_CPPFLAGS += -mabi=32
|
||||
PLATFORM_LDFLAGS += -m $(32bit-emul)
|
||||
OBJCOPYFLAGS += -O $(32bit-bfd)
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000
|
||||
endif
|
||||
|
||||
ifdef CONFIG_64BIT
|
||||
PLATFORM_CPPFLAGS += -mabi=64
|
||||
PLATFORM_LDFLAGS += -m$(64bit-emul)
|
||||
OBJCOPYFLAGS += -O $(64bit-bfd)
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -D__MIPS__
|
||||
PLATFORM_ELFENTRY = "__start"
|
||||
PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS)
|
||||
|
||||
#
|
||||
# From Linux arch/mips/Makefile
|
||||
#
|
||||
# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
|
||||
# code since it only slows down the whole thing. At some point we might make
|
||||
# use of global pointer optimizations but their use of $28 conflicts with
|
||||
# the current pointer optimization.
|
||||
#
|
||||
# The DECStation requires an ECOFF kernel for remote booting, other MIPS
|
||||
# machines may also. Since BFD is incredibly buggy with respect to
|
||||
# crossformat linking we rely on the elf2ecoff tool for format conversion.
|
||||
#
|
||||
# cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
|
||||
# cflags-y += -msoft-float
|
||||
# LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
|
||||
# MODFLAGS += -mlong-calls
|
||||
#
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
OBJCOPYFLAGS += -j .data.reloc -j .dtb.init.rodata
|
||||
LDFLAGS_FINAL += --emit-relocs
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -G 0 -mno-abicalls -fno-pic
|
||||
PLATFORM_CPPFLAGS += -msoft-float
|
||||
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
|
||||
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
|
||||
LDFLAGS_FINAL += --gc-sections
|
||||
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list
|
||||
|
||||
LDFLAGS_STANDALONE += --gc-sections
|
||||
@@ -0,0 +1,9 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
extra-y = start.o
|
||||
|
||||
obj-y += time.o
|
||||
obj-y += interrupts.o
|
||||
obj-y += cpu.o
|
||||
|
||||
obj-$(CONFIG_MIPS_CM) += cm_init.o
|
||||
@@ -0,0 +1,44 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* MIPS Coherence Manager (CM) Initialisation
|
||||
*
|
||||
* Copyright (c) 2016 Imagination Technologies Ltd.
|
||||
*/
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/asm.h>
|
||||
#include <asm/cm.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
LEAF(mips_cm_map)
|
||||
/* Config3 must exist for a CM to be present */
|
||||
mfc0 t0, CP0_CONFIG, 1
|
||||
bgez t0, 2f
|
||||
mfc0 t0, CP0_CONFIG, 2
|
||||
bgez t0, 2f
|
||||
|
||||
/* Check Config3.CMGCR to determine CM presence */
|
||||
mfc0 t0, CP0_CONFIG, 3
|
||||
and t0, t0, MIPS_CONF3_CMGCR
|
||||
beqz t0, 2f
|
||||
|
||||
/* Find the current physical GCR base address */
|
||||
1: MFC0 t0, CP0_CMGCRBASE
|
||||
PTR_SLL t0, t0, 4
|
||||
|
||||
/* If the GCRs are where we want, we're done */
|
||||
PTR_LI t1, CONFIG_MIPS_CM_BASE
|
||||
beq t0, t1, 2f
|
||||
|
||||
/* Move the GCRs to our configured base address */
|
||||
PTR_LI t2, CKSEG1
|
||||
PTR_ADDU t0, t0, t2
|
||||
sw zero, GCR_BASE_UPPER(t0)
|
||||
sw t1, GCR_BASE(t0)
|
||||
|
||||
/* Re-check the GCR base */
|
||||
b 1b
|
||||
|
||||
2: jr ra
|
||||
END(mips_cm_map)
|
||||
@@ -0,0 +1,35 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/reboot.h>
|
||||
|
||||
#ifndef CONFIG_SYSRESET
|
||||
void __weak _machine_restart(void)
|
||||
{
|
||||
fprintf(stderr, "*** reset failed ***\n");
|
||||
|
||||
while (1)
|
||||
/* NOP */;
|
||||
}
|
||||
|
||||
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
_machine_restart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
mips_cache_probe();
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,22 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <irq_func.h>
|
||||
|
||||
int interrupt_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
}
|
||||
|
||||
int disable_interrupts(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,269 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Startup Code for MIPS32 CPU-core
|
||||
*
|
||||
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
|
||||
*/
|
||||
|
||||
#include <asm-offsets.h>
|
||||
#include <config.h>
|
||||
#include <asm/asm.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
#ifndef CONFIG_SYS_INIT_SP_ADDR
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
|
||||
CONFIG_SYS_INIT_SP_OFFSET)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
# define MIPS_RELOC 3
|
||||
# define STATUS_SET 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
# ifdef CONFIG_SYS_LITTLE_ENDIAN
|
||||
# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
|
||||
(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
|
||||
# else
|
||||
# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
|
||||
((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
|
||||
# endif
|
||||
# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
|
||||
# define STATUS_SET ST0_KX
|
||||
#endif
|
||||
|
||||
.set noreorder
|
||||
|
||||
.macro init_wr sel
|
||||
MTC0 zero, CP0_WATCHLO,\sel
|
||||
mtc0 t1, CP0_WATCHHI,\sel
|
||||
mfc0 t0, CP0_WATCHHI,\sel
|
||||
bgez t0, wr_done
|
||||
nop
|
||||
.endm
|
||||
|
||||
.macro uhi_mips_exception
|
||||
move k0, t9 # preserve t9 in k0
|
||||
move k1, a0 # preserve a0 in k1
|
||||
li t9, 15 # UHI exception operation
|
||||
li a0, 0 # Use hard register context
|
||||
sdbbp 1 # Invoke UHI operation
|
||||
.endm
|
||||
|
||||
.macro setup_stack_gd
|
||||
li t0, -16
|
||||
PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
|
||||
and sp, t1, t0 # force 16 byte alignment
|
||||
PTR_SUBU \
|
||||
sp, sp, GD_SIZE # reserve space for gd
|
||||
and sp, sp, t0 # force 16 byte alignment
|
||||
move k0, sp # save gd pointer
|
||||
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
|
||||
li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
|
||||
PTR_SUBU \
|
||||
sp, sp, t2 # reserve space for early malloc
|
||||
and sp, sp, t0 # force 16 byte alignment
|
||||
#endif
|
||||
move fp, sp
|
||||
|
||||
/* Clear gd */
|
||||
move t0, k0
|
||||
1:
|
||||
PTR_S zero, 0(t0)
|
||||
blt t0, t1, 1b
|
||||
PTR_ADDIU t0, PTRSIZE
|
||||
|
||||
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
|
||||
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
|
||||
#endif
|
||||
.endm
|
||||
|
||||
ENTRY(_start)
|
||||
/* U-Boot entry point */
|
||||
b reset
|
||||
mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
|
||||
|
||||
#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
|
||||
/*
|
||||
* Store some board-specific boot configuration. This is used by some
|
||||
* MIPS systems like Malta.
|
||||
*/
|
||||
.org 0x10
|
||||
.word CONFIG_MIPS_BOOT_CONFIG_WORD0
|
||||
.word CONFIG_MIPS_BOOT_CONFIG_WORD1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
|
||||
/*
|
||||
* Exception vector entry points. When running from ROM, an exception
|
||||
* cannot be handled. Halt execution and transfer control to debugger,
|
||||
* if one is attached.
|
||||
*/
|
||||
.org 0x200
|
||||
/* TLB refill, 32 bit task */
|
||||
uhi_mips_exception
|
||||
|
||||
.org 0x280
|
||||
/* XTLB refill, 64 bit task */
|
||||
uhi_mips_exception
|
||||
|
||||
.org 0x300
|
||||
/* Cache error exception */
|
||||
uhi_mips_exception
|
||||
|
||||
.org 0x380
|
||||
/* General exception */
|
||||
uhi_mips_exception
|
||||
|
||||
.org 0x400
|
||||
/* Catch interrupt exceptions */
|
||||
uhi_mips_exception
|
||||
|
||||
.org 0x480
|
||||
/* EJTAG debug exception */
|
||||
1: b 1b
|
||||
nop
|
||||
|
||||
.org 0x500
|
||||
#endif
|
||||
|
||||
reset:
|
||||
#if __mips_isa_rev >= 6
|
||||
mfc0 t0, CP0_CONFIG, 5
|
||||
and t0, t0, MIPS_CONF5_VP
|
||||
beqz t0, 1f
|
||||
nop
|
||||
|
||||
b 2f
|
||||
mfc0 t0, CP0_GLOBALNUMBER
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_BMIPS
|
||||
1: mfc0 t0, CP0_DIAGNOSTIC, 3
|
||||
and t0, t0, (1 << 31)
|
||||
#else
|
||||
1: mfc0 t0, CP0_EBASE
|
||||
and t0, t0, EBASE_CPUNUM
|
||||
#endif
|
||||
|
||||
/* Hang if this isn't the first CPU in the system */
|
||||
2: beqz t0, 4f
|
||||
nop
|
||||
3: wait
|
||||
b 3b
|
||||
nop
|
||||
|
||||
/* Init CP0 Status */
|
||||
4: mfc0 t0, CP0_STATUS
|
||||
and t0, ST0_IMPL
|
||||
or t0, ST0_BEV | ST0_ERL | STATUS_SET
|
||||
mtc0 t0, CP0_STATUS
|
||||
|
||||
/*
|
||||
* Check whether CP0 Config1 is implemented. If not continue
|
||||
* with legacy Watch register initialization.
|
||||
*/
|
||||
mfc0 t0, CP0_CONFIG
|
||||
bgez t0, wr_legacy
|
||||
nop
|
||||
|
||||
/*
|
||||
* Check WR bit in CP0 Config1 to determine if Watch registers
|
||||
* are implemented.
|
||||
*/
|
||||
mfc0 t0, CP0_CONFIG, 1
|
||||
andi t0, (1 << 3)
|
||||
beqz t0, wr_done
|
||||
nop
|
||||
|
||||
/* Clear Watch Status bits and disable watch exceptions */
|
||||
li t1, 0x7 # Clear I, R and W conditions
|
||||
init_wr 0
|
||||
init_wr 1
|
||||
init_wr 2
|
||||
init_wr 3
|
||||
init_wr 4
|
||||
init_wr 5
|
||||
init_wr 6
|
||||
init_wr 7
|
||||
b wr_done
|
||||
nop
|
||||
|
||||
wr_legacy:
|
||||
MTC0 zero, CP0_WATCHLO
|
||||
mtc0 zero, CP0_WATCHHI
|
||||
|
||||
wr_done:
|
||||
/* Clear WP, IV and SW interrupts */
|
||||
mtc0 zero, CP0_CAUSE
|
||||
|
||||
/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
|
||||
mtc0 zero, CP0_COMPARE
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
mfc0 t0, CP0_CONFIG
|
||||
and t0, t0, MIPS_CONF_IMPL
|
||||
or t0, t0, CONF_CM_UNCACHED
|
||||
mtc0 t0, CP0_CONFIG
|
||||
ehb
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_CM
|
||||
PTR_LA t9, mips_cm_map
|
||||
jalr t9
|
||||
nop
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
|
||||
/* Set up initial stack and global data */
|
||||
setup_stack_gd
|
||||
|
||||
# ifdef CONFIG_DEBUG_UART
|
||||
/* Earliest point to set up debug uart */
|
||||
PTR_LA t9, debug_uart_init
|
||||
jalr t9
|
||||
nop
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
/* Initialize any external memory */
|
||||
PTR_LA t9, lowlevel_init
|
||||
jalr t9
|
||||
nop
|
||||
# endif
|
||||
|
||||
/* Initialize caches... */
|
||||
PTR_LA t9, mips_cache_reset
|
||||
jalr t9
|
||||
nop
|
||||
|
||||
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
/* Initialize any external memory */
|
||||
PTR_LA t9, lowlevel_init
|
||||
jalr t9
|
||||
nop
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
|
||||
/* Set up initial stack and global data */
|
||||
setup_stack_gd
|
||||
|
||||
# ifdef CONFIG_DEBUG_UART
|
||||
/* Earliest point to set up debug uart */
|
||||
PTR_LA t9, debug_uart_init
|
||||
jalr t9
|
||||
nop
|
||||
# endif
|
||||
#endif
|
||||
|
||||
move a0, zero # a0 <-- boot_flags = 0
|
||||
PTR_LA t9, board_init_f
|
||||
|
||||
jr t9
|
||||
move ra, zero
|
||||
|
||||
END(_start)
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
unsigned long notrace timer_read_counter(void)
|
||||
{
|
||||
return read_c0_count();
|
||||
}
|
||||
|
||||
ulong notrace get_tbclk(void)
|
||||
{
|
||||
return CONFIG_SYS_MIPS_TIMER_FREQ;
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, \
|
||||
LENGTH = IMAGE_MAX_SIZE }
|
||||
MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
|
||||
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text : {
|
||||
*(.text*)
|
||||
} > .spl_mem
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : {
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
} > .spl_mem
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : {
|
||||
*(SORT_BY_ALIGNMENT(.data*))
|
||||
*(SORT_BY_ALIGNMENT(.sdata*))
|
||||
} > .spl_mem
|
||||
|
||||
#ifdef CONFIG_SPL_DM
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
} > .spl_mem
|
||||
#endif
|
||||
|
||||
. = ALIGN(4);
|
||||
__image_copy_end = .;
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
__bss_start = .;
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} > .bss_mem
|
||||
|
||||
/* These mark the ABI of U-Boot for debuggers. */
|
||||
.mdebug.abi32 : {
|
||||
KEEP(*(.mdebug.abi32))
|
||||
}
|
||||
.mdebug.abi64 : {
|
||||
KEEP(*(.mdebug.abi64))
|
||||
}
|
||||
|
||||
/* This is the MIPS specific mdebug section. */
|
||||
.mdebug : { *(.mdebug) }
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/*
|
||||
* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to
|
||||
* the beginning of the section so we begin them at 0.
|
||||
*/
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : {
|
||||
*(.debug_info
|
||||
.gnu.linkonce.wi.*)
|
||||
}
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
||||
/* DWARF 3 */
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
/* GNU DWARF 2 extensions */
|
||||
.debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
|
||||
.debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
|
||||
/* DWARF 4 */
|
||||
.debug_types 0 : { *(.debug_types) }
|
||||
/* DWARF 5 */
|
||||
.debug_macro 0 : { *(.debug_macro) }
|
||||
.debug_addr 0 : { *(.debug_addr) }
|
||||
|
||||
/DISCARD/ : {
|
||||
/* ABI crap starts here */
|
||||
*(.MIPS.abiflags)
|
||||
*(.MIPS.options)
|
||||
*(.options)
|
||||
*(.pdr)
|
||||
*(.reginfo)
|
||||
*(.eh_frame)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,142 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk Engineering, <wd@denx.de>
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text : {
|
||||
__text_start = .;
|
||||
*(.text*)
|
||||
__text_end = .;
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : {
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : {
|
||||
*(.data*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : {
|
||||
*(.sdata*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
__image_copy_end = .;
|
||||
__init_end = .;
|
||||
|
||||
.data.reloc : {
|
||||
__rel_start = .;
|
||||
/*
|
||||
* Space for relocation table
|
||||
* This needs to be filled so that the
|
||||
* mips-reloc tool can overwrite the content.
|
||||
* An invalid value is left at the start of the
|
||||
* section to abort relocation if the table
|
||||
* has not been filled in.
|
||||
*/
|
||||
LONG(0xFFFFFFFF);
|
||||
FILL(0);
|
||||
. += CONFIG_MIPS_RELOCATION_TABLE_SIZE - 4;
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = .;
|
||||
|
||||
.bss __rel_start (OVERLAY) : {
|
||||
__bss_start = .;
|
||||
*(.sbss.*)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
}
|
||||
|
||||
/* These mark the ABI of U-Boot for debuggers. */
|
||||
.mdebug.abi32 : {
|
||||
KEEP(*(.mdebug.abi32))
|
||||
}
|
||||
.mdebug.abi64 : {
|
||||
KEEP(*(.mdebug.abi64))
|
||||
}
|
||||
|
||||
/* This is the MIPS specific mdebug section. */
|
||||
.mdebug : { *(.mdebug) }
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/*
|
||||
* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to
|
||||
* the beginning of the section so we begin them at 0.
|
||||
*/
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : {
|
||||
*(.debug_info
|
||||
.gnu.linkonce.wi.*)
|
||||
}
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
||||
/* DWARF 3 */
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
/* GNU DWARF 2 extensions */
|
||||
.debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
|
||||
.debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
|
||||
/* DWARF 4 */
|
||||
.debug_types 0 : { *(.debug_types) }
|
||||
/* DWARF 5 */
|
||||
.debug_macro 0 : { *(.debug_macro) }
|
||||
.debug_addr 0 : { *(.debug_addr) }
|
||||
|
||||
/DISCARD/ : {
|
||||
/* ABI crap starts here */
|
||||
*(.MIPS.abiflags)
|
||||
*(.MIPS.options)
|
||||
*(.options)
|
||||
*(.pdr)
|
||||
*(.reginfo)
|
||||
*(.eh_frame)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,41 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
dtb-$(CONFIG_ARCH_MTMIPS) += \
|
||||
gardena-smart-gateway-mt7688.dtb \
|
||||
linkit-smart-7688.dtb
|
||||
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
|
||||
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
|
||||
dtb-$(CONFIG_TARGET_AP152) += ap152.dtb
|
||||
dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
|
||||
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
|
||||
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
|
||||
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
|
||||
dtb-$(CONFIG_BOARD_BROADCOM_BCM968380GERG) += brcm,bcm968380gerg.dtb
|
||||
dtb-$(CONFIG_BOARD_COMTREND_AR5315U) += comtrend,ar-5315u.dtb
|
||||
dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
|
||||
dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
|
||||
dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
|
||||
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
|
||||
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
|
||||
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
|
||||
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
|
||||
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
|
||||
dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb
|
||||
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
|
||||
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
|
||||
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
|
||||
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
|
||||
dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
|
||||
dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb
|
||||
dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb
|
||||
|
||||
targets += $(dtb-y)
|
||||
|
||||
# Add any required device tree compiler flags here
|
||||
DTC_FLAGS +=
|
||||
|
||||
PHONY += dtbs
|
||||
dtbs: $(addprefix $(obj)/, $(dtb-y))
|
||||
@:
|
||||
|
||||
clean-files := *.dtb
|
||||
@@ -0,0 +1,47 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "ar933x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "AP121 Reference Board";
|
||||
compatible = "qca,ap121", "qca,ar933x";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&xtal {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
spi-max-frequency = <25000000>;
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
memory-map = <0x9f000000 0x00800000>;
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,47 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "qca953x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "AP143 Reference Board";
|
||||
compatible = "qca,ap143", "qca,qca953x";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&xtal {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
spi-max-frequency = <25000000>;
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
memory-map = <0x9f000000 0x00800000>;
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
@@ -0,0 +1,48 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Rosy Song <rosysong@rosinson.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "qca956x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "AP152 Reference Board";
|
||||
compatible = "qca,ap152", "qca,qca956x";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xtal {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <25000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
spi-max-frequency = <25000000>;
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-flash";
|
||||
memory-map = <0x9f000000 0x01000000>;
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,111 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "qca,ar933x";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "mips,mips24Kc";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
xtal: xtal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "xtal";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "qca,ar933x-pinctrl";
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x18040000 0x100>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ehci0: ehci@1b000100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x1b000100 0x100>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: uart@18020000 {
|
||||
compatible = "qca,ar9330-uart";
|
||||
reg = <0x18020000 0x20>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: eth@0x19000000 {
|
||||
compatible = "qca,ag933x-mac";
|
||||
reg = <0x19000000 0x200>;
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rmii";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: eth@0x1a000000 {
|
||||
compatible = "qca,ag933x-mac";
|
||||
reg = <0x1a000000 0x200>;
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@1f000000 {
|
||||
compatible = "qca,ar7100-spi";
|
||||
reg = <0x1f000000 0x10>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,111 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "qca,ar934x";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "mips,mips74Kc";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
xtal: xtal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "xtal";
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ehci0: ehci@1b000100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x1b000100 0x100>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: uart@18020000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x18020000 0x20>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: eth@0x19000000 {
|
||||
compatible = "qca,ag934x-mac";
|
||||
reg = <0x19000000 0x200>;
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: eth@0x1a000000 {
|
||||
compatible = "qca,ag934x-mac";
|
||||
reg = <0x1a000000 0x200>;
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy1: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@1f000000 {
|
||||
compatible = "qca,ar7100-spi";
|
||||
reg = <0x1f000000 0x10>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,170 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm3380-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/bcm3380-reset.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm3380";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
reg = <0x14e00000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_clk0: periph-clk@14e00004 {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0x14e00004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
periph_clk1: periph-clk@14e00008 {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0x14e00008 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
memory-controller@12000000 {
|
||||
compatible = "brcm,bcm6328-mc";
|
||||
reg = <0x12000000 0x1000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_rst0: reset-controller@14e0008c {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0x14e0008c 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
periph_rst1: reset-controller@14e00090 {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0x14e00090 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pll_cntl: syscon@14e00094 {
|
||||
compatible = "syscon";
|
||||
reg = <0x14e00094 0x4>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pll_cntl>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@14e000dc {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0x14e000dc 0xc>;
|
||||
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt>;
|
||||
};
|
||||
|
||||
gpio0: gpio-controller@14e00100 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@14e00104 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <3>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@14e00200 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x14e00200 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@14e00220 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x14e00220 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@14e02000 {
|
||||
compatible = "brcm,bcm6358-spi";
|
||||
reg = <0x14e02000 0x70c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&periph_clk0 BCM3380_CLK0_SPI>;
|
||||
resets = <&periph_rst0 BCM3380_RST0_SPI>;
|
||||
spi-max-frequency = <25000000>;
|
||||
num-cs = <6>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds: led-controller@14e00f00 {
|
||||
compatible = "brcm,bcm6328-leds";
|
||||
reg = <0x14e00f00 0x1c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,224 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm6318-clock.h>
|
||||
#include <dt-bindings/dma/bcm6318-dma.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/power-domain/bcm6318-power-domain.h>
|
||||
#include <dt-bindings/reset/bcm6318-reset.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6318";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
reg = <0x10000000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
hsspi_pll: hsspi-pll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_clk: periph-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0x10000004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ubus_clk: ubus-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0x10000008 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
periph_rst: reset-controller@10000010 {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0x10000010 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@10000068 {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0x10000068 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt>;
|
||||
};
|
||||
|
||||
pll_cntl: syscon@10000074 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000074 0x4>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pll_cntl>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@10000080 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x10000080 0x4>, <0x10000088 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <18>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio-controller@10000084 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x10000084 0x4>, <0x1000008c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@10000100 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000100 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds: led-controller@10000200 {
|
||||
compatible = "brcm,bcm6328-leds";
|
||||
reg = <0x10000200 0x28>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
periph_pwr: power-controller@100008e8 {
|
||||
compatible = "brcm,bcm6328-power-domain";
|
||||
reg = <0x100008e8 0x4>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
spi: spi@10003000 {
|
||||
compatible = "brcm,bcm6328-hsspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10003000 0x600>;
|
||||
clocks = <&periph_clk BCM6318_CLK_HSSPI>, <&hsspi_pll>;
|
||||
clock-names = "hsspi", "pll";
|
||||
resets = <&periph_rst BCM6318_RST_SPI>;
|
||||
spi-max-frequency = <33333334>;
|
||||
num-cs = <3>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@10004000 {
|
||||
compatible = "brcm,bcm6318-mc";
|
||||
reg = <0x10004000 0x38>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
ehci: usb-controller@10005000 {
|
||||
compatible = "brcm,bcm6318-ehci", "generic-ehci";
|
||||
reg = <0x10005000 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: usb-controller@10005100 {
|
||||
compatible = "brcm,bcm6318-ohci", "generic-ohci";
|
||||
reg = <0x10005100 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb-phy@10005200 {
|
||||
compatible = "brcm,bcm6318-usbh";
|
||||
reg = <0x10005200 0x30>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&periph_clk BCM6318_CLK_USB>;
|
||||
clock-names = "usbh";
|
||||
power-domains = <&periph_pwr BCM6318_PWR_USB>;
|
||||
resets = <&periph_rst BCM6318_RST_USBH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet: ethernet@10080000 {
|
||||
compatible = "brcm,bcm6368-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10080000 0x8000>;
|
||||
clocks = <&periph_clk BCM6318_CLK_ROBOSW250>,
|
||||
<&periph_clk BCM6318_CLK_ROBOSW025>,
|
||||
<&ubus_clk BCM6318_UCLK_ROBOSW>;
|
||||
resets = <&periph_rst BCM6318_RST_ENETSW>,
|
||||
<&periph_rst BCM6318_RST_EPHY>;
|
||||
dmas = <&iudma BCM6318_DMA_ENETSW_RX>,
|
||||
<&iudma BCM6318_DMA_ENETSW_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
brcm,num-ports = <5>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iudma: dma-controller@10088000 {
|
||||
compatible = "brcm,bcm6368-iudma";
|
||||
reg = <0x10088000 0x80>,
|
||||
<0x10088200 0x80>,
|
||||
<0x10088400 0x80>;
|
||||
reg-names = "dma",
|
||||
"dma-channels",
|
||||
"dma-sram";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,277 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm63268-clock.h>
|
||||
#include <dt-bindings/dma/bcm63268-dma.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/power-domain/bcm63268-power-domain.h>
|
||||
#include <dt-bindings/reset/bcm63268-reset.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm63268";
|
||||
|
||||
aliases {
|
||||
spi0 = &lsspi;
|
||||
spi1 = &hsspi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
reg = <0x10000000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
hsspi_pll: hsspi-pll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <400000000>;
|
||||
};
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_clk: periph-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0x10000004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
timer_clk: timer-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0x100000ac 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
pll_cntl: syscon@10000008 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000008 0x4>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pll_cntl>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
periph_rst: reset-controller@10000010 {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0x10000010 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@1000009c {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0x1000009c 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt>;
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@100000c0 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <20>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio-controller@100000c4 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@10000180 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000180 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@100001a0 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x100001a0 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand-controller@10000200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "brcm,nand-bcm6368",
|
||||
"brcm,brcmnand-v4.0",
|
||||
"brcm,brcmnand";
|
||||
reg-names = "nand",
|
||||
"nand-cache",
|
||||
"nand-int-base";
|
||||
reg = <0x10000200 0x180>,
|
||||
<0x10000600 0x200>,
|
||||
<0x100000b0 0x10>;
|
||||
clocks = <&periph_clk BCM63268_CLK_NAND>;
|
||||
clock-names = "nand";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
periph_pwr: power-controller@1000184c {
|
||||
compatible = "brcm,bcm6328-power-domain";
|
||||
reg = <0x1000184c 0x4>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
lsspi: spi@10000800 {
|
||||
compatible = "brcm,bcm6358-spi";
|
||||
reg = <0x10000800 0x70c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&periph_clk BCM63268_CLK_SPI>;
|
||||
resets = <&periph_rst BCM63268_RST_SPI>;
|
||||
spi-max-frequency = <20000000>;
|
||||
num-cs = <8>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsspi: spi@10001000 {
|
||||
compatible = "brcm,bcm6328-hsspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10001000 0x600>;
|
||||
clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
|
||||
clock-names = "hsspi", "pll";
|
||||
resets = <&periph_rst BCM63268_RST_SPI>;
|
||||
spi-max-frequency = <50000000>;
|
||||
num-cs = <8>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds: led-controller@10001900 {
|
||||
compatible = "brcm,bcm6328-leds";
|
||||
reg = <0x10001900 0x24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci: usb-controller@10002500 {
|
||||
compatible = "brcm,bcm63268-ehci", "generic-ehci";
|
||||
reg = <0x10002500 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: usb-controller@10002600 {
|
||||
compatible = "brcm,bcm63268-ohci", "generic-ohci";
|
||||
reg = <0x10002600 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb-phy@10002700 {
|
||||
compatible = "brcm,bcm63268-usbh";
|
||||
reg = <0x10002700 0x38>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>;
|
||||
clock-names = "usbh", "usb_ref";
|
||||
power-domains = <&periph_pwr BCM63268_PWR_USBH>;
|
||||
resets = <&periph_rst BCM63268_RST_USBH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@10003000 {
|
||||
compatible = "brcm,bcm6328-mc";
|
||||
reg = <0x10003000 0x894>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
iudma: dma-controller@1000d800 {
|
||||
compatible = "brcm,bcm6368-iudma";
|
||||
reg = <0x1000d800 0x80>,
|
||||
<0x1000da00 0x80>,
|
||||
<0x1000dc00 0x80>;
|
||||
reg-names = "dma",
|
||||
"dma-channels",
|
||||
"dma-sram";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
enet: ethernet@10700000 {
|
||||
compatible = "brcm,bcm6368-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10700000 0x10000>;
|
||||
clocks = <&periph_clk BCM63268_CLK_GMAC>,
|
||||
<&periph_clk BCM63268_CLK_ROBOSW>,
|
||||
<&periph_clk BCM63268_CLK_ROBOSW250>,
|
||||
<&timer_clk BCM63268_TCLK_EPHY1>,
|
||||
<&timer_clk BCM63268_TCLK_EPHY2>,
|
||||
<&timer_clk BCM63268_TCLK_EPHY3>,
|
||||
<&timer_clk BCM63268_TCLK_GPHY>;
|
||||
resets = <&periph_rst BCM63268_RST_ENETSW>,
|
||||
<&periph_rst BCM63268_RST_EPHY>,
|
||||
<&periph_rst BCM63268_RST_GPHY>;
|
||||
dmas = <&iudma BCM63268_DMA_ENETSW_RX>,
|
||||
<&iudma BCM63268_DMA_ENETSW_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
brcm,rgmii-override;
|
||||
brcm,rgmii-timing;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,237 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm6328-clock.h>
|
||||
#include <dt-bindings/dma/bcm6328-dma.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/power-domain/bcm6328-power-domain.h>
|
||||
#include <dt-bindings/reset/bcm6328-reset.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6328";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
reg = <0x10000000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
hsspi_pll: hsspi-pll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133333333>;
|
||||
};
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_clk: periph-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0x10000004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
periph_rst: reset-controller@10000010 {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0x10000010 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pll_cntl: syscon@10000068 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000068 0x4>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pll_cntl>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@1000005c {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0x1000005c 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@10000084 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x10000084 0x4>, <0x1000008c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@10000100 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000100 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10000120 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000120 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand-controller@10000200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "brcm,nand-bcm6368",
|
||||
"brcm,brcmnand-v2.2",
|
||||
"brcm,brcmnand";
|
||||
reg-names = "nand",
|
||||
"nand-cache",
|
||||
"nand-int-base";
|
||||
reg = <0x10000200 0x180>,
|
||||
<0x10000400 0x200>,
|
||||
<0x100000b0 0x10>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds: led-controller@10000800 {
|
||||
compatible = "brcm,bcm6328-leds";
|
||||
reg = <0x10000800 0x24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@10001000 {
|
||||
compatible = "brcm,bcm6328-hsspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10001000 0x600>;
|
||||
clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>;
|
||||
clock-names = "hsspi", "pll";
|
||||
resets = <&periph_rst BCM6328_RST_SPI>;
|
||||
spi-max-frequency = <33333334>;
|
||||
num-cs = <3>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
periph_pwr: power-controller@10001848 {
|
||||
compatible = "brcm,bcm6328-power-domain";
|
||||
reg = <0x10001848 0x4>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
ehci: usb-controller@10002500 {
|
||||
compatible = "brcm,bcm6328-ehci", "generic-ehci";
|
||||
reg = <0x10002500 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: usb-controller@10002600 {
|
||||
compatible = "brcm,bcm6328-ohci", "generic-ohci";
|
||||
reg = <0x10002600 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb-phy@10002700 {
|
||||
compatible = "brcm,bcm6328-usbh";
|
||||
reg = <0x10002700 0x38>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&periph_clk BCM6328_CLK_USBH>;
|
||||
clock-names = "usbh";
|
||||
power-domains = <&periph_pwr BCM6328_PWR_USBH>;
|
||||
resets = <&periph_rst BCM6328_RST_USBH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@10003000 {
|
||||
compatible = "brcm,bcm6328-mc";
|
||||
reg = <0x10003000 0x864>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
iudma: dma-controller@1000d800 {
|
||||
compatible = "brcm,bcm6368-iudma";
|
||||
reg = <0x1000d800 0x80>,
|
||||
<0x1000da00 0x80>,
|
||||
<0x1000dc00 0x80>;
|
||||
reg-names = "dma",
|
||||
"dma-channels",
|
||||
"dma-sram";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
enet: ethernet@10e00000 {
|
||||
compatible = "brcm,bcm6368-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10e00000 0x10000>;
|
||||
clocks = <&periph_clk BCM6328_CLK_ROBOSW>;
|
||||
resets = <&periph_rst BCM6328_RST_ENETSW>,
|
||||
<&periph_rst BCM6328_RST_EPHY>;
|
||||
dmas = <&iudma BCM6328_DMA_ENETSW_RX>,
|
||||
<&iudma BCM6328_DMA_ENETSW_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
brcm,num-ports = <5>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,163 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm6338-clock.h>
|
||||
#include <dt-bindings/dma/bcm6338-dma.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/bcm6338-reset.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6338";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
reg = <0xfffe0000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_clk: periph-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0xfffe0004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pflash: nor@1fc00000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x1fc00000 0x400000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
pll_cntl: syscon@fffe0008 {
|
||||
compatible = "syscon";
|
||||
reg = <0xfffe0008 0x4>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pll_cntl>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
periph_rst: reset-controller@fffe0028 {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0xfffe0028 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@fffe021c {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0xfffe021c 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt>;
|
||||
};
|
||||
|
||||
uart0: serial@fffe0300 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0xfffe0300 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio: gpio-controller@fffe0404 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <8>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@fffe0c00 {
|
||||
compatible = "brcm,bcm6348-spi";
|
||||
reg = <0xfffe0c00 0xc0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&periph_clk BCM6338_CLK_SPI>;
|
||||
resets = <&periph_rst BCM6338_RST_SPI>;
|
||||
spi-max-frequency = <20000000>;
|
||||
num-cs = <4>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@fffe3100 {
|
||||
compatible = "brcm,bcm6338-mc";
|
||||
reg = <0xfffe3100 0x38>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
iudma: dma-controller@fffe2400 {
|
||||
compatible = "brcm,bcm6348-iudma";
|
||||
reg = <0xfffe2400 0x1c>,
|
||||
<0xfffe2500 0x60>,
|
||||
<0xfffe2600 0x60>;
|
||||
reg-names = "dma",
|
||||
"dma-channels",
|
||||
"dma-sram";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <6>;
|
||||
resets = <&periph_rst BCM6338_RST_DMAMEM>;
|
||||
};
|
||||
|
||||
enet: ethernet@fffe2800 {
|
||||
compatible = "brcm,bcm6348-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xfffe2800 0x2dc>;
|
||||
clocks = <&periph_clk BCM6338_CLK_ENET>;
|
||||
resets = <&periph_rst BCM6338_RST_ENET>;
|
||||
dmas = <&iudma BCM6338_DMA_ENET_RX>,
|
||||
<&iudma BCM6338_DMA_ENET_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,205 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm6348-clock.h>
|
||||
#include <dt-bindings/dma/bcm6348-dma.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/bcm6348-reset.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6348";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
reg = <0xfffe0000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_clk: periph-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0xfffe0004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pflash: nor@1fc00000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x1fc00000 0x2000000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
pll_cntl: syscon@fffe0008 {
|
||||
compatible = "syscon";
|
||||
reg = <0xfffe0008 0x4>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pll_cntl>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
periph_rst: reset-controller@fffe0028 {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0xfffe0028 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@fffe021c {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0xfffe021c 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt>;
|
||||
};
|
||||
|
||||
uart0: serial@fffe0300 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0xfffe0300 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@fffe0400 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <5>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio-controller@fffe0404 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@fffe0c00 {
|
||||
compatible = "brcm,bcm6348-spi";
|
||||
reg = <0xfffe0c00 0xc0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&periph_clk BCM6348_CLK_SPI>;
|
||||
resets = <&periph_rst BCM6348_RST_SPI>;
|
||||
spi-max-frequency = <20000000>;
|
||||
num-cs = <4>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: usb-controller@fffe1b00 {
|
||||
compatible = "brcm,bcm6348-ohci", "generic-ohci";
|
||||
reg = <0xfffe1b00 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb-phy@fffe1c00 {
|
||||
compatible = "brcm,bcm6348-usbh";
|
||||
reg = <0xfffe1c00 0x4>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&periph_clk BCM6348_CLK_USBH>;
|
||||
clock-names = "usbh";
|
||||
resets = <&periph_rst BCM6348_RST_USBH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@fffe2300 {
|
||||
compatible = "brcm,bcm6338-mc";
|
||||
reg = <0xfffe2300 0x38>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
enet0: ethernet@fffe6000 {
|
||||
compatible = "brcm,bcm6348-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xfffe6000 0x2dc>;
|
||||
dmas = <&iudma BCM6348_DMA_ENET0_RX>,
|
||||
<&iudma BCM6348_DMA_ENET0_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet1: ethernet@fffe6800 {
|
||||
compatible = "brcm,bcm6348-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xfffe6800 0x2dc>;
|
||||
dmas = <&iudma BCM6348_DMA_ENET1_RX>,
|
||||
<&iudma BCM6348_DMA_ENET1_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iudma: dma-controller@fffe7000 {
|
||||
compatible = "brcm,bcm6348-iudma";
|
||||
reg = <0xfffe7000 0x1c>,
|
||||
<0xfffe7100 0x40>,
|
||||
<0xfffe7200 0x40>;
|
||||
reg-names = "dma",
|
||||
"dma-channels",
|
||||
"dma-sram";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <4>;
|
||||
clocks = <&periph_clk BCM6348_CLK_ENET>;
|
||||
resets = <&periph_rst BCM6348_RST_ENET>,
|
||||
<&periph_rst BCM6348_RST_DMAMEM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,240 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm6358-clock.h>
|
||||
#include <dt-bindings/dma/bcm6358-dma.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/bcm6358-reset.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6358";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
reg = <0xfffe0000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_clk: periph-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0xfffe0004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pflash: nor@1e000000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x1e000000 0x2000000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
pll_cntl: syscon@fffe0008 {
|
||||
compatible = "syscon";
|
||||
reg = <0xfffe0008 0x4>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pll_cntl>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
periph_rst: reset-controller@fffe0034 {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0xfffe0034 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@fffe005c {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0xfffe005c 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt>;
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@fffe0080 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <8>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio-controller@fffe0084 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds: led-controller@fffe00d0 {
|
||||
compatible = "brcm,bcm6358-leds";
|
||||
reg = <0xfffe00d0 0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@fffe0100 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0xfffe0100 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@fffe0120 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0xfffe0120 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@fffe0800 {
|
||||
compatible = "brcm,bcm6358-spi";
|
||||
reg = <0xfffe0800 0x70c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&periph_clk BCM6358_CLK_SPI>;
|
||||
resets = <&periph_rst BCM6358_RST_SPI>;
|
||||
spi-max-frequency = <20000000>;
|
||||
num-cs = <4>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@fffe1200 {
|
||||
compatible = "brcm,bcm6358-mc";
|
||||
reg = <0xfffe1200 0x4c>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
ehci: usb-controller@fffe1300 {
|
||||
compatible = "brcm,bcm6358-ehci", "generic-ehci";
|
||||
reg = <0xfffe1300 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: usb-controller@fffe1400 {
|
||||
compatible = "brcm,bcm6358-ohci", "generic-ohci";
|
||||
reg = <0xfffe1400 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb-phy@fffe1500 {
|
||||
compatible = "brcm,bcm6358-usbh";
|
||||
reg = <0xfffe1500 0x28>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&periph_rst BCM6358_RST_USBH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@fffe4000 {
|
||||
compatible = "brcm,bcm6348-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xfffe4000 0x2dc>;
|
||||
clocks = <&periph_clk BCM6358_CLK_ENET0>;
|
||||
dmas = <&iudma BCM6358_DMA_ENET0_RX>,
|
||||
<&iudma BCM6358_DMA_ENET0_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet1: ethernet@fffe4800 {
|
||||
compatible = "brcm,bcm6348-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xfffe4800 0x2dc>;
|
||||
clocks = <&periph_clk BCM6358_CLK_ENET1>;
|
||||
dmas = <&iudma BCM6358_DMA_ENET1_RX>,
|
||||
<&iudma BCM6358_DMA_ENET1_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iudma: dma-controller@fffe5000 {
|
||||
compatible = "brcm,bcm6348-iudma";
|
||||
reg = <0xfffe5000 0x24>,
|
||||
<0xfffe5100 0x80>,
|
||||
<0xfffe5200 0x80>;
|
||||
reg-names = "dma",
|
||||
"dma-channels",
|
||||
"dma-sram";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
clocks = <&periph_clk BCM6358_CLK_EMUSB>,
|
||||
<&periph_clk BCM6358_CLK_USBSU>,
|
||||
<&periph_clk BCM6358_CLK_EPHY>;
|
||||
resets = <&periph_rst BCM6358_RST_ENET>,
|
||||
<&periph_rst BCM6358_RST_EPHY>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,265 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm6362-clock.h>
|
||||
#include <dt-bindings/dma/bcm6362-dma.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/power-domain/bcm6362-power-domain.h>
|
||||
#include <dt-bindings/reset/bcm6362-reset.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6362";
|
||||
|
||||
aliases {
|
||||
spi0 = &lsspi;
|
||||
spi1 = &hsspi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
reg = <0x10000000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
hsspi_pll: hsspi-pll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133333333>;
|
||||
};
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_clk: periph-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0x10000004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
pll_cntl: syscon@10000008 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000008 0x4>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pll_cntl>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
periph_rst: reset-controller@10000010 {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0x10000010 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@1000005c {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0x1000005c 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt>;
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@10000080 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x10000080 0x4>, <0x10000088 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <16>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio-controller@10000084 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x10000084 0x4>, <0x1000008c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@10000100 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000100 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10000120 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000120 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand-controller@10000200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "brcm,nand-bcm6368",
|
||||
"brcm,brcmnand-v2.2",
|
||||
"brcm,brcmnand";
|
||||
reg-names = "nand",
|
||||
"nand-cache",
|
||||
"nand-int-base";
|
||||
reg = <0x10000200 0x180>,
|
||||
<0x10000600 0x200>,
|
||||
<0x100000b0 0x10>;
|
||||
clocks = <&periph_clk BCM6362_CLK_NAND>;
|
||||
clock-names = "nand";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lsspi: spi@10000800 {
|
||||
compatible = "brcm,bcm6358-spi";
|
||||
reg = <0x10000800 0x70c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&periph_clk BCM6362_CLK_SPI>;
|
||||
resets = <&periph_rst BCM6362_RST_SPI>;
|
||||
spi-max-frequency = <20000000>;
|
||||
num-cs = <8>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsspi: spi@10001000 {
|
||||
compatible = "brcm,bcm6328-hsspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10001000 0x600>;
|
||||
clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>;
|
||||
clock-names = "hsspi", "pll";
|
||||
resets = <&periph_rst BCM6362_RST_SPI>;
|
||||
spi-max-frequency = <50000000>;
|
||||
num-cs = <8>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds: led-controller@10001900 {
|
||||
compatible = "brcm,bcm6328-leds";
|
||||
reg = <0x10001900 0x24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
periph_pwr: power-controller@10001848 {
|
||||
compatible = "brcm,bcm6328-power-domain";
|
||||
reg = <0x10001848 0x4>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
ehci: usb-controller@10002500 {
|
||||
compatible = "brcm,bcm6362-ehci", "generic-ehci";
|
||||
reg = <0x10002500 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: usb-controller@10002600 {
|
||||
compatible = "brcm,bcm6362-ohci", "generic-ohci";
|
||||
reg = <0x10002600 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb-phy@10002700 {
|
||||
compatible = "brcm,bcm6368-usbh";
|
||||
reg = <0x10002700 0x38>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&periph_clk BCM6362_CLK_USBH>;
|
||||
clock-names = "usbh";
|
||||
power-domains = <&periph_pwr BCM6362_PWR_USBH>;
|
||||
resets = <&periph_rst BCM6362_RST_USBH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@10003000 {
|
||||
compatible = "brcm,bcm6328-mc";
|
||||
reg = <0x10003000 0x864>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
iudma: dma-controller@1000d800 {
|
||||
compatible = "brcm,bcm6368-iudma";
|
||||
reg = <0x1000d800 0x80>,
|
||||
<0x1000da00 0x80>,
|
||||
<0x1000dc00 0x80>;
|
||||
reg-names = "dma",
|
||||
"dma-channels",
|
||||
"dma-sram";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
enet: ethernet@10e00000 {
|
||||
compatible = "brcm,bcm6368-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10e00000 0x10000>;
|
||||
clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
|
||||
<&periph_clk BCM6362_CLK_SWPKT_SAR>,
|
||||
<&periph_clk BCM6362_CLK_ROBOSW>;
|
||||
resets = <&periph_rst BCM6362_RST_ENETSW>,
|
||||
<&periph_rst BCM6362_RST_EPHY>;
|
||||
dmas = <&iudma BCM6362_DMA_ENETSW_RX>,
|
||||
<&iudma BCM6362_DMA_ENETSW_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
brcm,num-ports = <6>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,246 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm6368-clock.h>
|
||||
#include <dt-bindings/dma/bcm6368-dma.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/bcm6368-reset.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6368";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
reg = <0x10000000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
periph_clk: periph-clk {
|
||||
compatible = "brcm,bcm6345-clk";
|
||||
reg = <0x10000004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pflash: nor@18000000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x18000000 0x2000000>;
|
||||
bank-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
pll_cntl: syscon@10000008 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000008 0x4>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pll_cntl>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
periph_rst: reset-controller@10000010 {
|
||||
compatible = "brcm,bcm6345-reset";
|
||||
reg = <0x10000010 0x4>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wdt: watchdog@1000005c {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0x1000005c 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt>;
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@10000080 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x10000080 0x4>, <0x10000088 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <6>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio-controller@10000084 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x10000084 0x4>, <0x1000008c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds: led-controller@100000d0 {
|
||||
compatible = "brcm,bcm6358-leds";
|
||||
reg = <0x100000d0 0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@10000100 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000100 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10000120 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000120 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand-controller@10000200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "brcm,nand-bcm6368",
|
||||
"brcm,brcmnand-v2.1",
|
||||
"brcm,brcmnand";
|
||||
reg-names = "nand",
|
||||
"nand-cache",
|
||||
"nand-int-base";
|
||||
reg = <0x10000200 0x180>,
|
||||
<0x10000600 0x200>,
|
||||
<0x100000b0 0x10>;
|
||||
clocks = <&periph_clk BCM6368_CLK_NAND>;
|
||||
clock-names = "nand";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@10000800 {
|
||||
compatible = "brcm,bcm6358-spi";
|
||||
reg = <0x10000800 0x70c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&periph_clk BCM6368_CLK_SPI>;
|
||||
resets = <&periph_rst BCM6368_RST_SPI>;
|
||||
spi-max-frequency = <20000000>;
|
||||
num-cs = <6>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@10001200 {
|
||||
compatible = "brcm,bcm6358-mc";
|
||||
reg = <0x10001200 0x4c>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
ehci: usb-controller@10001500 {
|
||||
compatible = "brcm,bcm6368-ehci", "generic-ehci";
|
||||
reg = <0x10001500 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: usb-controller@10001600 {
|
||||
compatible = "brcm,bcm6368-ohci", "generic-ohci";
|
||||
reg = <0x10001600 0x100>;
|
||||
phys = <&usbh>;
|
||||
big-endian;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb-phy@10001700 {
|
||||
compatible = "brcm,bcm6368-usbh";
|
||||
reg = <0x10001700 0x38>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&periph_clk BCM6368_CLK_USBH>;
|
||||
clock-names = "usbh";
|
||||
resets = <&periph_rst BCM6368_RST_USBH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iudma: dma-controller@10006800 {
|
||||
compatible = "brcm,bcm6368-iudma";
|
||||
reg = <0x10006800 0x80>,
|
||||
<0x10006a00 0x80>,
|
||||
<0x10006c00 0x80>;
|
||||
reg-names = "dma",
|
||||
"dma-channels",
|
||||
"dma-sram";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
enet: ethernet@10f00000 {
|
||||
compatible = "brcm,bcm6368-enet";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10f00000 0x10000>;
|
||||
clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,
|
||||
<&periph_clk BCM6368_CLK_SWPKT_SAR>,
|
||||
<&periph_clk BCM6368_CLK_ROBOSW>;
|
||||
resets = <&periph_rst BCM6368_RST_SWITCH>,
|
||||
<&periph_rst BCM6368_RST_EPHY>;
|
||||
dmas = <&iudma BCM6368_DMA_ENETSW_RX>,
|
||||
<&iudma BCM6368_DMA_ENETSW_TX>;
|
||||
dma-names = "rx",
|
||||
"tx";
|
||||
brcm,num-ports = <6>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,142 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6838";
|
||||
|
||||
cpus {
|
||||
reg = <0x14e00000 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
periph_osc: periph-osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
ubus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
memory: memory-controller@12000000 {
|
||||
compatible = "brcm,bcm6328-mc";
|
||||
reg = <0x12000000 0x1000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
gpio_test_port: syscon@14e00294 {
|
||||
compatible = "syscon";
|
||||
reg = <0x14e00294 0x1c>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "brcm,bcm6838-pinctrl";
|
||||
regmap = <&gpio_test_port>;
|
||||
brcm,pins-count = <74>;
|
||||
brcm,functions-count = <8>;
|
||||
};
|
||||
|
||||
uart0: serial@14e00500 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x14e00500 0x18>;
|
||||
clocks = <&periph_osc>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt0: watchdog@14e002d0 {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0x14e002d0 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt1: watchdog@14e002dc {
|
||||
compatible = "brcm,bcm6345-wdt";
|
||||
reg = <0x14e002dc 0xc>;
|
||||
clocks = <&periph_osc>;
|
||||
};
|
||||
|
||||
wdt-reboot {
|
||||
compatible = "wdt-reboot";
|
||||
wdt = <&wdt0>;
|
||||
};
|
||||
|
||||
leds: led-controller@14e00f00 {
|
||||
compatible = "brcm,bcm6328-leds";
|
||||
reg = <0x14e00f00 0x28>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio_lo: gpio-controller@14e00100 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x14e00100 0x4>, <0x14e0012c 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio_mid0: gpio-controller@14e00104 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x14e00104 0x4>, <0x14e00130 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio_mid1: gpio-controller@14e00108 {
|
||||
compatible = "brcm,bcm6345-gpio";
|
||||
reg = <0x14e00108 0x4>, <0x14e00134 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand-controller@14e02200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "brcm,nand-bcm6838",
|
||||
"brcm,brcmnand-v5.0",
|
||||
"brcm,brcmnand";
|
||||
reg-names = "nand", "nand-int-base", "nand-cache";
|
||||
reg = <0x14e02200 0x180>,
|
||||
<0x14e000f0 0x10>,
|
||||
<0x14e02600 0x180>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm6838.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom bcm68380gerg";
|
||||
compatible = "broadcom,bcm68380gerg", "brcm,bcm6838";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&memory {
|
||||
force-size = <0x10000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&leds {
|
||||
status = "okay";
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
active-low;
|
||||
label = "bcm968380gerg:green:usb";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio_lo {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio_mid0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio_mid1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
nandcs@0 {
|
||||
compatible = "brcm,nandcs";
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
brcm,nand-oob-sector-size = <16>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,122 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "jz4780.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "img,ci20", "ingenic,jz4780";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial4:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x10000000
|
||||
0x30000000 0x30000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ext {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nemc {
|
||||
status = "okay";
|
||||
|
||||
nandc: nand-controller@1 {
|
||||
compatible = "ingenic,jz4780-nand";
|
||||
reg = <1 0 0x1000000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ingenic,bch-controller = <&bch>;
|
||||
|
||||
ingenic,nemc-tAS = <10>;
|
||||
ingenic,nemc-tAH = <5>;
|
||||
ingenic,nemc-tBP = <10>;
|
||||
ingenic,nemc-tAW = <15>;
|
||||
ingenic,nemc-tSTRV = <100>;
|
||||
|
||||
nand@1 {
|
||||
reg = <1>;
|
||||
|
||||
nand-ecc-step-size = <1024>;
|
||||
nand-ecc-strength = <24>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot-spl";
|
||||
reg = <0x0 0x0 0x0 0x800000>;
|
||||
};
|
||||
|
||||
partition@0x800000 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x800000 0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@0xa00000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x0 0xa00000 0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@0xc00000 {
|
||||
label = "boot";
|
||||
reg = <0x0 0xc00000 0x0 0x4000000>;
|
||||
};
|
||||
|
||||
partition@0x8c00000 {
|
||||
label = "system";
|
||||
reg = <0x0 0x4c00000 0x1 0xfb400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&bch {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,128 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm6318.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Comtrend AR-5315u";
|
||||
compatible = "comtrend,ar5315-un", "brcm,bcm6318";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet {
|
||||
status = "okay";
|
||||
|
||||
port@0 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <0>;
|
||||
label = "fe4";
|
||||
brcm,phy-id = <1>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <1>;
|
||||
label = "fe3";
|
||||
brcm,phy-id = <2>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <2>;
|
||||
label = "fe2";
|
||||
brcm,phy-id = <3>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <3>;
|
||||
label = "fe1";
|
||||
brcm,phy-id = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&leds {
|
||||
status = "okay";
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
active-low;
|
||||
label = "AR-5315u:green:wps";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
active-low;
|
||||
label = "AR-5315u:green:power";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
active-low;
|
||||
label = "AR-5315u:green:usb";
|
||||
};
|
||||
|
||||
led@8 {
|
||||
reg = <8>;
|
||||
active-low;
|
||||
label = "AR-5315u:green:inet";
|
||||
};
|
||||
|
||||
led@9 {
|
||||
reg = <9>;
|
||||
active-low;
|
||||
label = "AR-5315u:red:inet";
|
||||
};
|
||||
|
||||
led@10 {
|
||||
reg = <10>;
|
||||
active-low;
|
||||
label = "AR-5315u:green:dsl";
|
||||
};
|
||||
|
||||
led@11 {
|
||||
reg = <11>;
|
||||
active-low;
|
||||
label = "AR-5315u:red:power";
|
||||
};
|
||||
};
|
||||
|
||||
&ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <62500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,112 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm6328.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Comtrend AR-5387un";
|
||||
compatible = "comtrend,ar5387-un", "brcm,bcm6328";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet {
|
||||
status = "okay";
|
||||
|
||||
port@0 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <0>;
|
||||
label = "fe1";
|
||||
brcm,phy-id = <1>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <1>;
|
||||
label = "fe2";
|
||||
brcm,phy-id = <2>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <2>;
|
||||
label = "fe3";
|
||||
brcm,phy-id = <3>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <3>;
|
||||
label = "fe4";
|
||||
brcm,phy-id = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&leds {
|
||||
status = "okay";
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
label = "AR-5387un:red:inet";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
reg = <4>;
|
||||
label = "AR-5387un:red:power";
|
||||
};
|
||||
|
||||
led@7 {
|
||||
reg = <7>;
|
||||
label = "AR-5387un:green:inet";
|
||||
};
|
||||
|
||||
led@8 {
|
||||
reg = <8>;
|
||||
label = "AR-5387un:green:power";
|
||||
};
|
||||
|
||||
led@11 {
|
||||
reg = <11>;
|
||||
active-low;
|
||||
label = "AR-5387un:green:dsl";
|
||||
};
|
||||
};
|
||||
|
||||
&ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <33333334>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,68 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm6348.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Comtrend CT-5361";
|
||||
compatible = "comtrend,ct-5361", "brcm,bcm6348";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power_green {
|
||||
label = "CT-5361:green:power";
|
||||
gpios = <&gpio0 0 1>;
|
||||
};
|
||||
|
||||
alarm_red {
|
||||
label = "CT-5361:red:alarm";
|
||||
gpios = <&gpio0 2 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&enet1 {
|
||||
status = "okay";
|
||||
phy = <&enet1phy>;
|
||||
phy-mode = "mii";
|
||||
|
||||
enet1phy: fixed-link {
|
||||
reg = <1>;
|
||||
speed = <100>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pflash {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,126 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm63268.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Comtrend VR-3032u";
|
||||
compatible = "comtrend,vr-3032u", "brcm,bcm63268";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet {
|
||||
status = "okay";
|
||||
|
||||
port@0 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <0>;
|
||||
label = "fe2";
|
||||
brcm,phy-id = <1>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <1>;
|
||||
label = "fe3";
|
||||
brcm,phy-id = <2>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <2>;
|
||||
label = "fe4";
|
||||
brcm,phy-id = <3>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <3>;
|
||||
label = "fe1";
|
||||
brcm,phy-id = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&leds {
|
||||
status = "okay";
|
||||
brcm,serial-leds;
|
||||
brcm,serial-dat-low;
|
||||
brcm,serial-shift-inv;
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
active-low;
|
||||
label = "VR-3032u:red:inet";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
active-low;
|
||||
label = "VR-3032u:green:dsl";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
reg = <4>;
|
||||
active-low;
|
||||
label = "VR-3032u:green:usb";
|
||||
};
|
||||
|
||||
led@7 {
|
||||
reg = <7>;
|
||||
active-low;
|
||||
label = "VR-3032u:green:wps";
|
||||
};
|
||||
|
||||
led@8 {
|
||||
reg = <8>;
|
||||
active-low;
|
||||
label = "VR-3032u:green:inet";
|
||||
};
|
||||
|
||||
led@20 {
|
||||
reg = <20>;
|
||||
active-low;
|
||||
label = "VR-3032u:green:power";
|
||||
};
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
nandcs@0 {
|
||||
compatible = "brcm,nandcs";
|
||||
reg = <0>;
|
||||
nand-ecc-strength = <15>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-on-flash-bbt;
|
||||
brcm,nand-oob-sector-size = <64>;
|
||||
};
|
||||
};
|
||||
|
||||
&ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,90 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm6368.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Comtrend WAP-5813n";
|
||||
compatible = "comtrend,wap-5813n", "brcm,bcm6368";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
inet_green {
|
||||
label = "WAP-5813n:green:inet";
|
||||
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power_green {
|
||||
label = "WAP-5813n:green:power";
|
||||
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
wps_green {
|
||||
label = "WAP-5813n:green:wps";
|
||||
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power_red {
|
||||
label = "WAP-5813n:red:power";
|
||||
gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
inet_red {
|
||||
label = "WAP-5813n:red:inet";
|
||||
gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet {
|
||||
status = "okay";
|
||||
|
||||
port@4 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <4>;
|
||||
label = "rgmii";
|
||||
brcm,phy-id = <0xff>;
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
bypass-link;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pflash {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,129 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2018 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "mt7628a.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc";
|
||||
model = "GARDENA smart Gateway (MT7688)";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power_blue {
|
||||
label = "smartgw:power:blue";
|
||||
gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
power_green {
|
||||
label = "smartgw:power:green";
|
||||
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
power_red {
|
||||
label = "smartgw:power:red";
|
||||
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
radio_blue {
|
||||
label = "smartgw:radio:blue";
|
||||
gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
radio_green {
|
||||
label = "smartgw:radio:green";
|
||||
gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
radio_red {
|
||||
label = "smartgw:radio:red";
|
||||
gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
internet_blue {
|
||||
label = "smartgw:internet:blue";
|
||||
gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
internet_green {
|
||||
label = "smartgw:internet:green";
|
||||
gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
internet_red {
|
||||
label = "smartgw:internet:red";
|
||||
gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
state_default: pin_state {
|
||||
p0led {
|
||||
groups = "p0led_a";
|
||||
function = "led";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
num-cs = <2>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_dual_pins>;
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
spi-nand@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-nand";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ephy_iot_mode>;
|
||||
mediatek,poll-link-phy = <0>;
|
||||
};
|
||||
@@ -0,0 +1,127 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm6358.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Huawei EchoLife HG556a";
|
||||
compatible = "huawei,hg556a", "brcm,bcm6358";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
message_red {
|
||||
label = "HG556a:red:message";
|
||||
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
hspa_red {
|
||||
label = "HG556a:red:hspa";
|
||||
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
dsl_red {
|
||||
label = "HG556a:red:dsl";
|
||||
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power_red {
|
||||
label = "HG556a:red:power";
|
||||
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
all_red {
|
||||
label = "HG556a:red:all";
|
||||
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan1_green {
|
||||
label = "HG556a:green:lan1";
|
||||
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan1_red {
|
||||
label = "HG556a:red:lan1";
|
||||
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan2_green {
|
||||
label = "HG556a:green:lan2";
|
||||
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan2_red {
|
||||
label = "HG556a:red:lan2";
|
||||
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan3_green {
|
||||
label = "HG556a:green:lan3";
|
||||
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan3_red {
|
||||
label = "HG556a:red:lan3";
|
||||
gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan4_green {
|
||||
label = "HG556a:green:lan4";
|
||||
gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan4_red {
|
||||
label = "HG556a:red:lan4";
|
||||
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet1 {
|
||||
status = "okay";
|
||||
phy = <&enet1phy>;
|
||||
phy-mode = "mii";
|
||||
|
||||
enet1phy: fixed-link {
|
||||
reg = <1>;
|
||||
speed = <100>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pflash {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,222 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/clock/boston-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "img,boston";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "img,mips";
|
||||
reg = <0>;
|
||||
clocks = <&clk_boston BOSTON_CLK_CPU>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller {
|
||||
compatible = "mti,gic";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
|
||||
timer {
|
||||
compatible = "mti,gic-timer";
|
||||
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
||||
clocks = <&clk_boston BOSTON_CLK_CPU>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@10000000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,axi-pcie-host-1.00.a";
|
||||
device_type = "pci";
|
||||
reg = <0x10000000 0x2000000>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ranges = <0x02000000 0 0x40000000
|
||||
0x40000000 0 0x40000000>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pci0_intc 0>,
|
||||
<0 0 0 2 &pci0_intc 1>,
|
||||
<0 0 0 3 &pci0_intc 2>,
|
||||
<0 0 0 4 &pci0_intc 3>;
|
||||
|
||||
pci0_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pci@12000000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,axi-pcie-host-1.00.a";
|
||||
device_type = "pci";
|
||||
reg = <0x12000000 0x2000000>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ranges = <0x02000000 0 0x20000000
|
||||
0x20000000 0 0x20000000>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pci1_intc 0>,
|
||||
<0 0 0 2 &pci1_intc 1>,
|
||||
<0 0 0 3 &pci1_intc 2>,
|
||||
<0 0 0 4 &pci1_intc 3>;
|
||||
|
||||
pci1_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pci@14000000 {
|
||||
compatible = "xlnx,axi-pcie-host-1.00.a";
|
||||
device_type = "pci";
|
||||
reg = <0x14000000 0x2000000>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ranges = <0x02000000 0 0x16000000
|
||||
0x16000000 0 0x100000>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pci2_intc 0>,
|
||||
<0 0 0 2 &pci2_intc 1>,
|
||||
<0 0 0 3 &pci2_intc 2>,
|
||||
<0 0 0 4 &pci2_intc 3>;
|
||||
|
||||
pci2_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
pci2_root@0,0,0 {
|
||||
compatible = "pci10ee,7021";
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
eg20t_bridge@1,0,0 {
|
||||
compatible = "pci8086,8800";
|
||||
reg = <0x00010000 0 0 0 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
eg20t_mac@2,0,1 {
|
||||
compatible = "pci8086,8802";
|
||||
reg = <0x00020100 0 0 0 0>;
|
||||
phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
eg20t_gpio: eg20t_gpio@2,0,2 {
|
||||
compatible = "pci8086,8803";
|
||||
reg = <0x00020200 0 0 0 0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
eg20t_i2c@2,12,2 {
|
||||
compatible = "pci8086,8817";
|
||||
reg = <0x00026200 0 0 0 0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtc@0x68 {
|
||||
compatible = "st,m41t81s";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
plat_regs: system-controller@17ffd000 {
|
||||
compatible = "img,boston-platform-regs", "syscon";
|
||||
reg = <0x17ffd000 0x1000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
clk_boston: clock {
|
||||
compatible = "img,boston-clock";
|
||||
#clock-cells = <1>;
|
||||
regmap = <&plat_regs>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&plat_regs>;
|
||||
offset = <0x10>;
|
||||
mask = <0x10>;
|
||||
};
|
||||
|
||||
uart0: uart@17ffe000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x17ffe000 0x1000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&clk_boston BOSTON_CLK_SYS>;
|
||||
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
lcd: lcd@17fff000 {
|
||||
compatible = "img,boston-lcd";
|
||||
reg = <0x17fff000 0x8>;
|
||||
};
|
||||
|
||||
flash@18000000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x18000000 0x8000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1 @@
|
||||
../../../../include/dt-bindings
|
||||
@@ -0,0 +1,150 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,jr2.dtsi"
|
||||
#include <dt-bindings/mscc/jr2_data.h>
|
||||
|
||||
/ {
|
||||
model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
|
||||
compatible = "mscc,jr2-pcb110", "mscc,jr2";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green {
|
||||
label = "pcb110:green:status";
|
||||
gpios = <&gpio 12 0>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb110:red:status";
|
||||
gpios = <&gpio 13 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <0>; /* CS0 */
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
/* SPIO only use DO, CLK, no inputs */
|
||||
sgpio1_pins: sgpio1-pins {
|
||||
pins = "GPIO_4", "GPIO_5";
|
||||
function = "sg1";
|
||||
};
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
sgpio-ports = <0x00ffffff>;
|
||||
};
|
||||
|
||||
&sgpio1 {
|
||||
status = "okay";
|
||||
sgpio-ports = <0x00ff0000>;
|
||||
};
|
||||
|
||||
&sgpio2 {
|
||||
status = "okay";
|
||||
sgpio-ports = <0x3f00ffff>;
|
||||
gpio-ranges = <&sgpio2 0 0 96>;
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
phy6: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
};
|
||||
phy7: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
|
||||
port0: port@0 {
|
||||
reg = <0>;
|
||||
phy-handle = <&phy0>;
|
||||
phys = <&serdes_hsio 0 SERDES1G(1) PHY_MODE_SGMII>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <1>;
|
||||
phy-handle = <&phy1>;
|
||||
phys = <&serdes_hsio 1 SERDES1G(2) PHY_MODE_SGMII>;
|
||||
};
|
||||
port2: port@2 {
|
||||
reg = <2>;
|
||||
phy-handle = <&phy2>;
|
||||
phys = <&serdes_hsio 2 SERDES1G(3) PHY_MODE_SGMII>;
|
||||
};
|
||||
port3: port@3 {
|
||||
reg = <3>;
|
||||
phy-handle = <&phy3>;
|
||||
phys = <&serdes_hsio 3 SERDES1G(4) PHY_MODE_SGMII>;
|
||||
};
|
||||
port4: port@4 {
|
||||
reg = <4>;
|
||||
phy-handle = <&phy4>;
|
||||
phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
|
||||
};
|
||||
port5: port@5 {
|
||||
reg = <5>;
|
||||
phy-handle = <&phy5>;
|
||||
phys = <&serdes_hsio 5 SERDES1G(6) PHY_MODE_SGMII>;
|
||||
};
|
||||
port6: port@6 {
|
||||
reg = <6>;
|
||||
phy-handle = <&phy6>;
|
||||
phys = <&serdes_hsio 6 SERDES1G(7) PHY_MODE_SGMII>;
|
||||
};
|
||||
port7: port@7 {
|
||||
reg = <7>;
|
||||
phy-handle = <&phy7>;
|
||||
phys = <&serdes_hsio 7 SERDES1G(8) PHY_MODE_SGMII>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,474 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,jr2.dtsi"
|
||||
#include <dt-bindings/mscc/jr2_data.h>
|
||||
|
||||
/ {
|
||||
model = "Jaguar2 Cu48 PCB111 Reference Board";
|
||||
compatible = "mscc,jr2-pcb111", "mscc,jr2";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green {
|
||||
label = "pcb111:green:status";
|
||||
gpios = <&gpio 12 0>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb111:red:status";
|
||||
gpios = <&gpio 13 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <0>; /* CS0 */
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
/* SPIO only use DO, CLK, no inputs */
|
||||
sgpio1_pins: sgpio1-pins {
|
||||
pins = "GPIO_4", "GPIO_5";
|
||||
function = "sg1";
|
||||
};
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
sgpio-ports = <0xffffffff>;
|
||||
};
|
||||
|
||||
&sgpio1 {
|
||||
status = "okay";
|
||||
sgpio-ports = <0x001effff>;
|
||||
};
|
||||
|
||||
&sgpio2 {
|
||||
status = "okay";
|
||||
sgpio-ports = <0xff000000>;
|
||||
gpio-ranges = <&sgpio2 0 0 96>;
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
phy6: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
};
|
||||
phy7: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
};
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
};
|
||||
phy9: ethernet-phy@9 {
|
||||
reg = <9>;
|
||||
};
|
||||
phy10: ethernet-phy@10 {
|
||||
reg = <10>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <11>;
|
||||
};
|
||||
phy12: ethernet-phy@12 {
|
||||
reg = <12>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <13>;
|
||||
};
|
||||
phy14: ethernet-phy@14 {
|
||||
reg = <14>;
|
||||
};
|
||||
phy15: ethernet-phy@15 {
|
||||
reg = <15>;
|
||||
};
|
||||
phy16: ethernet-phy@16 {
|
||||
reg = <16>;
|
||||
};
|
||||
phy17: ethernet-phy@17 {
|
||||
reg = <17>;
|
||||
};
|
||||
phy18: ethernet-phy@18 {
|
||||
reg = <18>;
|
||||
};
|
||||
phy19: ethernet-phy@19 {
|
||||
reg = <19>;
|
||||
};
|
||||
phy20: ethernet-phy@20 {
|
||||
reg = <20>;
|
||||
};
|
||||
phy21: ethernet-phy@21 {
|
||||
reg = <21>;
|
||||
};
|
||||
phy22: ethernet-phy@22 {
|
||||
reg = <22>;
|
||||
};
|
||||
phy23: ethernet-phy@23 {
|
||||
reg = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio2 {
|
||||
status = "okay";
|
||||
|
||||
phy24: ethernet-phy@24 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy25: ethernet-phy@25 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy26: ethernet-phy@26 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy27: ethernet-phy@27 {
|
||||
reg = <3>;
|
||||
};
|
||||
phy28: ethernet-phy@28 {
|
||||
reg = <4>;
|
||||
};
|
||||
phy29: ethernet-phy@29 {
|
||||
reg = <5>;
|
||||
};
|
||||
phy30: ethernet-phy@30 {
|
||||
reg = <6>;
|
||||
};
|
||||
phy31: ethernet-phy@31 {
|
||||
reg = <7>;
|
||||
};
|
||||
phy32: ethernet-phy@32 {
|
||||
reg = <8>;
|
||||
};
|
||||
phy33: ethernet-phy@33 {
|
||||
reg = <9>;
|
||||
};
|
||||
phy34: ethernet-phy@34 {
|
||||
reg = <10>;
|
||||
};
|
||||
phy35: ethernet-phy@35 {
|
||||
reg = <11>;
|
||||
};
|
||||
phy36: ethernet-phy@36 {
|
||||
reg = <12>;
|
||||
};
|
||||
phy37: ethernet-phy@37 {
|
||||
reg = <13>;
|
||||
};
|
||||
phy38: ethernet-phy@38 {
|
||||
reg = <14>;
|
||||
};
|
||||
phy39: ethernet-phy@39 {
|
||||
reg = <15>;
|
||||
};
|
||||
phy40: ethernet-phy@40 {
|
||||
reg = <16>;
|
||||
};
|
||||
phy41: ethernet-phy@41 {
|
||||
reg = <17>;
|
||||
};
|
||||
phy42: ethernet-phy@42 {
|
||||
reg = <18>;
|
||||
};
|
||||
phy43: ethernet-phy@43 {
|
||||
reg = <19>;
|
||||
};
|
||||
phy44: ethernet-phy@44 {
|
||||
reg = <20>;
|
||||
};
|
||||
phy45: ethernet-phy@45 {
|
||||
reg = <21>;
|
||||
};
|
||||
phy46: ethernet-phy@46 {
|
||||
reg = <22>;
|
||||
};
|
||||
phy47: ethernet-phy@47 {
|
||||
reg = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
port0: port@0 {
|
||||
reg = <0>;
|
||||
phy-handle = <&phy0>;
|
||||
phys = <&serdes_hsio 0 SERDES6G(4) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <1>;
|
||||
phy-handle = <&phy1>;
|
||||
phys = <&serdes_hsio 1 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port2: port@2 {
|
||||
reg = <2>;
|
||||
phy-handle = <&phy2>;
|
||||
phys = <&serdes_hsio 2 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port3: port@3 {
|
||||
reg = <3>;
|
||||
phy-handle = <&phy3>;
|
||||
phys = <&serdes_hsio 3 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port4: port@4 {
|
||||
reg = <4>;
|
||||
phy-handle = <&phy4>;
|
||||
phys = <&serdes_hsio 4 SERDES6G(5) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port5: port@5 {
|
||||
reg = <5>;
|
||||
phy-handle = <&phy5>;
|
||||
phys = <&serdes_hsio 5 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port6: port@6 {
|
||||
reg = <6>;
|
||||
phy-handle = <&phy6>;
|
||||
phys = <&serdes_hsio 6 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port7: port@7 {
|
||||
reg = <7>;
|
||||
phy-handle = <&phy7>;
|
||||
phys = <&serdes_hsio 7 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port8: port@8 {
|
||||
reg = <8>;
|
||||
phy-handle = <&phy8>;
|
||||
phys = <&serdes_hsio 8 SERDES6G(6) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port9: port@9 {
|
||||
reg = <9>;
|
||||
phy-handle = <&phy9>;
|
||||
phys = <&serdes_hsio 9 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port10: port@10 {
|
||||
reg = <10>;
|
||||
phy-handle = <&phy10>;
|
||||
phys = <&serdes_hsio 10 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port11: port@11 {
|
||||
reg = <11>;
|
||||
phy-handle = <&phy11>;
|
||||
phys = <&serdes_hsio 11 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port12: port@12 {
|
||||
reg = <12>;
|
||||
phy-handle = <&phy12>;
|
||||
phys = <&serdes_hsio 12 SERDES6G(7) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port13: port@13 {
|
||||
reg = <13>;
|
||||
phy-handle = <&phy13>;
|
||||
phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port14: port@14 {
|
||||
reg = <14>;
|
||||
phy-handle = <&phy14>;
|
||||
phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port15: port@15 {
|
||||
reg = <15>;
|
||||
phy-handle = <&phy15>;
|
||||
phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port16: port@16 {
|
||||
reg = <16>;
|
||||
phy-handle = <&phy16>;
|
||||
phys = <&serdes_hsio 16 SERDES6G(8) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port17: port@17 {
|
||||
reg = <17>;
|
||||
phy-handle = <&phy17>;
|
||||
phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port18: port@18 {
|
||||
reg = <18>;
|
||||
phy-handle = <&phy18>;
|
||||
phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port19: port@19 {
|
||||
reg = <19>;
|
||||
phy-handle = <&phy19>;
|
||||
phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port20: port@20 {
|
||||
reg = <20>;
|
||||
phy-handle = <&phy20>;
|
||||
phys = <&serdes_hsio 20 SERDES6G(9) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port21: port@21 {
|
||||
reg = <21>;
|
||||
phy-handle = <&phy21>;
|
||||
phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port22: port@22 {
|
||||
reg = <22>;
|
||||
phy-handle = <&phy22>;
|
||||
phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port23: port@23 {
|
||||
reg = <23>;
|
||||
phy-handle = <&phy23>;
|
||||
phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port24: port@24 {
|
||||
reg = <24>;
|
||||
phy-handle = <&phy24>;
|
||||
phys = <&serdes_hsio 24 SERDES6G(10) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port25: port@25 {
|
||||
reg = <25>;
|
||||
phy-handle = <&phy25>;
|
||||
phys = <&serdes_hsio 25 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port26: port@26 {
|
||||
reg = <26>;
|
||||
phy-handle = <&phy26>;
|
||||
phys = <&serdes_hsio 26 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port27: port@27 {
|
||||
reg = <27>;
|
||||
phy-handle = <&phy27>;
|
||||
phys = <&serdes_hsio 27 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port28: port@28 {
|
||||
reg = <28>;
|
||||
phy-handle = <&phy28>;
|
||||
phys = <&serdes_hsio 28 SERDES6G(11) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port29: port@29 {
|
||||
reg = <29>;
|
||||
phy-handle = <&phy29>;
|
||||
phys = <&serdes_hsio 29 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port30: port@30 {
|
||||
reg = <30>;
|
||||
phy-handle = <&phy30>;
|
||||
phys = <&serdes_hsio 30 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port31: port@31 {
|
||||
reg = <31>;
|
||||
phy-handle = <&phy31>;
|
||||
phys = <&serdes_hsio 31 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port32: port@32 {
|
||||
reg = <32>;
|
||||
phy-handle = <&phy32>;
|
||||
phys = <&serdes_hsio 32 SERDES6G(12) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port33: port@33 {
|
||||
reg = <33>;
|
||||
phy-handle = <&phy33>;
|
||||
phys = <&serdes_hsio 33 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port34: port@34 {
|
||||
reg = <34>;
|
||||
phy-handle = <&phy34>;
|
||||
phys = <&serdes_hsio 34 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port35: port@35 {
|
||||
reg = <35>;
|
||||
phy-handle = <&phy35>;
|
||||
phys = <&serdes_hsio 35 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port36: port@36 {
|
||||
reg = <36>;
|
||||
phy-handle = <&phy36>;
|
||||
phys = <&serdes_hsio 36 SERDES6G(13) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port37: port@37 {
|
||||
reg = <37>;
|
||||
phy-handle = <&phy37>;
|
||||
phys = <&serdes_hsio 37 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port38: port@38 {
|
||||
reg = <38>;
|
||||
phy-handle = <&phy38>;
|
||||
phys = <&serdes_hsio 38 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port39: port@39 {
|
||||
reg = <39>;
|
||||
phy-handle = <&phy39>;
|
||||
phys = <&serdes_hsio 39 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port40: port@40 {
|
||||
reg = <40>;
|
||||
phy-handle = <&phy40>;
|
||||
phys = <&serdes_hsio 40 SERDES6G(14) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port41: port@41 {
|
||||
reg = <41>;
|
||||
phy-handle = <&phy41>;
|
||||
phys = <&serdes_hsio 41 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port42: port@42 {
|
||||
reg = <42>;
|
||||
phy-handle = <&phy42>;
|
||||
phys = <&serdes_hsio 42 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port43: port@43 {
|
||||
reg = <43>;
|
||||
phy-handle = <&phy43>;
|
||||
phys = <&serdes_hsio 43 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port44: port@44 {
|
||||
reg = <44>;
|
||||
phy-handle = <&phy44>;
|
||||
phys = <&serdes_hsio 44 SERDES6G(15) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port45: port@45 {
|
||||
reg = <45>;
|
||||
phy-handle = <&phy45>;
|
||||
phys = <&serdes_hsio 45 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port46: port@46 {
|
||||
reg = <46>;
|
||||
phy-handle = <&phy46>;
|
||||
phys = <&serdes_hsio 46 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port47: port@47 {
|
||||
reg = <47>;
|
||||
phy-handle = <&phy47>;
|
||||
phys = <&serdes_hsio 47 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,164 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
#include <dt-bindings/clock/jz4780-cgu.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ingenic,jz4780";
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@10001000 {
|
||||
compatible = "ingenic,jz4780-intc";
|
||||
reg = <0x10001000 0x50>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
ext: ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rtc: rtc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
cgu: jz4780-cgu@10000000 {
|
||||
compatible = "ingenic,jz4780-cgu";
|
||||
reg = <0x10000000 0x100>;
|
||||
|
||||
clocks = <&ext>, <&rtc>;
|
||||
clock-names = "ext", "rtc";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mmc0: mmc@13450000 {
|
||||
compatible = "ingenic,jz4780-mmc";
|
||||
reg = <0x13450000 0x1000>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&cgu JZ4780_CLK_MSC0>;
|
||||
clock-names = "mmc";
|
||||
};
|
||||
|
||||
mmc1: mmc@13460000 {
|
||||
compatible = "ingenic,jz4780-mmc";
|
||||
reg = <0x13460000 0x1000>;
|
||||
|
||||
clocks = <&cgu JZ4780_CLK_MSC1>;
|
||||
clock-names = "mmc";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@10030000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10030000 0x100>;
|
||||
reg-shift = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <51>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10031000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10031000 0x100>;
|
||||
reg-shift = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <50>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@10032000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10032000 0x100>;
|
||||
reg-shift = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <49>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@10033000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10033000 0x100>;
|
||||
reg-shift = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <48>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@10034000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10034000 0x100>;
|
||||
reg-shift = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <34>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nemc: nemc@13410000 {
|
||||
compatible = "ingenic,jz4780-nemc";
|
||||
reg = <0x13410000 0x10000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0 0x1b000000 0x1000000
|
||||
2 0 0x1a000000 0x1000000
|
||||
3 0 0x19000000 0x1000000
|
||||
4 0 0x18000000 0x1000000
|
||||
5 0 0x17000000 0x1000000
|
||||
6 0 0x16000000 0x1000000>;
|
||||
|
||||
clocks = <&cgu JZ4780_CLK_NEMC>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bch: bch@134d0000 {
|
||||
compatible = "ingenic,jz4780-bch";
|
||||
reg = <0x134d0000 0x10000>;
|
||||
|
||||
clocks = <&cgu JZ4780_CLK_BCH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,59 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2018 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "mt7628a.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "seeed,linkit-smart-7688", "ralink,mt7628a-soc";
|
||||
model = "LinkIt-Smart-7688";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart2;
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
state_default: pin_state {
|
||||
p0led {
|
||||
groups = "p0led_a";
|
||||
function = "led";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
num-cs = <2>;
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ephy_iot_mode>;
|
||||
mediatek,poll-link-phy = <0>;
|
||||
};
|
||||
@@ -0,0 +1,252 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,luton.dtsi"
|
||||
#include <dt-bindings/mscc/luton_data.h>
|
||||
|
||||
/ {
|
||||
model = "Luton26 PCB090 Reference Board";
|
||||
compatible = "mscc,luton-pcb090", "mscc,luton";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green {
|
||||
label = "pcb090:green:status";
|
||||
gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb090:red:status";
|
||||
gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
gpio-ranges = <&sgpio 0 0 96>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <0>; /* CS0 */
|
||||
spi-cs-high;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
phy6: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
};
|
||||
phy7: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
};
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
};
|
||||
phy9: ethernet-phy@9 {
|
||||
reg = <9>;
|
||||
};
|
||||
phy10: ethernet-phy@10 {
|
||||
reg = <10>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <11>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
status = "okay";
|
||||
|
||||
phy12: ethernet-phy@12 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy14: ethernet-phy@14 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy15: ethernet-phy@15 {
|
||||
reg = <3>;
|
||||
};
|
||||
phy16: ethernet-phy@16 {
|
||||
reg = <4>;
|
||||
};
|
||||
phy17: ethernet-phy@17 {
|
||||
reg = <5>;
|
||||
};
|
||||
phy18: ethernet-phy@18 {
|
||||
reg = <6>;
|
||||
};
|
||||
phy19: ethernet-phy@19 {
|
||||
reg = <7>;
|
||||
};
|
||||
phy20: ethernet-phy@20 {
|
||||
reg = <8>;
|
||||
};
|
||||
phy21: ethernet-phy@21 {
|
||||
reg = <9>;
|
||||
};
|
||||
phy22: ethernet-phy@22 {
|
||||
reg = <10>;
|
||||
};
|
||||
phy23: ethernet-phy@23 {
|
||||
reg = <11>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
port0: port@0 {
|
||||
reg = <0>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <1>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
port2: port@2 {
|
||||
reg = <2>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
port3: port@3 {
|
||||
reg = <3>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
port4: port@4 {
|
||||
reg = <4>;
|
||||
phy-handle = <&phy4>;
|
||||
};
|
||||
port5: port@5 {
|
||||
reg = <5>;
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
port6: port@6 {
|
||||
reg = <6>;
|
||||
phy-handle = <&phy6>;
|
||||
};
|
||||
port7: port@7 {
|
||||
reg = <7>;
|
||||
phy-handle = <&phy7>;
|
||||
};
|
||||
port8: port@8 {
|
||||
reg = <8>;
|
||||
phy-handle = <&phy8>;
|
||||
};
|
||||
port9: port@9 {
|
||||
reg = <9>;
|
||||
phy-handle = <&phy9>;
|
||||
};
|
||||
port10: port@10 {
|
||||
reg = <10>;
|
||||
phy-handle = <&phy10>;
|
||||
};
|
||||
port11: port@11 {
|
||||
reg = <11>;
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
port12: port@12 {
|
||||
reg = <12>;
|
||||
phy-handle = <&phy12>;
|
||||
phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port13: port@13 {
|
||||
reg = <13>;
|
||||
phy-handle = <&phy13>;
|
||||
phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port14: port@14 {
|
||||
reg = <14>;
|
||||
phy-handle = <&phy14>;
|
||||
phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port15: port@15 {
|
||||
reg = <15>;
|
||||
phy-handle = <&phy15>;
|
||||
phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port16: port@16 {
|
||||
reg = <16>;
|
||||
phy-handle = <&phy16>;
|
||||
phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port17: port@17 {
|
||||
reg = <17>;
|
||||
phy-handle = <&phy17>;
|
||||
phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port18: port@18 {
|
||||
reg = <18>;
|
||||
phy-handle = <&phy18>;
|
||||
phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port19: port@19 {
|
||||
reg = <19>;
|
||||
phy-handle = <&phy19>;
|
||||
phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port20: port@20 {
|
||||
reg = <20>;
|
||||
phy-handle = <&phy20>;
|
||||
phys = <&serdes_hsio 20 SERDES6G(3) PHY_MODE_QSGMII>;
|
||||
};
|
||||
port21: port@21 {
|
||||
reg = <21>;
|
||||
phy-handle = <&phy21>;
|
||||
phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port22: port@22 {
|
||||
reg = <22>;
|
||||
phy-handle = <&phy22>;
|
||||
phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
port23: port@23 {
|
||||
reg = <23>;
|
||||
phy-handle = <&phy23>;
|
||||
phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,156 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,luton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Luton10 PCB091 Reference Board";
|
||||
compatible = "mscc,luton-pcb091", "mscc,luton";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
top_dimmer {
|
||||
label = "pcb091:top:dimmer";
|
||||
gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_green {
|
||||
label = "pcb091:green:status";
|
||||
gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb091:red:status";
|
||||
gpios = <&sgpio 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
mscc,sgpio-ports = <0xFFF000FF>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <0>; /* CS0 */
|
||||
spi-cs-high;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
phy6: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
};
|
||||
phy7: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
};
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
};
|
||||
phy9: ethernet-phy@9 {
|
||||
reg = <9>;
|
||||
};
|
||||
phy10: ethernet-phy@10 {
|
||||
reg = <10>;
|
||||
};
|
||||
phy11: ethernet-phy@11 {
|
||||
reg = <11>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
port0: port@0 {
|
||||
reg = <0>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <1>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
port2: port@2 {
|
||||
reg = <2>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
port3: port@3 {
|
||||
reg = <3>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
port4: port@4 {
|
||||
reg = <4>;
|
||||
phy-handle = <&phy4>;
|
||||
};
|
||||
port5: port@5 {
|
||||
reg = <5>;
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
port6: port@6 {
|
||||
reg = <6>;
|
||||
phy-handle = <&phy6>;
|
||||
};
|
||||
port7: port@7 {
|
||||
reg = <7>;
|
||||
phy-handle = <&phy7>;
|
||||
};
|
||||
port8: port@8 {
|
||||
reg = <8>;
|
||||
phy-handle = <&phy8>;
|
||||
};
|
||||
port9: port@9 {
|
||||
reg = <9>;
|
||||
phy-handle = <&phy9>;
|
||||
};
|
||||
port10: port@10 {
|
||||
reg = <10>;
|
||||
phy-handle = <&phy10>;
|
||||
};
|
||||
port11: port@11 {
|
||||
reg = <11>;
|
||||
phy-handle = <&phy11>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "img,xilfpga";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "mips,m14Kc";
|
||||
clocks = <&ext>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ext: ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,303 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mscc,jr2";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "mips,mips24KEc";
|
||||
device_type = "cpu";
|
||||
clocks = <&cpu_clk>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
cpuintc: interrupt-controller@0 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
cpu_clk: cpu-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <500000000>;
|
||||
};
|
||||
|
||||
ahb_clk: ahb-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x70000000 0x2000000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpu_ctrl: syscon@0 {
|
||||
compatible = "mscc,jr2-cpu-syscon", "syscon";
|
||||
reg = <0x0 0x2c>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@70 {
|
||||
compatible = "mscc,jr2-icpu-intr";
|
||||
reg = <0x70 0x94>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
uart0: serial@100000 {
|
||||
pinctrl-0 = <&uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100000 0x20>;
|
||||
interrupts = <6>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@100800 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100800 0x20>;
|
||||
interrupts = <7>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi-master@101000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x101000 0x40>;
|
||||
num-chipselect = <4>;
|
||||
bus-num = <0>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
clocks = <&ahb_clk>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reset@1010008 {
|
||||
compatible = "mscc,jr2-chip-reset";
|
||||
reg = <0x1010008 0x4>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@1070034 {
|
||||
compatible = "mscc,jaguar2-pinctrl";
|
||||
reg = <0x1010038 0x90>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 64>;
|
||||
|
||||
sgpio_pins: sgpio-pins {
|
||||
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
|
||||
function = "sg0";
|
||||
};
|
||||
|
||||
sgpio1_pins: sgpio1-pins {
|
||||
pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
|
||||
function = "sg1";
|
||||
};
|
||||
|
||||
sgpio2_pins: sgpio2-pins {
|
||||
pins = "GPIO_30", "GPIO_31",
|
||||
"GPIO_32", "GPIO_33";
|
||||
function = "sg2";
|
||||
};
|
||||
|
||||
uart_pins: uart-pins {
|
||||
pins = "GPIO_10", "GPIO_11";
|
||||
function = "uart";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins = "GPIO_24", "GPIO_25";
|
||||
function = "uart2";
|
||||
};
|
||||
};
|
||||
|
||||
sgpio: gpio@1010150 {
|
||||
compatible = "mscc,ocelot-sgpio";
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&sgpio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x1010150 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&sgpio 0 0 64>;
|
||||
gpio-bank-name = "sgpio0_";
|
||||
sgpio-clock = <0x14>;
|
||||
};
|
||||
|
||||
sgpio1: gpio@101025c {
|
||||
compatible = "mscc,ocelot-sgpio";
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&sgpio1_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x101025c 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&sgpio1 0 0 64>;
|
||||
gpio-bank-name = "sgpio1_";
|
||||
sgpio-clock = <0x14>;
|
||||
};
|
||||
|
||||
sgpio2: gpio@1010368 {
|
||||
compatible = "mscc,ocelot-sgpio";
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&sgpio2_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x1010368 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&sgpio2 0 0 64>;
|
||||
gpio-bank-name = "sgpio2_";
|
||||
sgpio-clock = <0x14>;
|
||||
};
|
||||
|
||||
switch: switch@1010000 {
|
||||
compatible = "mscc,vsc7454-switch";
|
||||
reg = <0x01040000 0x0100>, // VTSS_TO_DEV_0
|
||||
<0x01050000 0x0100>, // VTSS_TO_DEV_1
|
||||
<0x01060000 0x0100>, // VTSS_TO_DEV_2
|
||||
<0x01070000 0x0100>, // VTSS_TO_DEV_3
|
||||
<0x01080000 0x0100>, // VTSS_TO_DEV_4
|
||||
<0x01090000 0x0100>, // VTSS_TO_DEV_5
|
||||
<0x010a0000 0x0100>, // VTSS_TO_DEV_6
|
||||
<0x010b0000 0x0100>, // VTSS_TO_DEV_7
|
||||
<0x010c0000 0x0100>, // VTSS_TO_DEV_8
|
||||
<0x010d0000 0x0100>, // VTSS_TO_DEV_9
|
||||
<0x010e0000 0x0100>, // VTSS_TO_DEV_10
|
||||
<0x010f0000 0x0100>, // VTSS_TO_DEV_11
|
||||
<0x01100000 0x0100>, // VTSS_TO_DEV_12
|
||||
<0x01110000 0x0100>, // VTSS_TO_DEV_13
|
||||
<0x01120000 0x0100>, // VTSS_TO_DEV_14
|
||||
<0x01130000 0x0100>, // VTSS_TO_DEV_15
|
||||
<0x01140000 0x0100>, // VTSS_TO_DEV_16
|
||||
<0x01150000 0x0100>, // VTSS_TO_DEV_17
|
||||
<0x01160000 0x0100>, // VTSS_TO_DEV_18
|
||||
<0x01170000 0x0100>, // VTSS_TO_DEV_19
|
||||
<0x01180000 0x0100>, // VTSS_TO_DEV_20
|
||||
<0x01190000 0x0100>, // VTSS_TO_DEV_21
|
||||
<0x011a0000 0x0100>, // VTSS_TO_DEV_22
|
||||
<0x011b0000 0x0100>, // VTSS_TO_DEV_23
|
||||
<0x011c0000 0x0100>, // VTSS_TO_DEV_24
|
||||
<0x011d0000 0x0100>, // VTSS_TO_DEV_25
|
||||
<0x011e0000 0x0100>, // VTSS_TO_DEV_26
|
||||
<0x011f0000 0x0100>, // VTSS_TO_DEV_27
|
||||
<0x01200000 0x0100>, // VTSS_TO_DEV_28
|
||||
<0x01210000 0x0100>, // VTSS_TO_DEV_29
|
||||
<0x01220000 0x0100>, // VTSS_TO_DEV_30
|
||||
<0x01230000 0x0100>, // VTSS_TO_DEV_31
|
||||
<0x01240000 0x0100>, // VTSS_TO_DEV_32
|
||||
<0x01250000 0x0100>, // VTSS_TO_DEV_33
|
||||
<0x01260000 0x0100>, // VTSS_TO_DEV_34
|
||||
<0x01270000 0x0100>, // VTSS_TO_DEV_35
|
||||
<0x01280000 0x0100>, // VTSS_TO_DEV_36
|
||||
<0x01290000 0x0100>, // VTSS_TO_DEV_37
|
||||
<0x012a0000 0x0100>, // VTSS_TO_DEV_38
|
||||
<0x012b0000 0x0100>, // VTSS_TO_DEV_39
|
||||
<0x012c0000 0x0100>, // VTSS_TO_DEV_40
|
||||
<0x012d0000 0x0100>, // VTSS_TO_DEV_41
|
||||
<0x012e0000 0x0100>, // VTSS_TO_DEV_42
|
||||
<0x012f0000 0x0100>, // VTSS_TO_DEV_43
|
||||
<0x01300000 0x0100>, // VTSS_TO_DEV_44
|
||||
<0x01310000 0x0100>, // VTSS_TO_DEV_45
|
||||
<0x01320000 0x0100>, // VTSS_TO_DEV_46
|
||||
<0x01330000 0x0100>, // VTSS_TO_DEV_47
|
||||
<0x01f00000 0x100000>, // ANA_AC
|
||||
<0x01d00000 0x100000>, // ANA_CL
|
||||
<0x01e00000 0x100000>, // ANA_L2
|
||||
<0x01410000 0x10000>, // ASM
|
||||
<0x01460000 0x10000>, // HSIO
|
||||
<0x01420000 0x00000>, // LRN
|
||||
<0x017d0000 0x10000>, // QFWD
|
||||
<0x01020000 0x20000>, // QS
|
||||
<0x017e0000 0x10000>, // QSYS
|
||||
<0x01b00000 0x80000>; // REW
|
||||
reg-names = "port0", "port1", "port2", "port3", "port4",
|
||||
"port5", "port6", "port7", "port8", "port9",
|
||||
"port10", "port11", "port12", "port13",
|
||||
"port14", "port15", "port16", "port17",
|
||||
"port18", "port19", "port20", "port21",
|
||||
"port22", "port23", "port24", "port25",
|
||||
"port26", "port27", "port28", "port29",
|
||||
"port30", "port31", "port32", "port33",
|
||||
"port34", "port35", "port36", "port37",
|
||||
"port38", "port39", "port40", "port41",
|
||||
"port42", "port43", "port44", "port45",
|
||||
"port46", "port47", "ana_ac", "ana_cl",
|
||||
"ana_l2", "asm", "hsio", "lrn", "qfwd",
|
||||
"qs", "qsys", "rew";
|
||||
status = "okay";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0: mdio@010100c8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,jr2-miim";
|
||||
reg = <0x010100c8 0x24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio1: mdio@010100ec {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,jr2-miim";
|
||||
reg = <0x010100ec 0x24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio2: mdio@01010110 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,jr2-miim";
|
||||
reg = <0x01010110 0x24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsio: syscon@10d0000 {
|
||||
compatible = "mscc,jr2-hsio", "syscon", "simple-mfd";
|
||||
reg = <0x10d0000 0x10000>;
|
||||
|
||||
serdes_hsio: serdes_hsio {
|
||||
compatible = "mscc,vsc7454-serdes";
|
||||
#phy-cells = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,169 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mscc,luton";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "mips,mips24KEc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
sys_clk: sys-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
ahb_clk: ahb-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <208333333>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x60000000 0x10200000>;
|
||||
|
||||
uart0: serial@10100000 {
|
||||
pinctrl-0 = <&uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
compatible = "ns16550a";
|
||||
reg = <0x10100000 0x20>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio: pinctrl@70068 {
|
||||
compatible = "mscc,luton-pinctrl";
|
||||
reg = <0x70068 0x68>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 32>;
|
||||
|
||||
sgpio_pins: sgpio-pins {
|
||||
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
|
||||
function = "sio";
|
||||
};
|
||||
uart_pins: uart-pins {
|
||||
pins = "GPIO_30", "GPIO_31";
|
||||
function = "uart";
|
||||
};
|
||||
};
|
||||
|
||||
sgpio: gpio@70130 {
|
||||
compatible = "mscc,luton-sgpio";
|
||||
status = "disabled";
|
||||
clocks = <&sys_clk>;
|
||||
pinctrl-0 = <&sgpio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x0070130 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&sgpio 0 0 64>;
|
||||
};
|
||||
|
||||
spi0: spi-bitbang {
|
||||
compatible = "mscc,luton-bb-spi";
|
||||
status = "okay";
|
||||
reg = <0x10000064 0x4>;
|
||||
num-chipselects = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
switch: switch@1010000 {
|
||||
compatible = "mscc,vsc7527-switch";
|
||||
reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0
|
||||
<0x1f0000 0x0100>, // VTSS_TO_DEV_1
|
||||
<0x200000 0x0100>, // VTSS_TO_DEV_2
|
||||
<0x210000 0x0100>, // VTSS_TO_DEV_3
|
||||
<0x220000 0x0100>, // VTSS_TO_DEV_4
|
||||
<0x230000 0x0100>, // VTSS_TO_DEV_5
|
||||
<0x240000 0x0100>, // VTSS_TO_DEV_6
|
||||
<0x250000 0x0100>, // VTSS_TO_DEV_7
|
||||
<0x260000 0x0100>, // VTSS_TO_DEV_8
|
||||
<0x270000 0x0100>, // VTSS_TO_DEV_9
|
||||
<0x280000 0x0100>, // VTSS_TO_DEV_10
|
||||
<0x290000 0x0100>, // VTSS_TO_DEV_11
|
||||
<0x2a0000 0x0100>, // VTSS_TO_DEV_12
|
||||
<0x2b0000 0x0100>, // VTSS_TO_DEV_13
|
||||
<0x2c0000 0x0100>, // VTSS_TO_DEV_14
|
||||
<0x2d0000 0x0100>, // VTSS_TO_DEV_15
|
||||
<0x2e0000 0x0100>, // VTSS_TO_DEV_16
|
||||
<0x2f0000 0x0100>, // VTSS_TO_DEV_17
|
||||
<0x300000 0x0100>, // VTSS_TO_DEV_18
|
||||
<0x310000 0x0100>, // VTSS_TO_DEV_19
|
||||
<0x320000 0x0100>, // VTSS_TO_DEV_20
|
||||
<0x330000 0x0100>, // VTSS_TO_DEV_21
|
||||
<0x340000 0x0100>, // VTSS_TO_DEV_22
|
||||
<0x350000 0x0100>, // VTSS_TO_DEV_23
|
||||
<0x010000 0x1000>, // VTSS_TO_SYS
|
||||
<0x020000 0x1000>, // VTSS_TO_ANA
|
||||
<0x030000 0x1000>, // VTSS_TO_REW
|
||||
<0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
|
||||
<0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
|
||||
<0x0a0000 0x10000>; // VTSS_TO_HSIO
|
||||
reg-names = "port0", "port1", "port2", "port3",
|
||||
"port4", "port5", "port6", "port7",
|
||||
"port8", "port9", "port10", "port11",
|
||||
"port12", "port13", "port14", "port15",
|
||||
"port16", "port17", "port18", "port19",
|
||||
"port20", "port21", "port22", "port23",
|
||||
"sys", "ana", "rew", "gcb", "qs", "hsio";
|
||||
status = "okay";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0: mdio@700a0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,luton-miim";
|
||||
reg = <0x700a0 0x24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio1: mdio@700c4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,luton-miim";
|
||||
reg = <0x700c4 0x24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsio: syscon@10d0000 {
|
||||
compatible = "mscc,luton-hsio", "syscon", "simple-mfd";
|
||||
reg = <0xa0000 0x10000>;
|
||||
|
||||
serdes_hsio: serdes_hsio {
|
||||
compatible = "mscc,vsc7527-serdes";
|
||||
#phy-cells = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,245 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mscc,ocelot";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "mips,mips24KEc";
|
||||
device_type = "cpu";
|
||||
clocks = <&cpu_clk>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
cpuintc: interrupt-controller@0 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
cpu_clk: cpu-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <500000000>;
|
||||
};
|
||||
|
||||
sys_clk: sys-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
ahb_clk: ahb-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x70000000 0x2000000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpu_ctrl: syscon@0 {
|
||||
compatible = "mscc,ocelot-cpu-syscon", "syscon";
|
||||
reg = <0x0 0x2c>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@70 {
|
||||
compatible = "mscc,ocelot-icpu-intr";
|
||||
reg = <0x70 0x70>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
uart0: serial@100000 {
|
||||
pinctrl-0 = <&uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100000 0x20>;
|
||||
interrupts = <6>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@100800 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100800 0x20>;
|
||||
interrupts = <7>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi-master@101000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x101000 0x40>;
|
||||
num-chipselect = <4>;
|
||||
bus-num = <0>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
clocks = <&ahb_clk>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
switch: switch@1010000 {
|
||||
pinctrl-0 = <&miim1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
compatible = "mscc,vsc7514-switch";
|
||||
|
||||
reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0
|
||||
<0x11f0000 0x100>, // VTSS_TO_DEV_1
|
||||
<0x1200000 0x100>, // VTSS_TO_DEV_2
|
||||
<0x1210000 0x100>, // VTSS_TO_DEV_3
|
||||
<0x1220000 0x100>, // VTSS_TO_DEV_4
|
||||
<0x1230000 0x100>, // VTSS_TO_DEV_5
|
||||
<0x1240000 0x100>, // VTSS_TO_DEV_6
|
||||
<0x1250000 0x100>, // VTSS_TO_DEV_7
|
||||
<0x1260000 0x100>, // VTSS_TO_DEV_8
|
||||
<0x1270000 0x100>, // VTSS_TO_DEV_9
|
||||
<0x1280000 0x100>, // VTSS_TO_DEV_10
|
||||
<0x1010000 0x10000>, // VTSS_TO_SYS
|
||||
<0x1030000 0x10000>, // VTSS_TO_REW
|
||||
<0x1080000 0x100>, // VTSS_TO_DEVCPU_QS
|
||||
<0x10d0000 0x10000>, // VTSS_TO_HSIO
|
||||
<0x1800000 0x80000>,// VTSS_TO_QSYS
|
||||
<0x1880000 0x10000>;// VTSS_TO_ANA
|
||||
reg-names = "port0", "port1", "port2", "port3", "port4",
|
||||
"port5", "port6", "port7", "port8", "port9",
|
||||
"port10",
|
||||
"sys", "rew", "qs", "hsio", "qsys", "ana";
|
||||
interrupts = <21 22>;
|
||||
interrupt-names = "xtr", "inj";
|
||||
status = "okay";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0: mdio@107009c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,ocelot-miim";
|
||||
reg = <0x107009c 0x24>;
|
||||
interrupts = <14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio1: mdio@10700f0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,ocelot-miim";
|
||||
reg = <0x10700c0 0x24>;
|
||||
interrupts = <14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsio: syscon@10d0000 {
|
||||
compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
|
||||
reg = <0x10d0000 0x10000>;
|
||||
|
||||
serdes_hsio: serdes_hsio {
|
||||
compatible = "mscc,vsc7514-serdes";
|
||||
#phy-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
reset@1070008 {
|
||||
compatible = "mscc,ocelot-chip-reset";
|
||||
reg = <0x1070008 0x4>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@1070034 {
|
||||
compatible = "mscc,ocelot-pinctrl";
|
||||
reg = <0x1070034 0x68>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 22>;
|
||||
|
||||
sgpio_pins: sgpio-pins {
|
||||
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
|
||||
function = "sg0";
|
||||
};
|
||||
|
||||
uart_pins: uart-pins {
|
||||
pins = "GPIO_6", "GPIO_7";
|
||||
function = "uart";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins = "GPIO_12", "GPIO_13";
|
||||
function = "uart2";
|
||||
};
|
||||
|
||||
spi_cs1_pin: spi-cs1-pin {
|
||||
pins = "GPIO_8";
|
||||
function = "si";
|
||||
};
|
||||
|
||||
miim1_pins: miim1-pins {
|
||||
pins = "GPIO_14", "GPIO_15";
|
||||
function = "miim1";
|
||||
};
|
||||
|
||||
spi_cs2_pin: spi-cs2-pin {
|
||||
pins = "GPIO_9";
|
||||
function = "si";
|
||||
};
|
||||
|
||||
spi_cs3_pin: spi-cs3-pin {
|
||||
pins = "GPIO_16";
|
||||
function = "si";
|
||||
};
|
||||
|
||||
spi_cs4_pin: spi-cs4-pin {
|
||||
pins = "GPIO_17";
|
||||
function = "si";
|
||||
};
|
||||
};
|
||||
|
||||
sgpio: gpio@10700f8 {
|
||||
compatible = "mscc,ocelot-sgpio";
|
||||
status = "disabled";
|
||||
clocks = <&sys_clk>;
|
||||
pinctrl-0 = <&sgpio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x10700f8 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&sgpio 0 0 64>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,42 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,ocelot.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "mscc,ocelot";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spi_cs1_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <0>; /* CS0 */
|
||||
};
|
||||
|
||||
spi-nand@1 {
|
||||
compatible = "spi-nand";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <1>; /* CS1 */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,207 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mscc,serval";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "mips,mips24KEc";
|
||||
device_type = "cpu";
|
||||
clocks = <&cpu_clk>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
cpuintc: interrupt-controller@0 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
cpu_clk: cpu-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <416666666>;
|
||||
};
|
||||
|
||||
sys_clk: sys-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <208333333>;
|
||||
};
|
||||
|
||||
ahb_clk: ahb-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <208333333>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x70000000 0x2000000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpu_ctrl: syscon@0 {
|
||||
compatible = "mscc,serval-cpu-syscon", "syscon";
|
||||
reg = <0x0 0x2c>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@70 {
|
||||
compatible = "mscc,serval-icpu-intr";
|
||||
reg = <0x70 0x70>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
uart0: serial@100000 {
|
||||
pinctrl-0 = <&uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100000 0x20>;
|
||||
interrupts = <6>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@100800 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100800 0x20>;
|
||||
interrupts = <7>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reset@1070008 {
|
||||
compatible = "mscc,serval-chip-reset";
|
||||
reg = <0x1070008 0x4>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@1070034 {
|
||||
compatible = "mscc,serval-pinctrl";
|
||||
reg = <0x1070034 0x68>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 22>;
|
||||
|
||||
sgpio_pins: sgpio-pins {
|
||||
pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
|
||||
function = "sio";
|
||||
};
|
||||
|
||||
uart_pins: uart-pins {
|
||||
pins = "GPIO_26", "GPIO_27";
|
||||
function = "uart";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins = "GPIO_13", "GPIO_14";
|
||||
function = "uart2";
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi-bitbang {
|
||||
compatible = "mscc,luton-bb-spi";
|
||||
status = "okay";
|
||||
reg = <0x50 0x4>;
|
||||
num-chipselects = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
sgpio: gpio@10700b4 {
|
||||
compatible = "mscc,luton-sgpio";
|
||||
status = "disabled";
|
||||
clocks = <&sys_clk>;
|
||||
pinctrl-0 = <&sgpio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x10700b4 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&sgpio 0 0 64>;
|
||||
};
|
||||
|
||||
switch: switch@011e0000 {
|
||||
compatible = "mscc,vsc7418-switch";
|
||||
reg = <0x011e0000 0x0100>, // VTSS_TO_DEV0
|
||||
<0x011f0000 0x0100>, // VTSS_TO_DEV1
|
||||
<0x01200000 0x0100>, // VTSS_TO_DEV2
|
||||
<0x01210000 0x0100>, // VTSS_TO_DEV3
|
||||
<0x01220000 0x0100>, // VTSS_TO_DEV4
|
||||
<0x01230000 0x0100>, // VTSS_TO_DEV5
|
||||
<0x01240000 0x0100>, // VTSS_TO_DEV6
|
||||
<0x01250000 0x0100>, // VTSS_TO_DEV7
|
||||
<0x01260000 0x0100>, // VTSS_TO_DEV8
|
||||
<0x01270000 0x0100>, // VTSS_TO_DEV9
|
||||
<0x01280000 0x0100>, // VTSS_TO_DEV10
|
||||
<0x01900000 0x100000>, // ANA
|
||||
<0x01080000 0x20000>, // QS
|
||||
<0x01800000 0x100000>, // QSYS
|
||||
<0x01030000 0x10000>, // REW
|
||||
<0x01010000 0x20000>, // SYS
|
||||
<0x010a0000 0x10000>; // HSIO
|
||||
reg-names = "port0", "port1", "port2", "port3",
|
||||
"port4", "port5", "port6", "port7",
|
||||
"port8", "port9", "port10",
|
||||
"ana", "qs", "qsys", "rew", "sys",
|
||||
"hsio";
|
||||
status = "okay";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0: mdio@0107005c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,serval-miim";
|
||||
reg = <0x0107005c 0x24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio1: mdio@01070080 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,serval-miim";
|
||||
reg = <0x01070080 0x24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsio: syscon@10d0000 {
|
||||
compatible = "mscc,serval-hsio", "syscon", "simple-mfd";
|
||||
reg = <0x10a0000 0x10000>;
|
||||
|
||||
serdes_hsio: serdes_hsio {
|
||||
compatible = "mscc,vsc7418-serdes";
|
||||
#phy-cells = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,189 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mscc,servalt";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "mips,mips24KEc";
|
||||
device_type = "cpu";
|
||||
clocks = <&cpu_clk>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
cpuintc: interrupt-controller@0 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
cpu_clk: cpu-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <500000000>;
|
||||
};
|
||||
|
||||
sys_clk: sys-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
ahb_clk: ahb-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x70000000 0x2000000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpu_ctrl: syscon@0 {
|
||||
compatible = "mscc,servalt-cpu-syscon", "syscon";
|
||||
reg = <0x0 0x2c>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@70 {
|
||||
compatible = "mscc,servalt-icpu-intr";
|
||||
reg = <0x70 0x74>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
uart0: serial@100000 {
|
||||
pinctrl-0 = <&uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100000 0x20>;
|
||||
interrupts = <6>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@100800 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100800 0x20>;
|
||||
interrupts = <7>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reset@1010008 {
|
||||
compatible = "mscc,servalt-chip-reset";
|
||||
reg = <0x1010008 0x4>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@1010034 {
|
||||
compatible = "mscc,servalt-pinctrl";
|
||||
reg = <0x1010034 0x90>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 36>;
|
||||
|
||||
sgpio_pins: sgpio-pins {
|
||||
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
|
||||
function = "sio";
|
||||
};
|
||||
|
||||
uart_pins: uart-pins {
|
||||
pins = "GPIO_6", "GPIO_7";
|
||||
function = "uart";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins = "GPIO_20", "GPIO_21";
|
||||
function = "uart2";
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi-bitbang {
|
||||
compatible = "mscc,luton-bb-spi";
|
||||
status = "okay";
|
||||
reg = <0x50 0x4>;
|
||||
num-chipselects = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
sgpio: gpio@1010120 {
|
||||
compatible = "mscc,ocelot-sgpio";
|
||||
status = "disabled";
|
||||
clocks = <&sys_clk>;
|
||||
pinctrl-0 = <&sgpio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x1010120 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&sgpio 0 0 128>;
|
||||
};
|
||||
|
||||
switch: switch@1010000 {
|
||||
compatible = "mscc,vsc7437-switch";
|
||||
reg = <0x01030000 0x0100>, // VTSS_TO_DEV_0
|
||||
<0x01040000 0x0100>, // VTSS_TO_DEV_1
|
||||
<0x01f00000 0x100000>, // ANA_AC
|
||||
<0x01d00000 0x100000>, // ANA_CL
|
||||
<0x01e00000 0x100000>, // ANA_L2
|
||||
<0x01120000 0x10000>, // ASM
|
||||
<0x01130000 0x00000>, // LRN
|
||||
<0x017d0000 0x10000>, // QFWD
|
||||
<0x01020000 0x20000>, // QS
|
||||
<0x017e0000 0x10000>, // QSYS
|
||||
<0x01b00000 0x80000>; // REW
|
||||
reg-names = "port0", "port1",
|
||||
"ana_ac", "ana_cl", "ana_l2", "asm", "lrn",
|
||||
"qfwd", "qs", "qsys", "rew";
|
||||
status = "okay";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0: mdio@010100c4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,jr2-miim";
|
||||
reg = <0x010100c4 0x24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio1: mdio@010100e8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mscc,jr2-miim";
|
||||
reg = <0x010100e8 0x24>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,407 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include <dt-bindings/clock/mt7628-clk.h>
|
||||
#include <dt-bindings/reset/mt7628-reset.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ralink,mt7628a-soc";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "mti,mips24KEc";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
clk48m: clk48m@0 {
|
||||
compatible = "fixed-clock";
|
||||
|
||||
clock-frequency = <48000000>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
palmbus@10000000 {
|
||||
compatible = "palmbus", "simple-bus";
|
||||
reg = <0x10000000 0x200000>;
|
||||
ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysc: system-controller@0 {
|
||||
compatible = "ralink,mt7620a-sysc", "syscon";
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&sysc>;
|
||||
offset = <0x34>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
clkctrl: clkctrl@0x2c {
|
||||
reg = <0x2c 0x8>, <0x10 0x4>;
|
||||
reg-names = "syscfg0", "clkcfg";
|
||||
compatible = "mediatek,mt7628-clk";
|
||||
#clock-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
rstctrl: rstctrl@0x34 {
|
||||
reg = <0x34 0x4>;
|
||||
compatible = "mediatek,mtmips-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@60 {
|
||||
compatible = "mediatek,mt7628-pinctrl";
|
||||
reg = <0x3c 0x2c>, <0x1300 0x100>;
|
||||
reg-names = "gpiomode", "padconf";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pin_state {
|
||||
};
|
||||
|
||||
spi_single_pins: spi_single_pins {
|
||||
groups = "spi";
|
||||
function = "spi";
|
||||
};
|
||||
|
||||
spi_dual_pins: spi_dual_pins {
|
||||
spi_master_pins {
|
||||
groups = "spi";
|
||||
function = "spi";
|
||||
};
|
||||
|
||||
spi_cs1_pin {
|
||||
groups = "spi cs1";
|
||||
function = "spi cs1";
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0_pins {
|
||||
groups = "uart0";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
uart1_pins: uart1_pins {
|
||||
groups = "uart1";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
uart2_pins: uart2_pins {
|
||||
groups = "uart2";
|
||||
function = "uart2";
|
||||
};
|
||||
|
||||
i2c_pins: i2c_pins {
|
||||
groups = "i2c";
|
||||
function = "i2c";
|
||||
};
|
||||
|
||||
ephy_iot_mode: ephy_iot_mode {
|
||||
ephy4_1_dis {
|
||||
groups = "ephy4_1_pad";
|
||||
function = "digital";
|
||||
};
|
||||
|
||||
ephy0_en {
|
||||
groups = "ephy0";
|
||||
function = "enable";
|
||||
};
|
||||
};
|
||||
|
||||
ephy_router_mode: ephy_router_mode {
|
||||
ephy4_1_en {
|
||||
groups = "ephy4_1_pad";
|
||||
function = "analog";
|
||||
};
|
||||
|
||||
ephy0_en {
|
||||
groups = "ephy0";
|
||||
function = "enable";
|
||||
};
|
||||
};
|
||||
|
||||
sd_iot_mode: sd_iot_mode {
|
||||
ephy4_1_dis {
|
||||
groups = "ephy4_1_pad";
|
||||
function = "digital";
|
||||
};
|
||||
|
||||
sdxc_en {
|
||||
groups = "sdmode";
|
||||
function = "sdxc";
|
||||
};
|
||||
|
||||
sdxc_iot_mode {
|
||||
groups = "sd router";
|
||||
function = "iot";
|
||||
};
|
||||
|
||||
sd_clk_pad {
|
||||
pins = "sd_clk";
|
||||
drive-strength-4g = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
sd_router_mode: sd_router_mode {
|
||||
sdxc_router_mode {
|
||||
groups = "sd router";
|
||||
function = "router";
|
||||
};
|
||||
|
||||
sdxc_map_pins {
|
||||
groups = "gpio0", "i2s", "sdmode", \
|
||||
"i2c", "uart1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
sd_clk_pad {
|
||||
pins = "gpio0";
|
||||
drive-strength-28 = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc_iot_8bit_mode: emmc_iot_8bit_mode {
|
||||
ephy4_1_dis {
|
||||
groups = "ephy4_1_pad";
|
||||
function = "digital";
|
||||
};
|
||||
|
||||
emmc_en {
|
||||
groups = "sdmode";
|
||||
function = "sdxc";
|
||||
};
|
||||
|
||||
emmc_iot_mode {
|
||||
groups = "sd router";
|
||||
function = "iot";
|
||||
};
|
||||
|
||||
emmc_d4_d5 {
|
||||
groups = "uart2";
|
||||
function = "sdxc d5 d4";
|
||||
};
|
||||
|
||||
emmc_d6 {
|
||||
groups = "pwm1";
|
||||
function = "sdxc d6";
|
||||
};
|
||||
|
||||
emmc_d7 {
|
||||
groups = "pwm0";
|
||||
function = "sdxc d7";
|
||||
};
|
||||
|
||||
sd_clk_pad {
|
||||
pins = "sd_clk";
|
||||
drive-strength-4g = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
watchdog: watchdog@100 {
|
||||
compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
|
||||
reg = <0x100 0x30>;
|
||||
|
||||
resets = <&rstctrl MT7628_TIMER_RST>;
|
||||
reset-names = "wdt";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <24>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@200 {
|
||||
compatible = "ralink,rt2880-intc";
|
||||
reg = <0x200 0x100>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
resets = <&rstctrl MT7628_INT_RST>;
|
||||
reset-names = "intc";
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
|
||||
ralink,intc-registers = <0x9c 0xa0
|
||||
0x6c 0xa4
|
||||
0x80 0x78>;
|
||||
};
|
||||
|
||||
memory-controller@300 {
|
||||
compatible = "ralink,mt7620a-memc";
|
||||
reg = <0x300 0x100>;
|
||||
};
|
||||
|
||||
gpio@600 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
|
||||
reg = <0x600 0x100>;
|
||||
|
||||
resets = <&rstctrl MT7628_PIO_RST>;
|
||||
reset-names = "pio";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <6>;
|
||||
|
||||
gpio0: bank@0 {
|
||||
reg = <0>;
|
||||
compatible = "mtk,mt7621-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: bank@1 {
|
||||
reg = <1>;
|
||||
compatible = "mtk,mt7621-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: bank@2 {
|
||||
reg = <2>;
|
||||
compatible = "mtk,mt7621-gpio-bank";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@b00 {
|
||||
compatible = "ralink,mt7621-spi";
|
||||
reg = <0xb00 0x40>;
|
||||
|
||||
resets = <&rstctrl MT7628_SPI_RST>;
|
||||
reset-names = "spi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clocks = <&clkctrl CLK_SPI>;
|
||||
};
|
||||
|
||||
uart0: uartlite@c00 {
|
||||
compatible = "mediatek,hsuart", "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
clocks = <&clkctrl CLK_UART0>;
|
||||
|
||||
resets = <&rstctrl MT7628_UART0_RST>;
|
||||
reset-names = "uart0";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <20>;
|
||||
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
uart1: uart1@d00 {
|
||||
compatible = "mediatek,hsuart", "ns16550a";
|
||||
reg = <0xd00 0x100>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
|
||||
clocks = <&clkctrl CLK_UART1>;
|
||||
|
||||
resets = <&rstctrl MT7628_UART1_RST>;
|
||||
reset-names = "uart1";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <21>;
|
||||
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
uart2: uart2@e00 {
|
||||
compatible = "mediatek,hsuart", "ns16550a";
|
||||
reg = <0xe00 0x100>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
|
||||
clocks = <&clkctrl CLK_UART2>;
|
||||
|
||||
resets = <&rstctrl MT7628_UART2_RST>;
|
||||
reset-names = "uart2";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <22>;
|
||||
|
||||
reg-shift = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
eth: eth@10110000 {
|
||||
compatible = "mediatek,mt7628-eth";
|
||||
reg = <0x10100000 0x10000
|
||||
0x10110000 0x8000>;
|
||||
|
||||
resets = <&rstctrl MT7628_EPHY_RST>;
|
||||
reset-names = "ephy";
|
||||
|
||||
syscon = <&sysc>;
|
||||
};
|
||||
|
||||
usb_phy: usb-phy@10120000 {
|
||||
compatible = "mediatek,mt7628-usbphy";
|
||||
reg = <0x10120000 0x1000>;
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
ralink,sysctl = <&sysc>;
|
||||
|
||||
resets = <&rstctrl MT7628_UPHY_RST>;
|
||||
reset-names = "phy";
|
||||
|
||||
clocks = <&clkctrl CLK_UPHY>;
|
||||
clock-names = "cg";
|
||||
};
|
||||
|
||||
ehci@101c0000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x101c0000 0x1000>;
|
||||
|
||||
phys = <&usb_phy>;
|
||||
phy-names = "usb";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <18>;
|
||||
};
|
||||
|
||||
mmc: mmc@10130000 {
|
||||
compatible = "mediatek,mt7620-mmc";
|
||||
reg = <0x10130000 0x4000>;
|
||||
builtin-cd = <1>;
|
||||
r_smpl = <1>;
|
||||
|
||||
clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
|
||||
clock-names = "source", "hclk";
|
||||
|
||||
resets = <&rstctrl MT7628_SDXC_RST>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,32 @@
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x00000000 0x00001000; /* Exception vectors */
|
||||
/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mti,malta";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
isa@0 {
|
||||
compatible = "isa";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0 0 0x1000>;
|
||||
|
||||
uart0: serial@3f8 {
|
||||
compatible = "ns16550a";
|
||||
|
||||
reg = <1 0x3f8 0x40>;
|
||||
reg-shift = <0>;
|
||||
|
||||
clock-frequency = <1843200>;
|
||||
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,107 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm3380.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Netgear CG3100D";
|
||||
compatible = "netgear,cg3100d", "brcm,bcm3380";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
wifi_green {
|
||||
label = "CG3100D:green:wifi";
|
||||
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wps_green {
|
||||
label = "CG3100D:green:wps";
|
||||
gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power_red {
|
||||
label = "CG3100D:red:power";
|
||||
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&leds {
|
||||
status = "okay";
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
active-low;
|
||||
label = "CG3100D:green:power";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
active-low;
|
||||
label = "CG3100D:green:downlink";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
active-low;
|
||||
label = "CG3100D:orange:downlink";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
active-low;
|
||||
label = "CG3100D:green:uplink";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
reg = <4>;
|
||||
active-low;
|
||||
label = "CG3100D:orange:uplink";
|
||||
};
|
||||
|
||||
led@6 {
|
||||
reg = <6>;
|
||||
active-low;
|
||||
label = "CG3100D:green:inet";
|
||||
};
|
||||
|
||||
led@7 {
|
||||
reg = <7>;
|
||||
active-low;
|
||||
label = "CG3100D:green:stby";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,146 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm6362.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Netgear DGND3700v2";
|
||||
compatible = "netgear,dgnd3700v2", "brcm,bcm6362";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
inet_green {
|
||||
label = "DGND3700v2:green:inet";
|
||||
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
dsl_green {
|
||||
label = "DGND3700v2:green:dsl";
|
||||
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power_amber {
|
||||
label = "DGND3700v2:red:power";
|
||||
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet {
|
||||
status = "okay";
|
||||
|
||||
port@4 {
|
||||
compatible = "brcm,enetsw-port";
|
||||
reg = <4>;
|
||||
label = "rgmii";
|
||||
brcm,phy-id = <0xff>;
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
bypass-link;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&leds {
|
||||
status = "okay";
|
||||
brcm,serial-leds;
|
||||
brcm,serial-dat-low;
|
||||
brcm,serial-shift-inv;
|
||||
brcm,serial-mux;
|
||||
|
||||
led@8 {
|
||||
reg = <8>;
|
||||
label = "DGND3700v2:green:power";
|
||||
};
|
||||
|
||||
led@9 {
|
||||
reg = <9>;
|
||||
active-low;
|
||||
label = "DGND3700v2:green:wps";
|
||||
};
|
||||
|
||||
led@10 {
|
||||
reg = <10>;
|
||||
active-low;
|
||||
label = "DGND3700v2:green:usb1";
|
||||
};
|
||||
|
||||
led@11 {
|
||||
reg = <11>;
|
||||
active-low;
|
||||
label = "DGND3700v2:green:usb2";
|
||||
};
|
||||
|
||||
led@12 {
|
||||
reg = <12>;
|
||||
active-low;
|
||||
label = "DGND3700v2:amber:inet";
|
||||
};
|
||||
|
||||
led@13 {
|
||||
reg = <13>;
|
||||
active-low;
|
||||
label = "DGND3700v2:green:ethernet";
|
||||
};
|
||||
|
||||
led@14 {
|
||||
reg = <14>;
|
||||
active-low;
|
||||
label = "DGND3700v2:amber:dsl";
|
||||
};
|
||||
|
||||
led@16 {
|
||||
reg = <16>;
|
||||
active-low;
|
||||
label = "DGND3700v2:amber:usb1";
|
||||
};
|
||||
|
||||
led@17 {
|
||||
reg = <17>;
|
||||
active-low;
|
||||
label = "DGND3700v2:amber:usb2";
|
||||
};
|
||||
|
||||
led@18 {
|
||||
reg = <18>;
|
||||
active-low;
|
||||
label = "DGND3700v2:amber:ethernet";
|
||||
};
|
||||
};
|
||||
|
||||
&ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,61 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "microAptiv.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "digilent,nexys4ddr";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
|
||||
cpuintc: interrupt-controller@0 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
aliases {
|
||||
console = &axi_uart16550;
|
||||
};
|
||||
|
||||
axi_ethernetlite: ethernet@10e00000 {
|
||||
compatible = "xlnx,xps-ethernetlite-1.00.a";
|
||||
device_type = "network";
|
||||
local-mac-address = [08 86 4C 0D F7 09];
|
||||
phy-handle = <&phy0>;
|
||||
reg = <0x10e00000 0x10000>;
|
||||
xlnx,duplex = <0x1>;
|
||||
xlnx,include-global-buffers = <0x1>;
|
||||
xlnx,include-internal-loopback = <0x0>;
|
||||
xlnx,include-mdio = <0x1>;
|
||||
xlnx,instance = "axi_ethernetlite_inst";
|
||||
xlnx,rx-ping-pong = <0x1>;
|
||||
xlnx,s-axi-id-width = <0x1>;
|
||||
xlnx,tx-ping-pong = <0x1>;
|
||||
xlnx,use-internal = <0x0>;
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: phy@1 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <1>;
|
||||
} ;
|
||||
} ;
|
||||
} ;
|
||||
|
||||
|
||||
axi_uart16550: serial@10400000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x10400000 0x10000>;
|
||||
|
||||
reg-shift = <2>;
|
||||
reg-offset = <0x1000>;
|
||||
|
||||
clock-frequency = <50000000>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,163 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,ocelot_pcb.dtsi"
|
||||
#include <dt-bindings/mscc/ocelot_data.h>
|
||||
|
||||
/ {
|
||||
model = "Ocelot PCB120 Reference Board";
|
||||
compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
poe_green {
|
||||
label = "pcb120:green:poe";
|
||||
gpios = <&sgpio 44 1>; /* p12.1 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
poe_red {
|
||||
label = "pcb120:red:poe";
|
||||
gpios = <&sgpio 12 1>; /* p12.0 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
alarm_green {
|
||||
label = "pcb120:green:alarm";
|
||||
gpios = <&sgpio 45 1>; /* p13.1 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
alarm_red {
|
||||
label = "pcb120:red:alarm";
|
||||
gpios = <&sgpio 13 1>; /* p13.0 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
dc_a_green {
|
||||
label = "pcb120:green:dc_a";
|
||||
gpios = <&sgpio 46 1>; /* p14.1 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
dc_a_red {
|
||||
label = "pcb120:red:dc_a";
|
||||
gpios = <&sgpio 14 1>; /* p14.0 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
dc_b_green {
|
||||
label = "pcb120:green:dc_b";
|
||||
gpios = <&sgpio 47 1>; /* p15.1 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
dc_b_red {
|
||||
label = "pcb120:red:dc_b";
|
||||
gpios = <&sgpio 15 1>; /* p15.0 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
status_green {
|
||||
label = "pcb120:green:status";
|
||||
gpios = <&sgpio 48 1>; /* p16.1 */
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb120:red:alarm";
|
||||
gpios = <&sgpio 16 1>; /* p16.0 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
mscc,sgpio-ports = <0x000FFFFF>;
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <3>;
|
||||
};
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy6: ethernet-phy@6 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy7: ethernet-phy@7 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <3>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
port0: port@0 {
|
||||
reg = <5>;
|
||||
phy-handle = <&phy0>;
|
||||
phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <9>;
|
||||
phy-handle = <&phy1>;
|
||||
phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>;
|
||||
};
|
||||
port2: port@2 {
|
||||
reg = <6>;
|
||||
phy-handle = <&phy2>;
|
||||
phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>;
|
||||
};
|
||||
port3: port@3 {
|
||||
reg = <4>;
|
||||
phy-handle = <&phy3>;
|
||||
phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
|
||||
};
|
||||
port4: port@4 {
|
||||
reg = <3>;
|
||||
phy-handle = <&phy4>;
|
||||
};
|
||||
port5: port@5 {
|
||||
reg = <2>;
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
port6: port@6 {
|
||||
reg = <1>;
|
||||
phy-handle = <&phy6>;
|
||||
};
|
||||
port7: port@7 {
|
||||
reg = <0>;
|
||||
phy-handle = <&phy7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,75 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,ocelot_pcb.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ocelot PCB123 Reference Board";
|
||||
compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green {
|
||||
label = "pcb123:green:status";
|
||||
gpios = <&sgpio 43 1>; /* p11.1 */
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb123:red:status";
|
||||
gpios = <&sgpio 11 1>; /* p11.0 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
mscc,sgpio-ports = <0x00FFFFFF>;
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
port0: port@0 {
|
||||
reg = <2>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <3>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
port2: port@2 {
|
||||
reg = <0>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port3: port@3 {
|
||||
reg = <1>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,185 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2015 Microchip Technology, Inc.
|
||||
* Purna Chandra Mandal, <purna.mandal@microchip.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/microchip,clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "microchip,pic32mzda", "microchip,pic32mz";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpioA;
|
||||
gpio1 = &gpioB;
|
||||
gpio2 = &gpioC;
|
||||
gpio3 = &gpioD;
|
||||
gpio4 = &gpioE;
|
||||
gpio5 = &gpioF;
|
||||
gpio6 = &gpioG;
|
||||
gpio7 = &gpioH;
|
||||
gpio8 = &gpioJ;
|
||||
gpio9 = &gpioK;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "mips,mips14kc";
|
||||
};
|
||||
};
|
||||
|
||||
clock: clk@1f801200 {
|
||||
compatible = "microchip,pic32mzda-clk";
|
||||
reg = <0x1f801200 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1f822000 {
|
||||
compatible = "microchip,pic32mzda-uart";
|
||||
reg = <0x1f822000 0x50>;
|
||||
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&clock PB2CLK>;
|
||||
};
|
||||
|
||||
uart2: serial@1f822200 {
|
||||
compatible = "microchip,pic32mzda-uart";
|
||||
reg = <0x1f822200 0x50>;
|
||||
interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock PB2CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@1f822a00 {
|
||||
compatible = "microchip,pic32mzda-uart";
|
||||
reg = <0x1f822a00 0x50>;
|
||||
interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock PB2CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
evic: interrupt-controller@1f810000 {
|
||||
compatible = "microchip,pic32mzda-evic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1f810000 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@1f801400 {
|
||||
compatible = "microchip,pic32mzda-pinctrl";
|
||||
reg = <0x1f801400 0x100>, /* in */
|
||||
<0x1f801500 0x200>, /* out */
|
||||
<0x1f860000 0xa00>; /* port */
|
||||
reg-names = "ppsin","ppsout","port";
|
||||
status = "disabled";
|
||||
|
||||
ranges = <0 0x1f860000 0xa00>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
gpioA: gpio0@0 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x000 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioB: gpio1@100 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x100 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioC: gpio2@200 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x200 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioD: gpio3@300 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x300 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioE: gpio4@400 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x400 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioF: gpio5@500 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x500 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioG: gpio6@600 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x600 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioH: gpio7@700 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x700 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioJ: gpio8@800 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x800 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioK: gpio9@900 {
|
||||
compatible = "microchip,pic32mzda-gpio";
|
||||
reg = <0x900 0x48>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci: sdhci@1f8ec000 {
|
||||
compatible = "microchip,pic32mzda-sdhci";
|
||||
reg = <0x1f8ec000 0x100>;
|
||||
interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock REF4CLK>, <&clock PB5CLK>;
|
||||
clock-names = "base_clk", "sys_clk";
|
||||
clock-freq-min-max = <25000000>,<25000000>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet: ethernet@1f882000 {
|
||||
compatible = "microchip,pic32mzda-eth";
|
||||
reg = <0x1f882000 0x1000>;
|
||||
interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock PB5CLK>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
usb: musb@1f8e3000 {
|
||||
compatible = "microchip,pic32mzda-usb";
|
||||
reg = <0x1f8e3000 0x1000>,
|
||||
<0x1f884000 0x1000>;
|
||||
reg-names = "mc", "control";
|
||||
interrupts = <132 IRQ_TYPE_EDGE_RISING>,
|
||||
<133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock PB5CLK>;
|
||||
clock-names = "usb_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,58 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015 Purna Chandra Mandal, purna.mandal@microchip.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "pic32mzda.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Microchip PIC32MZDASK";
|
||||
compatible = "microchip,pic32mzdask", "microchip,pic32mzda";
|
||||
|
||||
aliases {
|
||||
console = &uart2;
|
||||
serial0 = &uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&clock {
|
||||
microchip,refo2-frequency = <50000000>;
|
||||
microchip,refo4-frequency = <25000000>;
|
||||
microchip,refo5-frequency = <40000000>;
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðernet {
|
||||
reset-gpios = <&gpioJ 15 0>;
|
||||
status = "okay";
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðernet_phy>;
|
||||
ethernet_phy: lan8740_phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,111 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "qca,qca953x";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "mips,mips24Kc";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
xtal: xtal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "xtal";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "qca,qca953x-pinctrl";
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x18040000 0x100>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
uart0: uart@18020000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x18020000 0x20>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <25000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: eth0@0x19000000 {
|
||||
compatible = "qca,ag953x-mac";
|
||||
reg = <0x19000000 0x200>;
|
||||
phy = <&phy4>;
|
||||
phy-mode = "rmii";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac1: eth1@0x1a000000 {
|
||||
compatible = "qca,ag953x-mac";
|
||||
reg = <0x1a000000 0x200>;
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@1f000000 {
|
||||
compatible = "qca,ar7100-spi";
|
||||
reg = <0x1f000000 0x10>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,87 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Rosy Song <rosysong@rosinson.com>
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "qca,qca956x";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "mips,mips74Kc";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
xtal: xtal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "xtal";
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
uart0: uart@18020000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x18020000 0x20>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: eth@0x19000000 {
|
||||
compatible = "qca,ag956x-mac";
|
||||
reg = <0x19000000 0x200>;
|
||||
phy = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@1f000000 {
|
||||
compatible = "qca,ar7100-spi";
|
||||
reg = <0x1f000000 0x10>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,73 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm6338.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sagem F@ST1704";
|
||||
compatible = "sagem,f@st1704", "brcm,bcm6338";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
inet_green {
|
||||
label = "F@ST1704:green:inet";
|
||||
gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power_green {
|
||||
label = "F@ST1704:green:power";
|
||||
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
inet_red {
|
||||
label = "F@ST1704:red:inet";
|
||||
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&enet {
|
||||
status = "okay";
|
||||
phy = <&enetphy>;
|
||||
phy-mode = "mii";
|
||||
|
||||
enetphy: fixed-link {
|
||||
reg = <1>;
|
||||
speed = <100>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,104 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,jr2.dtsi"
|
||||
#include <dt-bindings/mscc/jr2_data.h>
|
||||
|
||||
/ {
|
||||
model = "Serval2 NID PCB112 Reference Board";
|
||||
compatible = "mscc,serval2-pcb110", "mscc,jr2";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green {
|
||||
label = "pcb110:green:status";
|
||||
gpios = <&gpio 12 0>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb110:red:status";
|
||||
gpios = <&gpio 13 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <0>; /* CS0 */
|
||||
};
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
sgpio-ports = <0x0000ffff>;
|
||||
};
|
||||
|
||||
&sgpio2 {
|
||||
status = "okay";
|
||||
sgpio-ports = <0x3fe0ffff>;
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
|
||||
phy16: ethernet-phy@16 {
|
||||
reg = <16>;
|
||||
};
|
||||
phy17: ethernet-phy@17 {
|
||||
reg = <17>;
|
||||
};
|
||||
phy18: ethernet-phy@18 {
|
||||
reg = <18>;
|
||||
};
|
||||
phy19: ethernet-phy@19 {
|
||||
reg = <19>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
|
||||
port0: port@0 {
|
||||
reg = <24>;
|
||||
phy-handle = <&phy16>;
|
||||
phys = <&serdes_hsio 24 SERDES6G(0) PHY_MODE_SGMII>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <25>;
|
||||
phy-handle = <&phy17>;
|
||||
phys = <&serdes_hsio 25 SERDES6G(1) PHY_MODE_SGMII>;
|
||||
};
|
||||
port2: port@2 {
|
||||
reg = <26>;
|
||||
phy-handle = <&phy18>;
|
||||
phys = <&serdes_hsio 26 SERDES6G(2) PHY_MODE_SGMII>;
|
||||
};
|
||||
port3: port@3 {
|
||||
reg = <27>;
|
||||
phy-handle = <&phy19>;
|
||||
phys = <&serdes_hsio 27 SERDES6G(3) PHY_MODE_SGMII>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,100 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,serval.dtsi"
|
||||
#include <dt-bindings/mscc/serval_data.h>
|
||||
|
||||
/ {
|
||||
model = "Serval PCB105 Reference Board";
|
||||
compatible = "mscc,serval-pcb105", "mscc,serval";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green {
|
||||
label = "pcb105:green:status";
|
||||
gpios = <&sgpio 43 1>; /* p11.1 */
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb105:red:status";
|
||||
gpios = <&sgpio 11 1>; /* p11.0 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <0>; /* CS0 */
|
||||
spi-cs-high;
|
||||
};
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
sgpio-ports = <0x00FFFFFF>;
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
status = "okay";
|
||||
|
||||
phy16: ethernet-phy@16 {
|
||||
reg = <16>;
|
||||
};
|
||||
phy17: ethernet-phy@17 {
|
||||
reg = <17>;
|
||||
};
|
||||
phy18: ethernet-phy@18 {
|
||||
reg = <18>;
|
||||
};
|
||||
phy19: ethernet-phy@19 {
|
||||
reg = <19>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
|
||||
port0: port@0 {
|
||||
reg = <7>;
|
||||
phy-handle = <&phy16>;
|
||||
phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <6>;
|
||||
phy-handle = <&phy17>;
|
||||
phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
|
||||
};
|
||||
port2: port@2 {
|
||||
reg = <5>;
|
||||
phy-handle = <&phy18>;
|
||||
phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
|
||||
};
|
||||
port3: port@3 {
|
||||
reg = <4>;
|
||||
phy-handle = <&phy19>;
|
||||
phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,100 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,serval.dtsi"
|
||||
#include <dt-bindings/mscc/serval_data.h>
|
||||
|
||||
/ {
|
||||
model = "Serval PCB106 Reference Board";
|
||||
compatible = "mscc,serval-pcb106", "mscc,serval";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green {
|
||||
label = "pcb106:green:status";
|
||||
gpios = <&sgpio 43 1>; /* p11.1 */
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb106:red:status";
|
||||
gpios = <&sgpio 11 1>; /* p11.0 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <0>; /* CS0 */
|
||||
spi-cs-high;
|
||||
};
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
sgpio-ports = <0x00FFFFFF>;
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
status = "okay";
|
||||
|
||||
phy16: ethernet-phy@16 {
|
||||
reg = <16>;
|
||||
};
|
||||
phy17: ethernet-phy@17 {
|
||||
reg = <17>;
|
||||
};
|
||||
phy18: ethernet-phy@18 {
|
||||
reg = <18>;
|
||||
};
|
||||
phy19: ethernet-phy@19 {
|
||||
reg = <19>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
|
||||
port0: port@0 {
|
||||
reg = <7>;
|
||||
phy-handle = <&phy16>;
|
||||
phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <6>;
|
||||
phy-handle = <&phy17>;
|
||||
phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
|
||||
};
|
||||
port2: port@2 {
|
||||
reg = <5>;
|
||||
phy-handle = <&phy18>;
|
||||
phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
|
||||
};
|
||||
port3: port@3 {
|
||||
reg = <4>;
|
||||
phy-handle = <&phy19>;
|
||||
phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,81 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mscc,servalt.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ServalT PCB116 Reference Board";
|
||||
compatible = "mscc,servalt-pcb116", "mscc,servalt";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status_green {
|
||||
label = "pcb116:green:status";
|
||||
gpios = <&sgpio 70 0>; /* p6.2 */
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status_red {
|
||||
label = "pcb116:red:status";
|
||||
gpios = <&sgpio 102 0>; /* p6.3 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <18000000>; /* input clock */
|
||||
reg = <0>; /* CS0 */
|
||||
spi-cs-high;
|
||||
};
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
status = "okay";
|
||||
sgpio-ports = <0x0000fe7f>;
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ethernet-ports {
|
||||
|
||||
port0: port@0 {
|
||||
reg = <0>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
port1: port@1 {
|
||||
reg = <1>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,128 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "brcm,bcm6358.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SFR NeufBox 4 (Sercomm) Board";
|
||||
compatible = "sfr,nb4-ser", "brcm,bcm6358";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
traffic_white {
|
||||
label = "NB4-SER:white:traffic";
|
||||
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
service_blue {
|
||||
label = "NB4-SER:blue:service";
|
||||
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wifi_white {
|
||||
label = "NB4-SER:white:wifi";
|
||||
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
service_red {
|
||||
label = "NB4-SER:red:service";
|
||||
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
service_green {
|
||||
label = "NB4-SER:green:service";
|
||||
gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
phy = <&enet0phy>;
|
||||
phy-mode = "internal";
|
||||
|
||||
enet0phy: fixed-link {
|
||||
reg = <1>;
|
||||
speed = <100>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&enet1 {
|
||||
status = "okay";
|
||||
phy = <&enet1phy>;
|
||||
phy-mode = "mii";
|
||||
|
||||
enet1phy: fixed-link {
|
||||
reg = <1>;
|
||||
speed = <100>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&leds {
|
||||
status = "okay";
|
||||
brcm,clk-div = <1>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
active-low;
|
||||
label = "NB4-SER:white:alarm";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
active-low;
|
||||
label = "NB4-SER:white:tv";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
active-low;
|
||||
label = "NB4-SER:white:tel";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
reg = <4>;
|
||||
active-low;
|
||||
label = "NB4-SER:white:adsl";
|
||||
};
|
||||
};
|
||||
|
||||
&ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pflash {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Skeleton device tree; the bare minimum needed to boot; just include and
|
||||
* add a compatible value. The bootloader will typically populate the memory
|
||||
* node.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen {
|
||||
};
|
||||
|
||||
aliases {
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,52 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "ar934x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TP-Link WDR4300 Board";
|
||||
compatible = "tplink,wdr4300", "qca,ar934x";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
spi-max-frequency = <25000000>;
|
||||
status = "okay";
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
memory-map = <0x1e000000 0x00800000>;
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <40000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xtal {
|
||||
clock-frequency = <40000000>;
|
||||
};
|
||||
@@ -0,0 +1,164 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1996, 99 Ralf Baechle
|
||||
* Copyright (C) 2000, 2002 Maciej W. Rozycki
|
||||
* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef _ASM_ADDRSPACE_H
|
||||
#define _ASM_ADDRSPACE_H
|
||||
|
||||
#include <spaces.h>
|
||||
|
||||
/*
|
||||
* Configure language
|
||||
*/
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _ATYPE_
|
||||
#define _ATYPE32_
|
||||
#define _ATYPE64_
|
||||
#define _CONST64_(x) x
|
||||
#else
|
||||
#define _ATYPE_ __PTRDIFF_TYPE__
|
||||
#define _ATYPE32_ int
|
||||
#define _ATYPE64_ __s64
|
||||
#ifdef CONFIG_64BIT
|
||||
#define _CONST64_(x) x ## L
|
||||
#else
|
||||
#define _CONST64_(x) x ## LL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 32-bit MIPS address spaces
|
||||
*/
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _ACAST32_
|
||||
#define _ACAST64_
|
||||
#else
|
||||
#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
|
||||
#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Returns the kernel segment base of a given address
|
||||
*/
|
||||
#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
|
||||
|
||||
/*
|
||||
* Returns the physical address of a CKSEGx / XKPHYS address
|
||||
*/
|
||||
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
|
||||
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
|
||||
_CONST64_(0x0000ffffffffffff))
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
|
||||
/*
|
||||
* Memory segments (64bit kernel mode addresses)
|
||||
* The compatibility segments use the full 64-bit sign extended value. Note
|
||||
* the R8000 doesn't have them so don't reference these in generic MIPS code.
|
||||
*/
|
||||
#define XKUSEG _CONST64_(0x0000000000000000)
|
||||
#define XKSSEG _CONST64_(0x4000000000000000)
|
||||
#define XKPHYS _CONST64_(0x8000000000000000)
|
||||
#define XKSEG _CONST64_(0xc000000000000000)
|
||||
#define CKSEG0 _CONST64_(0xffffffff80000000)
|
||||
#define CKSEG1 _CONST64_(0xffffffffa0000000)
|
||||
#define CKSSEG _CONST64_(0xffffffffc0000000)
|
||||
#define CKSEG3 _CONST64_(0xffffffffe0000000)
|
||||
|
||||
#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
|
||||
#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
|
||||
#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
|
||||
#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
|
||||
|
||||
#else
|
||||
|
||||
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
|
||||
#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
|
||||
#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
|
||||
#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
|
||||
|
||||
/*
|
||||
* Map an address to a certain kernel segment
|
||||
*/
|
||||
#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
|
||||
#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
|
||||
#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
|
||||
#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
|
||||
|
||||
/*
|
||||
* Memory segments (32bit kernel mode addresses)
|
||||
* These are the traditional names used in the 32-bit universe.
|
||||
*/
|
||||
#define KUSEG 0x00000000
|
||||
#define KSEG0 0x80000000
|
||||
#define KSEG1 0xa0000000
|
||||
#define KSEG2 0xc0000000
|
||||
#define KSEG3 0xe0000000
|
||||
|
||||
#define CKUSEG 0x00000000
|
||||
#define CKSEG0 0x80000000
|
||||
#define CKSEG1 0xa0000000
|
||||
#define CKSEG2 0xc0000000
|
||||
#define CKSEG3 0xe0000000
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Cache modes for XKPHYS address conversion macros
|
||||
*/
|
||||
#define K_CALG_COH_EXCL1_NOL2 0
|
||||
#define K_CALG_COH_SHRL1_NOL2 1
|
||||
#define K_CALG_UNCACHED 2
|
||||
#define K_CALG_NONCOHERENT 3
|
||||
#define K_CALG_COH_EXCL 4
|
||||
#define K_CALG_COH_SHAREABLE 5
|
||||
#define K_CALG_NOTUSED 6
|
||||
#define K_CALG_UNCACHED_ACCEL 7
|
||||
|
||||
/*
|
||||
* 64-bit address conversions
|
||||
*/
|
||||
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
|
||||
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
|
||||
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
|
||||
#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
|
||||
(_CONST64_(cm) << 59) | (a))
|
||||
|
||||
/*
|
||||
* Returns the uncached address of a sdram address
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#if defined(CONFIG_TB0229)
|
||||
/* We use a 36 bit physical address map here and
|
||||
cannot access physical memory directly from core */
|
||||
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
|
||||
#else /* !CONFIG_TB0229 */
|
||||
#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
|
||||
#endif /* CONFIG_TB0229 */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
|
||||
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
|
||||
* R8000 implements most with its 48-bit physical address space.
|
||||
*/
|
||||
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
|
||||
|
||||
#ifndef CONFIG_CPU_R8000
|
||||
|
||||
/*
|
||||
* The R8000 doesn't have the 32-bit compat spaces so we don't define them
|
||||
* in order to catch bugs in the source code.
|
||||
*/
|
||||
|
||||
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
|
||||
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
|
||||
|
||||
#endif
|
||||
|
||||
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
|
||||
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
|
||||
|
||||
#endif /* _ASM_ADDRSPACE_H */
|
||||
@@ -0,0 +1,3 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#include <generated/asm-offsets.h>
|
||||
@@ -0,0 +1,424 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
|
||||
* Copyright (C) 1999 by Silicon Graphics, Inc.
|
||||
* Copyright (C) 2001 MIPS Technologies, Inc.
|
||||
* Copyright (C) 2002 Maciej W. Rozycki
|
||||
*
|
||||
* Some useful macros for MIPS assembler code
|
||||
*
|
||||
* Some of the routines below contain useless nops that will be optimized
|
||||
* away by gas in -O mode. These nops are however required to fill delay
|
||||
* slots in noreorder mode.
|
||||
*/
|
||||
#ifndef __ASM_ASM_H
|
||||
#define __ASM_ASM_H
|
||||
|
||||
#include <asm/sgidefs.h>
|
||||
|
||||
#ifndef CAT
|
||||
#ifdef __STDC__
|
||||
#define __CAT(str1, str2) str1##str2
|
||||
#else
|
||||
#define __CAT(str1, str2) str1/**/str2
|
||||
#endif
|
||||
#define CAT(str1, str2) __CAT(str1, str2)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PIC specific declarations
|
||||
* Not used for the kernel but here seems to be the right place.
|
||||
*/
|
||||
#ifdef __PIC__
|
||||
#define CPRESTORE(register) \
|
||||
.cprestore register
|
||||
#define CPADD(register) \
|
||||
.cpadd register
|
||||
#define CPLOAD(register) \
|
||||
.cpload register
|
||||
#else
|
||||
#define CPRESTORE(register)
|
||||
#define CPADD(register)
|
||||
#define CPLOAD(register)
|
||||
#endif
|
||||
|
||||
#define ENTRY(symbol) \
|
||||
.globl symbol; \
|
||||
.type symbol, @function; \
|
||||
.ent symbol, 0; \
|
||||
symbol:
|
||||
|
||||
/*
|
||||
* LEAF - declare leaf routine
|
||||
*/
|
||||
#define LEAF(symbol) \
|
||||
.globl symbol; \
|
||||
.align 2; \
|
||||
.type symbol, @function; \
|
||||
.ent symbol, 0; \
|
||||
.section .text.symbol, "x"; \
|
||||
symbol: .frame sp, 0, ra
|
||||
|
||||
/*
|
||||
* NESTED - declare nested routine entry point
|
||||
*/
|
||||
#define NESTED(symbol, framesize, rpc) \
|
||||
.globl symbol; \
|
||||
.align 2; \
|
||||
.type symbol, @function; \
|
||||
.ent symbol, 0; \
|
||||
.section .text.symbol, "x"; \
|
||||
symbol: .frame sp, framesize, rpc
|
||||
|
||||
/*
|
||||
* END - mark end of function
|
||||
*/
|
||||
#define END(function) \
|
||||
.end function; \
|
||||
.size function, .-function
|
||||
|
||||
/*
|
||||
* EXPORT - export definition of symbol
|
||||
*/
|
||||
#define EXPORT(symbol) \
|
||||
.globl symbol; \
|
||||
symbol:
|
||||
|
||||
/*
|
||||
* FEXPORT - export definition of a function symbol
|
||||
*/
|
||||
#define FEXPORT(symbol) \
|
||||
.globl symbol; \
|
||||
.type symbol, @function; \
|
||||
symbol:
|
||||
|
||||
/*
|
||||
* ABS - export absolute symbol
|
||||
*/
|
||||
#define ABS(symbol,value) \
|
||||
.globl symbol; \
|
||||
symbol = value
|
||||
|
||||
#define PANIC(msg) \
|
||||
.set push; \
|
||||
.set reorder; \
|
||||
PTR_LA a0, 8f; \
|
||||
jal panic; \
|
||||
9: b 9b; \
|
||||
.set pop; \
|
||||
TEXT(msg)
|
||||
|
||||
/*
|
||||
* Print formatted string
|
||||
*/
|
||||
#ifdef CONFIG_PRINTK
|
||||
#define PRINT(string) \
|
||||
.set push; \
|
||||
.set reorder; \
|
||||
PTR_LA a0, 8f; \
|
||||
jal printk; \
|
||||
.set pop; \
|
||||
TEXT(string)
|
||||
#else
|
||||
#define PRINT(string)
|
||||
#endif
|
||||
|
||||
#define TEXT(msg) \
|
||||
.pushsection .data; \
|
||||
8: .asciiz msg; \
|
||||
.popsection;
|
||||
|
||||
/*
|
||||
* Build text tables
|
||||
*/
|
||||
#define TTABLE(string) \
|
||||
.pushsection .text; \
|
||||
.word 1f; \
|
||||
.popsection \
|
||||
.pushsection .data; \
|
||||
1: .asciiz string; \
|
||||
.popsection
|
||||
|
||||
/*
|
||||
* MIPS IV pref instruction.
|
||||
* Use with .set noreorder only!
|
||||
*
|
||||
* MIPS IV implementations are free to treat this as a nop. The R5000
|
||||
* is one of them. So we should have an option not to use this instruction.
|
||||
*/
|
||||
#ifdef CONFIG_CPU_HAS_PREFETCH
|
||||
|
||||
#define PREF(hint, addr) \
|
||||
.set push; \
|
||||
.set arch=r5000; \
|
||||
pref hint, addr; \
|
||||
.set pop
|
||||
|
||||
#define PREFE(hint, addr) \
|
||||
.set push; \
|
||||
.set mips0; \
|
||||
.set eva; \
|
||||
prefe hint, addr; \
|
||||
.set pop
|
||||
|
||||
#define PREFX(hint, addr) \
|
||||
.set push; \
|
||||
.set arch=r5000; \
|
||||
prefx hint, addr; \
|
||||
.set pop
|
||||
|
||||
#else /* !CONFIG_CPU_HAS_PREFETCH */
|
||||
|
||||
#define PREF(hint, addr)
|
||||
#define PREFE(hint, addr)
|
||||
#define PREFX(hint, addr)
|
||||
|
||||
#endif /* !CONFIG_CPU_HAS_PREFETCH */
|
||||
|
||||
/*
|
||||
* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
|
||||
*/
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
|
||||
#define MOVN(rd, rs, rt) \
|
||||
.set push; \
|
||||
.set reorder; \
|
||||
beqz rt, 9f; \
|
||||
move rd, rs; \
|
||||
.set pop; \
|
||||
9:
|
||||
#define MOVZ(rd, rs, rt) \
|
||||
.set push; \
|
||||
.set reorder; \
|
||||
bnez rt, 9f; \
|
||||
move rd, rs; \
|
||||
.set pop; \
|
||||
9:
|
||||
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
|
||||
#define MOVN(rd, rs, rt) \
|
||||
.set push; \
|
||||
.set noreorder; \
|
||||
bnezl rt, 9f; \
|
||||
move rd, rs; \
|
||||
.set pop; \
|
||||
9:
|
||||
#define MOVZ(rd, rs, rt) \
|
||||
.set push; \
|
||||
.set noreorder; \
|
||||
beqzl rt, 9f; \
|
||||
move rd, rs; \
|
||||
.set pop; \
|
||||
9:
|
||||
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
|
||||
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
|
||||
#define MOVN(rd, rs, rt) \
|
||||
movn rd, rs, rt
|
||||
#define MOVZ(rd, rs, rt) \
|
||||
movz rd, rs, rt
|
||||
#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
|
||||
|
||||
/*
|
||||
* Stack alignment
|
||||
*/
|
||||
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
|
||||
#define ALSZ 7
|
||||
#define ALMASK ~7
|
||||
#endif
|
||||
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
|
||||
#define ALSZ 15
|
||||
#define ALMASK ~15
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macros to handle different pointer/register sizes for 32/64-bit code
|
||||
*/
|
||||
|
||||
/*
|
||||
* Size of a register
|
||||
*/
|
||||
#ifdef __mips64
|
||||
#define SZREG 8
|
||||
#else
|
||||
#define SZREG 4
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Use the following macros in assemblercode to load/store registers,
|
||||
* pointers etc.
|
||||
*/
|
||||
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
|
||||
#define REG_S sw
|
||||
#define REG_L lw
|
||||
#define REG_SUBU subu
|
||||
#define REG_ADDU addu
|
||||
#endif
|
||||
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
|
||||
#define REG_S sd
|
||||
#define REG_L ld
|
||||
#define REG_SUBU dsubu
|
||||
#define REG_ADDU daddu
|
||||
#endif
|
||||
|
||||
/*
|
||||
* How to add/sub/load/store/shift C int variables.
|
||||
*/
|
||||
#if (_MIPS_SZINT == 32)
|
||||
#define INT_ADD add
|
||||
#define INT_ADDU addu
|
||||
#define INT_ADDI addi
|
||||
#define INT_ADDIU addiu
|
||||
#define INT_SUB sub
|
||||
#define INT_SUBU subu
|
||||
#define INT_L lw
|
||||
#define INT_S sw
|
||||
#define INT_SLL sll
|
||||
#define INT_SLLV sllv
|
||||
#define INT_SRL srl
|
||||
#define INT_SRLV srlv
|
||||
#define INT_SRA sra
|
||||
#define INT_SRAV srav
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SZINT == 64)
|
||||
#define INT_ADD dadd
|
||||
#define INT_ADDU daddu
|
||||
#define INT_ADDI daddi
|
||||
#define INT_ADDIU daddiu
|
||||
#define INT_SUB dsub
|
||||
#define INT_SUBU dsubu
|
||||
#define INT_L ld
|
||||
#define INT_S sd
|
||||
#define INT_SLL dsll
|
||||
#define INT_SLLV dsllv
|
||||
#define INT_SRL dsrl
|
||||
#define INT_SRLV dsrlv
|
||||
#define INT_SRA dsra
|
||||
#define INT_SRAV dsrav
|
||||
#endif
|
||||
|
||||
/*
|
||||
* How to add/sub/load/store/shift C long variables.
|
||||
*/
|
||||
#if (_MIPS_SZLONG == 32)
|
||||
#define LONG_ADD add
|
||||
#define LONG_ADDU addu
|
||||
#define LONG_ADDI addi
|
||||
#define LONG_ADDIU addiu
|
||||
#define LONG_SUB sub
|
||||
#define LONG_SUBU subu
|
||||
#define LONG_L lw
|
||||
#define LONG_S sw
|
||||
#define LONG_SP swp
|
||||
#define LONG_SLL sll
|
||||
#define LONG_SLLV sllv
|
||||
#define LONG_SRL srl
|
||||
#define LONG_SRLV srlv
|
||||
#define LONG_SRA sra
|
||||
#define LONG_SRAV srav
|
||||
|
||||
#define LONG .word
|
||||
#define LONGSIZE 4
|
||||
#define LONGMASK 3
|
||||
#define LONGLOG 2
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SZLONG == 64)
|
||||
#define LONG_ADD dadd
|
||||
#define LONG_ADDU daddu
|
||||
#define LONG_ADDI daddi
|
||||
#define LONG_ADDIU daddiu
|
||||
#define LONG_SUB dsub
|
||||
#define LONG_SUBU dsubu
|
||||
#define LONG_L ld
|
||||
#define LONG_S sd
|
||||
#define LONG_SP sdp
|
||||
#define LONG_SLL dsll
|
||||
#define LONG_SLLV dsllv
|
||||
#define LONG_SRL dsrl
|
||||
#define LONG_SRLV dsrlv
|
||||
#define LONG_SRA dsra
|
||||
#define LONG_SRAV dsrav
|
||||
|
||||
#define LONG .dword
|
||||
#define LONGSIZE 8
|
||||
#define LONGMASK 7
|
||||
#define LONGLOG 3
|
||||
#endif
|
||||
|
||||
/*
|
||||
* How to add/sub/load/store/shift pointers.
|
||||
*/
|
||||
#if (_MIPS_SZPTR == 32)
|
||||
#define PTR_ADD add
|
||||
#define PTR_ADDU addu
|
||||
#define PTR_ADDI addi
|
||||
#define PTR_ADDIU addiu
|
||||
#define PTR_SUB sub
|
||||
#define PTR_SUBU subu
|
||||
#define PTR_L lw
|
||||
#define PTR_S sw
|
||||
#define PTR_LA la
|
||||
#define PTR_LI li
|
||||
#define PTR_SLL sll
|
||||
#define PTR_SLLV sllv
|
||||
#define PTR_SRL srl
|
||||
#define PTR_SRLV srlv
|
||||
#define PTR_SRA sra
|
||||
#define PTR_SRAV srav
|
||||
|
||||
#define PTR_SCALESHIFT 2
|
||||
|
||||
#define PTR .word
|
||||
#define PTRSIZE 4
|
||||
#define PTRLOG 2
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SZPTR == 64)
|
||||
#define PTR_ADD dadd
|
||||
#define PTR_ADDU daddu
|
||||
#define PTR_ADDI daddi
|
||||
#define PTR_ADDIU daddiu
|
||||
#define PTR_SUB dsub
|
||||
#define PTR_SUBU dsubu
|
||||
#define PTR_L ld
|
||||
#define PTR_S sd
|
||||
#define PTR_LA dla
|
||||
#define PTR_LI dli
|
||||
#define PTR_SLL dsll
|
||||
#define PTR_SLLV dsllv
|
||||
#define PTR_SRL dsrl
|
||||
#define PTR_SRLV dsrlv
|
||||
#define PTR_SRA dsra
|
||||
#define PTR_SRAV dsrav
|
||||
|
||||
#define PTR_SCALESHIFT 3
|
||||
|
||||
#define PTR .dword
|
||||
#define PTRSIZE 8
|
||||
#define PTRLOG 3
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some cp0 registers were extended to 64bit for MIPS III.
|
||||
*/
|
||||
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
|
||||
#define MFC0 mfc0
|
||||
#define MTC0 mtc0
|
||||
#endif
|
||||
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
|
||||
#define MFC0 dmfc0
|
||||
#define MTC0 dmtc0
|
||||
#endif
|
||||
|
||||
#define SSNOP sll zero, zero, 1
|
||||
|
||||
#ifdef CONFIG_SGI_IP28
|
||||
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
|
||||
#include <asm/cacheops.h>
|
||||
#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
|
||||
#else
|
||||
#define R10KCBARRIER(addr)
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ASM_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Cadence Design Systems Inc.
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ATOMIC_H
|
||||
#define _MIPS_ATOMIC_H
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm-generic/atomic.h>
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,903 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org)
|
||||
* Copyright (c) 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef _ASM_BITOPS_H
|
||||
#define _ASM_BITOPS_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/byteorder.h> /* sigh ... */
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <asm/sgidefs.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
#include <asm-generic/bitops/fls.h>
|
||||
#include <asm-generic/bitops/__fls.h>
|
||||
#include <asm-generic/bitops/fls64.h>
|
||||
#include <asm-generic/bitops/__ffs.h>
|
||||
|
||||
/*
|
||||
* clear_bit() doesn't provide any barrier for the compiler.
|
||||
*/
|
||||
#define smp_mb__before_clear_bit() barrier()
|
||||
#define smp_mb__after_clear_bit() barrier()
|
||||
|
||||
/*
|
||||
* Only disable interrupt for kernel mode stuff to keep usermode stuff
|
||||
* that dares to use kernel include files alive.
|
||||
*/
|
||||
#define __bi_flags unsigned long flags
|
||||
#define __bi_cli() __cli()
|
||||
#define __bi_save_flags(x) __save_flags(x)
|
||||
#define __bi_save_and_cli(x) __save_and_cli(x)
|
||||
#define __bi_restore_flags(x) __restore_flags(x)
|
||||
#else
|
||||
#define __bi_flags
|
||||
#define __bi_cli()
|
||||
#define __bi_save_flags(x)
|
||||
#define __bi_save_and_cli(x)
|
||||
#define __bi_restore_flags(x)
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_LLSC
|
||||
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
/*
|
||||
* These functions for MIPS ISA > 1 are interrupt and SMP proof and
|
||||
* interrupt friendly
|
||||
*/
|
||||
|
||||
/*
|
||||
* set_bit - Atomically set a bit in memory
|
||||
* @nr: the bit to set
|
||||
* @addr: the address to start counting from
|
||||
*
|
||||
* This function is atomic and may not be reordered. See __set_bit()
|
||||
* if you do not require the atomic guarantees.
|
||||
* Note that @nr may be almost arbitrarily large; this function is not
|
||||
* restricted to acting on a single-word quantity.
|
||||
*/
|
||||
static __inline__ void
|
||||
set_bit(int nr, volatile void *addr)
|
||||
{
|
||||
unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
|
||||
unsigned long temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1:\tll\t%0, %1\t\t# set_bit\n\t"
|
||||
"or\t%0, %2\n\t"
|
||||
"sc\t%0, %1\n\t"
|
||||
"beqz\t%0, 1b"
|
||||
: "=&r" (temp), "=m" (*m)
|
||||
: "ir" (1UL << (nr & 0x1f)), "m" (*m));
|
||||
}
|
||||
|
||||
/*
|
||||
* __set_bit - Set a bit in memory
|
||||
* @nr: the bit to set
|
||||
* @addr: the address to start counting from
|
||||
*
|
||||
* Unlike set_bit(), this function is non-atomic and may be reordered.
|
||||
* If it's called on the same region of memory simultaneously, the effect
|
||||
* may be that only one operation succeeds.
|
||||
*/
|
||||
static __inline__ void __set_bit(int nr, volatile void * addr)
|
||||
{
|
||||
unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
|
||||
|
||||
*m |= 1UL << (nr & 31);
|
||||
}
|
||||
#define PLATFORM__SET_BIT
|
||||
|
||||
/*
|
||||
* clear_bit - Clears a bit in memory
|
||||
* @nr: Bit to clear
|
||||
* @addr: Address to start counting from
|
||||
*
|
||||
* clear_bit() is atomic and may not be reordered. However, it does
|
||||
* not contain a memory barrier, so if it is used for locking purposes,
|
||||
* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
|
||||
* in order to ensure changes are visible on other processors.
|
||||
*/
|
||||
static __inline__ void
|
||||
clear_bit(int nr, volatile void *addr)
|
||||
{
|
||||
unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
|
||||
unsigned long temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1:\tll\t%0, %1\t\t# clear_bit\n\t"
|
||||
"and\t%0, %2\n\t"
|
||||
"sc\t%0, %1\n\t"
|
||||
"beqz\t%0, 1b\n\t"
|
||||
: "=&r" (temp), "=m" (*m)
|
||||
: "ir" (~(1UL << (nr & 0x1f))), "m" (*m));
|
||||
}
|
||||
|
||||
/*
|
||||
* change_bit - Toggle a bit in memory
|
||||
* @nr: Bit to clear
|
||||
* @addr: Address to start counting from
|
||||
*
|
||||
* change_bit() is atomic and may not be reordered.
|
||||
* Note that @nr may be almost arbitrarily large; this function is not
|
||||
* restricted to acting on a single-word quantity.
|
||||
*/
|
||||
static __inline__ void
|
||||
change_bit(int nr, volatile void *addr)
|
||||
{
|
||||
unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
|
||||
unsigned long temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1:\tll\t%0, %1\t\t# change_bit\n\t"
|
||||
"xor\t%0, %2\n\t"
|
||||
"sc\t%0, %1\n\t"
|
||||
"beqz\t%0, 1b"
|
||||
: "=&r" (temp), "=m" (*m)
|
||||
: "ir" (1UL << (nr & 0x1f)), "m" (*m));
|
||||
}
|
||||
|
||||
/*
|
||||
* __change_bit - Toggle a bit in memory
|
||||
* @nr: the bit to set
|
||||
* @addr: the address to start counting from
|
||||
*
|
||||
* Unlike change_bit(), this function is non-atomic and may be reordered.
|
||||
* If it's called on the same region of memory simultaneously, the effect
|
||||
* may be that only one operation succeeds.
|
||||
*/
|
||||
static __inline__ void __change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
|
||||
|
||||
*m ^= 1UL << (nr & 31);
|
||||
}
|
||||
|
||||
/*
|
||||
* test_and_set_bit - Set a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is atomic and cannot be reordered.
|
||||
* It also implies a memory barrier.
|
||||
*/
|
||||
static __inline__ int
|
||||
test_and_set_bit(int nr, volatile void *addr)
|
||||
{
|
||||
unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
|
||||
unsigned long temp, res;
|
||||
|
||||
__asm__ __volatile__(
|
||||
".set\tnoreorder\t\t# test_and_set_bit\n"
|
||||
"1:\tll\t%0, %1\n\t"
|
||||
"or\t%2, %0, %3\n\t"
|
||||
"sc\t%2, %1\n\t"
|
||||
"beqz\t%2, 1b\n\t"
|
||||
" and\t%2, %0, %3\n\t"
|
||||
".set\treorder"
|
||||
: "=&r" (temp), "=m" (*m), "=&r" (res)
|
||||
: "r" (1UL << (nr & 0x1f)), "m" (*m)
|
||||
: "memory");
|
||||
|
||||
return res != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* __test_and_set_bit - Set a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is non-atomic and can be reordered.
|
||||
* If two examples of this operation race, one can appear to succeed
|
||||
* but actually fail. You must protect multiple accesses with a lock.
|
||||
*/
|
||||
static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile int *a = addr;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
retval = (mask & *a) != 0;
|
||||
*a |= mask;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* test_and_clear_bit - Clear a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is atomic and cannot be reordered.
|
||||
* It also implies a memory barrier.
|
||||
*/
|
||||
static __inline__ int
|
||||
test_and_clear_bit(int nr, volatile void *addr)
|
||||
{
|
||||
unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
|
||||
unsigned long temp, res;
|
||||
|
||||
__asm__ __volatile__(
|
||||
".set\tnoreorder\t\t# test_and_clear_bit\n"
|
||||
"1:\tll\t%0, %1\n\t"
|
||||
"or\t%2, %0, %3\n\t"
|
||||
"xor\t%2, %3\n\t"
|
||||
"sc\t%2, %1\n\t"
|
||||
"beqz\t%2, 1b\n\t"
|
||||
" and\t%2, %0, %3\n\t"
|
||||
".set\treorder"
|
||||
: "=&r" (temp), "=m" (*m), "=&r" (res)
|
||||
: "r" (1UL << (nr & 0x1f)), "m" (*m)
|
||||
: "memory");
|
||||
|
||||
return res != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* __test_and_clear_bit - Clear a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is non-atomic and can be reordered.
|
||||
* If two examples of this operation race, one can appear to succeed
|
||||
* but actually fail. You must protect multiple accesses with a lock.
|
||||
*/
|
||||
static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile int *a = addr;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
retval = (mask & *a) != 0;
|
||||
*a &= ~mask;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* test_and_change_bit - Change a bit and return its new value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is atomic and cannot be reordered.
|
||||
* It also implies a memory barrier.
|
||||
*/
|
||||
static __inline__ int
|
||||
test_and_change_bit(int nr, volatile void *addr)
|
||||
{
|
||||
unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
|
||||
unsigned long temp, res;
|
||||
|
||||
__asm__ __volatile__(
|
||||
".set\tnoreorder\t\t# test_and_change_bit\n"
|
||||
"1:\tll\t%0, %1\n\t"
|
||||
"xor\t%2, %0, %3\n\t"
|
||||
"sc\t%2, %1\n\t"
|
||||
"beqz\t%2, 1b\n\t"
|
||||
" and\t%2, %0, %3\n\t"
|
||||
".set\treorder"
|
||||
: "=&r" (temp), "=m" (*m), "=&r" (res)
|
||||
: "r" (1UL << (nr & 0x1f)), "m" (*m)
|
||||
: "memory");
|
||||
|
||||
return res != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* __test_and_change_bit - Change a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is non-atomic and can be reordered.
|
||||
* If two examples of this operation race, one can appear to succeed
|
||||
* but actually fail. You must protect multiple accesses with a lock.
|
||||
*/
|
||||
static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile int *a = addr;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
retval = (mask & *a) != 0;
|
||||
*a ^= mask;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
#else /* MIPS I */
|
||||
|
||||
/*
|
||||
* set_bit - Atomically set a bit in memory
|
||||
* @nr: the bit to set
|
||||
* @addr: the address to start counting from
|
||||
*
|
||||
* This function is atomic and may not be reordered. See __set_bit()
|
||||
* if you do not require the atomic guarantees.
|
||||
* Note that @nr may be almost arbitrarily large; this function is not
|
||||
* restricted to acting on a single-word quantity.
|
||||
*/
|
||||
static __inline__ void set_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask;
|
||||
volatile int *a = addr;
|
||||
__bi_flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
__bi_save_and_cli(flags);
|
||||
*a |= mask;
|
||||
__bi_restore_flags(flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* __set_bit - Set a bit in memory
|
||||
* @nr: the bit to set
|
||||
* @addr: the address to start counting from
|
||||
*
|
||||
* Unlike set_bit(), this function is non-atomic and may be reordered.
|
||||
* If it's called on the same region of memory simultaneously, the effect
|
||||
* may be that only one operation succeeds.
|
||||
*/
|
||||
static __inline__ void __set_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask;
|
||||
volatile int *a = addr;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
*a |= mask;
|
||||
}
|
||||
|
||||
/*
|
||||
* clear_bit - Clears a bit in memory
|
||||
* @nr: Bit to clear
|
||||
* @addr: Address to start counting from
|
||||
*
|
||||
* clear_bit() is atomic and may not be reordered. However, it does
|
||||
* not contain a memory barrier, so if it is used for locking purposes,
|
||||
* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
|
||||
* in order to ensure changes are visible on other processors.
|
||||
*/
|
||||
static __inline__ void clear_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask;
|
||||
volatile int *a = addr;
|
||||
__bi_flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
__bi_save_and_cli(flags);
|
||||
*a &= ~mask;
|
||||
__bi_restore_flags(flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* change_bit - Toggle a bit in memory
|
||||
* @nr: Bit to clear
|
||||
* @addr: Address to start counting from
|
||||
*
|
||||
* change_bit() is atomic and may not be reordered.
|
||||
* Note that @nr may be almost arbitrarily large; this function is not
|
||||
* restricted to acting on a single-word quantity.
|
||||
*/
|
||||
static __inline__ void change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask;
|
||||
volatile int *a = addr;
|
||||
__bi_flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
__bi_save_and_cli(flags);
|
||||
*a ^= mask;
|
||||
__bi_restore_flags(flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* __change_bit - Toggle a bit in memory
|
||||
* @nr: the bit to set
|
||||
* @addr: the address to start counting from
|
||||
*
|
||||
* Unlike change_bit(), this function is non-atomic and may be reordered.
|
||||
* If it's called on the same region of memory simultaneously, the effect
|
||||
* may be that only one operation succeeds.
|
||||
*/
|
||||
static __inline__ void __change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
|
||||
|
||||
*m ^= 1UL << (nr & 31);
|
||||
}
|
||||
|
||||
/*
|
||||
* test_and_set_bit - Set a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is atomic and cannot be reordered.
|
||||
* It also implies a memory barrier.
|
||||
*/
|
||||
static __inline__ int test_and_set_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile int *a = addr;
|
||||
__bi_flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
__bi_save_and_cli(flags);
|
||||
retval = (mask & *a) != 0;
|
||||
*a |= mask;
|
||||
__bi_restore_flags(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* __test_and_set_bit - Set a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is non-atomic and can be reordered.
|
||||
* If two examples of this operation race, one can appear to succeed
|
||||
* but actually fail. You must protect multiple accesses with a lock.
|
||||
*/
|
||||
static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile int *a = addr;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
retval = (mask & *a) != 0;
|
||||
*a |= mask;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* test_and_clear_bit - Clear a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is atomic and cannot be reordered.
|
||||
* It also implies a memory barrier.
|
||||
*/
|
||||
static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile int *a = addr;
|
||||
__bi_flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
__bi_save_and_cli(flags);
|
||||
retval = (mask & *a) != 0;
|
||||
*a &= ~mask;
|
||||
__bi_restore_flags(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* __test_and_clear_bit - Clear a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is non-atomic and can be reordered.
|
||||
* If two examples of this operation race, one can appear to succeed
|
||||
* but actually fail. You must protect multiple accesses with a lock.
|
||||
*/
|
||||
static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile int *a = addr;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
retval = (mask & *a) != 0;
|
||||
*a &= ~mask;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* test_and_change_bit - Change a bit and return its new value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is atomic and cannot be reordered.
|
||||
* It also implies a memory barrier.
|
||||
*/
|
||||
static __inline__ int test_and_change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile int *a = addr;
|
||||
__bi_flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
__bi_save_and_cli(flags);
|
||||
retval = (mask & *a) != 0;
|
||||
*a ^= mask;
|
||||
__bi_restore_flags(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* __test_and_change_bit - Change a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is non-atomic and can be reordered.
|
||||
* If two examples of this operation race, one can appear to succeed
|
||||
* but actually fail. You must protect multiple accesses with a lock.
|
||||
*/
|
||||
static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile int *a = addr;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
retval = (mask & *a) != 0;
|
||||
*a ^= mask;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
#undef __bi_flags
|
||||
#undef __bi_cli
|
||||
#undef __bi_save_flags
|
||||
#undef __bi_restore_flags
|
||||
|
||||
#endif /* MIPS I */
|
||||
|
||||
/*
|
||||
* test_bit - Determine whether a bit is set
|
||||
* @nr: bit number to test
|
||||
* @addr: Address to start counting from
|
||||
*/
|
||||
static __inline__ int test_bit(int nr, const volatile void *addr)
|
||||
{
|
||||
return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0;
|
||||
}
|
||||
|
||||
#ifndef __MIPSEB__
|
||||
|
||||
/* Little endian versions. */
|
||||
|
||||
/*
|
||||
* find_first_zero_bit - find the first zero bit in a memory region
|
||||
* @addr: The address to start the search at
|
||||
* @size: The maximum size to search
|
||||
*
|
||||
* Returns the bit-number of the first zero bit, not the number of the byte
|
||||
* containing a bit.
|
||||
*/
|
||||
static __inline__ int find_first_zero_bit (void *addr, unsigned size)
|
||||
{
|
||||
unsigned long dummy;
|
||||
int res;
|
||||
|
||||
if (!size)
|
||||
return 0;
|
||||
|
||||
__asm__ (".set\tnoreorder\n\t"
|
||||
".set\tnoat\n"
|
||||
"1:\tsubu\t$1,%6,%0\n\t"
|
||||
"blez\t$1,2f\n\t"
|
||||
"lw\t$1,(%5)\n\t"
|
||||
"addiu\t%5,4\n\t"
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS2 ) || (_MIPS_ISA == _MIPS_ISA_MIPS3 ) || \
|
||||
(_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5 ) || \
|
||||
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
|
||||
"beql\t%1,$1,1b\n\t"
|
||||
"addiu\t%0,32\n\t"
|
||||
#else
|
||||
"addiu\t%0,32\n\t"
|
||||
"beq\t%1,$1,1b\n\t"
|
||||
"nop\n\t"
|
||||
"subu\t%0,32\n\t"
|
||||
#endif
|
||||
#ifdef __MIPSEB__
|
||||
#error "Fix this for big endian"
|
||||
#endif /* __MIPSEB__ */
|
||||
"li\t%1,1\n"
|
||||
"1:\tand\t%2,$1,%1\n\t"
|
||||
"beqz\t%2,2f\n\t"
|
||||
"sll\t%1,%1,1\n\t"
|
||||
"bnez\t%1,1b\n\t"
|
||||
"add\t%0,%0,1\n\t"
|
||||
".set\tat\n\t"
|
||||
".set\treorder\n"
|
||||
"2:"
|
||||
: "=r" (res), "=r" (dummy), "=r" (addr)
|
||||
: "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff),
|
||||
"2" (addr), "r" (size)
|
||||
: "$1");
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
/*
|
||||
* find_next_zero_bit - find the first zero bit in a memory region
|
||||
* @addr: The address to base the search on
|
||||
* @offset: The bitnumber to start searching at
|
||||
* @size: The maximum size to search
|
||||
*/
|
||||
static __inline__ int find_next_zero_bit (void * addr, int size, int offset)
|
||||
{
|
||||
unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
|
||||
int set = 0, bit = offset & 31, res;
|
||||
unsigned long dummy;
|
||||
|
||||
if (bit) {
|
||||
/*
|
||||
* Look for zero in first byte
|
||||
*/
|
||||
#ifdef __MIPSEB__
|
||||
#error "Fix this for big endian byte order"
|
||||
#endif
|
||||
__asm__(".set\tnoreorder\n\t"
|
||||
".set\tnoat\n"
|
||||
"1:\tand\t$1,%4,%1\n\t"
|
||||
"beqz\t$1,1f\n\t"
|
||||
"sll\t%1,%1,1\n\t"
|
||||
"bnez\t%1,1b\n\t"
|
||||
"addiu\t%0,1\n\t"
|
||||
".set\tat\n\t"
|
||||
".set\treorder\n"
|
||||
"1:"
|
||||
: "=r" (set), "=r" (dummy)
|
||||
: "0" (0), "1" (1 << bit), "r" (*p)
|
||||
: "$1");
|
||||
if (set < (32 - bit))
|
||||
return set + offset;
|
||||
set = 32 - bit;
|
||||
p++;
|
||||
}
|
||||
/*
|
||||
* No zero yet, search remaining full bytes for a zero
|
||||
*/
|
||||
res = find_first_zero_bit(p, size - 32 * (p - (unsigned int *) addr));
|
||||
return offset + set + res;
|
||||
}
|
||||
|
||||
#endif /* !(__MIPSEB__) */
|
||||
|
||||
/*
|
||||
* ffz - find first zero in word.
|
||||
* @word: The word to search
|
||||
*
|
||||
* Undefined if no zero exists, so code should check against ~0UL first.
|
||||
*/
|
||||
static __inline__ unsigned long ffz(unsigned long word)
|
||||
{
|
||||
unsigned int __res;
|
||||
unsigned int mask = 1;
|
||||
|
||||
__asm__ (
|
||||
".set\tnoreorder\n\t"
|
||||
".set\tnoat\n\t"
|
||||
"move\t%0,$0\n"
|
||||
"1:\tand\t$1,%2,%1\n\t"
|
||||
"beqz\t$1,2f\n\t"
|
||||
"sll\t%1,1\n\t"
|
||||
"bnez\t%1,1b\n\t"
|
||||
"addiu\t%0,1\n\t"
|
||||
".set\tat\n\t"
|
||||
".set\treorder\n"
|
||||
"2:\n\t"
|
||||
: "=&r" (__res), "=r" (mask)
|
||||
: "r" (word), "1" (mask)
|
||||
: "$1");
|
||||
|
||||
return __res;
|
||||
}
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/*
|
||||
* hweightN - returns the hamming weight of a N-bit word
|
||||
* @x: the word to weigh
|
||||
*
|
||||
* The Hamming Weight of a number is the total number of bits set in it.
|
||||
*/
|
||||
|
||||
#define hweight32(x) generic_hweight32(x)
|
||||
#define hweight16(x) generic_hweight16(x)
|
||||
#define hweight8(x) generic_hweight8(x)
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#ifdef __MIPSEB__
|
||||
/*
|
||||
* find_next_zero_bit - find the first zero bit in a memory region
|
||||
* @addr: The address to base the search on
|
||||
* @offset: The bitnumber to start searching at
|
||||
* @size: The maximum size to search
|
||||
*/
|
||||
static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
|
||||
{
|
||||
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
|
||||
unsigned long result = offset & ~31UL;
|
||||
unsigned long tmp;
|
||||
|
||||
if (offset >= size)
|
||||
return size;
|
||||
size -= result;
|
||||
offset &= 31UL;
|
||||
if (offset) {
|
||||
tmp = *(p++);
|
||||
tmp |= ~0UL >> (32-offset);
|
||||
if (size < 32)
|
||||
goto found_first;
|
||||
if (~tmp)
|
||||
goto found_middle;
|
||||
size -= 32;
|
||||
result += 32;
|
||||
}
|
||||
while (size & ~31UL) {
|
||||
if (~(tmp = *(p++)))
|
||||
goto found_middle;
|
||||
result += 32;
|
||||
size -= 32;
|
||||
}
|
||||
if (!size)
|
||||
return result;
|
||||
tmp = *p;
|
||||
|
||||
found_first:
|
||||
tmp |= ~0UL << size;
|
||||
found_middle:
|
||||
return result + ffz(tmp);
|
||||
}
|
||||
|
||||
/* Linus sez that gcc can optimize the following correctly, we'll see if this
|
||||
* holds on the Sparc as it does for the ALPHA.
|
||||
*/
|
||||
|
||||
#if 0 /* Fool kernel-doc since it doesn't do macros yet */
|
||||
/*
|
||||
* find_first_zero_bit - find the first zero bit in a memory region
|
||||
* @addr: The address to start the search at
|
||||
* @size: The maximum size to search
|
||||
*
|
||||
* Returns the bit-number of the first zero bit, not the number of the byte
|
||||
* containing a bit.
|
||||
*/
|
||||
static int find_first_zero_bit (void *addr, unsigned size);
|
||||
#endif
|
||||
|
||||
#define find_first_zero_bit(addr, size) \
|
||||
find_next_zero_bit((addr), (size), 0)
|
||||
|
||||
#endif /* (__MIPSEB__) */
|
||||
|
||||
/* Now for the ext2 filesystem bit operations and helper routines. */
|
||||
|
||||
#ifdef __MIPSEB__
|
||||
static __inline__ int ext2_set_bit(int nr, void * addr)
|
||||
{
|
||||
int mask, retval, flags;
|
||||
unsigned char *ADDR = (unsigned char *) addr;
|
||||
|
||||
ADDR += nr >> 3;
|
||||
mask = 1 << (nr & 0x07);
|
||||
save_and_cli(flags);
|
||||
retval = (mask & *ADDR) != 0;
|
||||
*ADDR |= mask;
|
||||
restore_flags(flags);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ int ext2_clear_bit(int nr, void * addr)
|
||||
{
|
||||
int mask, retval, flags;
|
||||
unsigned char *ADDR = (unsigned char *) addr;
|
||||
|
||||
ADDR += nr >> 3;
|
||||
mask = 1 << (nr & 0x07);
|
||||
save_and_cli(flags);
|
||||
retval = (mask & *ADDR) != 0;
|
||||
*ADDR &= ~mask;
|
||||
restore_flags(flags);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ int ext2_test_bit(int nr, const void * addr)
|
||||
{
|
||||
int mask;
|
||||
const unsigned char *ADDR = (const unsigned char *) addr;
|
||||
|
||||
ADDR += nr >> 3;
|
||||
mask = 1 << (nr & 0x07);
|
||||
return ((mask & *ADDR) != 0);
|
||||
}
|
||||
|
||||
#define ext2_find_first_zero_bit(addr, size) \
|
||||
ext2_find_next_zero_bit((addr), (size), 0)
|
||||
|
||||
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
|
||||
{
|
||||
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
|
||||
unsigned long result = offset & ~31UL;
|
||||
unsigned long tmp;
|
||||
|
||||
if (offset >= size)
|
||||
return size;
|
||||
size -= result;
|
||||
offset &= 31UL;
|
||||
if(offset) {
|
||||
/* We hold the little endian value in tmp, but then the
|
||||
* shift is illegal. So we could keep a big endian value
|
||||
* in tmp, like this:
|
||||
*
|
||||
* tmp = __swab32(*(p++));
|
||||
* tmp |= ~0UL >> (32-offset);
|
||||
*
|
||||
* but this would decrease preformance, so we change the
|
||||
* shift:
|
||||
*/
|
||||
tmp = *(p++);
|
||||
tmp |= __swab32(~0UL >> (32-offset));
|
||||
if(size < 32)
|
||||
goto found_first;
|
||||
if(~tmp)
|
||||
goto found_middle;
|
||||
size -= 32;
|
||||
result += 32;
|
||||
}
|
||||
while(size & ~31UL) {
|
||||
if(~(tmp = *(p++)))
|
||||
goto found_middle;
|
||||
result += 32;
|
||||
size -= 32;
|
||||
}
|
||||
if(!size)
|
||||
return result;
|
||||
tmp = *p;
|
||||
|
||||
found_first:
|
||||
/* tmp is little endian, so we would have to swab the shift,
|
||||
* see above. But then we have to swab tmp below for ffz, so
|
||||
* we might as well do this here.
|
||||
*/
|
||||
return result + ffz(__swab32(tmp) | (~0UL << size));
|
||||
found_middle:
|
||||
return result + ffz(__swab32(tmp));
|
||||
}
|
||||
#else /* !(__MIPSEB__) */
|
||||
|
||||
/* Native ext2 byte ordering, just collapse using defines. */
|
||||
#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr))
|
||||
#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr))
|
||||
#define ext2_test_bit(nr, addr) test_bit((nr), (addr))
|
||||
#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size))
|
||||
#define ext2_find_next_zero_bit(addr, size, offset) \
|
||||
find_next_zero_bit((addr), (size), (offset))
|
||||
|
||||
#endif /* !(__MIPSEB__) */
|
||||
|
||||
/*
|
||||
* Bitmap functions for the minix filesystem.
|
||||
* FIXME: These assume that Minix uses the native byte/bitorder.
|
||||
* This limits the Minix filesystem's value for data exchange very much.
|
||||
*/
|
||||
#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
|
||||
#define minix_set_bit(nr,addr) set_bit(nr,addr)
|
||||
#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
|
||||
#define minix_test_bit(nr,addr) test_bit(nr,addr)
|
||||
#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
|
||||
|
||||
#endif /* _ASM_BITOPS_H */
|
||||
@@ -0,0 +1,72 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1996, 99, 2003 by Ralf Baechle
|
||||
*/
|
||||
#ifndef _ASM_BYTEORDER_H
|
||||
#define _ASM_BYTEORDER_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
#ifdef __GNUC__
|
||||
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
|
||||
static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
|
||||
{
|
||||
__asm__(
|
||||
" wsbh %0, %1 \n"
|
||||
: "=r" (x)
|
||||
: "r" (x));
|
||||
|
||||
return x;
|
||||
}
|
||||
#define __arch__swab16(x) ___arch__swab16(x)
|
||||
|
||||
static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
|
||||
{
|
||||
__asm__(
|
||||
" wsbh %0, %1 \n"
|
||||
" rotr %0, %0, 16 \n"
|
||||
: "=r" (x)
|
||||
: "r" (x));
|
||||
|
||||
return x;
|
||||
}
|
||||
#define __arch__swab32(x) ___arch__swab32(x)
|
||||
|
||||
#ifdef CONFIG_CPU_MIPS64_R2
|
||||
|
||||
static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
|
||||
{
|
||||
__asm__(
|
||||
" dsbh %0, %1 \n"
|
||||
" dshd %0, %0 \n"
|
||||
" drotr %0, %0, 32 \n"
|
||||
: "=r" (x)
|
||||
: "r" (x));
|
||||
|
||||
return x;
|
||||
}
|
||||
|
||||
#define __arch__swab64(x) ___arch__swab64(x)
|
||||
|
||||
#endif /* CONFIG_CPU_MIPS64_R2 */
|
||||
|
||||
#endif /* CONFIG_CPU_MIPSR2 */
|
||||
|
||||
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
|
||||
# define __BYTEORDER_HAS_U64__
|
||||
# define __SWAB_64_THRU_32__
|
||||
#endif
|
||||
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#if defined(__MIPSEB__)
|
||||
# include <linux/byteorder/big_endian.h>
|
||||
#elif defined(__MIPSEL__)
|
||||
# include <linux/byteorder/little_endian.h>
|
||||
#else
|
||||
# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_BYTEORDER_H */
|
||||
@@ -0,0 +1,32 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors.
|
||||
*/
|
||||
|
||||
#ifndef __MIPS_CACHE_H__
|
||||
#define __MIPS_CACHE_H__
|
||||
|
||||
#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
|
||||
#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
|
||||
|
||||
/*
|
||||
* CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
|
||||
* DMA buffer alignment. Satisfy those drivers by providing it as a synonym
|
||||
* of ARCH_DMA_MINALIGN for now.
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/**
|
||||
* mips_cache_probe() - Probe the properties of the caches
|
||||
*
|
||||
* Call this to probe the properties such as line sizes of the caches
|
||||
* present in the system, if any. This must be done before cache maintenance
|
||||
* functions such as flush_cache may be called.
|
||||
*/
|
||||
void mips_cache_probe(void);
|
||||
#endif
|
||||
|
||||
#endif /* __MIPS_CACHE_H__ */
|
||||
@@ -0,0 +1,23 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
|
||||
*/
|
||||
#ifndef _ASM_CACHECTL
|
||||
#define _ASM_CACHECTL
|
||||
|
||||
/*
|
||||
* Options for cacheflush system call
|
||||
*/
|
||||
#define ICACHE (1<<0) /* flush instruction cache */
|
||||
#define DCACHE (1<<1) /* writeback and flush data cache */
|
||||
#define BCACHE (ICACHE|DCACHE) /* flush both caches */
|
||||
|
||||
/*
|
||||
* Caching modes for the cachectl(2) call
|
||||
*
|
||||
* cachectl(2) is currently not supported and returns ENOSYS.
|
||||
*/
|
||||
#define CACHEABLE 0 /* make pages cacheable */
|
||||
#define UNCACHEABLE 1 /* make pages uncacheable */
|
||||
|
||||
#endif /* _ASM_CACHECTL */
|
||||
@@ -0,0 +1,114 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Cache operations for the cache instruction.
|
||||
*
|
||||
* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
|
||||
* (C) Copyright 1999 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef __ASM_CACHEOPS_H
|
||||
#define __ASM_CACHEOPS_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
static inline void mips_cache(int op, const volatile void *addr)
|
||||
{
|
||||
#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
|
||||
__builtin_mips_cache(op, addr);
|
||||
#else
|
||||
__asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
|
||||
#endif
|
||||
}
|
||||
|
||||
#define MIPS32_WHICH_ICACHE 0x0
|
||||
#define MIPS32_FETCH_AND_LOCK 0x7
|
||||
|
||||
#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
|
||||
|
||||
/* Prefetch and lock instructions into cache */
|
||||
static inline void icache_lock(void *func, size_t len)
|
||||
{
|
||||
int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
|
||||
|
||||
for (i = 0; i < lines; i++) {
|
||||
asm volatile (" cache %0, %1(%2)"
|
||||
: /* No Output */
|
||||
: "I" ICACHE_LOAD_LOCK,
|
||||
"n" (i * ARCH_DMA_MINALIGN),
|
||||
"r" (func)
|
||||
: /* No Clobbers */);
|
||||
}
|
||||
}
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* Cache Operations available on all MIPS processors with R4000-style caches
|
||||
*/
|
||||
#define INDEX_INVALIDATE_I 0x00
|
||||
#define INDEX_WRITEBACK_INV_D 0x01
|
||||
#define INDEX_LOAD_TAG_I 0x04
|
||||
#define INDEX_LOAD_TAG_D 0x05
|
||||
#define INDEX_STORE_TAG_I 0x08
|
||||
#define INDEX_STORE_TAG_D 0x09
|
||||
#if defined(CONFIG_CPU_LOONGSON2)
|
||||
#define HIT_INVALIDATE_I 0x00
|
||||
#else
|
||||
#define HIT_INVALIDATE_I 0x10
|
||||
#endif
|
||||
#define HIT_INVALIDATE_D 0x11
|
||||
#define HIT_WRITEBACK_INV_D 0x15
|
||||
|
||||
/*
|
||||
* R4000-specific cacheops
|
||||
*/
|
||||
#define CREATE_DIRTY_EXCL_D 0x0d
|
||||
#define FILL 0x14
|
||||
#define HIT_WRITEBACK_I 0x18
|
||||
#define HIT_WRITEBACK_D 0x19
|
||||
|
||||
/*
|
||||
* R4000SC and R4400SC-specific cacheops
|
||||
*/
|
||||
#define INDEX_INVALIDATE_SI 0x02
|
||||
#define INDEX_WRITEBACK_INV_SD 0x03
|
||||
#define INDEX_LOAD_TAG_SI 0x06
|
||||
#define INDEX_LOAD_TAG_SD 0x07
|
||||
#define INDEX_STORE_TAG_SI 0x0A
|
||||
#define INDEX_STORE_TAG_SD 0x0B
|
||||
#define CREATE_DIRTY_EXCL_SD 0x0f
|
||||
#define HIT_INVALIDATE_SI 0x12
|
||||
#define HIT_INVALIDATE_SD 0x13
|
||||
#define HIT_WRITEBACK_INV_SD 0x17
|
||||
#define HIT_WRITEBACK_SD 0x1b
|
||||
#define HIT_SET_VIRTUAL_SI 0x1e
|
||||
#define HIT_SET_VIRTUAL_SD 0x1f
|
||||
|
||||
/*
|
||||
* R5000-specific cacheops
|
||||
*/
|
||||
#define R5K_PAGE_INVALIDATE_S 0x17
|
||||
|
||||
/*
|
||||
* RM7000-specific cacheops
|
||||
*/
|
||||
#define PAGE_INVALIDATE_T 0x16
|
||||
|
||||
/*
|
||||
* R10000-specific cacheops
|
||||
*
|
||||
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
|
||||
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
|
||||
*/
|
||||
#define INDEX_WRITEBACK_INV_S 0x03
|
||||
#define INDEX_LOAD_TAG_S 0x07
|
||||
#define INDEX_STORE_TAG_S 0x0B
|
||||
#define HIT_INVALIDATE_S 0x13
|
||||
#define CACHE_BARRIER 0x14
|
||||
#define HIT_WRITEBACK_INV_S 0x17
|
||||
#define INDEX_LOAD_DATA_I 0x18
|
||||
#define INDEX_LOAD_DATA_D 0x19
|
||||
#define INDEX_LOAD_DATA_S 0x1b
|
||||
#define INDEX_STORE_DATA_I 0x1c
|
||||
#define INDEX_STORE_DATA_D 0x1d
|
||||
#define INDEX_STORE_DATA_S 0x1f
|
||||
|
||||
#endif /* __ASM_CACHEOPS_H */
|
||||
@@ -0,0 +1,61 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* MIPS Coherence Manager (CM) Register Definitions
|
||||
*
|
||||
* Copyright (c) 2016 Imagination Technologies Ltd.
|
||||
*/
|
||||
#ifndef __MIPS_ASM_CM_H__
|
||||
#define __MIPS_ASM_CM_H__
|
||||
|
||||
/* Global Control Register (GCR) offsets */
|
||||
#define GCR_BASE 0x0008
|
||||
#define GCR_BASE_UPPER 0x000c
|
||||
#define GCR_REV 0x0030
|
||||
#define GCR_L2_CONFIG 0x0130
|
||||
#define GCR_L2_TAG_ADDR 0x0600
|
||||
#define GCR_L2_TAG_ADDR_UPPER 0x0604
|
||||
#define GCR_L2_TAG_STATE 0x0608
|
||||
#define GCR_L2_TAG_STATE_UPPER 0x060c
|
||||
#define GCR_L2_DATA 0x0610
|
||||
#define GCR_L2_DATA_UPPER 0x0614
|
||||
#define GCR_Cx_COHERENCE 0x2008
|
||||
|
||||
/* GCR_REV CM versions */
|
||||
#define GCR_REV_CM3 0x0800
|
||||
|
||||
/* GCR_L2_CONFIG fields */
|
||||
#define GCR_L2_CONFIG_ASSOC_SHIFT 0
|
||||
#define GCR_L2_CONFIG_ASSOC_BITS 8
|
||||
#define GCR_L2_CONFIG_LINESZ_SHIFT 8
|
||||
#define GCR_L2_CONFIG_LINESZ_BITS 4
|
||||
#define GCR_L2_CONFIG_SETSZ_SHIFT 12
|
||||
#define GCR_L2_CONFIG_SETSZ_BITS 4
|
||||
#define GCR_L2_CONFIG_BYPASS (1 << 20)
|
||||
|
||||
/* GCR_Cx_COHERENCE */
|
||||
#define GCR_Cx_COHERENCE_DOM_EN (0xff << 0)
|
||||
#define GCR_Cx_COHERENCE_EN (0x1 << 0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
static inline void *mips_cm_base(void)
|
||||
{
|
||||
return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
|
||||
}
|
||||
|
||||
static inline unsigned long mips_cm_l2_line_size(void)
|
||||
{
|
||||
unsigned long l2conf, line_sz;
|
||||
|
||||
l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG);
|
||||
|
||||
line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT;
|
||||
line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
|
||||
return line_sz ? (2 << line_sz) : 0;
|
||||
}
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* __MIPS_ASM_CM_H__ */
|
||||
@@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_CONFIG_H_
|
||||
#define _ASM_CONFIG_H_
|
||||
|
||||
#define CONFIG_LMB
|
||||
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2003, 2004 Ralf Baechle
|
||||
* Copyright (C) 2004 Maciej W. Rozycki
|
||||
*/
|
||||
#ifndef __ASM_CPU_FEATURES_H
|
||||
#define __ASM_CPU_FEATURES_H
|
||||
|
||||
#include <cpu-feature-overrides.h>
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
# ifndef cpu_has_64bits
|
||||
# define cpu_has_64bits 0
|
||||
# endif
|
||||
# ifndef cpu_has_64bit_addresses
|
||||
# define cpu_has_64bit_addresses 0
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
# ifndef cpu_has_64bits
|
||||
# define cpu_has_64bits 1
|
||||
# endif
|
||||
# ifndef cpu_has_64bit_addresses
|
||||
# define cpu_has_64bit_addresses 1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CPU_FEATURES_H */
|
||||
@@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2002-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_GBL_DATA_H
|
||||
#define __ASM_GBL_DATA_H
|
||||
|
||||
#include <asm/regdef.h>
|
||||
|
||||
/* Architecture-specific global data */
|
||||
struct arch_global_data {
|
||||
#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
|
||||
unsigned long io_port_base;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_ATH79
|
||||
unsigned long id;
|
||||
unsigned long soc;
|
||||
unsigned long rev;
|
||||
unsigned long ver;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
|
||||
unsigned short l1i_line_size;
|
||||
unsigned short l1d_line_size;
|
||||
#endif
|
||||
#ifdef CONFIG_MIPS_L2_CACHE
|
||||
unsigned short l2_line_size;
|
||||
#endif
|
||||
};
|
||||
|
||||
#include <asm-generic/global_data.h>
|
||||
|
||||
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
|
||||
|
||||
#endif /* __ASM_GBL_DATA_H */
|
||||
@@ -0,0 +1 @@
|
||||
#include <asm-generic/gpio.h>
|
||||
@@ -0,0 +1,585 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1994, 1995 Waldorf GmbH
|
||||
* Copyright (C) 1994 - 2000, 06 Ralf Baechle
|
||||
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
||||
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
|
||||
* Author: Maciej W. Rozycki <macro@mips.com>
|
||||
*/
|
||||
#ifndef _ASM_IO_H
|
||||
#define _ASM_IO_H
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/pgtable-bits.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/string.h>
|
||||
|
||||
#include <ioremap.h>
|
||||
#include <mangle-port.h>
|
||||
#include <spaces.h>
|
||||
|
||||
/*
|
||||
* Raw operations are never swapped in software. OTOH values that raw
|
||||
* operations are working on may or may not have been swapped by the bus
|
||||
* hardware. An example use would be for flash memory that's used for
|
||||
* execute in place.
|
||||
*/
|
||||
# define __raw_ioswabb(a, x) (x)
|
||||
# define __raw_ioswabw(a, x) (x)
|
||||
# define __raw_ioswabl(a, x) (x)
|
||||
# define __raw_ioswabq(a, x) (x)
|
||||
# define ____raw_ioswabq(a, x) (x)
|
||||
|
||||
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffff
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
|
||||
|
||||
static inline ulong mips_io_port_base(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
return gd->arch.io_port_base;
|
||||
}
|
||||
|
||||
static inline void set_io_port_base(unsigned long base)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->arch.io_port_base = base;
|
||||
barrier();
|
||||
}
|
||||
|
||||
#else /* !CONFIG_DYNAMIC_IO_PORT_BASE */
|
||||
|
||||
static inline ulong mips_io_port_base(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void set_io_port_base(unsigned long base)
|
||||
{
|
||||
BUG_ON(base);
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_DYNAMIC_IO_PORT_BASE */
|
||||
|
||||
/*
|
||||
* virt_to_phys - map virtual addresses to physical
|
||||
* @address: address to remap
|
||||
*
|
||||
* The returned physical address is the physical (CPU) mapping for
|
||||
* the memory address given. It is only valid to use this function on
|
||||
* addresses directly mapped or allocated via kmalloc.
|
||||
*
|
||||
* This function does not give bus mappings for DMA transfers. In
|
||||
* almost all conceivable cases a device driver should not be using
|
||||
* this function
|
||||
*/
|
||||
static inline unsigned long virt_to_phys(volatile const void *address)
|
||||
{
|
||||
unsigned long addr = (unsigned long)address;
|
||||
|
||||
/* this corresponds to kernel implementation of __pa() */
|
||||
#ifdef CONFIG_64BIT
|
||||
if (addr < CKSEG0)
|
||||
return XPHYSADDR(addr);
|
||||
#endif
|
||||
return CPHYSADDR(addr);
|
||||
}
|
||||
#define virt_to_phys virt_to_phys
|
||||
|
||||
/*
|
||||
* phys_to_virt - map physical address to virtual
|
||||
* @address: address to remap
|
||||
*
|
||||
* The returned virtual address is a current CPU mapping for
|
||||
* the memory address given. It is only valid to use this function on
|
||||
* addresses that have a kernel mapping
|
||||
*
|
||||
* This function does not handle bus mappings for DMA transfers. In
|
||||
* almost all conceivable cases a device driver should not be using
|
||||
* this function
|
||||
*/
|
||||
static inline void *phys_to_virt(unsigned long address)
|
||||
{
|
||||
return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
|
||||
}
|
||||
#define phys_to_virt phys_to_virt
|
||||
|
||||
/*
|
||||
* ISA I/O bus memory addresses are 1:1 with the physical address.
|
||||
*/
|
||||
static inline unsigned long isa_virt_to_bus(volatile void *address)
|
||||
{
|
||||
return (unsigned long)address - PAGE_OFFSET;
|
||||
}
|
||||
|
||||
static inline void *isa_bus_to_virt(unsigned long address)
|
||||
{
|
||||
return (void *)(address + PAGE_OFFSET);
|
||||
}
|
||||
|
||||
#define isa_page_to_bus page_to_phys
|
||||
|
||||
/*
|
||||
* However PCI ones are not necessarily 1:1 and therefore these interfaces
|
||||
* are forbidden in portable PCI drivers.
|
||||
*
|
||||
* Allow them for x86 for legacy drivers, though.
|
||||
*/
|
||||
#define virt_to_bus virt_to_phys
|
||||
#define bus_to_virt phys_to_virt
|
||||
|
||||
static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size,
|
||||
unsigned long flags)
|
||||
{
|
||||
void __iomem *addr;
|
||||
phys_addr_t phys_addr;
|
||||
|
||||
addr = plat_ioremap(offset, size, flags);
|
||||
if (addr)
|
||||
return addr;
|
||||
|
||||
phys_addr = fixup_bigphys_addr(offset, size);
|
||||
return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr);
|
||||
}
|
||||
|
||||
/*
|
||||
* ioremap - map bus memory into CPU space
|
||||
* @offset: bus address of the memory
|
||||
* @size: size of the resource to map
|
||||
*
|
||||
* ioremap performs a platform specific sequence of operations to
|
||||
* make bus memory CPU accessible via the readb/readw/readl/writeb/
|
||||
* writew/writel functions and the other mmio helpers. The returned
|
||||
* address is not guaranteed to be usable directly as a virtual
|
||||
* address.
|
||||
*/
|
||||
#define ioremap(offset, size) \
|
||||
__ioremap_mode((offset), (size), _CACHE_UNCACHED)
|
||||
|
||||
/*
|
||||
* ioremap_nocache - map bus memory into CPU space
|
||||
* @offset: bus address of the memory
|
||||
* @size: size of the resource to map
|
||||
*
|
||||
* ioremap_nocache performs a platform specific sequence of operations to
|
||||
* make bus memory CPU accessible via the readb/readw/readl/writeb/
|
||||
* writew/writel functions and the other mmio helpers. The returned
|
||||
* address is not guaranteed to be usable directly as a virtual
|
||||
* address.
|
||||
*
|
||||
* This version of ioremap ensures that the memory is marked uncachable
|
||||
* on the CPU as well as honouring existing caching rules from things like
|
||||
* the PCI bus. Note that there are other caches and buffers on many
|
||||
* busses. In particular driver authors should read up on PCI writes
|
||||
*
|
||||
* It's useful if some control registers are in such an area and
|
||||
* write combining or read caching is not desirable:
|
||||
*/
|
||||
#define ioremap_nocache(offset, size) \
|
||||
__ioremap_mode((offset), (size), _CACHE_UNCACHED)
|
||||
#define ioremap_uc ioremap_nocache
|
||||
|
||||
/*
|
||||
* ioremap_cachable - map bus memory into CPU space
|
||||
* @offset: bus address of the memory
|
||||
* @size: size of the resource to map
|
||||
*
|
||||
* ioremap_nocache performs a platform specific sequence of operations to
|
||||
* make bus memory CPU accessible via the readb/readw/readl/writeb/
|
||||
* writew/writel functions and the other mmio helpers. The returned
|
||||
* address is not guaranteed to be usable directly as a virtual
|
||||
* address.
|
||||
*
|
||||
* This version of ioremap ensures that the memory is marked cachable by
|
||||
* the CPU. Also enables full write-combining. Useful for some
|
||||
* memory-like regions on I/O busses.
|
||||
*/
|
||||
#define ioremap_cachable(offset, size) \
|
||||
__ioremap_mode((offset), (size), _page_cachable_default)
|
||||
|
||||
/*
|
||||
* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
|
||||
* requests a cachable mapping, ioremap_uncached_accelerated requests a
|
||||
* mapping using the uncached accelerated mode which isn't supported on
|
||||
* all processors.
|
||||
*/
|
||||
#define ioremap_cacheable_cow(offset, size) \
|
||||
__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
|
||||
#define ioremap_uncached_accelerated(offset, size) \
|
||||
__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
|
||||
|
||||
static inline void iounmap(const volatile void __iomem *addr)
|
||||
{
|
||||
plat_iounmap(addr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
||||
#define war_octeon_io_reorder_wmb() wmb()
|
||||
#else
|
||||
#define war_octeon_io_reorder_wmb() do { } while (0)
|
||||
#endif
|
||||
|
||||
#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
|
||||
\
|
||||
static inline void pfx##write##bwlq(type val, \
|
||||
volatile void __iomem *mem) \
|
||||
{ \
|
||||
volatile type *__mem; \
|
||||
type __val; \
|
||||
\
|
||||
war_octeon_io_reorder_wmb(); \
|
||||
\
|
||||
__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
|
||||
\
|
||||
__val = pfx##ioswab##bwlq(__mem, val); \
|
||||
\
|
||||
if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
|
||||
*__mem = __val; \
|
||||
else if (cpu_has_64bits) { \
|
||||
type __tmp; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
".set arch=r4000" "\t\t# __writeq""\n\t" \
|
||||
"dsll32 %L0, %L0, 0" "\n\t" \
|
||||
"dsrl32 %L0, %L0, 0" "\n\t" \
|
||||
"dsll32 %M0, %M0, 0" "\n\t" \
|
||||
"or %L0, %L0, %M0" "\n\t" \
|
||||
"sd %L0, %2" "\n\t" \
|
||||
".set mips0" "\n" \
|
||||
: "=r" (__tmp) \
|
||||
: "0" (__val), "m" (*__mem)); \
|
||||
} else \
|
||||
BUG(); \
|
||||
} \
|
||||
\
|
||||
static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
|
||||
{ \
|
||||
volatile type *__mem; \
|
||||
type __val; \
|
||||
\
|
||||
__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
|
||||
\
|
||||
if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
|
||||
__val = *__mem; \
|
||||
else if (cpu_has_64bits) { \
|
||||
__asm__ __volatile__( \
|
||||
".set arch=r4000" "\t\t# __readq" "\n\t" \
|
||||
"ld %L0, %1" "\n\t" \
|
||||
"dsra32 %M0, %L0, 0" "\n\t" \
|
||||
"sll %L0, %L0, 0" "\n\t" \
|
||||
".set mips0" "\n" \
|
||||
: "=r" (__val) \
|
||||
: "m" (*__mem)); \
|
||||
} else { \
|
||||
__val = 0; \
|
||||
BUG(); \
|
||||
} \
|
||||
\
|
||||
return pfx##ioswab##bwlq(__mem, __val); \
|
||||
}
|
||||
|
||||
#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p) \
|
||||
\
|
||||
static inline void pfx##out##bwlq##p(type val, unsigned long port) \
|
||||
{ \
|
||||
volatile type *__addr; \
|
||||
type __val; \
|
||||
\
|
||||
war_octeon_io_reorder_wmb(); \
|
||||
\
|
||||
__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \
|
||||
\
|
||||
__val = pfx##ioswab##bwlq(__addr, val); \
|
||||
\
|
||||
/* Really, we want this to be atomic */ \
|
||||
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
|
||||
\
|
||||
*__addr = __val; \
|
||||
} \
|
||||
\
|
||||
static inline type pfx##in##bwlq##p(unsigned long port) \
|
||||
{ \
|
||||
volatile type *__addr; \
|
||||
type __val; \
|
||||
\
|
||||
__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \
|
||||
\
|
||||
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
|
||||
\
|
||||
__val = *__addr; \
|
||||
\
|
||||
return pfx##ioswab##bwlq(__addr, __val); \
|
||||
}
|
||||
|
||||
#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
|
||||
\
|
||||
__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
|
||||
|
||||
#define BUILDIO_MEM(bwlq, type) \
|
||||
\
|
||||
__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
|
||||
__BUILD_MEMORY_PFX(, bwlq, type) \
|
||||
__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
|
||||
|
||||
BUILDIO_MEM(b, u8)
|
||||
BUILDIO_MEM(w, u16)
|
||||
BUILDIO_MEM(l, u32)
|
||||
BUILDIO_MEM(q, u64)
|
||||
|
||||
#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
|
||||
__BUILD_IOPORT_SINGLE(bus, bwlq, type, ) \
|
||||
__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p)
|
||||
|
||||
#define BUILDIO_IOPORT(bwlq, type) \
|
||||
__BUILD_IOPORT_PFX(, bwlq, type) \
|
||||
__BUILD_IOPORT_PFX(__mem_, bwlq, type)
|
||||
|
||||
BUILDIO_IOPORT(b, u8)
|
||||
BUILDIO_IOPORT(w, u16)
|
||||
BUILDIO_IOPORT(l, u32)
|
||||
#ifdef CONFIG_64BIT
|
||||
BUILDIO_IOPORT(q, u64)
|
||||
#endif
|
||||
|
||||
#define __BUILDIO(bwlq, type) \
|
||||
\
|
||||
__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
|
||||
|
||||
__BUILDIO(q, u64)
|
||||
|
||||
#define readb_relaxed readb
|
||||
#define readw_relaxed readw
|
||||
#define readl_relaxed readl
|
||||
#define readq_relaxed readq
|
||||
|
||||
#define writeb_relaxed writeb
|
||||
#define writew_relaxed writew
|
||||
#define writel_relaxed writel
|
||||
#define writeq_relaxed writeq
|
||||
|
||||
#define readb_be(addr) \
|
||||
__raw_readb((__force unsigned *)(addr))
|
||||
#define readw_be(addr) \
|
||||
be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
|
||||
#define readl_be(addr) \
|
||||
be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
|
||||
#define readq_be(addr) \
|
||||
be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
|
||||
|
||||
#define writeb_be(val, addr) \
|
||||
__raw_writeb((val), (__force unsigned *)(addr))
|
||||
#define writew_be(val, addr) \
|
||||
__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
|
||||
#define writel_be(val, addr) \
|
||||
__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
|
||||
#define writeq_be(val, addr) \
|
||||
__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
|
||||
|
||||
/*
|
||||
* Some code tests for these symbols
|
||||
*/
|
||||
#define readq readq
|
||||
#define writeq writeq
|
||||
|
||||
#define __BUILD_MEMORY_STRING(bwlq, type) \
|
||||
\
|
||||
static inline void writes##bwlq(volatile void __iomem *mem, \
|
||||
const void *addr, unsigned int count) \
|
||||
{ \
|
||||
const volatile type *__addr = addr; \
|
||||
\
|
||||
while (count--) { \
|
||||
__mem_write##bwlq(*__addr, mem); \
|
||||
__addr++; \
|
||||
} \
|
||||
} \
|
||||
\
|
||||
static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
|
||||
unsigned int count) \
|
||||
{ \
|
||||
volatile type *__addr = addr; \
|
||||
\
|
||||
while (count--) { \
|
||||
*__addr = __mem_read##bwlq(mem); \
|
||||
__addr++; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define __BUILD_IOPORT_STRING(bwlq, type) \
|
||||
\
|
||||
static inline void outs##bwlq(unsigned long port, const void *addr, \
|
||||
unsigned int count) \
|
||||
{ \
|
||||
const volatile type *__addr = addr; \
|
||||
\
|
||||
while (count--) { \
|
||||
__mem_out##bwlq(*__addr, port); \
|
||||
__addr++; \
|
||||
} \
|
||||
} \
|
||||
\
|
||||
static inline void ins##bwlq(unsigned long port, void *addr, \
|
||||
unsigned int count) \
|
||||
{ \
|
||||
volatile type *__addr = addr; \
|
||||
\
|
||||
while (count--) { \
|
||||
*__addr = __mem_in##bwlq(port); \
|
||||
__addr++; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define BUILDSTRING(bwlq, type) \
|
||||
\
|
||||
__BUILD_MEMORY_STRING(bwlq, type) \
|
||||
__BUILD_IOPORT_STRING(bwlq, type)
|
||||
|
||||
BUILDSTRING(b, u8)
|
||||
BUILDSTRING(w, u16)
|
||||
BUILDSTRING(l, u32)
|
||||
#ifdef CONFIG_64BIT
|
||||
BUILDSTRING(q, u64)
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
||||
#define mmiowb() wmb()
|
||||
#else
|
||||
/* Depends on MIPS II instruction set */
|
||||
#define mmiowb() asm volatile ("sync" ::: "memory")
|
||||
#endif
|
||||
|
||||
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
|
||||
{
|
||||
memset((void __force *)addr, val, count);
|
||||
}
|
||||
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
|
||||
{
|
||||
memcpy(dst, (void __force *)src, count);
|
||||
}
|
||||
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
|
||||
{
|
||||
memcpy((void __force *)dst, src, count);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read a 32-bit register that requires a 64-bit read cycle on the bus.
|
||||
* Avoid interrupt mucking, just adjust the address for 4-byte access.
|
||||
* Assume the addresses are 8-byte aligned.
|
||||
*/
|
||||
#ifdef __MIPSEB__
|
||||
#define __CSR_32_ADJUST 4
|
||||
#else
|
||||
#define __CSR_32_ADJUST 0
|
||||
#endif
|
||||
|
||||
#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
|
||||
#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
|
||||
|
||||
/*
|
||||
* U-Boot specific
|
||||
*/
|
||||
#define sync() mmiowb()
|
||||
|
||||
#define MAP_NOCACHE 1
|
||||
|
||||
static inline void *
|
||||
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
|
||||
{
|
||||
if (flags == MAP_NOCACHE)
|
||||
return ioremap(paddr, len);
|
||||
|
||||
return (void *)CKSEG0ADDR(paddr);
|
||||
}
|
||||
#define map_physmem map_physmem
|
||||
|
||||
#define __BUILD_CLRBITS(bwlq, sfx, end, type) \
|
||||
\
|
||||
static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
|
||||
{ \
|
||||
type __val = __raw_read##bwlq(mem); \
|
||||
__val = end##_to_cpu(__val); \
|
||||
__val &= ~clr; \
|
||||
__val = cpu_to_##end(__val); \
|
||||
__raw_write##bwlq(__val, mem); \
|
||||
}
|
||||
|
||||
#define __BUILD_SETBITS(bwlq, sfx, end, type) \
|
||||
\
|
||||
static inline void setbits_##sfx(volatile void __iomem *mem, type set) \
|
||||
{ \
|
||||
type __val = __raw_read##bwlq(mem); \
|
||||
__val = end##_to_cpu(__val); \
|
||||
__val |= set; \
|
||||
__val = cpu_to_##end(__val); \
|
||||
__raw_write##bwlq(__val, mem); \
|
||||
}
|
||||
|
||||
#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \
|
||||
\
|
||||
static inline void clrsetbits_##sfx(volatile void __iomem *mem, \
|
||||
type clr, type set) \
|
||||
{ \
|
||||
type __val = __raw_read##bwlq(mem); \
|
||||
__val = end##_to_cpu(__val); \
|
||||
__val &= ~clr; \
|
||||
__val |= set; \
|
||||
__val = cpu_to_##end(__val); \
|
||||
__raw_write##bwlq(__val, mem); \
|
||||
}
|
||||
|
||||
#define BUILD_CLRSETBITS(bwlq, sfx, end, type) \
|
||||
\
|
||||
__BUILD_CLRBITS(bwlq, sfx, end, type) \
|
||||
__BUILD_SETBITS(bwlq, sfx, end, type) \
|
||||
__BUILD_CLRSETBITS(bwlq, sfx, end, type)
|
||||
|
||||
#define __to_cpu(v) (v)
|
||||
#define cpu_to__(v) (v)
|
||||
|
||||
#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v),a)
|
||||
#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
|
||||
|
||||
#define out_le64(a, v) out_arch(q, le64, a, v)
|
||||
#define out_le32(a, v) out_arch(l, le32, a, v)
|
||||
#define out_le16(a, v) out_arch(w, le16, a, v)
|
||||
|
||||
#define in_le64(a) in_arch(q, le64, a)
|
||||
#define in_le32(a) in_arch(l, le32, a)
|
||||
#define in_le16(a) in_arch(w, le16, a)
|
||||
|
||||
#define out_be64(a, v) out_arch(q, be64, a, v)
|
||||
#define out_be32(a, v) out_arch(l, be32, a, v)
|
||||
#define out_be16(a, v) out_arch(w, be16, a, v)
|
||||
|
||||
#define in_be64(a) in_arch(q, be64, a)
|
||||
#define in_be32(a) in_arch(l, be32, a)
|
||||
#define in_be16(a) in_arch(w, be16, a)
|
||||
|
||||
#define out_8(a, v) __raw_writeb(v, a)
|
||||
#define in_8(a) __raw_readb(a)
|
||||
|
||||
BUILD_CLRSETBITS(b, 8, _, u8)
|
||||
BUILD_CLRSETBITS(w, le16, le16, u16)
|
||||
BUILD_CLRSETBITS(w, be16, be16, u16)
|
||||
BUILD_CLRSETBITS(w, 16, _, u16)
|
||||
BUILD_CLRSETBITS(l, le32, le32, u32)
|
||||
BUILD_CLRSETBITS(l, be32, be32, u32)
|
||||
BUILD_CLRSETBITS(l, 32, _, u32)
|
||||
BUILD_CLRSETBITS(q, le64, le64, u64)
|
||||
BUILD_CLRSETBITS(q, be64, be64, u64)
|
||||
BUILD_CLRSETBITS(q, 64, _, u64)
|
||||
|
||||
#include <asm-generic/io.h>
|
||||
|
||||
#endif /* _ASM_IO_H */
|
||||
@@ -0,0 +1,35 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Various ISA level dependent constants.
|
||||
* Most of the following constants reflect the different layout
|
||||
* of Coprocessor 0 registers.
|
||||
*
|
||||
* Copyright (c) 1998 Harald Koerfgen
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ISADEP_H
|
||||
#define __ASM_ISADEP_H
|
||||
|
||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
||||
/*
|
||||
* R2000 or R3000
|
||||
*/
|
||||
|
||||
/*
|
||||
* kernel or user mode? (CP0_STATUS)
|
||||
*/
|
||||
#define KU_MASK 0x08
|
||||
#define KU_USER 0x08
|
||||
#define KU_KERN 0x00
|
||||
|
||||
#else
|
||||
/*
|
||||
* kernel or user mode?
|
||||
*/
|
||||
#define KU_MASK 0x18
|
||||
#define KU_USER 0x10
|
||||
#define KU_KERN 0x00
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ISADEP_H */
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2003 Ralf Baechle
|
||||
*/
|
||||
#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
/* Intentionally empty file ... */
|
||||
|
||||
#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
|
||||
@@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_MACH_GENERIC_IOREMAP_H
|
||||
#define __ASM_MACH_GENERIC_IOREMAP_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
* Allow physical addresses to be fixed up to help peripherals located
|
||||
* outside the low 32-bit range -- generic pass-through version.
|
||||
*/
|
||||
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
|
||||
phys_addr_t size)
|
||||
{
|
||||
return phys_addr;
|
||||
}
|
||||
|
||||
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
|
||||
unsigned long flags)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline int plat_iounmap(const volatile void __iomem *addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
|
||||
|
||||
#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
|
||||
@@ -0,0 +1,49 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2003, 2004 Ralf Baechle
|
||||
*/
|
||||
#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
|
||||
#define __ASM_MACH_GENERIC_MANGLE_PORT_H
|
||||
|
||||
#define __swizzle_addr_b(port) (port)
|
||||
#define __swizzle_addr_w(port) (port)
|
||||
#define __swizzle_addr_l(port) (port)
|
||||
#define __swizzle_addr_q(port) (port)
|
||||
|
||||
/*
|
||||
* Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
|
||||
* less sane hardware forces software to fiddle with this...
|
||||
*
|
||||
* Regardless, if the host bus endianness mismatches that of PCI/ISA, then
|
||||
* you can't have the numerical value of data and byte addresses within
|
||||
* multibyte quantities both preserved at the same time. Hence two
|
||||
* variations of functions: non-prefixed ones that preserve the value
|
||||
* and prefixed ones that preserve byte addresses. The latters are
|
||||
* typically used for moving raw data between a peripheral and memory (cf.
|
||||
* string I/O functions), hence the "__mem_" prefix.
|
||||
*/
|
||||
#if defined(CONFIG_SWAP_IO_SPACE)
|
||||
|
||||
# define ioswabb(a, x) (x)
|
||||
# define __mem_ioswabb(a, x) (x)
|
||||
# define ioswabw(a, x) le16_to_cpu(x)
|
||||
# define __mem_ioswabw(a, x) (x)
|
||||
# define ioswabl(a, x) le32_to_cpu(x)
|
||||
# define __mem_ioswabl(a, x) (x)
|
||||
# define ioswabq(a, x) le64_to_cpu(x)
|
||||
# define __mem_ioswabq(a, x) (x)
|
||||
|
||||
#else
|
||||
|
||||
# define ioswabb(a, x) (x)
|
||||
# define __mem_ioswabb(a, x) (x)
|
||||
# define ioswabw(a, x) (x)
|
||||
# define __mem_ioswabw(a, x) cpu_to_le16(x)
|
||||
# define ioswabl(a, x) (x)
|
||||
# define __mem_ioswabl(a, x) cpu_to_le32(x)
|
||||
# define ioswabq(a, x) (x)
|
||||
# define __mem_ioswabq(a, x) cpu_to_le32(x)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
|
||||
@@ -0,0 +1,101 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
|
||||
* Copyright (C) 2000, 2002 Maciej W. Rozycki
|
||||
* Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef _ASM_MACH_GENERIC_SPACES_H
|
||||
#define _ASM_MACH_GENERIC_SPACES_H
|
||||
|
||||
#include <linux/const.h>
|
||||
|
||||
/*
|
||||
* This gives the physical RAM offset.
|
||||
*/
|
||||
#ifndef PHYS_OFFSET
|
||||
#define PHYS_OFFSET _AC(0, UL)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
#ifdef CONFIG_KVM_GUEST
|
||||
#define CAC_BASE _AC(0x40000000, UL)
|
||||
#else
|
||||
#define CAC_BASE _AC(0x80000000, UL)
|
||||
#endif
|
||||
#ifndef IO_BASE
|
||||
#define IO_BASE _AC(0xa0000000, UL)
|
||||
#endif
|
||||
#ifndef UNCAC_BASE
|
||||
#define UNCAC_BASE _AC(0xa0000000, UL)
|
||||
#endif
|
||||
|
||||
#ifndef MAP_BASE
|
||||
#ifdef CONFIG_KVM_GUEST
|
||||
#define MAP_BASE _AC(0x60000000, UL)
|
||||
#else
|
||||
#define MAP_BASE _AC(0xc0000000, UL)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Memory above this physical address will be considered highmem.
|
||||
*/
|
||||
#ifndef HIGHMEM_START
|
||||
#define HIGHMEM_START _AC(0x20000000, UL)
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_32BIT */
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
|
||||
#ifndef CAC_BASE
|
||||
#ifdef CONFIG_DMA_NONCOHERENT
|
||||
#define CAC_BASE _AC(0x9800000000000000, UL)
|
||||
#else
|
||||
#define CAC_BASE _AC(0xa800000000000000, UL)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef IO_BASE
|
||||
#define IO_BASE _AC(0x9000000000000000, UL)
|
||||
#endif
|
||||
|
||||
#ifndef UNCAC_BASE
|
||||
#define UNCAC_BASE _AC(0x9000000000000000, UL)
|
||||
#endif
|
||||
|
||||
#ifndef MAP_BASE
|
||||
#define MAP_BASE _AC(0xc000000000000000, UL)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Memory above this physical address will be considered highmem.
|
||||
* Fixme: 59 bits is a fictive number and makes assumptions about processors
|
||||
* in the distant future. Nobody will care for a few years :-)
|
||||
*/
|
||||
#ifndef HIGHMEM_START
|
||||
#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL))
|
||||
#endif
|
||||
|
||||
#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
|
||||
#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
|
||||
#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
|
||||
|
||||
#endif /* CONFIG_64BIT */
|
||||
|
||||
/*
|
||||
* This handles the memory map.
|
||||
*/
|
||||
#ifndef PAGE_OFFSET
|
||||
#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET)
|
||||
#endif
|
||||
|
||||
#ifndef FIXADDR_TOP
|
||||
#ifdef CONFIG_KVM_GUEST
|
||||
#define FIXADDR_TOP ((unsigned long)(long)(int)0x7ffe0000)
|
||||
#else
|
||||
#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_GENERIC_SPACES_H */
|
||||
@@ -0,0 +1,71 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2013 Imagination Technologies
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ASM_MALTA_H
|
||||
#define _MIPS_ASM_MALTA_H
|
||||
|
||||
#define MALTA_GT_BASE 0x1be00000
|
||||
#define MALTA_GT_PCIIO_BASE 0x18000000
|
||||
#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
|
||||
|
||||
#define MALTA_MSC01_BIU_BASE 0x1bc80000
|
||||
#define MALTA_MSC01_PCI_BASE 0x1bd00000
|
||||
#define MALTA_MSC01_PBC_BASE 0x1bd40000
|
||||
#define MALTA_MSC01_IP1_BASE 0x1bc00000
|
||||
#define MALTA_MSC01_IP1_SIZE 0x00400000
|
||||
#define MALTA_MSC01_IP2_BASE1 0x10000000
|
||||
#define MALTA_MSC01_IP2_SIZE1 0x08000000
|
||||
#define MALTA_MSC01_IP2_BASE2 0x18000000
|
||||
#define MALTA_MSC01_IP2_SIZE2 0x04000000
|
||||
#define MALTA_MSC01_IP3_BASE 0x1c000000
|
||||
#define MALTA_MSC01_IP3_SIZE 0x04000000
|
||||
#define MALTA_MSC01_PCIMEM_BASE 0x10000000
|
||||
#define MALTA_MSC01_PCIMEM_SIZE 0x10000000
|
||||
#define MALTA_MSC01_PCIMEM_MAP 0x10000000
|
||||
#define MALTA_MSC01_PCIIO_BASE 0x1b000000
|
||||
#define MALTA_MSC01_PCIIO_SIZE 0x00800000
|
||||
#define MALTA_MSC01_PCIIO_MAP 0x00000000
|
||||
#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8)
|
||||
|
||||
#define MALTA_ASCIIWORD 0x1f000410
|
||||
#define MALTA_ASCIIPOS0 0x1f000418
|
||||
#define MALTA_ASCIIPOS1 0x1f000420
|
||||
#define MALTA_ASCIIPOS2 0x1f000428
|
||||
#define MALTA_ASCIIPOS3 0x1f000430
|
||||
#define MALTA_ASCIIPOS4 0x1f000438
|
||||
#define MALTA_ASCIIPOS5 0x1f000440
|
||||
#define MALTA_ASCIIPOS6 0x1f000448
|
||||
#define MALTA_ASCIIPOS7 0x1f000450
|
||||
|
||||
#define MALTA_RESET_BASE 0x1f000500
|
||||
#define GORESET 0x42
|
||||
|
||||
#define MALTA_FLASH_BASE 0x1e000000
|
||||
|
||||
#define MALTA_REVISION 0x1fc00010
|
||||
#define MALTA_REVISION_CORID_SHF 10
|
||||
#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF)
|
||||
#define MALTA_REVISION_CORID_CORE_LV 1
|
||||
#define MALTA_REVISION_CORID_CORE_FPGA6 14
|
||||
|
||||
#define PCI_CFG_PIIX4_PIRQRCA 0x60
|
||||
#define PCI_CFG_PIIX4_PIRQRCB 0x61
|
||||
#define PCI_CFG_PIIX4_PIRQRCC 0x62
|
||||
#define PCI_CFG_PIIX4_PIRQRCD 0x63
|
||||
#define PCI_CFG_PIIX4_SERIRQC 0x64
|
||||
#define PCI_CFG_PIIX4_GENCFG 0xb0
|
||||
|
||||
#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7)
|
||||
#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6)
|
||||
|
||||
#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
|
||||
|
||||
#define PCI_CFG_PIIX4_IDETIM_PRI 0x40
|
||||
#define PCI_CFG_PIIX4_IDETIM_SEC 0x42
|
||||
|
||||
#define PCI_CFG_PIIX4_IDETIM_IDE (1 << 15)
|
||||
|
||||
#endif /* _MIPS_ASM_MALTA_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,282 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1994 - 2002 by Ralf Baechle
|
||||
* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
|
||||
* Copyright (C) 2002 Maciej W. Rozycki
|
||||
*/
|
||||
#ifndef _ASM_PGTABLE_BITS_H
|
||||
#define _ASM_PGTABLE_BITS_H
|
||||
|
||||
|
||||
/*
|
||||
* Note that we shift the lower 32bits of each EntryLo[01] entry
|
||||
* 6 bits to the left. That way we can convert the PFN into the
|
||||
* physical address by a single 'and' operation and gain 6 additional
|
||||
* bits for storing information which isn't present in a normal
|
||||
* MIPS page table.
|
||||
*
|
||||
* Similar to the Alpha port, we need to keep track of the ref
|
||||
* and mod bits in software. We have a software "yeah you can read
|
||||
* from this page" bit, and a hardware one which actually lets the
|
||||
* process read from the page. On the same token we have a software
|
||||
* writable bit and the real hardware one which actually lets the
|
||||
* process write to the page, this keeps a mod bit via the hardware
|
||||
* dirty bit.
|
||||
*
|
||||
* Certain revisions of the R4000 and R5000 have a bug where if a
|
||||
* certain sequence occurs in the last 3 instructions of an executable
|
||||
* page, and the following page is not mapped, the cpu can do
|
||||
* unpredictable things. The code (when it is written) to deal with
|
||||
* this problem will be in the update_mmu_cache() code for the r4k.
|
||||
*/
|
||||
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
|
||||
|
||||
/*
|
||||
* The following bits are implemented by the TLB hardware
|
||||
*/
|
||||
#define _PAGE_NO_EXEC_SHIFT 0
|
||||
#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
|
||||
#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
|
||||
#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
|
||||
#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
|
||||
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
|
||||
#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
|
||||
#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
|
||||
#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
|
||||
#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
|
||||
#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
|
||||
#define _CACHE_MASK (7 << _CACHE_SHIFT)
|
||||
|
||||
/*
|
||||
* The following bits are implemented in software
|
||||
*/
|
||||
#define _PAGE_PRESENT_SHIFT (24)
|
||||
#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
|
||||
#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
|
||||
#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
|
||||
#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
|
||||
#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
|
||||
#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
|
||||
#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
|
||||
#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
|
||||
#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
|
||||
|
||||
#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
|
||||
|
||||
/*
|
||||
* Bits for extended EntryLo0/EntryLo1 registers
|
||||
*/
|
||||
#define _PFNX_MASK 0xffffff
|
||||
|
||||
#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
||||
|
||||
/*
|
||||
* The following bits are implemented in software
|
||||
*/
|
||||
#define _PAGE_PRESENT_SHIFT (0)
|
||||
#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
|
||||
#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
|
||||
#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
|
||||
#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
|
||||
#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
|
||||
#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
|
||||
#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
|
||||
#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
|
||||
#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
|
||||
|
||||
/*
|
||||
* The following bits are implemented by the TLB hardware
|
||||
*/
|
||||
#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
|
||||
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
|
||||
#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
|
||||
#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
|
||||
#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
|
||||
#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
|
||||
#define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
|
||||
#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
|
||||
#define _CACHE_MASK _CACHE_UNCACHED
|
||||
|
||||
#define _PFN_SHIFT PAGE_SHIFT
|
||||
|
||||
#else
|
||||
/*
|
||||
* Below are the "Normal" R4K cases
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following bits are implemented in software
|
||||
*/
|
||||
#define _PAGE_PRESENT_SHIFT 0
|
||||
#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
|
||||
/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
|
||||
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
|
||||
#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
|
||||
#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
|
||||
#else
|
||||
#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
|
||||
#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
|
||||
#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
|
||||
#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
|
||||
#endif
|
||||
#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
|
||||
#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
|
||||
#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
|
||||
#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
|
||||
|
||||
#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
|
||||
/* Huge TLB page */
|
||||
#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
|
||||
#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
|
||||
#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
|
||||
#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
|
||||
#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
|
||||
|
||||
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
|
||||
/* XI - page cannot be executed */
|
||||
#ifdef _PAGE_SPLITTING_SHIFT
|
||||
#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
|
||||
#else
|
||||
#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
|
||||
#endif
|
||||
#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
|
||||
|
||||
/* RI - page cannot be read */
|
||||
#define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
|
||||
#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
|
||||
#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
|
||||
#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
|
||||
#endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */
|
||||
|
||||
#if defined(_PAGE_NO_READ_SHIFT)
|
||||
#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
|
||||
#elif defined(_PAGE_SPLITTING_SHIFT)
|
||||
#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
|
||||
#else
|
||||
#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
|
||||
#endif
|
||||
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
|
||||
|
||||
#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
|
||||
#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
|
||||
#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
|
||||
#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
|
||||
#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
|
||||
#define _CACHE_MASK (7 << _CACHE_SHIFT)
|
||||
|
||||
#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
|
||||
|
||||
#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
|
||||
|
||||
#ifndef _PAGE_NO_EXEC
|
||||
#define _PAGE_NO_EXEC 0
|
||||
#endif
|
||||
#ifndef _PAGE_NO_READ
|
||||
#define _PAGE_NO_READ 0
|
||||
#endif
|
||||
|
||||
#define _PAGE_SILENT_READ _PAGE_VALID
|
||||
#define _PAGE_SILENT_WRITE _PAGE_DIRTY
|
||||
|
||||
#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
|
||||
|
||||
/*
|
||||
* The final layouts of the PTE bits are:
|
||||
*
|
||||
* 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
|
||||
* 32-bit, R1 or earler: CCC D V G M A W R P
|
||||
* 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
|
||||
* 32-bit, R2 or later: CCC D V G RI/R XI M A W P
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/*
|
||||
* pte_to_entrylo converts a page table entry (PTE) into a Mips
|
||||
* entrylo0/1 value.
|
||||
*/
|
||||
static inline uint64_t pte_to_entrylo(unsigned long pte_val)
|
||||
{
|
||||
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
|
||||
if (cpu_has_rixi) {
|
||||
int sa;
|
||||
#ifdef CONFIG_32BIT
|
||||
sa = 31 - _PAGE_NO_READ_SHIFT;
|
||||
#else
|
||||
sa = 63 - _PAGE_NO_READ_SHIFT;
|
||||
#endif
|
||||
/*
|
||||
* C has no way to express that this is a DSRL
|
||||
* _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
|
||||
* in the fast path this is done in assembly
|
||||
*/
|
||||
return (pte_val >> _PAGE_GLOBAL_SHIFT) |
|
||||
((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
|
||||
}
|
||||
#endif
|
||||
|
||||
return pte_val >> _PAGE_GLOBAL_SHIFT;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Cache attributes
|
||||
*/
|
||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
||||
|
||||
#define _CACHE_CACHABLE_NONCOHERENT 0
|
||||
#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
|
||||
|
||||
#elif defined(CONFIG_CPU_SB1)
|
||||
|
||||
/* No penalty for being coherent on the SB1, so just
|
||||
use it for "noncoherent" spaces, too. Shouldn't hurt. */
|
||||
|
||||
#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
|
||||
|
||||
#elif defined(CONFIG_CPU_LOONGSON3)
|
||||
|
||||
/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
|
||||
|
||||
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
|
||||
#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
|
||||
|
||||
#elif defined(CONFIG_MACH_INGENIC)
|
||||
|
||||
/* Ingenic uses the WA bit to achieve write-combine memory writes */
|
||||
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef _CACHE_CACHABLE_NO_WA
|
||||
#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
|
||||
#endif
|
||||
#ifndef _CACHE_CACHABLE_WA
|
||||
#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
|
||||
#endif
|
||||
#ifndef _CACHE_UNCACHED
|
||||
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
|
||||
#endif
|
||||
#ifndef _CACHE_CACHABLE_NONCOHERENT
|
||||
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
|
||||
#endif
|
||||
#ifndef _CACHE_CACHABLE_CE
|
||||
#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
|
||||
#endif
|
||||
#ifndef _CACHE_CACHABLE_COW
|
||||
#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
|
||||
#endif
|
||||
#ifndef _CACHE_CACHABLE_CUW
|
||||
#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
|
||||
#endif
|
||||
#ifndef _CACHE_UNCACHED_ACCELERATED
|
||||
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
|
||||
#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
|
||||
|
||||
#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
|
||||
_PFN_MASK | _CACHE_MASK)
|
||||
|
||||
#endif /* _ASM_PGTABLE_BITS_H */
|
||||
@@ -0,0 +1,125 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle
|
||||
*/
|
||||
#ifndef _ASM_POSIX_TYPES_H
|
||||
#define _ASM_POSIX_TYPES_H
|
||||
|
||||
/*
|
||||
* This file is generally used by user-level software, so you need to
|
||||
* be a little careful about namespace pollution etc. Also, we cannot
|
||||
* assume GCC is being used.
|
||||
*/
|
||||
|
||||
typedef unsigned int __kernel_dev_t;
|
||||
typedef unsigned long __kernel_ino_t;
|
||||
typedef unsigned int __kernel_mode_t;
|
||||
typedef int __kernel_nlink_t;
|
||||
typedef long __kernel_off_t;
|
||||
typedef int __kernel_pid_t;
|
||||
typedef int __kernel_ipc_pid_t;
|
||||
typedef int __kernel_uid_t;
|
||||
typedef int __kernel_gid_t;
|
||||
#if _MIPS_SZLONG != 64
|
||||
typedef unsigned int __kernel_size_t;
|
||||
typedef int __kernel_ssize_t;
|
||||
typedef int __kernel_ptrdiff_t;
|
||||
#else
|
||||
typedef unsigned long __kernel_size_t;
|
||||
typedef long __kernel_ssize_t;
|
||||
typedef long __kernel_ptrdiff_t;
|
||||
#endif
|
||||
typedef long __kernel_time_t;
|
||||
typedef long __kernel_suseconds_t;
|
||||
typedef long __kernel_clock_t;
|
||||
typedef long __kernel_daddr_t;
|
||||
typedef char * __kernel_caddr_t;
|
||||
|
||||
typedef unsigned short __kernel_uid16_t;
|
||||
typedef unsigned short __kernel_gid16_t;
|
||||
typedef int __kernel_uid32_t;
|
||||
typedef int __kernel_gid32_t;
|
||||
typedef __kernel_uid_t __kernel_old_uid_t;
|
||||
typedef __kernel_gid_t __kernel_old_gid_t;
|
||||
|
||||
#ifdef __GNUC__
|
||||
typedef long long __kernel_loff_t;
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
long val[2];
|
||||
} __kernel_fsid_t;
|
||||
|
||||
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
|
||||
|
||||
#undef __FD_SET
|
||||
static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
|
||||
{
|
||||
unsigned long __tmp = __fd / __NFDBITS;
|
||||
unsigned long __rem = __fd % __NFDBITS;
|
||||
__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
|
||||
}
|
||||
|
||||
#undef __FD_CLR
|
||||
static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
|
||||
{
|
||||
unsigned long __tmp = __fd / __NFDBITS;
|
||||
unsigned long __rem = __fd % __NFDBITS;
|
||||
__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
|
||||
}
|
||||
|
||||
#undef __FD_ISSET
|
||||
static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
|
||||
{
|
||||
unsigned long __tmp = __fd / __NFDBITS;
|
||||
unsigned long __rem = __fd % __NFDBITS;
|
||||
return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This will unroll the loop for the normal constant case (8 ints,
|
||||
* for a 256-bit fd_set)
|
||||
*/
|
||||
#undef __FD_ZERO
|
||||
static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
|
||||
{
|
||||
unsigned long *__tmp = __p->fds_bits;
|
||||
int __i;
|
||||
|
||||
if (__builtin_constant_p(__FDSET_LONGS)) {
|
||||
switch (__FDSET_LONGS) {
|
||||
case 16:
|
||||
__tmp[ 0] = 0; __tmp[ 1] = 0;
|
||||
__tmp[ 2] = 0; __tmp[ 3] = 0;
|
||||
__tmp[ 4] = 0; __tmp[ 5] = 0;
|
||||
__tmp[ 6] = 0; __tmp[ 7] = 0;
|
||||
__tmp[ 8] = 0; __tmp[ 9] = 0;
|
||||
__tmp[10] = 0; __tmp[11] = 0;
|
||||
__tmp[12] = 0; __tmp[13] = 0;
|
||||
__tmp[14] = 0; __tmp[15] = 0;
|
||||
return;
|
||||
|
||||
case 8:
|
||||
__tmp[ 0] = 0; __tmp[ 1] = 0;
|
||||
__tmp[ 2] = 0; __tmp[ 3] = 0;
|
||||
__tmp[ 4] = 0; __tmp[ 5] = 0;
|
||||
__tmp[ 6] = 0; __tmp[ 7] = 0;
|
||||
return;
|
||||
|
||||
case 4:
|
||||
__tmp[ 0] = 0; __tmp[ 1] = 0;
|
||||
__tmp[ 2] = 0; __tmp[ 3] = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
__i = __FDSET_LONGS;
|
||||
while (__i) {
|
||||
__i--;
|
||||
*__tmp = 0;
|
||||
__tmp++;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
|
||||
|
||||
#endif /* _ASM_POSIX_TYPES_H */
|
||||
@@ -0,0 +1,137 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1994 Waldorf GMBH
|
||||
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
|
||||
* Copyright (C) 1996 Paul M. Antoine
|
||||
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef _ASM_PROCESSOR_H
|
||||
#define _ASM_PROCESSOR_H
|
||||
|
||||
#include <asm/isadep.h>
|
||||
|
||||
#include <asm/cachectl.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/reg.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
/*
|
||||
* Return current * instruction pointer ("program counter").
|
||||
*/
|
||||
#define current_text_addr() ({ __label__ _l; _l: &&_l;})
|
||||
|
||||
/*
|
||||
* System setup and hardware flags..
|
||||
*/
|
||||
extern void (*cpu_wait)(void);
|
||||
|
||||
extern unsigned int vced_count, vcei_count;
|
||||
|
||||
#define NUM_FPU_REGS 32
|
||||
|
||||
typedef __u64 fpureg_t;
|
||||
|
||||
/*
|
||||
* It would be nice to add some more fields for emulator statistics, but there
|
||||
* are a number of fixed offsets in offset.h and elsewhere that would have to
|
||||
* be recalculated by hand. So the additional information will be private to
|
||||
* the FPU emulator for now. See asm-mips/fpu_emulator.h.
|
||||
*/
|
||||
|
||||
struct mips_fpu_struct {
|
||||
fpureg_t fpr[NUM_FPU_REGS];
|
||||
unsigned int fcr31;
|
||||
};
|
||||
|
||||
#define NUM_DSP_REGS 6
|
||||
|
||||
typedef __u32 dspreg_t;
|
||||
|
||||
struct mips_dsp_state {
|
||||
dspreg_t dspr[NUM_DSP_REGS];
|
||||
unsigned int dspcontrol;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
unsigned long seg;
|
||||
} mm_segment_t;
|
||||
|
||||
#define ARCH_MIN_TASKALIGN 8
|
||||
|
||||
struct mips_abi;
|
||||
|
||||
/*
|
||||
* If you change thread_struct remember to change the #defines below too!
|
||||
*/
|
||||
struct thread_struct {
|
||||
/* Saved main processor registers. */
|
||||
unsigned long reg16;
|
||||
unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
|
||||
unsigned long reg29, reg30, reg31;
|
||||
|
||||
/* Saved cp0 stuff. */
|
||||
unsigned long cp0_status;
|
||||
|
||||
/* Saved fpu/fpu emulator stuff. */
|
||||
struct mips_fpu_struct fpu;
|
||||
#ifdef CONFIG_MIPS_MT_FPAFF
|
||||
/* Emulated instruction count */
|
||||
unsigned long emulated_fp;
|
||||
/* Saved per-thread scheduler affinity mask */
|
||||
cpumask_t user_cpus_allowed;
|
||||
#endif /* CONFIG_MIPS_MT_FPAFF */
|
||||
|
||||
/* Saved state of the DSP ASE, if available. */
|
||||
struct mips_dsp_state dsp;
|
||||
|
||||
/* Other stuff associated with the thread. */
|
||||
unsigned long cp0_badvaddr; /* Last user fault */
|
||||
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
|
||||
unsigned long error_code;
|
||||
unsigned long trap_no;
|
||||
unsigned long irix_trampoline; /* Wheee... */
|
||||
unsigned long irix_oldctx;
|
||||
struct mips_abi *abi;
|
||||
};
|
||||
|
||||
struct task_struct;
|
||||
|
||||
/* Free all resources held by a thread. */
|
||||
#define release_thread(thread) do { } while(0)
|
||||
|
||||
/* Prepare to copy thread state - unlazy all lazy status */
|
||||
#define prepare_to_copy(tsk) do { } while (0)
|
||||
|
||||
#define cpu_relax() barrier()
|
||||
|
||||
/*
|
||||
* Return_address is a replacement for __builtin_return_address(count)
|
||||
* which on certain architectures cannot reasonably be implemented in GCC
|
||||
* (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
|
||||
* Note that __builtin_return_address(x>=1) is forbidden because GCC
|
||||
* aborts compilation on some CPUs. It's simply not possible to unwind
|
||||
* some CPU's stackframes.
|
||||
*
|
||||
* __builtin_return_address works only for non-leaf functions. We avoid the
|
||||
* overhead of a function call by forcing the compiler to save the return
|
||||
* address register on the stack.
|
||||
*/
|
||||
#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_PREFETCH
|
||||
|
||||
#define ARCH_HAS_PREFETCH
|
||||
|
||||
static inline void prefetch(const void *addr)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" .set mips4 \n"
|
||||
" pref %0, (%1) \n"
|
||||
" .set mips0 \n"
|
||||
:
|
||||
: "i" (Pref_Load), "r" (addr));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_PROCESSOR_H */
|
||||
@@ -0,0 +1,105 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
|
||||
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef _ASM_PTRACE_H
|
||||
#define _ASM_PTRACE_H
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/isadep.h>
|
||||
|
||||
/*
|
||||
* This struct defines the way the registers are stored on the stack during a
|
||||
* system call/exception. As usual the registers k0/k1 aren't being saved.
|
||||
*
|
||||
* If you add a register here, also add it to regoffset_table[] in
|
||||
* arch/mips/kernel/ptrace.c.
|
||||
*/
|
||||
struct pt_regs {
|
||||
#ifdef CONFIG_32BIT
|
||||
/* Pad bytes for argument save space on the stack. */
|
||||
unsigned long pad0[8];
|
||||
#endif
|
||||
|
||||
/* Saved main processor registers. */
|
||||
unsigned long regs[32];
|
||||
|
||||
/* Saved special registers. */
|
||||
unsigned long cp0_status;
|
||||
unsigned long hi;
|
||||
unsigned long lo;
|
||||
#ifdef CONFIG_CPU_HAS_SMARTMIPS
|
||||
unsigned long acx;
|
||||
#endif
|
||||
unsigned long cp0_badvaddr;
|
||||
unsigned long cp0_cause;
|
||||
unsigned long cp0_epc;
|
||||
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
||||
unsigned long long mpl[6]; /* MTM{0-5} */
|
||||
unsigned long long mtp[6]; /* MTP{0-5} */
|
||||
#endif
|
||||
unsigned long __last[0];
|
||||
} __aligned(8);
|
||||
|
||||
static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
|
||||
{
|
||||
return regs->regs[31];
|
||||
}
|
||||
|
||||
/*
|
||||
* Don't use asm-generic/ptrace.h it defines FP accessors that don't make
|
||||
* sense on MIPS. We rather want an error if they get invoked.
|
||||
*/
|
||||
|
||||
static inline void instruction_pointer_set(struct pt_regs *regs,
|
||||
unsigned long val)
|
||||
{
|
||||
regs->cp0_epc = val;
|
||||
}
|
||||
|
||||
/* Query offset/name of register from its name/offset */
|
||||
extern int regs_query_register_offset(const char *name);
|
||||
#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
|
||||
|
||||
/**
|
||||
* regs_get_register() - get register value from its offset
|
||||
* @regs: pt_regs from which register value is gotten.
|
||||
* @offset: offset number of the register.
|
||||
*
|
||||
* regs_get_register returns the value of a register. The @offset is the
|
||||
* offset of the register in struct pt_regs address which specified by @regs.
|
||||
* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
|
||||
*/
|
||||
static inline unsigned long regs_get_register(struct pt_regs *regs,
|
||||
unsigned int offset)
|
||||
{
|
||||
if (unlikely(offset > MAX_REG_OFFSET))
|
||||
return 0;
|
||||
|
||||
return *(unsigned long *)((unsigned long)regs + offset);
|
||||
}
|
||||
|
||||
/*
|
||||
* Does the process account for user or for system time?
|
||||
*/
|
||||
#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
|
||||
|
||||
#define instruction_pointer(regs) ((regs)->cp0_epc)
|
||||
#define profile_pc(regs) instruction_pointer(regs)
|
||||
|
||||
/* Helpers for working with the user stack pointer */
|
||||
|
||||
static inline unsigned long user_stack_pointer(struct pt_regs *regs)
|
||||
{
|
||||
return regs->regs[29];
|
||||
}
|
||||
|
||||
static inline void user_stack_pointer_set(struct pt_regs *regs,
|
||||
unsigned long val)
|
||||
{
|
||||
regs->regs[29] = val;
|
||||
}
|
||||
|
||||
#endif /* _ASM_PTRACE_H */
|
||||
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
|
||||
* Copyright (C) 2001 MIPS Technologies, Inc.
|
||||
*/
|
||||
#ifndef _ASM_REBOOT_H
|
||||
#define _ASM_REBOOT_H
|
||||
|
||||
extern void _machine_restart(void);
|
||||
|
||||
#endif /* _ASM_REBOOT_H */
|
||||
@@ -0,0 +1,123 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Various register offset definitions for debuggers, core file
|
||||
* examiners and whatnot.
|
||||
*
|
||||
* Copyright (C) 1995, 1999 by Ralf Baechle
|
||||
* Copyright (C) 1995, 1999 Silicon Graphics
|
||||
*/
|
||||
#ifndef __ASM_MIPS_REG_H
|
||||
#define __ASM_MIPS_REG_H
|
||||
|
||||
#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
|
||||
|
||||
#define EF_R0 6
|
||||
#define EF_R1 7
|
||||
#define EF_R2 8
|
||||
#define EF_R3 9
|
||||
#define EF_R4 10
|
||||
#define EF_R5 11
|
||||
#define EF_R6 12
|
||||
#define EF_R7 13
|
||||
#define EF_R8 14
|
||||
#define EF_R9 15
|
||||
#define EF_R10 16
|
||||
#define EF_R11 17
|
||||
#define EF_R12 18
|
||||
#define EF_R13 19
|
||||
#define EF_R14 20
|
||||
#define EF_R15 21
|
||||
#define EF_R16 22
|
||||
#define EF_R17 23
|
||||
#define EF_R18 24
|
||||
#define EF_R19 25
|
||||
#define EF_R20 26
|
||||
#define EF_R21 27
|
||||
#define EF_R22 28
|
||||
#define EF_R23 29
|
||||
#define EF_R24 30
|
||||
#define EF_R25 31
|
||||
|
||||
/*
|
||||
* k0/k1 unsaved
|
||||
*/
|
||||
#define EF_R26 32
|
||||
#define EF_R27 33
|
||||
|
||||
#define EF_R28 34
|
||||
#define EF_R29 35
|
||||
#define EF_R30 36
|
||||
#define EF_R31 37
|
||||
|
||||
/*
|
||||
* Saved special registers
|
||||
*/
|
||||
#define EF_LO 38
|
||||
#define EF_HI 39
|
||||
|
||||
#define EF_CP0_EPC 40
|
||||
#define EF_CP0_BADVADDR 41
|
||||
#define EF_CP0_STATUS 42
|
||||
#define EF_CP0_CAUSE 43
|
||||
#define EF_UNUSED0 44
|
||||
|
||||
#define EF_SIZE 180
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
|
||||
#define EF_R0 0
|
||||
#define EF_R1 1
|
||||
#define EF_R2 2
|
||||
#define EF_R3 3
|
||||
#define EF_R4 4
|
||||
#define EF_R5 5
|
||||
#define EF_R6 6
|
||||
#define EF_R7 7
|
||||
#define EF_R8 8
|
||||
#define EF_R9 9
|
||||
#define EF_R10 10
|
||||
#define EF_R11 11
|
||||
#define EF_R12 12
|
||||
#define EF_R13 13
|
||||
#define EF_R14 14
|
||||
#define EF_R15 15
|
||||
#define EF_R16 16
|
||||
#define EF_R17 17
|
||||
#define EF_R18 18
|
||||
#define EF_R19 19
|
||||
#define EF_R20 20
|
||||
#define EF_R21 21
|
||||
#define EF_R22 22
|
||||
#define EF_R23 23
|
||||
#define EF_R24 24
|
||||
#define EF_R25 25
|
||||
|
||||
/*
|
||||
* k0/k1 unsaved
|
||||
*/
|
||||
#define EF_R26 26
|
||||
#define EF_R27 27
|
||||
|
||||
#define EF_R28 28
|
||||
#define EF_R29 29
|
||||
#define EF_R30 30
|
||||
#define EF_R31 31
|
||||
|
||||
/*
|
||||
* Saved special registers
|
||||
*/
|
||||
#define EF_LO 32
|
||||
#define EF_HI 33
|
||||
|
||||
#define EF_CP0_EPC 34
|
||||
#define EF_CP0_BADVADDR 35
|
||||
#define EF_CP0_STATUS 36
|
||||
#define EF_CP0_CAUSE 37
|
||||
|
||||
#define EF_SIZE 304 /* size in bytes */
|
||||
|
||||
#endif /* CONFIG_64BIT */
|
||||
|
||||
#endif /* __ASM_MIPS_REG_H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user