GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*/
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#ifndef __ASM_NIOS2_BITOPS_H_
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#define __ASM_NIOS2_BITOPS_H_
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/* copied from linux-2.6/include/asm-generic/bitops */
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#include <asm/bitops/atomic.h>
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#include <asm/bitops/non-atomic.h>
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#include <asm/bitops/ffs.h>
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#include <asm-generic/bitops/fls.h>
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/__ffs.h>
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#endif /* __ASM_NIOS2_BITOPS_H */
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@@ -0,0 +1,189 @@
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#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_
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#define _ASM_GENERIC_BITOPS_ATOMIC_H_
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#include <asm/types.h>
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#include <asm/system.h>
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#ifdef CONFIG_SMP
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#include <asm/spinlock.h>
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#include <asm/cache.h> /* we use L1_CACHE_BYTES */
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/* Use an array of spinlocks for our atomic_ts.
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* Hash function to index into a different SPINLOCK.
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* Since "a" is usually an address, use one spinlock per cacheline.
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*/
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# define ATOMIC_HASH_SIZE 4
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# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
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extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
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/* Can't use raw_spin_lock_irq because of #include problems, so
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* this is the substitute */
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#define _atomic_spin_lock_irqsave(l,f) do { \
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raw_spinlock_t *s = ATOMIC_HASH(l); \
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local_irq_save(f); \
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__raw_spin_lock(s); \
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} while(0)
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#define _atomic_spin_unlock_irqrestore(l,f) do { \
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raw_spinlock_t *s = ATOMIC_HASH(l); \
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__raw_spin_unlock(s); \
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local_irq_restore(f); \
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} while(0)
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#else
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# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
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# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
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#endif
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/*
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* NMI events can occur at any time, including when interrupts have been
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* disabled by *_irqsave(). So you can get NMI events occurring while a
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* *_bit function is holding a spin lock. If the NMI handler also wants
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* to do bit manipulation (and they do) then you can get a deadlock
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* between the original caller of *_bit() and the NMI handler.
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*
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* by Keith Owens
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*/
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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*
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* Note: there are no guarantees that this function will not be reordered
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* on non x86 architectures, so if you are writing portable code,
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* make sure not to rely on its reordering guarantees.
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*
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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*p |= mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static inline void clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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*p &= ~mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered. It may be
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* reordered on other architectures than x86.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void change_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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*p ^= mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It may be reordered on other architectures than x86.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old;
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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old = *p;
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*p = old | mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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return (old & mask) != 0;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It can be reorderdered on other architectures other than x86.
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* It also implies a memory barrier.
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*/
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static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old;
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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old = *p;
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*p = old & ~mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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return (old & mask) != 0;
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old;
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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old = *p;
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*p = old ^ mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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return (old & mask) != 0;
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}
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#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */
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@@ -0,0 +1,41 @@
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#ifndef _ASM_GENERIC_BITOPS_FFS_H_
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#define _ASM_GENERIC_BITOPS_FFS_H_
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/**
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* ffs - find first bit set
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* @x: the word to search
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*
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* This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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* differs in spirit from the above ffz (man ffs).
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*/
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static inline int ffs(int x)
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{
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int r = 1;
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if (!x)
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return 0;
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if (!(x & 0xffff)) {
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x >>= 16;
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r += 16;
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}
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if (!(x & 0xff)) {
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x >>= 8;
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r += 8;
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}
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if (!(x & 0xf)) {
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x >>= 4;
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r += 4;
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}
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if (!(x & 3)) {
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x >>= 2;
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r += 2;
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}
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if (!(x & 1)) {
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x >>= 1;
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r += 1;
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}
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return r;
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}
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#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */
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@@ -0,0 +1,112 @@
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#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
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#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
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#include <asm/types.h>
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/**
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* __set_bit - Set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike set_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static inline void __set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p |= mask;
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}
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#define PLATFORM__SET_BIT
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static inline void __clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p &= ~mask;
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}
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#define PLATFORM__CLEAR_BIT
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/**
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to change
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static inline void __change_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p ^= mask;
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}
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/**
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* __test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old | mask;
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return (old & mask) != 0;
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}
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/**
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* __test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old & ~mask;
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return (old & mask) != 0;
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}
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/* WARNING: non atomic and it can be reordered! */
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static inline int __test_and_change_bit(int nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old ^ mask;
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return (old & mask) != 0;
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}
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/**
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* test_bit - Determine whether a bit is set
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* @nr: bit number to test
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* @addr: Address to start counting from
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*/
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static inline int test_bit(int nr, const volatile unsigned long *addr)
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{
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return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
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}
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#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */
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@@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*/
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#ifndef __ASM_NIOS2_BYTEORDER_H_
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#define __ASM_NIOS2_BYTEORDER_H_
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#include <asm/types.h>
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#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
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# define __BYTEORDER_HAS_U64__
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# define __SWAB_64_THRU_32__
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#endif
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#include <linux/byteorder/little_endian.h>
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#endif /* __ASM_NIOS2_BYTEORDER_H_ */
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@@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
|
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/*
|
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
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* Scott McNutt <smcnutt@psyent.com>
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*/
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#ifndef __ASM_NIOS2_CACHE_H_
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#define __ASM_NIOS2_CACHE_H_
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/*
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* Valid L1 data cache line sizes for the NIOS2 architecture are 4,
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* 16, and 32 bytes. We default to the largest of these values for
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* alignment of DMA buffers.
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*/
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#define ARCH_DMA_MINALIGN 32
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#endif /* __ASM_NIOS2_CACHE_H_ */
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@@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*/
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#endif
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@@ -0,0 +1,24 @@
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#ifndef __ASM_NIOS2_DMA_MAPPING_H
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#define __ASM_NIOS2_DMA_MAPPING_H
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#include <memalign.h>
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#include <asm/io.h>
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|
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/*
|
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* dma_alloc_coherent() return cache-line aligned allocation which is mapped
|
||||
* to uncached io region.
|
||||
*/
|
||||
static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
|
||||
{
|
||||
unsigned long addr = (unsigned long)malloc_cache_aligned(len);
|
||||
|
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if (!addr)
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return NULL;
|
||||
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invalidate_dcache_range(addr, addr + len);
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if (handle)
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*handle = addr;
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return map_physmem(addr, len, MAP_NOCACHE);
|
||||
}
|
||||
#endif /* __ASM_NIOS2_DMA_MAPPING_H */
|
||||
@@ -0,0 +1,28 @@
|
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/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
||||
* Scott McNutt <smcnutt@psyent.com>
|
||||
*/
|
||||
#ifndef __ASM_NIOS2_GLOBALDATA_H_
|
||||
#define __ASM_NIOS2_GLOBALDATA_H_
|
||||
|
||||
/* Architecture-specific global data */
|
||||
struct arch_global_data {
|
||||
u32 dcache_line_size;
|
||||
u32 icache_line_size;
|
||||
u32 dcache_size;
|
||||
u32 icache_size;
|
||||
u32 reset_addr;
|
||||
u32 exception_addr;
|
||||
int has_initda;
|
||||
int has_mmu;
|
||||
u32 io_region_base;
|
||||
u32 mem_region_base;
|
||||
u32 physaddr_mask;
|
||||
};
|
||||
|
||||
#include <asm-generic/global_data.h>
|
||||
|
||||
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
|
||||
|
||||
#endif /* __ASM_NIOS2_GLOBALDATA_H_ */
|
||||
@@ -0,0 +1 @@
|
||||
#include <asm-generic/gpio.h>
|
||||
@@ -0,0 +1,174 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
||||
* Scott McNutt <smcnutt@psyent.com>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_NIOS2_IO_H_
|
||||
#define __ASM_NIOS2_IO_H_
|
||||
|
||||
static inline void sync(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sync" : : : "memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* Given a physical address and a length, return a virtual address
|
||||
* that can be used to access the memory range with the caching
|
||||
* properties specified by "flags".
|
||||
*/
|
||||
#define MAP_NOCACHE 1
|
||||
|
||||
static inline void *
|
||||
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
if (flags)
|
||||
return (void *)(paddr | gd->arch.io_region_base);
|
||||
else
|
||||
return (void *)(paddr | gd->arch.mem_region_base);
|
||||
}
|
||||
#define map_physmem map_physmem
|
||||
|
||||
static inline void *phys_to_virt(phys_addr_t paddr)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
return (void *)(paddr | gd->arch.mem_region_base);
|
||||
}
|
||||
#define phys_to_virt phys_to_virt
|
||||
|
||||
static inline phys_addr_t virt_to_phys(void * vaddr)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
return (phys_addr_t)vaddr & gd->arch.physaddr_mask;
|
||||
}
|
||||
#define virt_to_phys virt_to_phys
|
||||
|
||||
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
|
||||
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
|
||||
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
|
||||
|
||||
#define __raw_readb(a) (*(volatile unsigned char *)(a))
|
||||
#define __raw_readw(a) (*(volatile unsigned short *)(a))
|
||||
#define __raw_readl(a) (*(volatile unsigned int *)(a))
|
||||
|
||||
#define readb(addr)\
|
||||
({unsigned char val;\
|
||||
asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
|
||||
#define readw(addr)\
|
||||
({unsigned short val;\
|
||||
asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
|
||||
#define readl(addr)\
|
||||
({unsigned long val;\
|
||||
asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
|
||||
|
||||
#define writeb(val,addr)\
|
||||
asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr))
|
||||
#define writew(val,addr)\
|
||||
asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr))
|
||||
#define writel(val,addr)\
|
||||
asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr))
|
||||
|
||||
#define inb(addr) readb(addr)
|
||||
#define inw(addr) readw(addr)
|
||||
#define inl(addr) readl(addr)
|
||||
#define outb(val, addr) writeb(val,addr)
|
||||
#define outw(val, addr) writew(val,addr)
|
||||
#define outl(val, addr) writel(val,addr)
|
||||
|
||||
static inline void insb (unsigned long port, void *dst, unsigned long count)
|
||||
{
|
||||
unsigned char *p = dst;
|
||||
while (count--) *p++ = inb (port);
|
||||
}
|
||||
static inline void insw (unsigned long port, void *dst, unsigned long count)
|
||||
{
|
||||
unsigned short *p = dst;
|
||||
while (count--) *p++ = inw (port);
|
||||
}
|
||||
static inline void insl (unsigned long port, void *dst, unsigned long count)
|
||||
{
|
||||
unsigned long *p = dst;
|
||||
while (count--) *p++ = inl (port);
|
||||
}
|
||||
|
||||
static inline void outsb (unsigned long port, const void *src, unsigned long count)
|
||||
{
|
||||
const unsigned char *p = src;
|
||||
while (count--) outb (*p++, port);
|
||||
}
|
||||
|
||||
static inline void outsw (unsigned long port, const void *src, unsigned long count)
|
||||
{
|
||||
const unsigned short *p = src;
|
||||
while (count--) outw (*p++, port);
|
||||
}
|
||||
static inline void outsl (unsigned long port, const void *src, unsigned long count)
|
||||
{
|
||||
const unsigned long *p = src;
|
||||
while (count--) outl (*p++, port);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear and set bits in one shot. These macros can be used to clear and
|
||||
* set multiple bits in a register using a single call. These macros can
|
||||
* also be used to set a multiple-bit bit pattern using a mask, by
|
||||
* specifying the mask in the 'clear' parameter and the new bit pattern
|
||||
* in the 'set' parameter.
|
||||
*/
|
||||
|
||||
#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a)
|
||||
#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a))
|
||||
|
||||
#define out_le32(a,v) out_arch(l,le32,a,v)
|
||||
#define out_le16(a,v) out_arch(w,le16,a,v)
|
||||
|
||||
#define in_le32(a) in_arch(l,le32,a)
|
||||
#define in_le16(a) in_arch(w,le16,a)
|
||||
|
||||
#define out_be32(a,v) out_arch(l,be32,a,v)
|
||||
#define out_be16(a,v) out_arch(w,be16,a,v)
|
||||
|
||||
#define in_be32(a) in_arch(l,be32,a)
|
||||
#define in_be16(a) in_arch(w,be16,a)
|
||||
|
||||
#define out_8(a,v) __raw_writeb(v,a)
|
||||
#define in_8(a) __raw_readb(a)
|
||||
|
||||
#define clrbits(type, addr, clear) \
|
||||
out_##type((addr), in_##type(addr) & ~(clear))
|
||||
|
||||
#define setbits(type, addr, set) \
|
||||
out_##type((addr), in_##type(addr) | (set))
|
||||
|
||||
#define clrsetbits(type, addr, clear, set) \
|
||||
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
|
||||
|
||||
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
|
||||
#define setbits_be32(addr, set) setbits(be32, addr, set)
|
||||
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
|
||||
|
||||
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
|
||||
#define setbits_le32(addr, set) setbits(le32, addr, set)
|
||||
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
|
||||
|
||||
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
|
||||
#define setbits_be16(addr, set) setbits(be16, addr, set)
|
||||
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
|
||||
|
||||
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
|
||||
#define setbits_le16(addr, set) setbits(le16, addr, set)
|
||||
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
|
||||
|
||||
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
|
||||
#define setbits_8(addr, set) setbits(8, addr, set)
|
||||
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
|
||||
|
||||
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
|
||||
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
|
||||
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
|
||||
|
||||
#include <asm-generic/io.h>
|
||||
|
||||
#endif /* __ASM_NIOS2_IO_H_ */
|
||||
@@ -0,0 +1,39 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
||||
* Scott McNutt <smcnutt@psyent.com>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_NIOS2_H__
|
||||
#define __ASM_NIOS2_H__
|
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* Control registers -- use with wrctl() & rdctl()
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CTL_STATUS 0 /* Processor status reg */
|
||||
#define CTL_ESTATUS 1 /* Exception status reg */
|
||||
#define CTL_BSTATUS 2 /* Break status reg */
|
||||
#define CTL_IENABLE 3 /* Interrut enable reg */
|
||||
#define CTL_IPENDING 4 /* Interrut pending reg */
|
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* Access to control regs
|
||||
*----------------------------------------------------------------------*/
|
||||
|
||||
#define rdctl(reg) __builtin_rdctl(reg)
|
||||
#define wrctl(reg, val) __builtin_wrctl(reg, val)
|
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* Control reg bit masks
|
||||
*----------------------------------------------------------------------*/
|
||||
#define STATUS_IE (1<<0) /* Interrupt enable */
|
||||
#define STATUS_U (1<<1) /* User-mode */
|
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* Bit-31 Cache bypass -- only valid for data access. When data cache
|
||||
* is not implemented, bit 31 is ignored for compatibility.
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CACHE_BYPASS(a) ((a) | 0x80000000)
|
||||
#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000)
|
||||
|
||||
#endif /* __ASM_NIOS2_H__ */
|
||||
@@ -0,0 +1,114 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
||||
* Scott McNutt <smcnutt@psyent.com>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_NIOS2_OPCODES_H_
|
||||
#define __ASM_NIOS2_OPCODES_H_
|
||||
|
||||
#define OPCODE_OP(inst) ((inst) & 0x3f)
|
||||
#define OPCODE_OPX(inst) (((inst)>>11) & 0x3f)
|
||||
#define OPCODE_RA(inst) (((inst)>>27) & 01f)
|
||||
#define OPCODE_RB(inst) (((inst)>>22) & 01f)
|
||||
#define OPCODE_RC(inst) (((inst)>>17) & 01f)
|
||||
|
||||
/* I-TYPE (immediate) and J-TYPE (jump) opcodes
|
||||
*/
|
||||
#define OPCODE_CALL 0x00
|
||||
#define OPCODE_LDBU 0x03
|
||||
#define OPCODE_ADDI 0x04
|
||||
#define OPCODE_STB 0x05
|
||||
#define OPCODE_BR 0x06
|
||||
#define OPCODE_LDB 0x07
|
||||
#define OPCODE_CMPGEI 0x08
|
||||
#define OPCODE_LDHU 0x0B
|
||||
#define OPCODE_ANDI 0x0C
|
||||
#define OPCODE_STH 0x0D
|
||||
#define OPCODE_BGE 0x0E
|
||||
#define OPCODE_LDH 0x0F
|
||||
#define OPCODE_CMPLTI 0x10
|
||||
#define OPCODE_XORI 0x1C
|
||||
#define OPCODE_ORI 0x14
|
||||
#define OPCODE_STW 0x15
|
||||
#define OPCODE_BLT 0x16
|
||||
#define OPCODE_LDW 0x17
|
||||
#define OPCODE_CMPNEI 0x18
|
||||
#define OPCODE_BNE 0x1E
|
||||
#define OPCODE_CMPEQI 0x20
|
||||
#define OPCODE_LDBUIO 0x23
|
||||
#define OPCODE_MULI 0x24
|
||||
#define OPCODE_STBIO 0x25
|
||||
#define OPCODE_BEQ 0x26
|
||||
#define OPCODE_LDBIO 0x27
|
||||
#define OPCODE_CMPGEUI 0x28
|
||||
#define OPCODE_ANDHI 0x2C
|
||||
#define OPCODE_STHIO 0x2D
|
||||
#define OPCODE_BGEU 0x2E
|
||||
#define OPCODE_LDHIO 0x2F
|
||||
#define OPCODE_CMPLTUI 0x30
|
||||
#define OPCODE_CUSTOM 0x32
|
||||
#define OPCODE_INITD 0x33
|
||||
#define OPCODE_ORHI 0x34
|
||||
#define OPCODE_STWIO 0x35
|
||||
#define OPCODE_BLTU 0x36
|
||||
#define OPCODE_LDWIO 0x37
|
||||
#define OPCODE_RTYPE 0x3A
|
||||
#define OPCODE_LDHUIO 0x2B
|
||||
#define OPCODE_FLUSHD 0x3B
|
||||
#define OPCODE_XORHI 0x3C
|
||||
|
||||
/* R-Type (register) OPX field encodings
|
||||
*/
|
||||
#define OPCODE_ERET 0x01
|
||||
#define OPCODE_ROLI 0x02
|
||||
#define OPCODE_ROL 0x03
|
||||
#define OPCODE_FLUSHP 0x04
|
||||
#define OPCODE_RET 0x05
|
||||
#define OPCODE_NOR 0x06
|
||||
#define OPCODE_MULXUU 0x07
|
||||
#define OPCODE_CMPGE 0x08
|
||||
#define OPCODE_BRET 0x09
|
||||
#define OPCODE_ROR 0x0B
|
||||
#define OPCODE_FLUSHI 0x0C
|
||||
#define OPCODE_JMP 0x0D
|
||||
#define OPCODE_AND 0x0E
|
||||
|
||||
#define OPCODE_CMPLT 0x10
|
||||
#define OPCODE_SLLI 0x12
|
||||
#define OPCODE_SLL 0x13
|
||||
#define OPCODE_OR 0x16
|
||||
#define OPCODE_MULXSU 0x17
|
||||
#define OPCODE_CMPNE 0x18
|
||||
#define OPCODE_SRLI 0x1A
|
||||
#define OPCODE_SRL 0x1B
|
||||
#define OPCODE_NEXTPC 0x1C
|
||||
#define OPCODE_CALLR 0x1D
|
||||
#define OPCODE_XOR 0x1E
|
||||
#define OPCODE_MULXSS 0x1F
|
||||
|
||||
#define OPCODE_CMPEQ 0x20
|
||||
#define OPCODE_CMPLTU 0x30
|
||||
#define OPCODE_ADD 0x31
|
||||
#define OPCODE_DIVU 0x24
|
||||
#define OPCODE_DIV 0x25
|
||||
#define OPCODE_RDCTL 0x26
|
||||
#define OPCODE_MUL 0x27
|
||||
#define OPCODE_CMPGEU 0x28
|
||||
#define OPCODE_TRAP 0x2D
|
||||
#define OPCODE_WRCTL 0x2E
|
||||
|
||||
#define OPCODE_BREAK 0x34
|
||||
#define OPCODE_SYNC 0x36
|
||||
#define OPCODE_INITI 0x29
|
||||
#define OPCODE_SUB 0x39
|
||||
#define OPCODE_SRAI 0x3A
|
||||
#define OPCODE_SRA 0x3B
|
||||
|
||||
/*Full instruction encodings for R-Type, without the R's ;-)
|
||||
*
|
||||
* TODO: BREAK, BRET, ERET, RET, SYNC (as needed)
|
||||
*/
|
||||
#define OPC_TRAP 0x003b683a
|
||||
|
||||
#endif /* __ASM_NIOS2_OPCODES_H_ */
|
||||
@@ -0,0 +1,67 @@
|
||||
#ifndef __ASM_NIOS2_POSIX_TYPES_H_
|
||||
#define __ASM_NIOS2_POSIX_TYPES_H_
|
||||
|
||||
/*
|
||||
* This file is generally used by user-level software, so you need to
|
||||
* be a little careful about namespace pollution etc. Also, we cannot
|
||||
* assume GCC is being used.
|
||||
*/
|
||||
|
||||
typedef unsigned short __kernel_dev_t;
|
||||
typedef unsigned long __kernel_ino_t;
|
||||
typedef unsigned short __kernel_mode_t;
|
||||
typedef unsigned short __kernel_nlink_t;
|
||||
typedef long __kernel_off_t;
|
||||
typedef int __kernel_pid_t;
|
||||
typedef unsigned short __kernel_ipc_pid_t;
|
||||
typedef unsigned short __kernel_uid_t;
|
||||
typedef unsigned short __kernel_gid_t;
|
||||
#ifdef __GNUC__
|
||||
typedef __SIZE_TYPE__ __kernel_size_t;
|
||||
#else
|
||||
typedef unsigned long __kernel_size_t;
|
||||
#endif
|
||||
typedef long __kernel_ssize_t;
|
||||
typedef int __kernel_ptrdiff_t;
|
||||
typedef long __kernel_time_t;
|
||||
typedef long __kernel_suseconds_t;
|
||||
typedef long __kernel_clock_t;
|
||||
typedef int __kernel_daddr_t;
|
||||
typedef char * __kernel_caddr_t;
|
||||
typedef unsigned short __kernel_uid16_t;
|
||||
typedef unsigned short __kernel_gid16_t;
|
||||
typedef unsigned int __kernel_uid32_t;
|
||||
typedef unsigned int __kernel_gid32_t;
|
||||
|
||||
typedef unsigned short __kernel_old_uid_t;
|
||||
typedef unsigned short __kernel_old_gid_t;
|
||||
|
||||
#ifdef __GNUC__
|
||||
typedef long long __kernel_loff_t;
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
#if defined(__KERNEL__) || defined(__USE_ALL)
|
||||
int val[2];
|
||||
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
|
||||
int __val[2];
|
||||
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
|
||||
} __kernel_fsid_t;
|
||||
|
||||
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
|
||||
|
||||
#undef __FD_SET
|
||||
#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
|
||||
|
||||
#undef __FD_CLR
|
||||
#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
|
||||
|
||||
#undef __FD_ISSET
|
||||
#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
|
||||
|
||||
#undef __FD_ZERO
|
||||
#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
|
||||
|
||||
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
|
||||
|
||||
#endif /* __ASM_NIOS2_POSIX_TYPES_H_ */
|
||||
@@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
||||
* Scott McNutt <smcnutt@psyent.com>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_NIOS2_PROCESSOR_H_
|
||||
#define __ASM_NIOS2_PROCESSOR_H_
|
||||
#endif /* __ASM_NIOS2_PROCESSOR_H_ */
|
||||
@@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
||||
* Scott McNutt <smcnutt@psyent.com>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_NIOS2_PTRACE_H_
|
||||
#define __ASM_NIOS2_PTRACE_H_
|
||||
|
||||
struct pt_regs {
|
||||
unsigned reg[32];
|
||||
unsigned status;
|
||||
};
|
||||
|
||||
|
||||
#endif /* __ASM_NIOS2_PTRACE_H_ */
|
||||
@@ -0,0 +1 @@
|
||||
#include <asm-generic/sections.h>
|
||||
@@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
||||
* Scott McNutt <smcnutt@psyent.com>
|
||||
*/
|
||||
#ifndef __ASM_NIOS2_STRING_H_
|
||||
#define __ASM_NIOS2_STRING_H_
|
||||
|
||||
#undef __HAVE_ARCH_STRRCHR
|
||||
extern char * strrchr(const char * s, int c);
|
||||
|
||||
#undef __HAVE_ARCH_STRCHR
|
||||
extern char * strchr(const char * s, int c);
|
||||
|
||||
#undef __HAVE_ARCH_MEMCPY
|
||||
extern void * memcpy(void *, const void *, __kernel_size_t);
|
||||
|
||||
#undef __HAVE_ARCH_MEMMOVE
|
||||
extern void * memmove(void *, const void *, __kernel_size_t);
|
||||
|
||||
#undef __HAVE_ARCH_MEMCHR
|
||||
extern void * memchr(const void *, int, __kernel_size_t);
|
||||
|
||||
#undef __HAVE_ARCH_MEMSET
|
||||
extern void * memset(void *, int, __kernel_size_t);
|
||||
|
||||
#undef __HAVE_ARCH_MEMZERO
|
||||
extern void memzero(void *ptr, __kernel_size_t n);
|
||||
|
||||
#endif /* __ASM_NIOS2_STRING_H_ */
|
||||
@@ -0,0 +1,49 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
||||
* Scott McNutt <smcnutt@psyent.com>
|
||||
*/
|
||||
#ifndef __ASM_NIOS2_SYSTEM_H_
|
||||
#define __ASM_NIOS2_SYSTEM_H_
|
||||
|
||||
#define local_irq_enable() __asm__ __volatile__ ( \
|
||||
"rdctl r8, status\n" \
|
||||
"ori r8, r8, 1\n" \
|
||||
"wrctl status, r8\n" \
|
||||
: : : "r8")
|
||||
|
||||
#define local_irq_disable() __asm__ __volatile__ ( \
|
||||
"rdctl r8, status\n" \
|
||||
"andi r8, r8, 0xfffe\n" \
|
||||
"wrctl status, r8\n" \
|
||||
: : : "r8")
|
||||
|
||||
#define local_save_flags(x) __asm__ __volatile__ ( \
|
||||
"rdctl r8, status\n" \
|
||||
"mov %0, r8\n" \
|
||||
: "=r" (x) : : "r8", "memory")
|
||||
|
||||
#define local_irq_restore(x) __asm__ __volatile__ ( \
|
||||
"mov r8, %0\n" \
|
||||
"wrctl status, r8\n" \
|
||||
: : "r" (x) : "r8", "memory")
|
||||
|
||||
/* For spinlocks etc */
|
||||
#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \
|
||||
while (0)
|
||||
|
||||
#define irqs_disabled() \
|
||||
({ \
|
||||
unsigned long flags; \
|
||||
local_save_flags(flags); \
|
||||
((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \
|
||||
})
|
||||
|
||||
/* indirect call to go beyond 256MB limitation of toolchain */
|
||||
#define nios2_callr(addr) __asm__ __volatile__ ( \
|
||||
"callr %0" \
|
||||
: : "r" (addr))
|
||||
|
||||
void display_sysid(void);
|
||||
|
||||
#endif /* __ASM_NIOS2_SYSTEM_H */
|
||||
@@ -0,0 +1,60 @@
|
||||
#ifndef __ASM_NIOS2_TYPES_H_
|
||||
#define __ASM_NIOS2_TYPES_H_
|
||||
|
||||
/*
|
||||
* This file is never included by application software unless
|
||||
* explicitly requested (e.g., via linux/types.h) in which case the
|
||||
* application is Linux specific so (user-) name space pollution is
|
||||
* not a major issue. However, for interoperability, libraries still
|
||||
* need to be careful to avoid a name clashes.
|
||||
*/
|
||||
|
||||
typedef unsigned short umode_t;
|
||||
|
||||
/*
|
||||
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
|
||||
* header files exported to user space
|
||||
*/
|
||||
|
||||
typedef __signed__ char __s8;
|
||||
typedef unsigned char __u8;
|
||||
|
||||
typedef __signed__ short __s16;
|
||||
typedef unsigned short __u16;
|
||||
|
||||
typedef __signed__ int __s32;
|
||||
typedef unsigned int __u32;
|
||||
|
||||
#if defined(__GNUC__)
|
||||
__extension__ typedef __signed__ long long __s64;
|
||||
__extension__ typedef unsigned long long __u64;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These aren't exported outside the kernel to avoid name space clashes
|
||||
*/
|
||||
#ifdef __KERNEL__
|
||||
|
||||
typedef signed char s8;
|
||||
typedef unsigned char u8;
|
||||
|
||||
typedef signed short s16;
|
||||
typedef unsigned short u16;
|
||||
|
||||
typedef signed int s32;
|
||||
typedef unsigned int u32;
|
||||
|
||||
typedef signed long long s64;
|
||||
typedef unsigned long long u64;
|
||||
|
||||
#define BITS_PER_LONG 32
|
||||
|
||||
/* Dma addresses are 32-bits wide. */
|
||||
|
||||
typedef u32 dma_addr_t;
|
||||
|
||||
typedef unsigned long phys_addr_t;
|
||||
typedef unsigned long phys_size_t;
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ASM_NIOS2_TYPES_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
||||
* Scott McNutt <smcnutt@psyent.com>
|
||||
*
|
||||
********************************************************************
|
||||
* NOTE: This header file defines an interface to U-Boot. Including
|
||||
* this (unmodified) header file in another file is considered normal
|
||||
* use of U-Boot, and does *not* fall under the heading of "derived
|
||||
* work".
|
||||
********************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __ASM_NIOS2_U_BOOT_H_
|
||||
#define __ASM_NIOS2_U_BOOT_H_
|
||||
|
||||
#include <asm-generic/u-boot.h>
|
||||
|
||||
/* For image.h:image_check_target_arch() */
|
||||
#define IH_ARCH_DEFAULT IH_ARCH_NIOS2
|
||||
|
||||
#endif /* __ASM_NIOS2_U_BOOT_H_ */
|
||||
@@ -0,0 +1 @@
|
||||
#include <asm-generic/unaligned.h>
|
||||
Reference in New Issue
Block a user