GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <vsprintf.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <mpc86xx.h>
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#include <asm/fsl_law.h>
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#include <asm/ppc.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Default board reset function
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*/
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static void
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__board_reset(void)
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{
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/* Do nothing */
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}
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void board_reset(void) __attribute__((weak, alias("__board_reset")));
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int
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checkcpu(void)
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{
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sys_info_t sysinfo;
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uint pvr, svr;
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uint major, minor;
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char buf1[32], buf2[32];
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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struct cpu_type *cpu;
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uint msscr0 = mfspr(MSSCR0);
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svr = get_svr();
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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if (cpu_numcores() > 1) {
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#ifndef CONFIG_MP
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puts("Unicore software on multiprocessor system!!\n"
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"To enable mutlticore build define CONFIG_MP\n");
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#endif
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}
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puts("CPU: ");
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cpu = gd->arch.cpu;
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puts(cpu->name);
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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puts("Core: ");
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pvr = get_pvr();
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major = PVR_E600_MAJ(pvr);
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minor = PVR_E600_MIN(pvr);
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printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
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if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
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puts("\n Core1Translation Enabled");
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debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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get_sys_info(&sysinfo);
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puts("Clock Configuration:\n");
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printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
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printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
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printf(" DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, sysinfo.freq_systembus / 2),
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strmhz(buf2, sysinfo.freq_systembus));
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if (sysinfo.freq_localbus > LCRR_CLKDIV) {
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printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
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} else {
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printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
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sysinfo.freq_localbus);
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}
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puts("L1: D-cache 32 KiB enabled\n");
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puts(" I-cache 32 KiB enabled\n");
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puts("L2: ");
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if (get_l2cr() & 0x80000000) {
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#if defined(CONFIG_ARCH_MPC8610)
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puts("256");
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#elif defined(CONFIG_ARCH_MPC8641)
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puts("512");
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#endif
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puts(" KiB enabled\n");
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} else {
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puts("Disabled\n");
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}
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return 0;
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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/* Attempt board-specific reset */
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board_reset();
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/* Next try asserting HRESET_REQ */
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out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
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while (1)
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;
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return 1;
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}
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/*
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* Get timebase clock frequency
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*/
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unsigned long
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get_tbclk(void)
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{
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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return (sys_info.freq_systembus + 3L) / 4L;
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}
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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#if defined(CONFIG_ARCH_MPC8610)
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/*
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* This actually feed the hard enabled watchdog.
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*/
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_wdt_t *wdt = &immap->im_wdt;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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u32 tmp = gur->pordevsr;
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if (tmp & 0x4000) {
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wdt->swsrr = 0x556c;
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wdt->swsrr = 0xaa39;
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}
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#endif
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}
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#endif /* CONFIG_WATCHDOG */
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/*
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* Print out the state of various machine registers.
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* Currently prints out LAWs, BR0/OR0, and BATs
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*/
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void print_reginfo(void)
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{
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print_bats();
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print_laws();
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print_lbc_regs();
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}
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/*
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* Set the DDR BATs to reflect the actual size of DDR.
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*
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* dram_size is the actual size of DDR, in bytes
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*
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* Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
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* are using a single BAT to cover DDR.
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*
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* If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
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* is not defined) then we might have a situation where U-Boot will attempt
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* to relocated itself outside of the region mapped by DBAT0.
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* This will cause a machine check.
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*
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* Currently we are limited to power of two sized DDR since we only use a
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* single bat. If a non-power of two size is used that is less than
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* CONFIG_MAX_MEM_MAPPED u-boot will crash.
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*
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*/
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void setup_ddr_bat(phys_addr_t dram_size)
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{
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unsigned long batu, bl;
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bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
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if (BATU_SIZE(bl) != dram_size) {
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u64 sz = (u64)dram_size - BATU_SIZE(bl);
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print_size(sz, " left unmapped\n");
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}
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batu = bl | BATU_VS | BATU_VP;
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write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
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write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
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}
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