GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,29 @@
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# SPDX-License-Identifier: GPL-2.0+
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dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
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dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
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dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
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dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
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dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
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dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
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dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
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dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
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dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
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dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
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dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
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dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
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dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
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dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
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dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
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dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
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targets += $(dtb-y)
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# Add any required device tree compiler flags here
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DTC_FLAGS +=
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PHONY += dtbs
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dtbs: $(addprefix $(obj)/, $(dtb-y))
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@:
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clean-files := *.dtb
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@@ -0,0 +1,33 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* e500mc Power ISA Device Tree Source (include)
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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/ {
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cpus {
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power-isa-version = "2.06";
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power-isa-b; // Base
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power-isa-e; // Embedded
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power-isa-atb; // Alternate Time Base
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power-isa-cs; // Cache Specification
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power-isa-ds; // Decorated Storage
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power-isa-e.ed; // Embedded.Enhanced Debug
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power-isa-e.pd; // Embedded.External PID
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power-isa-e.hv; // Embedded.Hypervisor
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power-isa-e.le; // Embedded.Little-Endian
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power-isa-e.pm; // Embedded.Performance Monitor
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power-isa-e.pc; // Embedded.Processor Control
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power-isa-ecl; // Embedded Cache Locking
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power-isa-exp; // External Proxy
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power-isa-fp; // Floating Point
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power-isa-fp.r; // Floating Point.Record
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power-isa-mmc; // Memory Coherence
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power-isa-scpm; // Store Conditional Page Mobility
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power-isa-wt; // Wait
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fsl,eref-deo; // Data Cache Extended Operations
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mmu-type = "power-embedded";
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};
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};
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@@ -0,0 +1,26 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* e500v2 Power ISA Device Tree Source (include)
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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/ {
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cpus {
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power-isa-version = "2.03";
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power-isa-b; // Base
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power-isa-e; // Embedded
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power-isa-atb; // Alternate Time Base
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power-isa-cs; // Cache Specification
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power-isa-e.le; // Embedded.Little-Endian
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power-isa-e.pm; // Embedded.Performance Monitor
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power-isa-ecl; // Embedded Cache Locking
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power-isa-mmc; // Memory Coherence
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power-isa-sp; // Signal Processing Engine
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power-isa-sp.fd; // SPE.Embedded Float Scalar Double
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power-isa-sp.fs; // SPE.Embedded Float Scalar Single
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power-isa-sp.fv; // SPE.Embedded Float Vector
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mmu-type = "power-embedded";
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};
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};
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@@ -0,0 +1,34 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* e5500 Power ISA Device Tree Source (include)
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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/ {
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cpus {
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power-isa-version = "2.06";
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power-isa-b; // Base
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power-isa-e; // Embedded
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power-isa-atb; // Alternate Time Base
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power-isa-cs; // Cache Specification
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power-isa-ds; // Decorated Storage
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power-isa-e.ed; // Embedded.Enhanced Debug
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power-isa-e.pd; // Embedded.External PID
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power-isa-e.hv; // Embedded.Hypervisor
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power-isa-e.le; // Embedded.Little-Endian
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power-isa-e.pm; // Embedded.Performance Monitor
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power-isa-e.pc; // Embedded.Processor Control
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power-isa-ecl; // Embedded Cache Locking
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power-isa-exp; // External Proxy
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power-isa-fp; // Floating Point
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power-isa-fp.r; // Floating Point.Record
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power-isa-mmc; // Memory Coherence
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power-isa-scpm; // Store Conditional Page Mobility
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power-isa-wt; // Wait
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power-isa-64; // 64-bit
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fsl,eref-deo; // Data Cache Extended Operations
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mmu-type = "power-embedded";
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};
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};
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@@ -0,0 +1,39 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* e6500 Power ISA Device Tree Source (include)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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* Copyright 2018 NXP
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*/
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/ {
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cpus {
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power-isa-version = "2.06";
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power-isa-b; // Base
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power-isa-e; // Embedded
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power-isa-atb; // Alternate Time Base
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power-isa-cs; // Cache Specification
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power-isa-ds; // Decorated Storage
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power-isa-e.ed; // Embedded.Enhanced Debug
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power-isa-e.pd; // Embedded.External PID
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power-isa-e.hv; // Embedded.Hypervisor
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power-isa-e.le; // Embedded.Little-Endian
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power-isa-e.pm; // Embedded.Performance Monitor
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power-isa-e.pc; // Embedded.Processor Control
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power-isa-ecl; // Embedded Cache Locking
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power-isa-exp; // External Proxy
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power-isa-fp; // Floating Point
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power-isa-fp.r; // Floating Point.Record
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power-isa-mmc; // Memory Coherence
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power-isa-scpm; // Store Conditional Page Mobility
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power-isa-wt; // Wait
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power-isa-64; // 64-bit
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power-isa-e.pt; // Embedded.Page Table
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power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT
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power-isa-e.em; // Embedded Multi-Threading
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power-isa-v; // Vector (AltiVec)
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fsl,eref-er; // Enhanced Reservations
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fsl,eref-deo; // Data Cache Extended Operations
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mmu-type = "power-embedded";
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};
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};
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@@ -0,0 +1,602 @@
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/*
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* Gazerbeam CON Device Tree Source
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*
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* (C) Copyright 2015
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include "gdsys/mpc8308.dtsi"
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/include/ "gdsys/gazerbeam-base.dtsi"
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/include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi"
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/include/ "gdsys/soc/i2c/dallas-rtc.dtsi"
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/include/ "gdsys/soc/lbc/gazerbeam.dtsi"
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/include/ "gdsys/soc/nor/flash-80k-partition.dtsi"
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&board_lbc {
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FPGA0:iocon_uart@1,0 {
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reg = <0x1 0x0 0x100000>;
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little-endian;
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interrupts = <48 0x8>;
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interrupt-parent = <&ipic>;
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};
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FPGA1:iocon_uart@2,0 {
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reg = <0x2 0x0 0x100000>;
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little-endian;
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interrupts = <17 0x8>;
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interrupt-parent = <&ipic>;
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};
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};
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&FPGA0 {
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compatible = "gdsys,iocon_fpga";
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#gpio-cells = <2>;
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gpio-controller;
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bus = <&FPGA0BUS>;
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unit_id = <0>;
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fpga-type = <1>;
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usb_base = <0x0080>;
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audio_base = <0x0040>;
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timebase_base = <0x013c>;
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/*
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* for every interrupt source there must be a dataset specifying
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* 1. type (1: standard)
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* 2. status register offset
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* 3. mask register offset
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* 4. default mask
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*/
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fpga_interrupt_sources =
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<1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
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<1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
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/*
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* for every interrupt there must be a dataset specifying
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* 1. type (1: status, 2: event)
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* 2. interrupt source index
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* 3. interrupt register bit
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* 4. mask register bit
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*/
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#fpga_interrupt_map-cells = <4>;
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fpga_interrupt_map =
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<1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
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<1 0 0 0>, /* 1: VIDEO 0 */
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<1 0 1 1>, /* 2: VIDEO 1 */
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<1 0 2 2>, /* 3: VIDEO IC 0 */
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<1 0 3 3>, /* 4: VIDEO IC 1 */
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<1 0 4 4>, /* 5: IIC MAIN */
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<1 0 6 6>, /* 6: IIC VIDEO 0 */
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<1 0 7 7>, /* 7: IIC VIDEO 1 */
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<1 1 0 0>, /* 8: OSD 0 */
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<1 1 1 1>, /* 9: OSD 1 */
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<1 1 2 2>, /* 10: SPDIF 0 */
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<1 1 3 3>, /* 11: SPDIF 1 */
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<1 0 12 12>, /* 12: COMM 0 */
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<1 0 13 13>, /* 13: COMM 1 */
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<1 0 10 10>, /* 14: COMM 2 */
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<1 0 11 11>, /* 15: COMM 3 */
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<2 0 5 5>, /* 16: MDIO */
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<1 0 8 8>, /* 17: PHY */
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<1 1 4 4>, /* 18: RS232 */
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<1 1 5 5>, /* 19: AUDIO */
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<1 1 8 8>, /* 20: PROC_AUDIO */
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<1 1 7 7>, /* 21: USB/ETH-UART INT */
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<2 1 10 10>, /* 22: AXI Bridge 0 */
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<2 1 11 11>, /* 23: AXI Bridge 1 */
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<2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
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<>;
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};
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&FPGA1 {
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compatible = "gdsys,iocon_fpga";
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#gpio-cells = <2>;
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gpio-controller;
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bus = <&FPGA1BUS>;
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unit_id = <1>;
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fpga-type = <1>;
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usb_base = <0x0070>;
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audio_base = <0x0040>;
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timebase_base = <0x013c>;
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/*
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* for every interrupt source there must be a dataset specifying
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* 1. type (1: standard)
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* 2. status register offset
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* 3. mask register offset
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* 4. default mask
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*/
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fpga_interrupt_sources =
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<1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
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<1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
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/*
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* for every interrupt there must be a dataset specifying
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* 1. type (1: status, 2: event)
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* 2. interrupt source index
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* 3. interrupt register bit
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* 4. mask register bit
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*/
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#fpga_interrupt_map-cells = <4>;
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fpga_interrupt_map =
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<1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
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<1 0 0 0>, /* 1: VIDEO 0 */
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<1 0 1 1>, /* 2: VIDEO 1 */
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<1 0 2 2>, /* 3: VIDEO IC 0 */
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<1 0 3 3>, /* 4: VIDEO IC 1 */
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<1 0 4 4>, /* 5: IIC MAIN */
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<1 0 6 6>, /* 6: IIC VIDEO 0 */
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<1 0 7 7>, /* 7: IIC VIDEO 1 */
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<1 1 0 0>, /* 8: OSD 0 */
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<1 1 1 1>, /* 9: OSD 1 */
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<1 1 2 2>, /* 10: SPDIF 0 */
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<1 1 3 3>, /* 11: SPDIF 1 */
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<1 0 12 12>, /* 12: COMM 0 */
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<1 0 13 13>, /* 13: COMM 1 */
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<1 0 10 10>, /* 14: COMM 2 */
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<1 0 11 11>, /* 15: COMM 3 */
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<2 0 5 5>, /* 16: MDIO */
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<1 0 8 8>, /* 17: PHY */
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<1 1 4 4>, /* 18: RS232 */
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<1 1 5 5>, /* 19: AUDIO */
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<1 1 8 8>, /* 20: PROC_AUDIO */
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<1 1 7 7>, /* 21: USB/ETH-UART INT */
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<2 1 10 10>, /* 22: AXI Bridge 0 */
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<2 1 11 11>, /* 23: AXI Bridge 1 */
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<2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
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<>;
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};
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/ {
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FPGA0BUS: fpga0bus {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x00002000>;
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compatible = "gdsys,soc";
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fpga0_rs232 {
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compatible = "gdsys,ihs_trans_rs232";
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reg = <0x50 0x08>;
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little-endian;
|
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};
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fpga0_uart_usb {
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compatible = "gdsys,ihs_simple_uart";
|
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reg = <0xa0 0x08>;
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little-endian;
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fpga_interrupts = <21>;
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line = <0>;
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};
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fpga0_iic_main {
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compatible = "gdsys,ihs_i2cmaster";
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reg = <0x60 0x10>;
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little-endian;
|
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fpga_interrupts = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
|
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fpga0_dp_video0_redriver: fpga0_dp_video0_redriver {
|
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compatible = "ti,sn75dp130";
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reg = <0x2c>;
|
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eq-i2c-enable = <3 2 1 0
|
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3 2 1 0
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3 2 1 0
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3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
|
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};
|
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fpga0_dp_video1_redriver: fpga0_dp_video1_redriver {
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compatible = "ti,sn75dp130";
|
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reg = <0x2e>;
|
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eq-i2c-enable = <3 2 1 0
|
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3 2 1 0
|
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3 2 1 0
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3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
|
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};
|
||||
lm77@48 {
|
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compatible = "national,lm77";
|
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reg = <0x48>;
|
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};
|
||||
ads1015@49 {
|
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compatible = "ti,ads1015";
|
||||
reg = <0x49>;
|
||||
};
|
||||
ads1015@4b {
|
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compatible = "ti,ads1015";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_video0 {
|
||||
compatible = "gdsys,ihs_video_out";
|
||||
reg = <0x100 0x40>;
|
||||
little-endian;
|
||||
fpga_interrupts = <1 8>; /* VIDEO OSD */
|
||||
osd_base = <0x180>;
|
||||
osd_buffer_base = <0x1000>;
|
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spdif_audio_base = <0x1e0>;
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video_index = <0>;
|
||||
video_id = <0>;
|
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fpga-force-pos-pol;
|
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sync-source;
|
||||
fpga-pb-pixels = <2730>; /* 8192 / 3 */
|
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fpga-ra-lines = <2>;
|
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video_tx = <&fpga0_dp_video0>;
|
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clk_gen = <&fpga0_video0_clkgen>;
|
||||
ddc_ci = <&fpga0_dp_video0>;
|
||||
};
|
||||
|
||||
fpga0_iic_video0 {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x1c0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga0_video0_clkgen: fpga0_video0_clkgen {
|
||||
compatible = "idt,ics8n3qv01";
|
||||
reg = <0x6e>;
|
||||
channel = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_axi_video0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "gdsys,ihs_axi";
|
||||
reg = <0x170 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <22>;
|
||||
|
||||
fpga0_dp_video0: fpga0_dp_video0 {
|
||||
compatible = "gdsys,logicore_dp_tx";
|
||||
reg = <0x44a10000 0x1000>;
|
||||
little-endian;
|
||||
redriver = <&fpga0_dp_video0_redriver>;
|
||||
video_id = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_video1 {
|
||||
compatible = "gdsys,ihs_video_out";
|
||||
reg = <0x200 0x40>;
|
||||
little-endian;
|
||||
fpga_interrupts = <2 9>; /* VIDEO OSD */
|
||||
osd_base = <0x280>;
|
||||
osd_buffer_base = <0x2000>;
|
||||
spdif_audio_base = <0x2e0>;
|
||||
video_index = <1>;
|
||||
video_id = <1>;
|
||||
fpga-force-pos-pol;
|
||||
sync-source;
|
||||
fpga-pb-pixels = <2730>; /* 8192 / 3 */
|
||||
fpga-ra-lines = <2>;
|
||||
video_tx = <&fpga0_dp_video1>;
|
||||
clk_gen = <&fpga0_video1_clkgen>;
|
||||
ddc_ci = <&fpga0_dp_video1>;
|
||||
};
|
||||
|
||||
fpga0_iic_video1 {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x2c0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga0_video1_clkgen: fpga0_video1_clkgen {
|
||||
compatible = "idt,ics8n3qv01";
|
||||
reg = <0x6e>;
|
||||
channel = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_axi_video1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "gdsys,ihs_axi";
|
||||
reg = <0x270 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <23>;
|
||||
|
||||
fpga0_dp_video1: fpga0_dp_video1 {
|
||||
compatible = "gdsys,logicore_dp_tx";
|
||||
reg = <0x44a10000 0x1000>;
|
||||
little-endian;
|
||||
redriver = <&fpga0_dp_video1_redriver>;
|
||||
video_id = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_iic_usb {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0xb0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pca9555@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
fpga0_ep0 {
|
||||
compatible = "gdsys,io-endpoint";
|
||||
reg = < 0x020 0x10
|
||||
0x320 0x10
|
||||
0x340 0x10
|
||||
0x360 0x10>;
|
||||
little-endian;
|
||||
irq-model-local;
|
||||
fpga_interrupts = <12 13 14 15>;
|
||||
pollcycle = <200>;
|
||||
nprot_channel = <16>;
|
||||
uart_line = <0>;
|
||||
ep_index = <0>;
|
||||
line_protocol = <1>;
|
||||
};
|
||||
|
||||
fpga0_mdio {
|
||||
compatible = "gdsys,ihs_mdiomaster";
|
||||
reg = <0x0058 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga0_phy0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <0>;
|
||||
};
|
||||
fpga0_phy1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <1>;
|
||||
};
|
||||
fpga0_phy2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <2>;
|
||||
};
|
||||
fpga0_phy3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
||||
FPGA1BUS: fpga1bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x00002000>;
|
||||
|
||||
compatible = "gdsys,soc";
|
||||
|
||||
fpga1_uart_usb {
|
||||
compatible = "gdsys,ihs_simple_uart";
|
||||
reg = <0xa0 0x08>;
|
||||
little-endian;
|
||||
fpga_interrupts = <21>;
|
||||
line = <4>; /* TODO check and FIX */
|
||||
};
|
||||
|
||||
fpga1_iic_main {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x60 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga1_dp_video0_redriver: fpga1_dp_video0_redriver {
|
||||
compatible = "ti,sn75dp130";
|
||||
reg = <0x2c>;
|
||||
eq-i2c-enable = <3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
|
||||
};
|
||||
fpga1_dp_video1_redriver: fpga1_dp_video1_redriver {
|
||||
compatible = "ti,sn75dp130";
|
||||
reg = <0x2e>;
|
||||
eq-i2c-enable = <3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0
|
||||
3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
|
||||
};
|
||||
lm77@48 {
|
||||
compatible = "national,lm77";
|
||||
reg = <0x48>;
|
||||
};
|
||||
ads1015@49 {
|
||||
compatible = "ti,ads1015";
|
||||
reg = <0x49>;
|
||||
};
|
||||
ads1015@4b {
|
||||
compatible = "ti,ads1015";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_video0 {
|
||||
compatible = "gdsys,ihs_video_out";
|
||||
reg = <0x100 0x40>;
|
||||
little-endian;
|
||||
fpga_interrupts = <1 8>; /* VIDEO OSD */
|
||||
osd_base = <0x180>;
|
||||
osd_buffer_base = <0x1000>;
|
||||
spdif_audio_base = <0x1e0>;
|
||||
video_index = <0>;
|
||||
video_id = <4>;
|
||||
fpga-force-pos-pol;
|
||||
sync-source;
|
||||
fpga-pb-pixels = <2730>; /* 8192 / 3 */
|
||||
fpga-ra-lines = <2>;
|
||||
video_tx = <&fpga1_dp_video0>;
|
||||
clk_gen = <&fpga1_video0_clkgen>;
|
||||
ddc_ci = <&fpga1_dp_video0>;
|
||||
};
|
||||
|
||||
fpga1_iic_video0 {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x1c0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga1_video0_clkgen: fpga1_video0_clkgen {
|
||||
compatible = "idt,ics8n3qv01";
|
||||
reg = <0x6e>;
|
||||
channel = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_axi_video0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "gdsys,ihs_axi";
|
||||
reg = <0x170 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <22>;
|
||||
|
||||
fpga1_dp_video0: fpga1_dp_video0 {
|
||||
compatible = "gdsys,logicore_dp_tx";
|
||||
reg = <0x44a10000 0x1000>;
|
||||
little-endian;
|
||||
redriver = <&fpga1_dp_video0_redriver>;
|
||||
video_id = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_video1 {
|
||||
compatible = "gdsys,ihs_video_out";
|
||||
reg = <0x200 0x40>;
|
||||
little-endian;
|
||||
fpga_interrupts = <2 9>; /* VIDEO OSD */
|
||||
osd_base = <0x280>;
|
||||
osd_buffer_base = <0x2000>;
|
||||
spdif_audio_base = <0x2e0>;
|
||||
video_index = <1>;
|
||||
video_id = <5>;
|
||||
fpga-force-pos-pol;
|
||||
sync-source;
|
||||
fpga-pb-pixels = <2730>; /* 8192 / 3 */
|
||||
fpga-ra-lines = <2>;
|
||||
video_tx = <&fpga1_dp_video1>;
|
||||
clk_gen = <&fpga1_video1_clkgen>;
|
||||
ddc_ci = <&fpga1_dp_video1>;
|
||||
};
|
||||
|
||||
fpga1_iic_video1 {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0x2c0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga1_video1_clkgen: fpga1_video1_clkgen {
|
||||
compatible = "idt,ics8n3qv01";
|
||||
reg = <0x6e>;
|
||||
channel = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_axi_video1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "gdsys,ihs_axi";
|
||||
reg = <0x270 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <23>;
|
||||
|
||||
fpga1_dp_video1: fpga1_dp_video1 {
|
||||
compatible = "gdsys,logicore_dp_tx";
|
||||
reg = <0x44a10000 0x1000>;
|
||||
little-endian;
|
||||
redriver = <&fpga1_dp_video1_redriver>;
|
||||
video_id = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_iic_usb {
|
||||
compatible = "gdsys,ihs_i2cmaster";
|
||||
reg = <0xb0 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pca9555@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
fpga1_ep0 {
|
||||
compatible = "gdsys,io-endpoint";
|
||||
reg = < 0x020 0x10
|
||||
0x320 0x10
|
||||
0x340 0x10
|
||||
0x360 0x10>;
|
||||
little-endian;
|
||||
irq-model-local;
|
||||
fpga_interrupts = <12 13 14 15>;
|
||||
pollcycle = <200>;
|
||||
nprot_channel = <17>;
|
||||
uart_line = <1>;
|
||||
ep_index = <0>;
|
||||
line_protocol = <1>;
|
||||
};
|
||||
|
||||
fpga1_mdio {
|
||||
compatible = "gdsys,ihs_mdiomaster";
|
||||
reg = <0x0058 0x10>;
|
||||
little-endian;
|
||||
fpga_interrupts = <16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fpga1_phy0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <0>;
|
||||
};
|
||||
fpga1_phy1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <1>;
|
||||
};
|
||||
fpga1_phy2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <2>;
|
||||
};
|
||||
fpga1_phy3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
device_type ="ethernet-phy";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
#include "gdsys/gazerbeam-uboot.dtsi"
|
||||
@@ -0,0 +1,185 @@
|
||||
/*
|
||||
* Gazerbeam Device Tree Source
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "gdsys,gazerbeam";
|
||||
compatible = "fsl,mpc8308rdb";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
};
|
||||
|
||||
&enet1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&IIC {
|
||||
fsl,preserve-clocking;
|
||||
|
||||
at97sc3205t@29 {
|
||||
compatible = "atmel,at97sc3204t";
|
||||
reg = <0x29>;
|
||||
};
|
||||
|
||||
lm77@48 {
|
||||
compatible = "national,lm77";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
ads1015@49 {
|
||||
compatible = "ti,ads1015";
|
||||
reg = <0x49>;
|
||||
};
|
||||
|
||||
lm77@4a {
|
||||
compatible = "national,lm77";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
|
||||
emc2305@2e {
|
||||
compatible = "smsc,emc2305";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2e>;
|
||||
fan@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
fan@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
fan@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
fan@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
fan@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
emc2305@4c {
|
||||
compatible = "smsc,emc2305";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4c>;
|
||||
fan@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
fan@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
fan@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
fan@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
fan@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
at24c512@54 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
/* PPC-Board */
|
||||
pca9698@22 {
|
||||
compatible = "nxp,pca9698";
|
||||
reg = <0x22>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
/* IO-Board */
|
||||
pca9698@20 {
|
||||
compatible = "nxp,pca9698";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
&IIC2 {
|
||||
fsl,preserve-clocking;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* MC2/SC-Board */
|
||||
GPIO_VB0: pca9698@20 {
|
||||
compatible = "nxp,pca9698";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
/* MC4-Board */
|
||||
GPIO_VB1: pca9698@22 {
|
||||
compatible = "nxp,pca9698";
|
||||
reg = <0x22>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
&SPI {
|
||||
gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0
|
||||
/*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0
|
||||
/*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0
|
||||
/*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0
|
||||
/*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0
|
||||
/*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>;
|
||||
|
||||
m25p16@0 {
|
||||
compatible = "st,n25q128a11";
|
||||
reg = <0x0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@1 {
|
||||
compatible = "st,n25q128a11";
|
||||
reg = <0x1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@2 {
|
||||
compatible = "st,m25p40";
|
||||
reg = <0x2>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@3 {
|
||||
compatible = "st,m25p40";
|
||||
reg = <0x3>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@4 {
|
||||
compatible = "st,m25p40";
|
||||
reg = <0x4>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
||||
m25p16@5 {
|
||||
compatible = "st,m25p40";
|
||||
reg = <0x5>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,250 @@
|
||||
#include <dt-bindings/memory/mpc83xx-sdram.h>
|
||||
#include <dt-bindings/clk/mpc83xx-clk.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
i2c0 = &IIC;
|
||||
i2c1 = &IIC2;
|
||||
i2c2 = "/fpga0bus/fpga0_iic_main";
|
||||
i2c3 = "/fpga0bus/fpga0_iic_video0";
|
||||
i2c4 = "/fpga0bus/fpga0_iic_video1";
|
||||
i2c5 = "/fpga0bus/fpga0_iic_usb";
|
||||
gdsys_soc0 = "/fpga0bus";
|
||||
gdsys_soc1 = "/fpga1bus";
|
||||
ioep0 = "/fpga0bus/fpga0_ep0";
|
||||
ioep1 = "/fpga0bus/fpga1_ep0";
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
compatible = "cpu_bus";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
PowerPC,8308@0 {
|
||||
compatible = "fsl,mpc8308";
|
||||
clocks = <&socclocks MPC83XX_CLK_CORE
|
||||
&socclocks MPC83XX_CLK_CSB>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
board {
|
||||
compatible = "gdsys,board_gazerbeam";
|
||||
csb = <&board_soc>;
|
||||
serdes = <&SERDES>;
|
||||
rxaui0 = <&RXAUI0_0>;
|
||||
rxaui1 = <&RXAUI0_1>;
|
||||
rxaui2 = <&RXAUI0_2>;
|
||||
rxaui3 = <&RXAUI0_3>;
|
||||
rxaui4 = <&RXAUI1_0>;
|
||||
rxaui5 = <&RXAUI1_1>;
|
||||
rxaui6 = <&RXAUI1_2>;
|
||||
rxaui7 = <&RXAUI1_3>;
|
||||
fpga0 = <&FPGA0>;
|
||||
fpga1 = <&FPGA1>;
|
||||
ioep0 = <&IOEP0>;
|
||||
ioep1 = <&IOEP1>;
|
||||
|
||||
ver-gpios = <&PPCPCA 12 0
|
||||
&PPCPCA 13 0
|
||||
&PPCPCA 14 0
|
||||
&PPCPCA 15 0>;
|
||||
|
||||
/* MC2/SC-Board */
|
||||
var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */
|
||||
&GPIO_VB0 11 0>; /* VAR-CON */
|
||||
/* MC4-Board */
|
||||
var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */
|
||||
&GPIO_VB1 11 0>; /* VAR-CON */
|
||||
|
||||
reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
|
||||
};
|
||||
|
||||
socclocks: clocks {
|
||||
compatible = "fsl,mpc8308-clk";
|
||||
#clock-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "fsl,mpc83xx-timer";
|
||||
clocks = <&socclocks MPC83XX_CLK_CSB>;
|
||||
};
|
||||
};
|
||||
|
||||
&FPGA0 {
|
||||
reset-gpios = <&PPCPCA 26 0>;
|
||||
done-gpios = <&GPIO_VB0 19 0>;
|
||||
};
|
||||
|
||||
&FPGA1 {
|
||||
status = "disable"
|
||||
};
|
||||
|
||||
&FPGA0BUS {
|
||||
ranges = <0x0 0xe0600000 0x00004000>;
|
||||
fpga = <&FPGA0>;
|
||||
|
||||
fpga0_video0 {
|
||||
mode = "640_480_60";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
RXAUI0_0: fpga0_rxaui@fc0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fc0 0x10>;
|
||||
};
|
||||
|
||||
fpga0_iic_video0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fpga0_axi_video0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fpga0_video1 {
|
||||
mode = "640_480_60";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fpga0_iic_video1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fpga0_axi_video1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
IOEP0: fpga0_ep0 {
|
||||
};
|
||||
|
||||
RXAUI0_1: fpga0_rxaui@fd0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fd0 0x10>;
|
||||
};
|
||||
|
||||
RXAUI0_2: fpga0_rxaui@fe0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fe0 0x10>;
|
||||
};
|
||||
|
||||
RXAUI0_3: fpga0_rxaui@ff0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0ff0 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
&FPGA1BUS {
|
||||
ranges = <0x0 0xe0700000 0x00004000>;
|
||||
fpga = <&FPGA1>;
|
||||
|
||||
status = "disable"
|
||||
|
||||
fpga1_video0 {
|
||||
mode = "640_480_60";
|
||||
};
|
||||
|
||||
RXAUI1_0: fpga0_rxaui@fc0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fc0 0x10>;
|
||||
};
|
||||
|
||||
fpga1_video1 {
|
||||
mode = "640_480_60";
|
||||
};
|
||||
|
||||
IOEP1: fpga1_ep0 {
|
||||
};
|
||||
|
||||
RXAUI1_1: fpga0_rxaui@fd0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fd0 0x10>;
|
||||
};
|
||||
|
||||
RXAUI1_2: fpga0_rxaui@fe0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0fe0 0x10>;
|
||||
};
|
||||
|
||||
RXAUI1_3: fpga0_rxaui@ff0 {
|
||||
compatible = "gdsys,rxaui_ctrl";
|
||||
reg = <0x0ff0 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
&board_soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
clocks = <&socclocks MPC83XX_CLK_CSB>;
|
||||
|
||||
memory@2000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
clocks = <&socclocks MPC83XX_CLK_SDHC>;
|
||||
clock-names = "per";
|
||||
};
|
||||
|
||||
SERDES: serdes@e3000 {
|
||||
reg = <0xe3000 0x200>;
|
||||
compatible = "fsl,mpc83xx-serdes";
|
||||
proto = "pex";
|
||||
serdes-clk = <100>;
|
||||
vdd;
|
||||
};
|
||||
};
|
||||
|
||||
&IIC {
|
||||
clocks = <&socclocks MPC83XX_CLK_I2C1>;
|
||||
|
||||
PPCPCA: pca9698@20 {
|
||||
label = "ppc";
|
||||
};
|
||||
|
||||
IOPCA: pca9698@22 {
|
||||
label = "io";
|
||||
};
|
||||
|
||||
at97sc3205t@29 {
|
||||
u-boot,i2c-offset-len = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&IIC2 {
|
||||
clocks = <&socclocks MPC83XX_CLK_I2C2>;
|
||||
|
||||
GPIO_VB0: pca9698@20 {
|
||||
label = "mc2-sc";
|
||||
};
|
||||
|
||||
GPIO_VB1: pca9698@22 {
|
||||
label = "mc4";
|
||||
};
|
||||
};
|
||||
|
||||
&board_soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&GPIO_VB0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
clocks = <&socclocks MPC83XX_CLK_CSB>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
clocks = <&socclocks MPC83XX_CLK_CSB>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
clocks = <&socclocks MPC83XX_CLK_PCIEXP1>;
|
||||
};
|
||||
@@ -0,0 +1,354 @@
|
||||
/*
|
||||
* Basic platform for gdsys mpc8308 based devices
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
||||
*
|
||||
* based on mpc8308rdb
|
||||
* Copyright 2009 Freescale Semiconductor Inc.
|
||||
* Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/memory/mpc83xx-sdram.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,mpc8308rdb";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8308@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <16384>;
|
||||
i-cache-size = <16384>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
board_lbc: localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
board_soc: immr@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8308-immr", "simple-bus";
|
||||
ranges = <0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
memory@2000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc83xx-mem-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
device_type = "memory";
|
||||
|
||||
driver_software_override = <DSO_ENABLE>;
|
||||
p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
|
||||
n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
|
||||
odt_termination_value = <ODT_TERMINATION_150_OHM>;
|
||||
ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
|
||||
|
||||
clock_adjust = <CLOCK_ADJUST_05>;
|
||||
|
||||
read_to_write = <0>;
|
||||
write_to_read = <0>;
|
||||
read_to_read = <0>;
|
||||
write_to_write = <0>;
|
||||
active_powerdown_exit = <2>;
|
||||
precharge_powerdown_exit = <6>;
|
||||
odt_powerdown_exit = <8>;
|
||||
mode_reg_set_cycle = <2>;
|
||||
|
||||
precharge_to_activate = <2>;
|
||||
activate_to_precharge = <6>;
|
||||
activate_to_readwrite = <2>;
|
||||
mcas_latency = <CASLAT_40>;
|
||||
refresh_recovery = <17>;
|
||||
last_data_to_precharge = <2>;
|
||||
activate_to_activate = <2>;
|
||||
last_write_data_to_read = <2>;
|
||||
|
||||
additive_latency = <0>;
|
||||
mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
|
||||
write_latency = <3>;
|
||||
read_to_precharge = <2>;
|
||||
write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
|
||||
minimum_cke_pulse_width = <3>;
|
||||
four_activates_window = <5>;
|
||||
|
||||
self_refresh = <SREN_ENABLE>;
|
||||
sdram_type = <TYPE_DDR2>;
|
||||
databus_width = <DATA_BUS_WIDTH_32>;
|
||||
|
||||
force_self_refresh = <MODE_NORMAL>;
|
||||
dll_reset = <DLL_RESET_ENABLE>;
|
||||
dqs_config = <DQS_TRUE>;
|
||||
odt_config = <ODT_ASSERT_READS>;
|
||||
posted_refreshes = <1>;
|
||||
|
||||
refresh_interval = <2084>;
|
||||
precharge_interval = <256>;
|
||||
|
||||
sdmode = <0x0242>;
|
||||
esdmode = <0x0440>;
|
||||
|
||||
ram@0 {
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
compatible = "nanya,nt5tu64m16hg";
|
||||
|
||||
odt_rd_cfg = <ODT_RD_NEVER>;
|
||||
odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
|
||||
bank_bits = <3>;
|
||||
row_bits = <13>;
|
||||
col_bits = <10>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC:i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
IIC2: i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
SPI:spi@7000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,esdhc", "fsl,mpc8308-esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
sdhci,auto-cmd12;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <133333333>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <133333333>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
gpio0: gpio@c00 {
|
||||
#gpio-cells = <2>;
|
||||
device_type = "gpio";
|
||||
compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
|
||||
reg = <0xc00 0x18>;
|
||||
interrupts = <74 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: interrupt-controller@700 {
|
||||
compatible = "fsl,ipic";
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
ipic-msi@7c0 {
|
||||
compatible = "fsl,ipic-msi";
|
||||
reg = <0x7c0 0x40>;
|
||||
msi-available-ranges = <0x0 0x100>;
|
||||
interrupts = < 0x43 0x8
|
||||
0x4 0x8
|
||||
0x51 0x8
|
||||
0x52 0x8
|
||||
0x56 0x8
|
||||
0x57 0x8
|
||||
0x58 0x8
|
||||
0x59 0x8 >;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
dma@2c000 {
|
||||
compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
|
||||
reg = <0x2c000 0x1800>;
|
||||
interrupts = <3 0x8
|
||||
94 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar", "fsl,tsec";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
tbi-handle = < &tbi0 >;
|
||||
phy-handle = < &phy1 >;
|
||||
fsl,magic-packet;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
phy2: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar", "fsl,tsec";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = < &phy2 >;
|
||||
status = "disabled";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@e0009000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
|
||||
reg = <0xe0009000 0x00001000
|
||||
0xb0000000 0x01000000>;
|
||||
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
|
||||
bus-range = <0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &ipic 1 8
|
||||
0 0 0 2 &ipic 1 8
|
||||
0 0 0 3 &ipic 1 8
|
||||
0 0 0 4 &ipic 1 8>;
|
||||
interrupts = <0x1 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
clock-frequency = <0>;
|
||||
|
||||
pcie@0 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
ranges = <0x02000000 0 0xa0000000
|
||||
0x02000000 0 0xa0000000
|
||||
0 0x10000000
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
&IIC {
|
||||
cs4265@4f {
|
||||
compatible = "cirrus,cs4265";
|
||||
reg = <0x0000004f>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,6 @@
|
||||
&IIC {
|
||||
ds1339@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,5 @@
|
||||
&board_lbc {
|
||||
ranges = <0x0 0x0 0xfe000000 0x00800000
|
||||
0x1 0x0 0xe0600000 0x00003000
|
||||
0x2 0x0 0xe0700000 0x00003000>;
|
||||
};
|
||||
+20
@@ -0,0 +1,20 @@
|
||||
&board_lbc {
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x100000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
u-boot@0 {
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
env@80000 {
|
||||
reg = <0x80000 0x10000>;
|
||||
};
|
||||
env1@90000 {
|
||||
reg = <0x90000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* MCR3000 Device Tree Source
|
||||
*
|
||||
* Copyright 2017 CS Systemes d'Information
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
WDT: watchdog@0 {
|
||||
compatible = "fsl,pq1-wdt";
|
||||
};
|
||||
SERIAL: smc@0 {
|
||||
compatible = "fsl,pq1-smc";
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &SERIAL;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,36 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* MPC8548 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8548-immr", "simple-bus";
|
||||
bus-frequency = <0x0>;
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
single-cpu-affinity;
|
||||
last-interrupt-source = <255>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
};
|
||||
@@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* MPC8548CDS Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,29 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* MPC8548CDS Device Tree Source
|
||||
*
|
||||
* Copyright 2006 - 2012 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "mpc8548.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,MPC8548CDS";
|
||||
compatible = "fsl,MPC8548CDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
soc: soc8548@e0000000 {
|
||||
ranges = <0x0 0x0 0xe0000000 0x100000>;
|
||||
};
|
||||
|
||||
pcie: pcie@e000a000 {
|
||||
reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */
|
||||
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "mpc8548-post.dtsi"
|
||||
@@ -0,0 +1,29 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* MPC8548CDS (36-bit address map) Device Tree Source
|
||||
*
|
||||
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "mpc8548.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,MPC8548CDS";
|
||||
compatible = "fsl,MPC8548CDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
soc: soc8548@fe0000000 {
|
||||
ranges = <0x0 0xf 0xe0000000 0x100000>;
|
||||
};
|
||||
|
||||
pcie: pcie@fe000a000 {
|
||||
reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "mpc8548-post.dtsi"
|
||||
@@ -0,0 +1,54 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P1020 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1020-immr", "simple-bus";
|
||||
bus-frequency = <0x0>;
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
single-cpu-affinity;
|
||||
last-interrupt-source = <255>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@2e000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCIe controller base address 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
};
|
||||
|
||||
/* PCIe controller base address 0xa000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
};
|
||||
@@ -0,0 +1,31 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P1020 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,P1020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu1: PowerPC,P1020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,35 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P1020RDB-PC Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "p1020.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P1020RDB-PC";
|
||||
compatible = "fsl,P1020RDB-PC";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
soc: soc@ffe00000 {
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pci0: pcie@ffe0a000 {
|
||||
reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "p1020-post.dtsi"
|
||||
@@ -0,0 +1,35 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P1020RDB-PC (36-bit address map) Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "p1020.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P1020RDB-PC";
|
||||
compatible = "fsl,P1020RDB-PC";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
soc: soc@fffe00000 {
|
||||
ranges = <0x0 0xf 0xffe00000 0x100000>;
|
||||
};
|
||||
|
||||
pci1: pcie@fffe09000 {
|
||||
reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pci0: pcie@fffe0a000 {
|
||||
reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "p1020-post.dtsi"
|
||||
@@ -0,0 +1,35 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P1020RDB-PD Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "p1020.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P1020RDB-PD";
|
||||
compatible = "fsl,P1020RDB-PD";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
soc: soc@ffe00000 {
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pci0: pcie@ffe0a000 {
|
||||
reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "p1020-post.dtsi"
|
||||
@@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P2020 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p2020-immr", "simple-bus";
|
||||
bus-frequency = <0x0>;
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
single-cpu-affinity;
|
||||
last-interrupt-source = <255>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@2e000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PCIe controller base address 0x8000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
|
||||
law_trgt_if = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
};
|
||||
|
||||
/* PCIe controller base address 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
};
|
||||
|
||||
/* PCIe controller base address 0xa000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
};
|
||||
@@ -0,0 +1,31 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P2020 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,P2020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu1: PowerPC,P2020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,40 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P2020RDB-PC Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "p2020.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P2020RDB-PC";
|
||||
compatible = "fsl,P2020RDB-PC";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
soc: soc@ffe00000 {
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
};
|
||||
|
||||
pci2: pcie@ffe08000 {
|
||||
reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pci0: pcie@ffe0a000 {
|
||||
reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "p2020-post.dtsi"
|
||||
@@ -0,0 +1,40 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P2020RDB-PC (36-bit address map) Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "p2020.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P2020RDB-PC";
|
||||
compatible = "fsl,P2020RDB-PC";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
soc: soc@fffe00000 {
|
||||
ranges = <0x0 0xf 0xffe00000 0x100000>;
|
||||
};
|
||||
|
||||
pci2: pcie@fffe08000 {
|
||||
reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci1: pcie@fffe09000 {
|
||||
reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pci0: pcie@fffe0a000 {
|
||||
reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "p2020-post.dtsi"
|
||||
@@ -0,0 +1,114 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P2041 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500mc_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P2041";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500mc@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e500mc@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
fsl,portid-mapping = <0x40000000>;
|
||||
};
|
||||
cpu2: PowerPC,e500mc@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
fsl,portid-mapping = <0x20000000>;
|
||||
};
|
||||
cpu3: PowerPC,e500mc@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
fsl,portid-mapping = <0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
clock-frequency = <0x0>;
|
||||
};
|
||||
|
||||
sata: sata@220000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
sata-offset = <0x1000>;
|
||||
sata-number = <2>;
|
||||
sata-fpdma = <0>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@114000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@ffe200000 {
|
||||
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe201000 {
|
||||
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe202000 {
|
||||
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P2041RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "p2041.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P2041RDB";
|
||||
compatible = "fsl,P2041RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
};
|
||||
@@ -0,0 +1,126 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P3041 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500mc_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P3041";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500mc@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e500mc@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
fsl,portid-mapping = <0x40000000>;
|
||||
};
|
||||
cpu2: PowerPC,e500mc@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
fsl,portid-mapping = <0x20000000>;
|
||||
};
|
||||
cpu3: PowerPC,e500mc@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
fsl,portid-mapping = <0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
clock-frequency = <0x0>;
|
||||
};
|
||||
|
||||
sata: sata@220000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
sata-offset = <0x1000>;
|
||||
sata-number = <2>;
|
||||
sata-fpdma = <0>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@114000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@ffe200000 {
|
||||
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe201000 {
|
||||
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe202000 {
|
||||
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe203000 {
|
||||
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <3>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P3041DS Device Tree Source
|
||||
*
|
||||
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "p3041.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P3041DS";
|
||||
compatible = "fsl,P3041DS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
};
|
||||
@@ -0,0 +1,125 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P4080/P4040 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500mc_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P4080";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500mc@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e500mc@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
fsl,portid-mapping = <0x40000000>;
|
||||
};
|
||||
cpu2: PowerPC,e500mc@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
fsl,portid-mapping = <0x20000000>;
|
||||
};
|
||||
cpu3: PowerPC,e500mc@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
fsl,portid-mapping = <0x10000000>;
|
||||
};
|
||||
cpu4: PowerPC,e500mc@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4>;
|
||||
fsl,portid-mapping = <0x08000000>;
|
||||
};
|
||||
cpu5: PowerPC,e500mc@5 {
|
||||
device_type = "cpu";
|
||||
reg = <5>;
|
||||
fsl,portid-mapping = <0x04000000>;
|
||||
};
|
||||
cpu6: PowerPC,e500mc@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6>;
|
||||
fsl,portid-mapping = <0x02000000>;
|
||||
};
|
||||
cpu7: PowerPC,e500mc@7 {
|
||||
device_type = "cpu";
|
||||
reg = <7>;
|
||||
fsl,portid-mapping = <0x01000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
clock-frequency = <0x0>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@114000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@ffe200000 {
|
||||
compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe201000 {
|
||||
compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe202000 {
|
||||
compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P4080DS Device Tree Source
|
||||
*
|
||||
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "p4080.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P4080DS";
|
||||
compatible = "fsl,P4080DS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
};
|
||||
@@ -0,0 +1,113 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P5040 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e5500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e5500@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
fsl,portid-mapping = <0x40000000>;
|
||||
};
|
||||
cpu2: PowerPC,e5500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
fsl,portid-mapping = <0x20000000>;
|
||||
};
|
||||
cpu3: PowerPC,e5500@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
fsl,portid-mapping = <0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
clock-frequency = <0x0>;
|
||||
};
|
||||
|
||||
sata: sata@220000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
sata-offset = <0x1000>;
|
||||
sata-number = <2>;
|
||||
sata-fpdma = <0>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@114000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@ffe200000 {
|
||||
compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe201000 {
|
||||
compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe202000 {
|
||||
compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* P5040DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "p5040.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,P5040DS";
|
||||
compatible = "fsl,P5040DS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
};
|
||||
@@ -0,0 +1,40 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2019
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de
|
||||
*/
|
||||
/ {
|
||||
binman {
|
||||
filename = "u-boot-socrates.bin";
|
||||
pad-byte = <0xff>;
|
||||
// Place dtb one sector before u-boot-nodtb.bin
|
||||
blob {
|
||||
filename = "dts/dt.dtb";
|
||||
};
|
||||
u-boot-nodtb {
|
||||
filename = "u-boot-nodtb.bin";
|
||||
offset = <0x20000>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial0;
|
||||
};
|
||||
|
||||
soc8544@e0000000 {
|
||||
i2c@3000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
clock-frequency = <33000000>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x01000000 0x0 0xe2000000 0xe2000000 0x0 0x01000000>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
clock-frequency = <333333330>;
|
||||
};
|
||||
@@ -0,0 +1,349 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Device Tree Source for the Socrates board (MPC8544).
|
||||
*
|
||||
* Copyright (c) 2008 Emcraft Systems.
|
||||
* Sergei Poselenov, <sposelenov@emcraft.com>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "abb,socrates";
|
||||
compatible = "abb,socrates";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8544@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000>; // Filled in by U-Boot
|
||||
};
|
||||
|
||||
soc8544@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
|
||||
ranges = <0x00000000 0xe0000000 0x00100000>;
|
||||
bus-frequency = <0>; // Filled in by U-Boot
|
||||
compatible = "fsl,mpc8544-immr", "simple-bus";
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8544-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8544-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8544-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>;
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8544-i2c", "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,preserve-clocking;
|
||||
|
||||
dtt@28 {
|
||||
compatible = "winbond,w83782d";
|
||||
reg = <0x28>;
|
||||
};
|
||||
rtc@32 {
|
||||
compatible = "epson,rx8025";
|
||||
reg = <0x32>;
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
dtt@4c {
|
||||
compatible = "dallas,ds75";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
ts@4a {
|
||||
compatible = "ti,tsc2003";
|
||||
reg = <0x4a>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,mpc8544-i2c", "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,preserve-clocking;
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0 1>;
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0 1>;
|
||||
reg = <1>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
localbus {
|
||||
compatible = "fsl,mpc8544-localbus",
|
||||
"fsl,pq3-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xe0005000 0x40>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
|
||||
ranges = <0 0 0xfc000000 0x04000000
|
||||
2 0 0xc8000000 0x04000000
|
||||
3 0 0xc0000000 0x00100000
|
||||
>; /* Overwritten by U-Boot */
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl256n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x0 0x000000 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x0 0x1e0000>;
|
||||
read-only;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x1e0000 0x20000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x200000 0x200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <0x400000 0x3b80000>;
|
||||
};
|
||||
partition@3f80000 {
|
||||
label = "env";
|
||||
reg = <0x3f80000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
partition@3fc0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
display@2,0 {
|
||||
compatible = "fujitsu,lime";
|
||||
reg = <2 0x0 0x4000000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <6 1>;
|
||||
};
|
||||
|
||||
fpga_pic: fpga-pic@3,10 {
|
||||
compatible = "abb,socrates-fpga-pic";
|
||||
reg = <3 0x10 0x10>;
|
||||
interrupt-controller;
|
||||
/* IRQs 2, 10, 11, active low, level-sensitive */
|
||||
interrupts = <2 1 10 1 11 1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
spi@3,60 {
|
||||
compatible = "abb,socrates-spi";
|
||||
reg = <3 0x60 0x10>;
|
||||
interrupts = <8 4 0>; // number, type, routing
|
||||
interrupt-parent = <&fpga_pic>;
|
||||
};
|
||||
|
||||
nand@3,70 {
|
||||
compatible = "abb,socrates-nand";
|
||||
reg = <3 0x70 0x04>;
|
||||
bank-width = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
data@0 {
|
||||
label = "data";
|
||||
reg = <0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
can@3,100 {
|
||||
compatible = "philips,sja1000";
|
||||
reg = <3 0x100 0x80>;
|
||||
interrupts = <2 8 1>; // number, type, routing
|
||||
interrupt-parent = <&fpga_pic>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008000 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xe0008000 0x1000>;
|
||||
clock-frequency = <66666666>;
|
||||
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x11 */
|
||||
0x8800 0x0 0x0 1 &mpic 5 1
|
||||
/* IDSEL 0x12 */
|
||||
0x9000 0x0 0x0 1 &mpic 4 1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
|
||||
};
|
||||
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* T1024RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "t102x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,T1024RDB";
|
||||
compatible = "fsl,T1024RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
@@ -0,0 +1,103 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* T102X Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e5500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
cpu1: PowerPC,e5500@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
clock-frequency = <0x0>;
|
||||
};
|
||||
|
||||
sata: sata@220000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
sata-offset = <0x1000>;
|
||||
sata-number = <2>;
|
||||
sata-fpdma = <0>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@114000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@ffe240000 {
|
||||
compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe250000 {
|
||||
compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe260000 {
|
||||
compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* T1042D4RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "t104x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,T1042D4RDB";
|
||||
compatible = "fsl,T1042D4RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
@@ -0,0 +1,125 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* T104X Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e5500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
cpu1: PowerPC,e5500@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
cpu2: PowerPC,e5500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
cpu3: PowerPC,e5500@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic", "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
clock-frequency = <0x0>;
|
||||
};
|
||||
|
||||
sata: sata@220000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
sata-offset = <0x1000>;
|
||||
sata-number = <2>;
|
||||
sata-fpdma = <0>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@114000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@ffe240000 {
|
||||
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe250000 {
|
||||
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe260000 {
|
||||
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe270000 {
|
||||
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <3>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,155 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* T2080/T2081 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic";
|
||||
device_type = "open-pic";
|
||||
clock-frequency = <0x0>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@114000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
interrupts = <48 2 0 0>;
|
||||
clock-frequency = <0>;
|
||||
sdhci,auto-cmd12;
|
||||
bus-width = <4>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
};
|
||||
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <0x210000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <44 0x2 0 0>;
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x211000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <45 0x2 0 0>;
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
sata0: sata@220000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
sata-number = <0x0>;
|
||||
sata-fpdma = <0x0>;
|
||||
};
|
||||
|
||||
sata1: sata@221000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x221000 0x1000>;
|
||||
interrupts = <69 0x2 0 0>;
|
||||
sata-number = <0x0>;
|
||||
sata-fpdma = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@ffe240000 {
|
||||
compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */
|
||||
law_trgt_if = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe250000 {
|
||||
compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe260000 {
|
||||
compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe270000 {
|
||||
compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
|
||||
law_trgt_if = <3>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* T2080QDS Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
/include/ "t2080.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,T2080QDS";
|
||||
compatible = "fsl,T2080QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* T2080RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "t2080.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,T2080RDB";
|
||||
compatible = "fsl,T2080RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
@@ -0,0 +1,165 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* T4240 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu4: PowerPC,e6500@8 {
|
||||
device_type = "cpu";
|
||||
reg = <8 9>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu5: PowerPC,e6500@10 {
|
||||
device_type = "cpu";
|
||||
reg = <10 11>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu6: PowerPC,e6500@12 {
|
||||
device_type = "cpu";
|
||||
reg = <12 13>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu7: PowerPC,e6500@14 {
|
||||
device_type = "cpu";
|
||||
reg = <14 15>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu8: PowerPC,e6500@16 {
|
||||
device_type = "cpu";
|
||||
reg = <16 17>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu9: PowerPC,e6500@18 {
|
||||
device_type = "cpu";
|
||||
reg = <18 19>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu10: PowerPC,e6500@20 {
|
||||
device_type = "cpu";
|
||||
reg = <20 21>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu11: PowerPC,e6500@22 {
|
||||
device_type = "cpu";
|
||||
reg = <22 23>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "fsl,mpic";
|
||||
device_type = "open-pic";
|
||||
clock-frequency = <0x0>;
|
||||
};
|
||||
|
||||
sata: sata@220000 {
|
||||
compatible = "fsl,pq-sata-v2";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <68 0x2 0 0>;
|
||||
sata-offset = <0x1000>;
|
||||
sata-number = <2>;
|
||||
sata-fpdma = <0>;
|
||||
};
|
||||
|
||||
esdhc: esdhc@114000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x114000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@ffe240000 {
|
||||
compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */
|
||||
law_trgt_if = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe250000 {
|
||||
compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe250000 0x0 0x4000>; /* registers */
|
||||
law_trgt_if = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe260000 {
|
||||
compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe260000 0x0 0x4000>; /* registers */
|
||||
law_trgt_if = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
|
||||
pcie@ffe270000 {
|
||||
compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
|
||||
reg = <0xf 0xfe270000 0x0 0x4000>; /* registers */
|
||||
law_trgt_if = <3>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
|
||||
0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* T4240RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/include/ "t4240.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,T4240RDB";
|
||||
compatible = "fsl,T4240RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
@@ -0,0 +1,35 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/ {
|
||||
binman {
|
||||
filename = "u-boot-with-dtb.bin";
|
||||
skip-at-start = <CONFIG_SYS_TEXT_BASE>;
|
||||
sort-by-offset;
|
||||
pad-byte = <0xff>;
|
||||
size = <CONFIG_SYS_MONITOR_LEN>;
|
||||
|
||||
u-boot-with-ucode-ptr {
|
||||
offset = <CONFIG_SYS_TEXT_BASE>;
|
||||
optional-ucode;
|
||||
};
|
||||
|
||||
u-boot-dtb-with-ucode {
|
||||
#ifdef CONFIG_MPC85xx
|
||||
align = <256>;
|
||||
#endif
|
||||
};
|
||||
#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#endif
|
||||
powerpc-mpc85xx-bootpg-resetvec {
|
||||
offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
|
||||
};
|
||||
#endif
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user