GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/arch/sh/cpu/sh4/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+obj-y	= cpu.o interrupts.o watchdog.o cache.o

source/bootloader/u-boot-2020.01/arch/sh/cpu/sh4/cache.c

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+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com>
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+
+#define CACHE_VALID       1
+#define CACHE_UPDATED     2
+
+static inline void cache_wback_all(void)
+{
+	unsigned long addr, data, i, j;
+
+	for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
+		for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
+			addr = CACHE_OC_ADDRESS_ARRAY
+				| (j << CACHE_OC_WAY_SHIFT)
+				| (i << CACHE_OC_ENTRY_SHIFT);
+			data = inl(addr);
+			if (data & CACHE_UPDATED) {
+				data &= ~CACHE_UPDATED;
+				outl(data, addr);
+			}
+		}
+	}
+}
+
+#define CACHE_ENABLE      0
+#define CACHE_DISABLE     1
+
+static int cache_control(unsigned int cmd)
+{
+	unsigned long ccr;
+
+	jump_to_P2();
+	ccr = inl(CCR);
+
+	if (ccr & CCR_CACHE_ENABLE)
+		cache_wback_all();
+
+	if (cmd == CACHE_DISABLE)
+		outl(CCR_CACHE_STOP, CCR);
+	else
+		outl(CCR_CACHE_INIT, CCR);
+	back_to_P1();
+
+	return 0;
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	u32 v;
+
+	start &= ~(L1_CACHE_BYTES - 1);
+	for (v = start; v < end; v += L1_CACHE_BYTES) {
+		asm volatile ("ocbp     %0" :	/* no output */
+			      : "m" (__m(v)));
+	}
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	u32 v;
+
+	start &= ~(L1_CACHE_BYTES - 1);
+	for (v = start; v < end; v += L1_CACHE_BYTES) {
+		asm volatile ("ocbi     %0" :	/* no output */
+			      : "m" (__m(v)));
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	flush_dcache_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+	cache_control(CACHE_ENABLE);
+}
+
+void icache_disable(void)
+{
+	cache_control(CACHE_DISABLE);
+}
+
+int icache_status(void)
+{
+	return 0;
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/sh/cpu/sh4/config.mk

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+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+PLATFORM_CPPFLAGS += $(call cc-option,-m4-nofpu,-m4)

source/bootloader/u-boot-2020.01/arch/sh/cpu/sh4/cpu.c

@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <irq_func.h>
+#include <cpu_func.h>
+#include <netdev.h>
+#include <asm/processor.h>
+
+int checkcpu(void)
+{
+	puts("CPU: SH4\n");
+	return 0;
+}
+
+int cpu_init (void)
+{
+	return 0;
+}
+
+int cleanup_before_linux (void)
+{
+	disable_interrupts();
+	return 0;
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+	reset_cpu (0);
+	return 0;
+}
+
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+	sh_eth_initialize(bis);
+#endif
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/sh/cpu/sh4/interrupts.c

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+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#include <common.h>
+#include <irq_func.h>
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+void enable_interrupts(void)
+{
+
+}
+
+int disable_interrupts(void){
+	return 0;
+}

source/bootloader/u-boot-2020.01/arch/sh/cpu/sh4/watchdog.c

@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/io.h>
+
+#define WDT_BASE	WTCNT
+
+#define WDT_WD		(1 << 6)
+#define WDT_RST_P	(0)
+#define WDT_RST_M	(1 << 5)
+#define WDT_ENABLE	(1 << 7)
+
+#if defined(CONFIG_WATCHDOG)
+static unsigned char csr_read(void)
+{
+	return inb(WDT_BASE + 0x04);
+}
+
+static void cnt_write(unsigned char value)
+{
+	outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
+}
+
+static void csr_write(unsigned char value)
+{
+	outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
+}
+
+void watchdog_reset(void)
+{
+	outl(0x55000000, WDT_BASE + 0x08);
+}
+
+int watchdog_init(void)
+{
+	/* Set overflow time*/
+	cnt_write(0);
+	/* Power on reset */
+	csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
+
+	return 0;
+}
+
+int watchdog_disable(void)
+{
+	csr_write(csr_read() & ~WDT_ENABLE);
+	return 0;
+}
+#endif
+
+void reset_cpu(unsigned long ignored)
+{
+	/* Address error with SR.BL=1 first. */
+	trigger_address_error();
+
+	while (1)
+		;
+}