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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/bootloader/u-boot-2020.01/arch/sh/include/asm/bitops.h
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#ifndef __ASM_SH_BITOPS_H
#define __ASM_SH_BITOPS_H
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/__ffs.h>
#ifdef __KERNEL__
#include <asm/irqflags.h>
/* For __swab32 */
#include <asm/byteorder.h>
static inline void set_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a |= mask;
local_irq_restore(flags);
}
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
static inline void clear_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a &= ~mask;
local_irq_restore(flags);
}
static inline void change_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a ^= mask;
local_irq_restore(flags);
}
static inline int test_and_set_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a |= mask;
local_irq_restore(flags);
return retval;
}
static inline int test_and_clear_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a &= ~mask;
local_irq_restore(flags);
return retval;
}
static inline int test_and_change_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a ^= mask;
local_irq_restore(flags);
return retval;
}
static inline unsigned long ffz(unsigned long word)
{
unsigned long result;
__asm__("1:\n\t"
"shlr %1\n\t"
"bt/s 1b\n\t"
" add #1, %0"
: "=r" (result), "=r" (word)
: "0" (~0L), "1" (word)
: "t");
return result;
}
/**
* ffs - find first bit in word.
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static inline int ffs (int x)
{
int r = 1;
if (!x)
return 0;
if (!(x & 0xffff)) {
x >>= 16;
r += 16;
}
if (!(x & 0xff)) {
x >>= 8;
r += 8;
}
if (!(x & 0xf)) {
x >>= 4;
r += 4;
}
if (!(x & 3)) {
x >>= 2;
r += 2;
}
if (!(x & 1)) {
x >>= 1;
r += 1;
}
return r;
}
#define PLATFORM_FFS
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
#endif /* __KERNEL__ */
#endif /* __ASM_SH_BITOPS_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/byteorder.h
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __ASM_SH_BYTEORDER_H_
#define __ASM_SH_BYTEORDER_H_
#include <config.h>
#include <asm/types.h>
#ifdef __LITTLE_ENDIAN__
#include <linux/byteorder/little_endian.h>
#else
#include <linux/byteorder/big_endian.h>
#endif
#endif
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cache.h
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#ifndef __ASM_SH_CACHE_H
#define __ASM_SH_CACHE_H
#if defined(CONFIG_CPU_SH4)
#define L1_CACHE_BYTES 32
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
#else
/*
* 32-bytes is the largest L1 data cache line size for SH the architecture. So
* it is a safe default for DMA alignment.
*/
#define ARCH_DMA_MINALIGN 32
#endif /* CONFIG_CPU_SH4 */
/*
* Use the L1 data cache line size value for the minimum DMA buffer alignment
* on SH.
*/
#ifndef ARCH_DMA_MINALIGN
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#endif
#endif /* __ASM_SH_CACHE_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/config.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*/
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#include <asm/processor.h>
#define CONFIG_LMB
/* Timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
#endif
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh4.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#ifndef _ASM_CPU_SH4_H_
#define _ASM_CPU_SH4_H_
/* cache control */
#define CCR_CACHE_STOP 0x00000808
#define CCR_CACHE_ENABLE 0x00000101
#define CCR_CACHE_ICI 0x00000800
#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
#if defined (CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751)
#define CACHE_OC_WAY_SHIFT 14
#define CACHE_OC_NUM_ENTRIES 512
#else
#define CACHE_OC_WAY_SHIFT 13
#define CACHE_OC_NUM_ENTRIES 256
#endif
#define CACHE_OC_ENTRY_SHIFT 5
#if defined (CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751)
# include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h>
#elif defined (CONFIG_CPU_SH7734)
# include <asm/cpu_sh7734.h>
#elif defined (CONFIG_CPU_SH7752)
# include <asm/cpu_sh7752.h>
#elif defined (CONFIG_CPU_SH7753)
# include <asm/cpu_sh7753.h>
#elif defined (CONFIG_CPU_SH7757)
# include <asm/cpu_sh7757.h>
#elif defined (CONFIG_CPU_SH7763)
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
# include <asm/cpu_sh7780.h>
#else
# error "Unknown SH4 variant"
#endif
#if defined(CONFIG_SH_32BIT)
#define PMB_ADDR_ARRAY 0xf6100000
#define PMB_ADDR_ENTRY 8
#define PMB_VPN 24
#define PMB_DATA_ARRAY 0xf7100000
#define PMB_DATA_ENTRY 8
#define PMB_PPN 24
#define PMB_UB 9 /* Buffered write */
#define PMB_V 8 /* Valid */
#define PMB_SZ1 7 /* Page size (upper bit) */
#define PMB_SZ0 4 /* Page size (lower bit) */
#define PMB_C 3 /* Cacheability */
#define PMB_WT 0 /* Write-through */
#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN))
#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \
((ppn << PMB_PPN) | (ub << PMB_UB) | \
(v << PMB_V) | (sz1 << PMB_SZ1) | \
(sz0 << PMB_SZ0) | (c << PMB_C) | \
(wt << PMB_WT))
#endif
#endif /* _ASM_CPU_SH4_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh7722.h
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source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh7723.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2008 Renesas Solutions Corp.
*
* SH7723 Internal I/O register
*/
#ifndef _ASM_CPU_SH7723_H_
#define _ASM_CPU_SH7723_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000090d
/* EXP */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* MMU */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define PASCR 0xFF000070
#define IRMCR 0xFF000078
/* CACHE */
#define CCR 0xFF00001C
#define RAMCR 0xFF000074
/* INTC */
/* BSC */
#define CMNCR 0xFEC10000
#define CS0BCR 0xFEC10004
#define CS2BCR 0xFEC10008
#define CS4BCR 0xFEC10010
#define CS5ABCR 0xFEC10014
#define CS5BBCR 0xFEC10018
#define CS6ABCR 0xFEC1001C
#define CS6BBCR 0xFEC10020
#define CS0WCR 0xFEC10024
#define CS2WCR 0xFEC10028
#define CS4WCR 0xFEC10030
#define CS5AWCR 0xFEC10034
#define CS5BWCR 0xFEC10038
#define CS6AWCR 0xFEC1003C
#define CS6BWCR 0xFEC10040
#define RBWTCNT 0xFEC10054
/* SBSC */
#define SBSC_SDCR 0xFE400008
#define SBSC_SDWCR 0xFE40000C
#define SBSC_SDPCR 0xFE400010
#define SBSC_RTCSR 0xFE400014
#define SBSC_RTCNT 0xFE400018
#define SBSC_RTCOR 0xFE40001C
#define SBSC_RFCR 0xFE400020
/* DMAC */
/* CPG */
#define FRQCR 0xA4150000
#define VCLKCR 0xA4150004
#define SCLKACR 0xA4150008
#define SCLKBCR 0xA415000C
#define IRDACLKCR 0xA4150018
#define PLLCR 0xA4150024
#define DLLFRQ 0xA4150050
/* LOW POWER MODE */
#define STBCR 0xA4150020
#define MSTPCR0 0xA4150030
#define MSTPCR1 0xA4150034
#define MSTPCR2 0xA4150038
/* RWDT */
#define RWTCNT 0xA4520000
#define RWTCSR 0xA4520004
#define WTCNT RWTCNT
/* TMU */
#define TMU_BASE 0xFFD80000
/* TPU */
/* CMT */
#define CMSTR 0xA44A0000
#define CMCSR 0xA44A0060
#define CMCNT 0xA44A0064
#define CMCOR 0xA44A0068
/* MSIOF */
/* SCIF */
#define SCIF0_BASE 0xFFE00000
#define SCIF1_BASE 0xFFE10000
#define SCIF2_BASE 0xFFE20000
#define SCIF3_BASE 0xa4e30000
#define SCIF4_BASE 0xa4e40000
#define SCIF5_BASE 0xa4e50000
/* RTC */
/* IrDA */
/* KEYSC */
/* USB */
/* IIC */
/* FLCTL */
/* VPU */
/* VIO(CEU) */
/* VIO(VEU) */
/* VIO(BEU) */
/* 2DG */
/* LCDC */
/* VOU */
/* TSIF */
/* SIU */
/* ATAPI */
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PDCR 0xA4050106
#define PECR 0xA4050108
#define PFCR 0xA405010A
#define PGCR 0xA405010C
#define PHCR 0xA405010E
#define PJCR 0xA4050110
#define PKCR 0xA4050112
#define PLCR 0xA4050114
#define PMCR 0xA4050116
#define PNCR 0xA4050118
#define PQCR 0xA405011A
#define PRCR 0xA405011C
#define PSCR 0xA405011E
#define PTCR 0xA4050140
#define PUCR 0xA4050142
#define PVCR 0xA4050144
#define PWCR 0xA4050146
#define PXCR 0xA4050148
#define PYCR 0xA405014A
#define PZCR 0xA405014C
#define PSELA 0xA405014E
#define PSELB 0xA4050150
#define PSELC 0xA4050152
#define PSELD 0xA4050154
#define HIZCRA 0xA4050158
#define HIZCRB 0xA405015A
#define HIZCRC 0xA405015C
#define HIZCRD 0xA405015E
#define MSELCRA 0xA4050180
#define MSELCRB 0xA4050182
#define PULCR 0xA4050184
#define DRVCRA 0xA405018A
#define DRVCRB 0xA405018C
/* I/O Port */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
#define PDDR 0xA4050126
#define PEDR 0xA4050128
#define PFDR 0xA405012A
#define PGDR 0xA405012C
#define PHDR 0xA405012E
#define PJDR 0xA4050130
#define PKDR 0xA4050132
#define PLDR 0xA4050134
#define PMDR 0xA4050136
#define PNDR 0xA4050138
#define PQDR 0xA405013A
#define PRDR 0xA405013C
#define PSDR 0xA405013E
#define PTDR 0xA4050160
#define PUDR 0xA4050162
#define PVDR 0xA4050164
#define PWDR 0xA4050166
#define PXDR 0xA4050168
#define PYDR 0xA405016A
#define PZDR 0xA405016C
/* UBC */
/* H-UDI */
#endif /* _ASM_CPU_SH7723_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh7734.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2008, 2011 Renesas Solutions Corp.
*
* SH7734 Internal I/O register
*/
#ifndef _ASM_CPU_SH7734_H_
#define _ASM_CPU_SH7734_H_
#define CCR 0xFF00001C
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000090d
/* SCIF */
#define SCIF0_BASE 0xFFE40000
#define SCIF1_BASE 0xFFE41000
#define SCIF2_BASE 0xFFE42000
#define SCIF3_BASE 0xFFE43000
#define SCIF4_BASE 0xFFE44000
#define SCIF5_BASE 0xFFE45000
/* Timer */
#define TMU_BASE 0xFFD80000
/* PFC */
#define PMMR (0xFFFC0000)
#define MODESEL0 (0xFFFC004C)
#define MODESEL2 (MODESEL0 + 0x4)
#define MODESEL2_INIT (0x00003000)
#define IPSR0 (0xFFFC001C)
#define IPSR1 (IPSR0 + 0x4)
#define IPSR2 (IPSR0 + 0x8)
#define IPSR3 (IPSR0 + 0xC)
#define IPSR4 (IPSR0 + 0x10)
#define IPSR5 (IPSR0 + 0x14)
#define IPSR6 (IPSR0 + 0x18)
#define IPSR7 (IPSR0 + 0x1C)
#define IPSR8 (IPSR0 + 0x20)
#define IPSR9 (IPSR0 + 0x24)
#define IPSR10 (IPSR0 + 0x28)
#define IPSR11 (IPSR0 + 0x2C)
#define GPSR0 (0xFFFC0004)
#define GPSR1 (GPSR0 + 0x4)
#define GPSR2 (GPSR0 + 0x8)
#define GPSR3 (GPSR0 + 0xC)
#define GPSR4 (GPSR0 + 0x10)
#define GPSR5 (GPSR0 + 0x14)
#endif /* _ASM_CPU_SH7734_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh7750.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SH7750/SH7750S/SH7750R/SH7751/SH7751R
* Internal I/O register
*/
#ifndef _ASM_CPU_SH7750_H_
#define _ASM_CPU_SH7750_H_
#ifdef CONFIG_CPU_TYPE_R
#define CACHE_OC_NUM_WAYS 2
#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
#else
#define CACHE_OC_NUM_WAYS 1
#define CCR_CACHE_INIT 0x0000090B
#endif
/* OCN */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define BASRA 0xFF000014
#define BASRB 0xFF000018
#define CCR 0xFF00001C
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
#define PTEA 0xFF000034
#define QACR0 0xFF000038
#define QACR1 0xFF00003C
/* UBC */
#define BARA 0xFF200000
#define BAMRA 0xFF200004
#define BBRA 0xFF200008
#define BARB 0xFF20000C
#define BAMRB 0xFF200010
#define BBRB 0xFF200014
#define BDRB 0xFF200018
#define BDMRB 0xFF20001C
#define BRCR 0xFF200020
/* BSC */
#define BCR1 0xFF800000
#define BCR2 0xFF800004
#define BCR3 0xFF800050
#define BCR4 0xFE0A00F0
#define WCR1 0xFF800008
#define WCR2 0xFF80000C
#define WCR3 0xFF800010
#define MCR 0xFF800014
#define PCR 0xFF800018
#define RTCSR 0xFF80001C
#define RTCNT 0xFF800020
#define RTCOR 0xFF800024
#define RFCR 0xFF800028
#define PCTRA 0xFF80002C
#define PDTRA 0xFF800030
#define PCTRB 0xFF800040
#define PDTRB 0xFF800044
#define GPIOIC 0xFF800048
/* DMAC */
#define SAR0 0xFFA00000
#define DAR0 0xFFA00004
#define DMATCR0 0xFFA00008
#define CHCR0 0xFFA0000C
#define SAR1 0xFFA00010
#define DAR1 0xFFA00014
#define DMATCR1 0xFFA00018
#define CHCR1 0xFFA0001C
#define SAR2 0xFFA00020
#define DAR2 0xFFA00024
#define DMATCR2 0xFFA00028
#define CHCR2 0xFFA0002C
#define SAR3 0xFFA00030
#define DAR3 0xFFA00034
#define DMATCR3 0xFFA00038
#define CHCR3 0xFFA0003C
#define DMAOR 0xFFA00040
#define SAR4 0xFFA00050
#define DAR4 0xFFA00054
#define DMATCR4 0xFFA00058
/* CPG */
#define FRQCR 0xFFC00000
#define STBCR 0xFFC00004
#define WTCNT 0xFFC00008
#define WTCSR 0xFFC0000C
#define STBCR2 0xFFC00010
/* RTC */
#define R64CNT 0xFFC80000
#define RSECCNT 0xFFC80004
#define RMINCNT 0xFFC80008
#define RHRCNT 0xFFC8000C
#define RWKCNT 0xFFC80010
#define RDAYCNT 0xFFC80014
#define RMONCNT 0xFFC80018
#define RYRCNT 0xFFC8001C
#define RSECAR 0xFFC80020
#define RMINAR 0xFFC80024
#define RHRAR 0xFFC80028
#define RWKAR 0xFFC8002C
#define RDAYAR 0xFFC80030
#define RMONAR 0xFFC80034
#define RCR1 0xFFC80038
#define RCR2 0xFFC8003C
#define RCR3 0xFFC80050
#define RYRAR 0xFFC80054
/* ICR */
#define ICR 0xFFD00000
#define IPRA 0xFFD00004
#define IPRB 0xFFD00008
#define IPRC 0xFFD0000C
#define IPRD 0xFFD00010
#define INTPRI 0xFE080000
#define INTREQ 0xFE080020
#define INTMSK 0xFE080040
#define INTMSKCL 0xFE080060
/* CPG */
#define CLKSTP 0xFE0A0000
#define CLKSTPCLR 0xFE0A0008
/* TMU */
#define TMU_BASE 0xFFD80000
/* SCI */
#define SCSMR1 0xFFE00000
#define SCF0_BASE SCSMR1
/* SCIF */
#define SCSMR2 0xFFE80000
#define SCIF1_BASE SCSMR2
/* H-UDI */
#define SDIR 0xFFF00000
#define SDDR 0xFFF00008
#define SDINT 0xFFF00014
#endif /* _ASM_CPU_SH7750_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh7752.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*/
#ifndef _ASM_CPU_SH7752_H_
#define _ASM_CPU_SH7752_H_
#define CCR 0xFF00001C
#define WTCNT 0xFFCC0000
#define CCR_CACHE_INIT 0x0000090b
#define CACHE_OC_NUM_WAYS 1
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
/* MMU */
struct mmu_regs {
unsigned int reserved[4];
unsigned int mmucr;
};
#define MMU_BASE ((struct mmu_regs *)0xff000000)
/* Watchdog */
#define WTCSR0 0xffcc0002
#define WRSTCSR_R 0xffcc0003
#define WRSTCSR_W 0xffcc0002
#define WTCSR_PREFIX 0xa500
#define WRSTCSR_PREFIX 0x6900
#define WRSTCSR_WOVF_PREFIX 0x9600
/* SCIF */
#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
/* TMU0 */
#define TMU_BASE 0xFE430000
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
unsigned int reserved[114];
unsigned int mahr;
unsigned int reserved2;
unsigned int malr;
};
#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
/* GETHER */
struct gether_control_regs {
unsigned int gbecont;
};
#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
#define GBECONT_RMII1 0x00020000
#define GBECONT_RMII0 0x00010000
/* SerMux */
struct sermux_regs {
unsigned char smr0;
unsigned char smr1;
unsigned char smr2;
unsigned char smr3;
unsigned char smr4;
unsigned char smr5;
};
#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
/* USB0/1 */
struct usb_common_regs {
unsigned short reserved[129];
unsigned short suspmode;
};
#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
struct usb0_phy_regs {
unsigned short reset;
unsigned short reserved[4];
unsigned short portsel;
};
#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
struct usb1_port_regs {
unsigned int port1sel;
unsigned int reserved;
unsigned int usb1intsts;
};
#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
struct usb1_alignment_regs {
unsigned int ehcidatac; /* 0xfe4fe018 */
unsigned int reserved[63];
unsigned int ohcidatac;
};
#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
/* GPIO */
struct gpio_regs {
unsigned short pacr;
unsigned short pbcr;
unsigned short pccr;
unsigned short pdcr;
unsigned short pecr;
unsigned short pfcr;
unsigned short pgcr;
unsigned short phcr;
unsigned short picr;
unsigned short pjcr;
unsigned short pkcr;
unsigned short plcr;
unsigned short pmcr;
unsigned short pncr;
unsigned short pocr;
unsigned short reserved;
unsigned short pqcr;
unsigned short prcr;
unsigned short pscr;
unsigned short ptcr;
unsigned short pucr;
unsigned short pvcr;
unsigned short pwcr;
unsigned short pxcr;
unsigned short pycr;
unsigned short pzcr;
unsigned char padr;
unsigned char reserved_a;
unsigned char pbdr;
unsigned char reserved_b;
unsigned char pcdr;
unsigned char reserved_c;
unsigned char pddr;
unsigned char reserved_d;
unsigned char pedr;
unsigned char reserved_e;
unsigned char pfdr;
unsigned char reserved_f;
unsigned char pgdr;
unsigned char reserved_g;
unsigned char phdr;
unsigned char reserved_h;
unsigned char pidr;
unsigned char reserved_i;
unsigned char pjdr;
unsigned char reserved_j;
unsigned char pkdr;
unsigned char reserved_k;
unsigned char pldr;
unsigned char reserved_l;
unsigned char pmdr;
unsigned char reserved_m;
unsigned char pndr;
unsigned char reserved_n;
unsigned char podr;
unsigned char reserved_o;
unsigned char ppdr;
unsigned char reserved_p;
unsigned char pqdr;
unsigned char reserved_q;
unsigned char prdr;
unsigned char reserved_r;
unsigned char psdr;
unsigned char reserved_s;
unsigned char ptdr;
unsigned char reserved_t;
unsigned char pudr;
unsigned char reserved_u;
unsigned char pvdr;
unsigned char reserved_v;
unsigned char pwdr;
unsigned char reserved_w;
unsigned char pxdr;
unsigned char reserved_x;
unsigned char pydr;
unsigned char reserved_y;
unsigned char pzdr;
unsigned char reserved_z;
unsigned short ncer;
unsigned short ncmcr;
unsigned short nccsr;
unsigned char reserved2[2];
unsigned short psel0; /* +0x70 */
unsigned short psel1;
unsigned short psel2;
unsigned short psel3;
unsigned short psel4;
unsigned short psel5;
unsigned short psel6;
unsigned short reserved3[2];
unsigned short psel7;
};
#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
#endif /* ifndef __ASSEMBLY__ */
#endif /* _ASM_CPU_SH7752_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh7753.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*/
#ifndef _ASM_CPU_SH7753_H_
#define _ASM_CPU_SH7753_H_
#define CCR 0xFF00001C
#define WTCNT 0xFFCC0000
#define CCR_CACHE_INIT 0x0000090b
#define CACHE_OC_NUM_WAYS 1
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
/* MMU */
struct mmu_regs {
unsigned int reserved[4];
unsigned int mmucr;
};
#define MMU_BASE ((struct mmu_regs *)0xff000000)
/* Watchdog */
#define WTCSR0 0xffcc0002
#define WRSTCSR_R 0xffcc0003
#define WRSTCSR_W 0xffcc0002
#define WTCSR_PREFIX 0xa500
#define WRSTCSR_PREFIX 0x6900
#define WRSTCSR_WOVF_PREFIX 0x9600
/* SCIF */
#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
/* TMU0 */
#define TMU_BASE 0xFE430000
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
unsigned int reserved[114];
unsigned int mahr;
unsigned int reserved2;
unsigned int malr;
};
#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
/* GETHER */
struct gether_control_regs {
unsigned int gbecont;
};
#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
#define GBECONT_RMII1 0x00020000
#define GBECONT_RMII0 0x00010000
/* SerMux */
struct sermux_regs {
unsigned char smr0;
unsigned char smr1;
unsigned char smr2;
unsigned char smr3;
unsigned char smr4;
unsigned char smr5;
};
#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
/* USB0/1 */
struct usb_common_regs {
unsigned short reserved[129];
unsigned short suspmode;
};
#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
struct usb0_phy_regs {
unsigned short reset;
unsigned short reserved[4];
unsigned short portsel;
};
#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
struct usb1_port_regs {
unsigned int port1sel;
unsigned int reserved;
unsigned int usb1intsts;
};
#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
struct usb1_alignment_regs {
unsigned int ehcidatac; /* 0xfe4fe018 */
unsigned int reserved[63];
unsigned int ohcidatac;
};
#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
/* GPIO */
struct gpio_regs {
unsigned short pacr;
unsigned short pbcr;
unsigned short pccr;
unsigned short pdcr;
unsigned short pecr;
unsigned short pfcr;
unsigned short pgcr;
unsigned short phcr;
unsigned short picr;
unsigned short pjcr;
unsigned short pkcr;
unsigned short plcr;
unsigned short pmcr;
unsigned short pncr;
unsigned short pocr;
unsigned short reserved;
unsigned short pqcr;
unsigned short prcr;
unsigned short pscr;
unsigned short ptcr;
unsigned short pucr;
unsigned short pvcr;
unsigned short pwcr;
unsigned short pxcr;
unsigned short pycr;
unsigned short pzcr;
unsigned char padr;
unsigned char reserved_a;
unsigned char pbdr;
unsigned char reserved_b;
unsigned char pcdr;
unsigned char reserved_c;
unsigned char pddr;
unsigned char reserved_d;
unsigned char pedr;
unsigned char reserved_e;
unsigned char pfdr;
unsigned char reserved_f;
unsigned char pgdr;
unsigned char reserved_g;
unsigned char phdr;
unsigned char reserved_h;
unsigned char pidr;
unsigned char reserved_i;
unsigned char pjdr;
unsigned char reserved_j;
unsigned char pkdr;
unsigned char reserved_k;
unsigned char pldr;
unsigned char reserved_l;
unsigned char pmdr;
unsigned char reserved_m;
unsigned char pndr;
unsigned char reserved_n;
unsigned char podr;
unsigned char reserved_o;
unsigned char ppdr;
unsigned char reserved_p;
unsigned char pqdr;
unsigned char reserved_q;
unsigned char prdr;
unsigned char reserved_r;
unsigned char psdr;
unsigned char reserved_s;
unsigned char ptdr;
unsigned char reserved_t;
unsigned char pudr;
unsigned char reserved_u;
unsigned char pvdr;
unsigned char reserved_v;
unsigned char pwdr;
unsigned char reserved_w;
unsigned char pxdr;
unsigned char reserved_x;
unsigned char pydr;
unsigned char reserved_y;
unsigned char pzdr;
unsigned char reserved_z;
unsigned short ncer;
unsigned short ncmcr;
unsigned short nccsr;
unsigned char reserved2[2];
unsigned short psel0; /* +0x70 */
unsigned short psel1;
unsigned short psel2;
unsigned short psel3;
unsigned short psel4;
unsigned short psel5;
unsigned short psel6;
unsigned short reserved3[2];
unsigned short psel7;
};
#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
#endif /* ifndef __ASSEMBLY__ */
#endif /* _ASM_CPU_SH7753_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh7757.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Renesas Solutions Corp.
*/
#ifndef _ASM_CPU_SH7757_H_
#define _ASM_CPU_SH7757_H_
#define CCR 0xFF00001C
#define WTCNT 0xFFCC0000
#define CCR_CACHE_INIT 0x0000090b
#define CACHE_OC_NUM_WAYS 1
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
/* MMU */
struct mmu_regs {
unsigned int reserved[4];
unsigned int mmucr;
};
#define MMU_BASE ((struct mmu_regs *)0xff000000)
/* Watchdog */
#define WTCSR0 0xffcc0002
#define WRSTCSR_R 0xffcc0003
#define WRSTCSR_W 0xffcc0002
#define WTCSR_PREFIX 0xa500
#define WRSTCSR_PREFIX 0x6900
#define WRSTCSR_WOVF_PREFIX 0x9600
/* SCIF */
#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
/* SerMux */
#define SMR0 0xfe470000
/* TMU0 */
#define TMU_BASE 0xFE430000
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
unsigned int reserved[114];
unsigned int mahr;
unsigned int reserved2;
unsigned int malr;
};
#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
/* GETHER */
struct gether_control_regs {
unsigned int gbecont;
};
#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
#define GBECONT_RMII1 0x00020000
#define GBECONT_RMII0 0x00010000
/* USB0/1 */
struct usb_common_regs {
unsigned short reserved[129];
unsigned short suspmode;
};
#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
struct usb0_phy_regs {
unsigned short reset;
unsigned short reserved[4];
unsigned short portsel;
};
#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
struct usb1_port_regs {
unsigned int port1sel;
unsigned int reserved;
unsigned int usb1intsts;
};
#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
struct usb1_alignment_regs {
unsigned int ehcidatac; /* 0xfe4fe018 */
unsigned int reserved[63];
unsigned int ohcidatac;
};
#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
/* GCTRL, GRA */
struct gctrl_regs {
unsigned int wprotect;
unsigned int gplldiv;
unsigned int gracr2; /* GRA */
unsigned int gracr3; /* GRA */
unsigned int reserved[4];
unsigned int fcntcr1;
unsigned int fcntcr2;
unsigned int reserved2[2];
unsigned int gpll1div;
unsigned int vcompsel;
unsigned int reserved3[62];
unsigned int fdlmon;
unsigned int reserved4[2];
unsigned int flcrmon;
unsigned int reserved5[944];
unsigned int spibootcan;
};
#define GCTRL_BASE ((struct gctrl_regs *)0xffc10000)
/* PCIe setup */
struct pcie_setup_regs {
unsigned int pbictl0;
unsigned int gradevctl;
unsigned int reserved[2];
unsigned int bmcinf[6];
unsigned int reserved2[118];
unsigned int idset[2];
unsigned int subidset;
unsigned int reserved3[2];
unsigned int linkconfset[4];
unsigned int trsid;
unsigned int reserved4[6];
unsigned int toutset;
unsigned int reserved5[7];
unsigned int lad0;
unsigned int ladmsk0;
unsigned int lad1;
unsigned int ladmsk1;
unsigned int lad2;
unsigned int ladmsk2;
unsigned int lad3;
unsigned int ladmsk3;
unsigned int lad4;
unsigned int ladmsk4;
unsigned int lad5;
unsigned int ladmsk5;
unsigned int reserved6[94];
unsigned int vdmrxvid[2];
unsigned int reserved7;
unsigned int pbiintfr;
unsigned int pbiinten;
unsigned int msimap;
unsigned int barmap;
unsigned int baracsize;
unsigned int advserest;
unsigned int pbictl3;
unsigned int reserved8[8];
unsigned int pbictl1;
unsigned int scratch0;
unsigned int reserved9[6];
unsigned int pbictl2;
unsigned int reserved10;
unsigned int pbirev;
};
#define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000)
struct pcie_system_bus_regs {
unsigned int reserved[3];
unsigned int endictl0;
unsigned int endictl1;
};
#define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600)
/* PCIe-Bridge */
struct pciebrg_regs {
unsigned short ctrl_h8s;
unsigned short reserved[7];
unsigned short cp_addr;
unsigned short reserved2;
unsigned short cp_data;
unsigned short reserved3;
unsigned short cp_ctrl;
};
#define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000)
/* CPU version */
#define CCN_PRR 0xff000044
#define prr_mask(_val) ((_val >> 4) & 0xff)
#define PRR_SH7757_B0 0x10
#define PRR_SH7757_C0 0x11
#define is_sh7757_b0(_val) \
({ \
int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \
__ret; \
})
#endif /* ifndef __ASSEMBLY__ */
#endif /* _ASM_CPU_SH7757_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh7763.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu
*/
#ifndef _ASM_CPU_SH7763_H_
#define _ASM_CPU_SH7763_H_
/* CACHE */
#define CACHE_OC_NUM_WAYS 1
#define CCR 0xFF00001C
#define CCR_CACHE_INIT 0x0000090b
/* SCIF */
/* SCIF0 */
#define SCIF0_BASE SCSMR0
#define SCSMR0 0xFFE00000
/* SCIF1 */
#define SCIF1_BASE SCSMR1
#define SCSMR1 0xFFE08000
/* SCIF2 */
#define SCIF2_BASE SCSMR2
#define SCSMR2 0xFFE10000
/* Watchdog Timer */
#define WTCNT WDTST
#define WDTST 0xFFCC0000
/* TMU */
#define TMU_BASE 0xFFD80000
#endif /* _ASM_CPU_SH7763_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/cpu_sh7780.h
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef _ASM_CPU_SH7780_H_
#define _ASM_CPU_SH7780_H_
/*
* Copyright (c) 2007,2008 Nobuhiro Iwamatsu
* Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*/
#define CACHE_OC_NUM_WAYS 1
#define CCR_CACHE_INIT 0x0000090b
/* Exceptions */
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
/* Memory Management Unit */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define PASCR 0xFF000070
#define IRMCR 0xFF000078
/* Cache Controller */
#define CCR 0xFF00001C
#define QACR0 0xFF000038
#define QACR1 0xFF00003C
#define RAMCR 0xFF000074
/* L Memory */
#define RAMCR 0xFF000074
#define LSA0 0xFF000050
#define LSA1 0xFF000054
#define LDA0 0xFF000058
#define LDA1 0xFF00005C
/* Interrupt Controller */
#define ICR0 0xFFD00000
#define ICR1 0xFFD0001C
#define INTPRI 0xFFD00010
#define INTREQ 0xFFD00024
#define INTMSK0 0xFFD00044
#define INTMSK1 0xFFD00048
#define INTMSK2 0xFFD40080
#define INTMSKCLR0 0xFFD00064
#define INTMSKCLR1 0xFFD00068
#define INTMSKCLR2 0xFFD40084
#define NMIFCR 0xFFD000C0
#define USERIMASK 0xFFD30000
#define INT2PRI0 0xFFD40000
#define INT2PRI1 0xFFD40004
#define INT2PRI2 0xFFD40008
#define INT2PRI3 0xFFD4000C
#define INT2PRI4 0xFFD40010
#define INT2PRI5 0xFFD40014
#define INT2PRI6 0xFFD40018
#define INT2PRI7 0xFFD4001C
#define INT2A0 0xFFD40030
#define INT2A1 0xFFD40034
#define INT2MSKR 0xFFD40038
#define INT2MSKCR 0xFFD4003C
#define INT2B0 0xFFD40040
#define INT2B1 0xFFD40044
#define INT2B2 0xFFD40048
#define INT2B3 0xFFD4004C
#define INT2B4 0xFFD40050
#define INT2B5 0xFFD40054
#define INT2B6 0xFFD40058
#define INT2B7 0xFFD4005C
#define INT2GPIC 0xFFD40090
/* local Bus State Controller */
#define MMSELR 0xFF400020
#define BCR 0xFF801000
#define CS0BCR 0xFF802000
#define CS1BCR 0xFF802010
#define CS2BCR 0xFF802020
#define CS4BCR 0xFF802040
#define CS5BCR 0xFF802050
#define CS6BCR 0xFF802060
#define CS0WCR 0xFF802008
#define CS1WCR 0xFF802018
#define CS2WCR 0xFF802028
#define CS4WCR 0xFF802048
#define CS5WCR 0xFF802058
#define CS6WCR 0xFF802068
#define CS5PCR 0xFF802070
#define CS6PCR 0xFF802080
/* DDR-SDRAM I/F */
#define MIM_1 0xFE800008
#define MIM_2 0xFE80000C
#define SCR_1 0xFE800010
#define SCR_2 0xFE800014
#define STR_1 0xFE800018
#define STR_2 0xFE80001C
#define SDR_1 0xFE800030
#define SDR_2 0xFE800034
#define DBK_1 0xFE800400
#define DBK_2 0xFE800404
/* PCI Controller */
#define SH7780_PCIECR 0xFE000008
#define SH7780_PCIVID 0xFE040000
#define SH7780_PCIDID 0xFE040002
#define SH7780_PCICMD 0xFE040004
#define SH7780_PCISTATUS 0xFE040006
#define SH7780_PCIRID 0xFE040008
#define SH7780_PCIPIF 0xFE040009
#define SH7780_PCISUB 0xFE04000A
#define SH7780_PCIBCC 0xFE04000B
#define SH7780_PCICLS 0xFE04000C
#define SH7780_PCILTM 0xFE04000D
#define SH7780_PCIHDR 0xFE04000E
#define SH7780_PCIBIST 0xFE04000F
#define SH7780_PCIIBAR 0xFE040010
#define SH7780_PCIMBAR0 0xFE040014
#define SH7780_PCIMBAR1 0xFE040018
#define SH7780_PCISVID 0xFE04002C
#define SH7780_PCISID 0xFE04002E
#define SH7780_PCICP 0xFE040034
#define SH7780_PCIINTLINE 0xFE04003C
#define SH7780_PCIINTPIN 0xFE04003D
#define SH7780_PCIMINGNT 0xFE04003E
#define SH7780_PCIMAXLAT 0xFE04003F
#define SH7780_PCICID 0xFE040040
#define SH7780_PCINIP 0xFE040041
#define SH7780_PCIPMC 0xFE040042
#define SH7780_PCIPMCSR 0xFE040044
#define SH7780_PCIPMCSRBSE 0xFE040046
#define SH7780_PCI_CDD 0xFE040047
#define SH7780_PCICR 0xFE040100
#define SH7780_PCILSR0 0xFE040104
#define SH7780_PCILSR1 0xFE040108
#define SH7780_PCILAR0 0xFE04010C
#define SH7780_PCILAR1 0xFE040110
#define SH7780_PCIIR 0xFE040114
#define SH7780_PCIIMR 0xFE040118
#define SH7780_PCIAIR 0xFE04011C
#define SH7780_PCICIR 0xFE040120
#define SH7780_PCIAINT 0xFE040130
#define SH7780_PCIAINTM 0xFE040134
#define SH7780_PCIBMIR 0xFE040138
#define SH7780_PCIPAR 0xFE0401C0
#define SH7780_PCIPINT 0xFE0401CC
#define SH7780_PCIPINTM 0xFE0401D0
#define SH7780_PCIMBR0 0xFE0401E0
#define SH7780_PCIMBMR0 0xFE0401E4
#define SH7780_PCIMBR1 0xFE0401E8
#define SH7780_PCIMBMR1 0xFE0401EC
#define SH7780_PCIMBR2 0xFE0401F0
#define SH7780_PCIMBMR2 0xFE0401F4
#define SH7780_PCIIOBR 0xFE0401F8
#define SH7780_PCIIOBMR 0xFE0401FC
#define SH7780_PCICSCR0 0xFE040210
#define SH7780_PCICSCR1 0xFE040214
#define SH7780_PCICSAR0 0xFE040218
#define SH7780_PCICSAR1 0xFE04021C
#define SH7780_PCIPDR 0xFE040220
/* DMAC */
#define DMAC_SAR0 0xFC808020
#define DMAC_DAR0 0xFC808024
#define DMAC_TCR0 0xFC808028
#define DMAC_CHCR0 0xFC80802C
#define DMAC_SAR1 0xFC808030
#define DMAC_DAR1 0xFC808034
#define DMAC_TCR1 0xFC808038
#define DMAC_CHCR1 0xFC80803C
#define DMAC_SAR2 0xFC808040
#define DMAC_DAR2 0xFC808044
#define DMAC_TCR2 0xFC808048
#define DMAC_CHCR2 0xFC80804C
#define DMAC_SAR3 0xFC808050
#define DMAC_DAR3 0xFC808054
#define DMAC_TCR3 0xFC808058
#define DMAC_CHCR3 0xFC80805C
#define DMAC_DMAOR0 0xFC808060
#define DMAC_SAR4 0xFC808070
#define DMAC_DAR4 0xFC808074
#define DMAC_TCR4 0xFC808078
#define DMAC_CHCR4 0xFC80807C
#define DMAC_SAR5 0xFC808080
#define DMAC_DAR5 0xFC808084
#define DMAC_TCR5 0xFC808088
#define DMAC_CHCR5 0xFC80808C
#define DMAC_SARB0 0xFC808120
#define DMAC_DARB0 0xFC808124
#define DMAC_TCRB0 0xFC808128
#define DMAC_SARB1 0xFC808130
#define DMAC_DARB1 0xFC808134
#define DMAC_TCRB1 0xFC808138
#define DMAC_SARB2 0xFC808140
#define DMAC_DARB2 0xFC808144
#define DMAC_TCRB2 0xFC808148
#define DMAC_SARB3 0xFC808150
#define DMAC_DARB3 0xFC808154
#define DMAC_TCRB3 0xFC808158
#define DMAC_DMARS0 0xFC809000
#define DMAC_DMARS1 0xFC809004
#define DMAC_DMARS2 0xFC809008
#define DMAC_SAR6 0xFC818020
#define DMAC_DAR6 0xFC818024
#define DMAC_TCR6 0xFC818028
#define DMAC_CHCR6 0xFC81802C
#define DMAC_SAR7 0xFC818030
#define DMAC_DAR7 0xFC818034
#define DMAC_TCR7 0xFC818038
#define DMAC_CHCR7 0xFC81803C
#define DMAC_SAR8 0xFC818040
#define DMAC_DAR8 0xFC818044
#define DMAC_TCR8 0xFC818048
#define DMAC_CHCR8 0xFC81804C
#define DMAC_SAR9 0xFC818050
#define DMAC_DAR9 0xFC818054
#define DMAC_TCR9 0xFC818058
#define DMAC_CHCR9 0xFC81805C
#define DMAC_DMAOR1 0xFC818060
#define DMAC_SAR10 0xFC818070
#define DMAC_DAR10 0xFC818074
#define DMAC_TCR10 0xFC818078
#define DMAC_CHCR10 0xFC81807C
#define DMAC_SAR11 0xFC818080
#define DMAC_DAR11 0xFC818084
#define DMAC_TCR11 0xFC818088
#define DMAC_CHCR11 0xFC81808C
#define DMAC_SARB6 0xFC818120
#define DMAC_DARB6 0xFC818124
#define DMAC_TCRB6 0xFC818128
#define DMAC_SARB7 0xFC818130
#define DMAC_DARB7 0xFC818134
#define DMAC_TCRB7 0xFC818138
#define DMAC_SARB8 0xFC818140
#define DMAC_DARB8 0xFC818144
#define DMAC_TCRB8 0xFC818148
#define DMAC_SARB9 0xFC818150
#define DMAC_DARB9 0xFC818154
#define DMAC_TCRB9 0xFC818158
/* Clock Pulse Generator */
#define FRQCR 0xFFC80000
#define PLLCR 0xFFC80024
#define MSTPCR 0xFFC80030
/* Watchdog Timer and Reset */
#define WTCNT WDTCNT
#define WDTST 0xFFCC0000
#define WDTCSR 0xFFCC0004
#define WDTBST 0xFFCC0008
#define WDTCNT 0xFFCC0010
#define WDTBCNT 0xFFCC0018
/* System Control */
#define MSTPCR 0xFFC80030
/* Timer Unit */
#define TMU_BASE 0xFFD80000
/* Timer/Counter */
#define CMTCFG 0xFFE30000
#define CMTFRT 0xFFE30004
#define CMTCTL 0xFFE30008
#define CMTIRQS 0xFFE3000C
#define CMTCH0T 0xFFE30010
#define CMTCH0ST 0xFFE30020
#define CMTCH0C 0xFFE30030
#define CMTCH1T 0xFFE30014
#define CMTCH1ST 0xFFE30024
#define CMTCH1C 0xFFE30034
#define CMTCH2T 0xFFE30018
#define CMTCH2C 0xFFE30038
#define CMTCH3T 0xFFE3001C
#define CMTCH3C 0xFFE3003C
/* Realtime Clock */
#define R64CNT 0xFFE80000
#define RSECCNT 0xFFE80004
#define RMINCNT 0xFFE80008
#define RHRCNT 0xFFE8000C
#define RWKCNT 0xFFE80010
#define RDAYCNT 0xFFE80014
#define RMONCNT 0xFFE80018
#define RYRCNT 0xFFE8001C
#define RSECAR 0xFFE80020
#define RMINAR 0xFFE80024
#define RHRAR 0xFFE80028
#define RWKAR 0xFFE8002C
#define RDAYAR 0xFFE80030
#define RMONAR 0xFFE80034
#define RCR1 0xFFE80038
#define RCR2 0xFFE8003C
#define RCR3 0xFFE80050
#define RYRAR 0xFFE80054
/* Serial Communication Interface with FIFO */
#define SCSMR0 0xFFE00000
#define SCIF0_BASE SCSMR0
/* Serial I/O with FIFO */
#define SIMDR 0xFFE20000
#define SISCR 0xFFE20002
#define SITDAR 0xFFE20004
#define SIRDAR 0xFFE20006
#define SICDAR 0xFFE20008
#define SICTR 0xFFE2000C
#define SIFCTR 0xFFE20010
#define SISTR 0xFFE20014
#define SIIER 0xFFE20016
#define SITCR 0xFFE20028
#define SIRCR 0xFFE2002C
#define SPICR 0xFFE20030
/* Serial Protocol Interface */
#define SPCR 0xFFE50000
#define SPSR 0xFFE50004
#define SPSCR 0xFFE50008
#define SPTBR 0xFFE5000C
#define SPRBR 0xFFE50010
/* Multimedia Card Interface */
#define CMDR0 0xFFE60000
#define CMDR1 0xFFE60001
#define CMDR2 0xFFE60002
#define CMDR3 0xFFE60003
#define CMDR4 0xFFE60004
#define CMDR5 0xFFE60005
#define CMDSTRT 0xFFE60006
#define OPCR 0xFFE6000A
#define CSTR 0xFFE6000B
#define INTCR0 0xFFE6000C
#define INTCR1 0xFFE6000D
#define INTSTR0 0xFFE6000E
#define INTSTR1 0xFFE6000F
#define CLKON 0xFFE60010
#define CTOCR 0xFFE60011
#define TBCR 0xFFE60014
#define MODER 0xFFE60016
#define CMDTYR 0xFFE60018
#define RSPTYR 0xFFE60019
#define TBNCR 0xFFE6001A
#define RSPR0 0xFFE60020
#define RSPR1 0xFFE60021
#define RSPR2 0xFFE60022
#define RSPR3 0xFFE60023
#define RSPR4 0xFFE60024
#define RSPR5 0xFFE60025
#define RSPR6 0xFFE60026
#define RSPR7 0xFFE60027
#define RSPR8 0xFFE60028
#define RSPR9 0xFFE60029
#define RSPR10 0xFFE6002A
#define RSPR11 0xFFE6002B
#define RSPR12 0xFFE6002C
#define RSPR13 0xFFE6002D
#define RSPR14 0xFFE6002E
#define RSPR15 0xFFE6002F
#define RSPR16 0xFFE60030
#define RSPRD 0xFFE60031
#define DTOUTR 0xFFE60032
#define DR 0xFFE60040
#define DMACR 0xFFE60044
#define INTCR2 0xFFE60046
#define INTSTR2 0xFFE60048
/* Audio Codec Interface */
#define HACCR 0xFFE40008
#define HACCSAR 0xFFE40020
#define HACCSDR 0xFFE40024
#define HACPCML 0xFFE40028
#define HACPCMR 0xFFE4002C
#define HACTIER 0xFFE40050
#define HACTSR 0xFFE40054
#define HACRIER 0xFFE40058
#define HACRSR 0xFFE4005C
#define HACACR 0xFFE40060
/* Serial Sound Interface */
#define SSICR 0xFFE70000
#define SSISR 0xFFE70004
#define SSITDR 0xFFE70008
#define SSIRDR 0xFFE7000C
/* Flash memory Controller */
#define FLCMNCR 0xFFE90000
#define FLCMDCR 0xFFE90004
#define FLCMCDR 0xFFE90008
#define FLADR 0xFFE9000C
#define FLDATAR 0xFFE90010
#define FLDTCNTR 0xFFE90014
#define FLINTDMACR 0xFFE90018
#define FLBSYTMR 0xFFE9001C
#define FLBSYCNT 0xFFE90020
#define FLTRCR 0xFFE9002C
/* General Purpose I/O */
#define PACR 0xFFEA0000
#define PBCR 0xFFEA0002
#define PCCR 0xFFEA0004
#define PDCR 0xFFEA0006
#define PECR 0xFFEA0008
#define PFCR 0xFFEA000A
#define PGCR 0xFFEA000C
#define PHCR 0xFFEA000E
#define PJCR 0xFFEA0010
#define PKCR 0xFFEA0012
#define PLCR 0xFFEA0014
#define PMCR 0xFFEA0016
#define PADR 0xFFEA0020
#define PBDR 0xFFEA0022
#define PCDR 0xFFEA0024
#define PDDR 0xFFEA0026
#define PEDR 0xFFEA0028
#define PFDR 0xFFEA002A
#define PGDR 0xFFEA002C
#define PHDR 0xFFEA002E
#define PJDR 0xFFEA0030
#define PKDR 0xFFEA0032
#define PLDR 0xFFEA0034
#define PMDR 0xFFEA0036
#define PEPUPR 0xFFEA0048
#define PHPUPR 0xFFEA004E
#define PJPUPR 0xFFEA0050
#define PKPUPR 0xFFEA0052
#define PMPUPR 0xFFEA0056
#define PPUPR1 0xFFEA0060
#define PPUPR2 0xFFEA0062
#define PMSELR 0xFFEA0080
/* User Break Controller */
#define CBR0 0xFF200000
#define CRR0 0xFF200004
#define CAR0 0xFF200008
#define CAMR0 0xFF20000C
#define CBR1 0xFF200020
#define CRR1 0xFF200024
#define CAR1 0xFF200028
#define CAMR1 0xFF20002C
#define CDR1 0xFF200030
#define CDMR1 0xFF200034
#define CETR1 0xFF200038
#define CCMFR 0xFF200600
#define CBCR 0xFF200620
#endif /* _ASM_CPU_SH7780_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/global_data.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2002-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#ifndef __ASM_SH_GLOBALDATA_H_
#define __ASM_SH_GLOBALDATA_H_
/* Architecture-specific global data */
struct arch_global_data {
};
#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13")
#endif /* __ASM_SH_GLOBALDATA_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/io.h
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/*
* linux/include/asm-sh/io.h
*
* Copyright (C) 1996-2000 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Modifications:
* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
* constant addresses and variable addresses.
* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
* specific IO header files.
* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
* 04-Apr-1999 PJB Added check_signature.
* 12-Dec-1999 RMK More cleanups
* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
*/
#ifndef __ASM_SH_IO_H
#define __ASM_SH_IO_H
#ifdef __KERNEL__
#include <linux/types.h>
#include <asm/byteorder.h>
/*
* Generic virtual read/write. Note that we don't support half-word
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code.
*/
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
extern void __raw_readsl(unsigned int addr, void *data, int longlen);
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
#define __raw_writel(v, a) __arch_putl(v, a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
* These are only valid for small values of "off" (< 1<<12)
*/
#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
#define __raw_base_readb(base, off) __arch_base_getb(base, off)
#define __raw_base_readw(base, off) __arch_base_getw(base, off)
#define __raw_base_readl(base, off) __arch_base_getl(base, off)
/*
* IO port access primitives
* -------------------------
*
* The SH doesn't have special IO access instructions; all IO is memory
* mapped. Note that these are defined to perform little endian accesses
* only. Their primary purpose is to access PCI and ISA peripherals.
*
* Note that we prevent GCC re-ordering or caching values in expressions
* by introducing sequence points into the in*() definitions. Note that
* __raw_* do not guarantee this behaviour.
*
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
*/
#define outb(v, p) __raw_writeb(v, p)
#define outw(v, p) __raw_writew(cpu_to_le16(v), p)
#define outl(v, p) __raw_writel(cpu_to_le32(v), p)
#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; })
#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
#define outsb(p, d, l) __raw_writesb(p, d, l)
#define outsw(p, d, l) __raw_writesw(p, d, l)
#define outsl(p, d, l) __raw_writesl(p, d, l)
#define insb(p, d, l) __raw_readsb(p, d, l)
#define insw(p, d, l) __raw_readsw(p, d, l)
#define insl(p, d, l) __raw_readsl(p, d, l)
#define outb_p(val, port) outb((val), (port))
#define outw_p(val, port) outw((val), (port))
#define outl_p(val, port) outl((val), (port))
#define inb_p(port) inb((port))
#define inw_p(port) inw((port))
#define inl_p(port) inl((port))
#define outsb_p(port, from, len) outsb(port, from, len)
#define outsw_p(port, from, len) outsw(port, from, len)
#define outsl_p(port, from, len) outsl(port, from, len)
#define insb_p(port, to, len) insb(port, to, len)
#define insw_p(port, to, len) insw(port, to, len)
#define insl_p(port, to, len) insl(port, to, len)
/* for U-Boot PCI */
#define out_8(port, val) outb(val, port)
#define out_le16(port, val) outw(val, port)
#define out_le32(port, val) outl(val, port)
#define in_8(port) inb(port)
#define in_le16(port) inw(port)
#define in_le32(port) inl(port)
/*
* DMA-consistent mapping functions. These allocate/free a region of
* uncached, unwrite-buffered mapped memory space for use with DMA
* devices. This is the "generic" version. The PCI specific version
* is in pci.h
*/
extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
extern void consistent_sync(void *vaddr, size_t size, int rw);
/*
* String version of IO memory access ops:
*/
extern void _memcpy_fromio(void *, unsigned long, size_t);
extern void _memcpy_toio(unsigned long, const void *, size_t);
extern void _memset_io(unsigned long, int, size_t);
/*
* If this architecture has PCI memory IO, then define the read/write
* macros. These should only be used with the cookie passed from
* ioremap.
*/
#ifdef __mem_pci
#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
#define readw(c)\
({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
#define readl(c)\
({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
#define eth_io_copy_and_sum(s, c, l, b) \
eth_copy_and_sum((s), __mem_pci(c), (l), (b))
static inline int
check_signature(unsigned long io_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#elif !defined(readb)
#define readb(addr) __raw_readb(addr)
#define readw(addr) __raw_readw(addr)
#define readl(addr) __raw_readl(addr)
#define writeb(v, addr) __raw_writeb(v, addr)
#define writew(v, addr) __raw_writew(v, addr)
#define writel(v, addr) __raw_writel(v, addr)
#define check_signature(io, sig, len) (0)
#endif /* __mem_pci */
static inline void sync(void)
{
}
/*
* Clear and set bits in one shot. These macros can be used to clear and
* set multiple bits in a register using a single call. These macros can
* also be used to set a multiple-bit bit pattern using a mask, by
* specifying the mask in the 'clear' parameter and the new bit pattern
* in the 'set' parameter.
*/
#define clrbits(type, addr, clear) \
out_##type((addr), in_##type(addr) & ~(clear))
#define setbits(type, addr, set) \
out_##type((addr), in_##type(addr) | (set))
#define clrsetbits(type, addr, clear, set) \
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
#define setbits_be32(addr, set) setbits(be32, addr, set)
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
#include <asm-generic/io.h>
#endif /* __KERNEL__ */
#endif /* __ASM_SH_IO_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/irqflags.h
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#ifndef __ASM_SH_IRQFLAGS_H
#define __ASM_SH_IRQFLAGS_H
static inline void raw_local_irq_enable(void)
{
unsigned long __dummy0, __dummy1;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"and %1, %0\n\t"
#ifdef CONFIG_CPU_HAS_SR_RB
"stc r6_bank, %1\n\t"
"or %1, %0\n\t"
#endif
"ldc %0, sr\n\t"
: "=&r" (__dummy0), "=r" (__dummy1)
: "1" (~0x000000f0)
: "memory"
);
}
static inline void raw_local_irq_disable(void)
{
unsigned long flags;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"or #0xf0, %0\n\t"
"ldc %0, sr\n\t"
: "=&z" (flags)
: /* no inputs */
: "memory"
);
}
static inline void set_bl_bit(void)
{
unsigned long __dummy0, __dummy1;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"or %2, %0\n\t"
"and %3, %0\n\t"
"ldc %0, sr\n\t"
: "=&r" (__dummy0), "=r" (__dummy1)
: "r" (0x10000000), "r" (0xffffff0f)
: "memory"
);
}
static inline void clear_bl_bit(void)
{
unsigned long __dummy0, __dummy1;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"and %2, %0\n\t"
"ldc %0, sr\n\t"
: "=&r" (__dummy0), "=r" (__dummy1)
: "1" (~0x10000000)
: "memory"
);
}
static inline unsigned long __raw_local_save_flags(void)
{
unsigned long flags;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"and #0xf0, %0\n\t"
: "=&z" (flags)
: /* no inputs */
: "memory"
);
return flags;
}
#define raw_local_save_flags(flags) \
do { (flags) = __raw_local_save_flags(); } while (0)
static inline int raw_irqs_disabled_flags(unsigned long flags)
{
return (flags != 0);
}
static inline int raw_irqs_disabled(void)
{
unsigned long flags = __raw_local_save_flags();
return raw_irqs_disabled_flags(flags);
}
static inline unsigned long __raw_local_irq_save(void)
{
unsigned long flags, __dummy;
__asm__ __volatile__ (
"stc sr, %1\n\t"
"mov %1, %0\n\t"
"or #0xf0, %0\n\t"
"ldc %0, sr\n\t"
"mov %1, %0\n\t"
"and #0xf0, %0\n\t"
: "=&z" (flags), "=&r" (__dummy)
: /* no inputs */
: "memory"
);
return flags;
}
#define raw_local_irq_save(flags) \
do { (flags) = __raw_local_irq_save(); } while (0)
#define local_irq_save raw_local_irq_save
static inline void raw_local_irq_restore(unsigned long flags)
{
if ((flags & 0xf0) != 0xf0)
raw_local_irq_enable();
}
#define local_irq_restore raw_local_irq_restore
#endif /* __ASM_SH_IRQFLAGS_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/linkage.h
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source/bootloader/u-boot-2020.01/arch/sh/include/asm/macro.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#ifndef __MACRO_H__
#define __MACRO_H__
#ifdef __ASSEMBLY__
.macro write32, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.l r0, @r1
.endm
.macro write16, addr, data
mov.l \addr ,r1
mov.w \data ,r0
mov.w r0, @r1
.endm
.macro write8, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.b r0, @r1
.endm
.macro wait_timer, time
mov.l \time ,r3
1:
nop
tst r3, r3
bf/s 1b
dt r3
.endm
#endif /* __ASSEMBLY__ */
#endif /* __MACRO_H__ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/mmc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Renesas SuperH MMCIF driver.
*
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2012 Renesas Solutions Corp.
*
*/
#ifndef _SH_MMC_H_
#define _SH_MMC_H_
int mmcif_mmc_init(void);
#endif /* _SH_MMC_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/pci.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* SH4 PCI Controller (PCIC) for U-Boot.
* (C) Dustin McIntire (dustin@sensoria.com)
* (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* u-boot/include/asm-sh/pci.h
*/
#ifndef _ASM_PCI_H_
#define _ASM_PCI_H_
#include <pci.h>
#if defined(CONFIG_SH7751_PCI)
int pci_sh7751_init(struct pci_controller *hose);
#elif defined(CONFIG_SH7780_PCI)
int pci_sh7780_init(struct pci_controller *hose);
#else
#error "Not support PCI."
#endif
int pci_sh4_init(struct pci_controller *hose);
/* PCI dword read for sh4 */
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 *value);
/* PCI dword write for sh4 */
int pci_sh4_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value);
#endif /* _ASM_PCI_H_ */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/posix_types.h
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#ifndef __ASM_SH_POSIX_TYPES_H
#define __ASM_SH_POSIX_TYPES_H
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
typedef unsigned short __kernel_dev_t;
typedef unsigned long __kernel_ino_t;
typedef unsigned short __kernel_mode_t;
typedef unsigned short __kernel_nlink_t;
typedef long __kernel_off_t;
typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
typedef int __kernel_timer_t;
typedef int __kernel_clockid_t;
typedef int __kernel_daddr_t;
typedef char * __kernel_caddr_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
typedef unsigned int __kernel_gid32_t;
typedef unsigned short __kernel_old_uid_t;
typedef unsigned short __kernel_old_gid_t;
typedef unsigned short __kernel_old_dev_t;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
int __val[2];
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
#undef __FD_SET
static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
{
unsigned long __tmp = __fd / __NFDBITS;
unsigned long __rem = __fd % __NFDBITS;
__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
}
#undef __FD_CLR
static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
{
unsigned long __tmp = __fd / __NFDBITS;
unsigned long __rem = __fd % __NFDBITS;
__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
}
#undef __FD_ISSET
static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
{
unsigned long __tmp = __fd / __NFDBITS;
unsigned long __rem = __fd % __NFDBITS;
return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
}
/*
* This will unroll the loop for the normal constant case (8 ints,
* for a 256-bit fd_set)
*/
#undef __FD_ZERO
static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
{
unsigned long *__tmp = __p->fds_bits;
int __i;
if (__builtin_constant_p(__FDSET_LONGS)) {
switch (__FDSET_LONGS) {
case 16:
__tmp[ 0] = 0; __tmp[ 1] = 0;
__tmp[ 2] = 0; __tmp[ 3] = 0;
__tmp[ 4] = 0; __tmp[ 5] = 0;
__tmp[ 6] = 0; __tmp[ 7] = 0;
__tmp[ 8] = 0; __tmp[ 9] = 0;
__tmp[10] = 0; __tmp[11] = 0;
__tmp[12] = 0; __tmp[13] = 0;
__tmp[14] = 0; __tmp[15] = 0;
return;
case 8:
__tmp[ 0] = 0; __tmp[ 1] = 0;
__tmp[ 2] = 0; __tmp[ 3] = 0;
__tmp[ 4] = 0; __tmp[ 5] = 0;
__tmp[ 6] = 0; __tmp[ 7] = 0;
return;
case 4:
__tmp[ 0] = 0; __tmp[ 1] = 0;
__tmp[ 2] = 0; __tmp[ 3] = 0;
return;
}
}
__i = __FDSET_LONGS;
while (__i) {
__i--;
*__tmp = 0;
__tmp++;
}
}
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
#endif /* __ASM_SH_POSIX_TYPES_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/processor.h
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#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
# include <asm/cpu_sh4.h>
#endif
source/bootloader/u-boot-2020.01/arch/sh/include/asm/ptrace.h
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#ifndef __ASM_SH_PTRACE_H
#define __ASM_SH_PTRACE_H
/*
* Copyright (C) 1999, 2000 Niibe Yutaka
* from linux kernel code.
*/
/*
* GCC defines register number like this:
* -----------------------------
* 0 - 15 are integer registers
* 17 - 22 are control/special registers
* 24 - 39 fp registers
* 40 - 47 xd registers
* 48 - fpscr register
* -----------------------------
*
* We follows above, except:
* 16 --- program counter (PC)
* 22 --- syscall #
* 23 --- floating point communication register
*/
#define REG_REG0 0
#define REG_REG15 15
#define REG_PC 16
#define REG_PR 17
#define REG_SR 18
#define REG_GBR 19
#define REG_MACH 20
#define REG_MACL 21
#define REG_SYSCALL 22
#define REG_FPREG0 23
#define REG_FPREG15 38
#define REG_XFREG0 39
#define REG_XFREG15 54
#define REG_FPSCR 55
#define REG_FPUL 56
/* options set using PTRACE_SETOPTIONS */
#define PTRACE_O_TRACESYSGOOD 0x00000001
/*
* This struct defines the way the registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_regs {
unsigned long regs[16];
unsigned long pc;
unsigned long pr;
unsigned long sr;
unsigned long gbr;
unsigned long mach;
unsigned long macl;
long tra;
};
/*
* This struct defines the way the DSP registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_dspregs {
unsigned long a1;
unsigned long a0g;
unsigned long a1g;
unsigned long m0;
unsigned long m1;
unsigned long a0;
unsigned long x0;
unsigned long x1;
unsigned long y0;
unsigned long y1;
unsigned long dsr;
unsigned long rs;
unsigned long re;
unsigned long mod;
};
#define PTRACE_GETDSPREGS 55
#define PTRACE_SETDSPREGS 56
#ifdef __KERNEL__
#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
#define instruction_pointer(regs) ((regs)->pc)
extern void show_regs(struct pt_regs *);
#ifdef CONFIG_SH_DSP
#define task_pt_regs(task) \
((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
- sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
#else
#define task_pt_regs(task) \
((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
- sizeof(unsigned long)) - 1)
#endif
static inline unsigned long profile_pc(struct pt_regs *regs)
{
unsigned long pc = instruction_pointer(regs);
if (pc >= 0xa0000000UL && pc < 0xc0000000UL)
pc -= 0x20000000;
return pc;
}
#endif
#endif /* __ASM_SH_PTRACE_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/sections.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2012 The Chromium OS Authors.
*/
#ifndef __ASM_SH_SECTIONS_H
#define __ASM_SH_SECTIONS_H
#include <asm-generic/sections.h>
#endif
source/bootloader/u-boot-2020.01/arch/sh/include/asm/string.h
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#ifndef __ASM_SH_STRING_H
#define __ASM_SH_STRING_H
/*
* Copyright (C) 1999 Niibe Yutaka
* But consider these trivial functions to be public domain.
*
* from linux kernel code.
*/
#ifdef __KERNEL__ /* only set these up for kernel code */
#define __HAVE_ARCH_STRCPY
static inline char *strcpy(char *__dest, const char *__src)
{
register char *__xdest = __dest;
unsigned long __dummy;
__asm__ __volatile__("1:\n\t"
"mov.b @%1+, %2\n\t"
"mov.b %2, @%0\n\t"
"cmp/eq #0, %2\n\t"
"bf/s 1b\n\t"
" add #1, %0\n\t"
: "=r" (__dest), "=r" (__src), "=&z" (__dummy)
: "0" (__dest), "1" (__src)
: "memory", "t");
return __xdest;
}
#define __HAVE_ARCH_STRNCPY
static inline char *strncpy(char *__dest, const char *__src, size_t __n)
{
register char *__xdest = __dest;
unsigned long __dummy;
if (__n == 0)
return __xdest;
__asm__ __volatile__(
"1:\n"
"mov.b @%1+, %2\n\t"
"mov.b %2, @%0\n\t"
"cmp/eq #0, %2\n\t"
"bt/s 2f\n\t"
" cmp/eq %5,%1\n\t"
"bf/s 1b\n\t"
" add #1, %0\n"
"2:"
: "=r" (__dest), "=r" (__src), "=&z" (__dummy)
: "0" (__dest), "1" (__src), "r" (__src+__n)
: "memory", "t");
return __xdest;
}
#define __HAVE_ARCH_STRCMP
static inline int strcmp(const char *__cs, const char *__ct)
{
register int __res;
unsigned long __dummy;
__asm__ __volatile__(
"mov.b @%1+, %3\n"
"1:\n\t"
"mov.b @%0+, %2\n\t"
"cmp/eq #0, %3\n\t"
"bt 2f\n\t"
"cmp/eq %2, %3\n\t"
"bt/s 1b\n\t"
" mov.b @%1+, %3\n\t"
"add #-2, %1\n\t"
"mov.b @%1, %3\n\t"
"sub %3, %2\n"
"2:"
: "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
: "0" (__cs), "1" (__ct)
: "t");
return __res;
}
#undef __HAVE_ARCH_STRNCMP
extern int strncmp(const char *__cs, const char *__ct, size_t __n);
#undef __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);
#undef __HAVE_ARCH_MEMCPY
extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
#undef __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
#undef __HAVE_ARCH_MEMCHR
extern void *memchr(const void *__s, int __c, size_t __n);
#undef __HAVE_ARCH_STRLEN
extern size_t strlen(const char *);
/* arch/sh/lib/strcasecmp.c */
extern int strcasecmp(const char *, const char *);
#else /* KERNEL */
/*
* let user libraries deal with these,
* IMHO the kernel has no place defining these functions for user apps
*/
#define __HAVE_ARCH_STRCPY 1
#define __HAVE_ARCH_STRNCPY 1
#define __HAVE_ARCH_STRCAT 1
#define __HAVE_ARCH_STRNCAT 1
#define __HAVE_ARCH_STRCMP 1
#define __HAVE_ARCH_STRNCMP 1
#define __HAVE_ARCH_STRNICMP 1
#define __HAVE_ARCH_STRCHR 1
#define __HAVE_ARCH_STRRCHR 1
#define __HAVE_ARCH_STRSTR 1
#define __HAVE_ARCH_STRLEN 1
#define __HAVE_ARCH_STRNLEN 1
#define __HAVE_ARCH_MEMSET 1
#define __HAVE_ARCH_MEMCPY 1
#define __HAVE_ARCH_MEMMOVE 1
#define __HAVE_ARCH_MEMSCAN 1
#define __HAVE_ARCH_MEMCMP 1
#define __HAVE_ARCH_MEMCHR 1
#define __HAVE_ARCH_STRTOK 1
#endif /* KERNEL */
#endif /* __ASM_SH_STRING_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/system.h
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#ifndef __ASM_SH_SYSTEM_H
#define __ASM_SH_SYSTEM_H
/*
* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
* Copyright (C) 2002 Paul Mundt
*
* from linux kernel code.
*/
#include <asm/irqflags.h>
#include <asm/types.h>
/*
* switch_to() should switch tasks to task nr n, first
*/
#define switch_to(prev, next, last) do { \
struct task_struct *__last; \
register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
__asm__ __volatile__ (".balign 4\n\t" \
"stc.l gbr, @-r15\n\t" \
"sts.l pr, @-r15\n\t" \
"mov.l r8, @-r15\n\t" \
"mov.l r9, @-r15\n\t" \
"mov.l r10, @-r15\n\t" \
"mov.l r11, @-r15\n\t" \
"mov.l r12, @-r15\n\t" \
"mov.l r13, @-r15\n\t" \
"mov.l r14, @-r15\n\t" \
"mov.l r15, @r1 ! save SP\n\t" \
"mov.l @r6, r15 ! change to new stack\n\t" \
"mova 1f, %0\n\t" \
"mov.l %0, @r2 ! save PC\n\t" \
"mov.l 2f, %0\n\t" \
"jmp @%0 ! call __switch_to\n\t" \
" lds r7, pr ! with return to new PC\n\t" \
".balign 4\n" \
"2:\n\t" \
".long __switch_to\n" \
"1:\n\t" \
"mov.l @r15+, r14\n\t" \
"mov.l @r15+, r13\n\t" \
"mov.l @r15+, r12\n\t" \
"mov.l @r15+, r11\n\t" \
"mov.l @r15+, r10\n\t" \
"mov.l @r15+, r9\n\t" \
"mov.l @r15+, r8\n\t" \
"lds.l @r15+, pr\n\t" \
"ldc.l @r15+, gbr\n\t" \
: "=z" (__last) \
: "r" (__ts1), "r" (__ts2), "r" (__ts4), \
"r" (__ts5), "r" (__ts6), "r" (__ts7) \
: "r3", "t"); \
last = __last; \
} while (0)
/*
* On SMP systems, when the scheduler does migration-cost autodetection,
* it needs a way to flush as much of the CPU's caches as possible.
*
* TODO: fill this in!
*/
static inline void sched_cacheflush(void)
{
}
#ifdef CONFIG_CPU_SH4A
#define __icbi() \
{ \
unsigned long __addr; \
__addr = 0xa8000000; \
__asm__ __volatile__( \
"icbi %0\n\t" \
: /* no output */ \
: "m" (__m(__addr))); \
}
#endif
static inline unsigned long tas(volatile int *m)
{
unsigned long retval;
__asm__ __volatile__ ("tas.b @%1\n\t"
"movt %0"
: "=r" (retval): "r" (m): "t", "memory");
return retval;
}
/*
* A brief note on ctrl_barrier(), the control register write barrier.
*
* Legacy SH cores typically require a sequence of 8 nops after
* modification of a control register in order for the changes to take
* effect. On newer cores (like the sh4a and sh5) this is accomplished
* with icbi.
*
* Also note that on sh4a in the icbi case we can forego a synco for the
* write barrier, as it's not necessary for control registers.
*
* Historically we have only done this type of barrier for the MMUCR, but
* it's also necessary for the CCR, so we make it generic here instead.
*/
#ifdef CONFIG_CPU_SH4A
#define mb() __asm__ __volatile__ ("synco": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("synco": : :"memory")
#define ctrl_barrier() __icbi()
#define read_barrier_depends() do { } while(0)
#else
#define mb() __asm__ __volatile__ ("": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("": : :"memory")
#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
#define read_barrier_depends() do { } while(0)
#endif
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() do { } while(0)
#endif
#define set_mb(var, value) do { xchg(&var, value); } while (0)
/*
* Jump to P2 area.
* When handling TLB or caches, we need to do it from P2 area.
*/
#define jump_to_P2() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"or %1, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy) \
: "r" (0x20000000)); \
} while (0)
/*
* Back to P1 area.
*/
#define back_to_P1() \
do { \
unsigned long __dummy; \
ctrl_barrier(); \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy)); \
} while (0)
static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
{
unsigned long flags, retval;
local_irq_save(flags);
retval = *m;
*m = val;
local_irq_restore(flags);
return retval;
}
static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
{
unsigned long flags, retval;
local_irq_save(flags);
retval = *m;
*m = val & 0xff;
local_irq_restore(flags);
return retval;
}
extern void __xchg_called_with_bad_pointer(void);
#define __xchg(ptr, x, size) \
({ \
unsigned long __xchg__res; \
volatile void *__xchg_ptr = (ptr); \
switch (size) { \
case 4: \
__xchg__res = xchg_u32(__xchg_ptr, x); \
break; \
case 1: \
__xchg__res = xchg_u8(__xchg_ptr, x); \
break; \
default: \
__xchg_called_with_bad_pointer(); \
__xchg__res = x; \
break; \
} \
\
__xchg__res; \
})
#define xchg(ptr,x) \
((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
unsigned long new)
{
__u32 retval;
unsigned long flags;
local_irq_save(flags);
retval = *m;
if (retval == old)
*m = new;
local_irq_restore(flags); /* implies memory barrier */
return retval;
}
/* This function doesn't exist, so you'll get a linker error
* if something tries to do an invalid cmpxchg(). */
extern void __cmpxchg_called_with_bad_pointer(void);
#define __HAVE_ARCH_CMPXCHG 1
static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
unsigned long new, int size)
{
switch (size) {
case 4:
return __cmpxchg_u32(ptr, old, new);
}
__cmpxchg_called_with_bad_pointer();
return old;
}
#define cmpxchg(ptr,o,n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
(unsigned long)_n_, sizeof(*(ptr))); \
})
extern void *set_exception_table_vec(unsigned int vec, void *handler);
static inline void *set_exception_table_evt(unsigned int evt, void *handler)
{
return set_exception_table_vec(evt >> 5, handler);
}
/* XXX
* disable hlt during certain critical i/o operations
*/
#define HAVE_DISABLE_HLT
void disable_hlt(void);
void enable_hlt(void);
#define arch_align_stack(x) (x)
static inline void trigger_address_error(void)
{
set_bl_bit();
__asm__ __volatile__ (
"mov.l @%1, %0"
:
: "r" (0x10000000), "r" (0x80000001)
);
}
#endif
source/bootloader/u-boot-2020.01/arch/sh/include/asm/types.h
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#ifndef __ASM_SH_TYPES_H
#define __ASM_SH_TYPES_H
#include <asm-generic/int-ll64.h>
#ifndef __ASSEMBLY__
typedef unsigned short umode_t;
#endif /* __ASSEMBLY__ */
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
#ifdef __KERNEL__
#define BITS_PER_LONG 32
#ifndef __ASSEMBLY__
/* Dma addresses are 32-bits wide. */
typedef u32 dma_addr_t;
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_SH_TYPES_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/u-boot.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
********************************************************************
* NOTE: This header file defines an interface to U-Boot. Including
* this (unmodified) header file in another file is considered normal
* use of U-Boot, and does *not* fall under the heading of "derived
* work".
********************************************************************
*/
#ifndef __ASM_SH_U_BOOT_H_
#define __ASM_SH_U_BOOT_H_
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_SH
#endif
source/bootloader/u-boot-2020.01/arch/sh/include/asm/unaligned-sh4a.h
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#ifndef __ASM_SH_UNALIGNED_SH4A_H
#define __ASM_SH_UNALIGNED_SH4A_H
/*
* SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
* Support for 64-bit accesses are done through shifting and masking
* relative to the endianness. Unaligned stores are not supported by the
* instruction encoding, so these continue to use the packed
* struct.
*
* The same note as with the movli.l/movco.l pair applies here, as long
* as the load is gauranteed to be inlined, nothing else will hook in to
* r0 and we get the return value for free.
*
* NOTE: Due to the fact we require r0 encoding, care should be taken to
* avoid mixing these heavily with other r0 consumers, such as the atomic
* ops. Failure to adhere to this can result in the compiler running out
* of spill registers and blowing up when building at low optimization
* levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777.
*/
#include <linux/types.h>
#include <asm/byteorder.h>
static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
{
unsigned long unaligned;
__asm__ __volatile__ (
"movua.l @%1, %0\n\t"
: "=z" (unaligned)
: "r" (p)
);
return unaligned;
}
struct __una_u16 { u16 x __attribute__((packed)); };
struct __una_u32 { u32 x __attribute__((packed)); };
struct __una_u64 { u64 x __attribute__((packed)); };
static inline u16 __get_unaligned_cpu16(const u8 *p)
{
#ifdef __LITTLE_ENDIAN
return p[0] | p[1] << 8;
#else
return p[0] << 8 | p[1];
#endif
}
/*
* Even though movua.l supports auto-increment on the read side, it can
* only store to r0 due to instruction encoding constraints, so just let
* the compiler sort it out on its own.
*/
static inline u64 __get_unaligned_cpu64(const u8 *p)
{
#ifdef __LITTLE_ENDIAN
return (u64)__get_unaligned_cpu32(p + 4) << 32 |
__get_unaligned_cpu32(p);
#else
return (u64)__get_unaligned_cpu32(p) << 32 |
__get_unaligned_cpu32(p + 4);
#endif
}
static inline u16 get_unaligned_le16(const void *p)
{
return le16_to_cpu(__get_unaligned_cpu16(p));
}
static inline u32 get_unaligned_le32(const void *p)
{
return le32_to_cpu(__get_unaligned_cpu32(p));
}
static inline u64 get_unaligned_le64(const void *p)
{
return le64_to_cpu(__get_unaligned_cpu64(p));
}
static inline u16 get_unaligned_be16(const void *p)
{
return be16_to_cpu(__get_unaligned_cpu16(p));
}
static inline u32 get_unaligned_be32(const void *p)
{
return be32_to_cpu(__get_unaligned_cpu32(p));
}
static inline u64 get_unaligned_be64(const void *p)
{
return be64_to_cpu(__get_unaligned_cpu64(p));
}
static inline void __put_le16_noalign(u8 *p, u16 val)
{
*p++ = val;
*p++ = val >> 8;
}
static inline void __put_le32_noalign(u8 *p, u32 val)
{
__put_le16_noalign(p, val);
__put_le16_noalign(p + 2, val >> 16);
}
static inline void __put_le64_noalign(u8 *p, u64 val)
{
__put_le32_noalign(p, val);
__put_le32_noalign(p + 4, val >> 32);
}
static inline void __put_be16_noalign(u8 *p, u16 val)
{
*p++ = val >> 8;
*p++ = val;
}
static inline void __put_be32_noalign(u8 *p, u32 val)
{
__put_be16_noalign(p, val >> 16);
__put_be16_noalign(p + 2, val);
}
static inline void __put_be64_noalign(u8 *p, u64 val)
{
__put_be32_noalign(p, val >> 32);
__put_be32_noalign(p + 4, val);
}
static inline void put_unaligned_le16(u16 val, void *p)
{
#ifdef __LITTLE_ENDIAN
((struct __una_u16 *)p)->x = val;
#else
__put_le16_noalign(p, val);
#endif
}
static inline void put_unaligned_le32(u32 val, void *p)
{
#ifdef __LITTLE_ENDIAN
((struct __una_u32 *)p)->x = val;
#else
__put_le32_noalign(p, val);
#endif
}
static inline void put_unaligned_le64(u64 val, void *p)
{
#ifdef __LITTLE_ENDIAN
((struct __una_u64 *)p)->x = val;
#else
__put_le64_noalign(p, val);
#endif
}
static inline void put_unaligned_be16(u16 val, void *p)
{
#ifdef __BIG_ENDIAN
((struct __una_u16 *)p)->x = val;
#else
__put_be16_noalign(p, val);
#endif
}
static inline void put_unaligned_be32(u32 val, void *p)
{
#ifdef __BIG_ENDIAN
((struct __una_u32 *)p)->x = val;
#else
__put_be32_noalign(p, val);
#endif
}
static inline void put_unaligned_be64(u64 val, void *p)
{
#ifdef __BIG_ENDIAN
((struct __una_u64 *)p)->x = val;
#else
__put_be64_noalign(p, val);
#endif
}
/*
* Cause a link-time error if we try an unaligned access other than
* 1,2,4 or 8 bytes long
*/
extern void __bad_unaligned_access_size(void);
#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \
__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \
__bad_unaligned_access_size())))); \
}))
#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \
__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \
__bad_unaligned_access_size())))); \
}))
#define __put_unaligned_le(val, ptr) ({ \
void *__gu_p = (ptr); \
switch (sizeof(*(ptr))) { \
case 1: \
*(u8 *)__gu_p = (__force u8)(val); \
break; \
case 2: \
put_unaligned_le16((__force u16)(val), __gu_p); \
break; \
case 4: \
put_unaligned_le32((__force u32)(val), __gu_p); \
break; \
case 8: \
put_unaligned_le64((__force u64)(val), __gu_p); \
break; \
default: \
__bad_unaligned_access_size(); \
break; \
} \
(void)0; })
#define __put_unaligned_be(val, ptr) ({ \
void *__gu_p = (ptr); \
switch (sizeof(*(ptr))) { \
case 1: \
*(u8 *)__gu_p = (__force u8)(val); \
break; \
case 2: \
put_unaligned_be16((__force u16)(val), __gu_p); \
break; \
case 4: \
put_unaligned_be32((__force u32)(val), __gu_p); \
break; \
case 8: \
put_unaligned_be64((__force u64)(val), __gu_p); \
break; \
default: \
__bad_unaligned_access_size(); \
break; \
} \
(void)0; })
#ifdef __LITTLE_ENDIAN
# define get_unaligned __get_unaligned_le
# define put_unaligned __put_unaligned_le
#else
# define get_unaligned __get_unaligned_be
# define put_unaligned __put_unaligned_be
#endif
#endif /* __ASM_SH_UNALIGNED_SH4A_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/unaligned.h
+25
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@@ -0,0 +1,25 @@
#ifndef _ASM_SH_UNALIGNED_H
#define _ASM_SH_UNALIGNED_H
/* Copy from linux-kernel. */
#ifdef CONFIG_CPU_SH4A
/* SH-4A can handle unaligned loads in a relatively neutered fashion. */
#include <asm/unaligned-sh4a.h>
#else
/* Otherwise, SH can't handle unaligned accesses. */
#include <linux/compiler.h>
#if defined(__BIG_ENDIAN__)
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
#elif defined(__LITTLE_ENDIAN__)
#define get_unaligned __get_unaligned_le
#define put_unaligned __put_unaligned_le
#endif
#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/generic.h>
#endif
#endif /* _ASM_SH_UNALIGNED_H */
source/bootloader/u-boot-2020.01/arch/sh/include/asm/zimage.h
+24
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@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Renesas Solutions Corp.
* Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*/
#ifndef _ASM_ZIMAGE_H_
#define _ASM_ZIMAGE_H_
#define MOUNT_ROOT_RDONLY 0x000
#define RAMDISK_FLAGS 0x004
#define ORIG_ROOT_DEV 0x008
#define LOADER_TYPE 0x00c
#define INITRD_START 0x010
#define INITRD_SIZE 0x014
#define COMMAND_LINE 0x100
#define RD_PROMPT (1<<15)
#define RD_DOLOAD (1<<14)
#define CMD_ARG_RD_PROMPT "prompt_ramdisk="
#define CMD_ARG_RD_DOLOAD "load_ramdisk="
#endif