GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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config INTEL_BRASWELL
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bool
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select HAVE_FSP
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select ARCH_MISC_INIT
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select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
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imply HAVE_INTEL_ME
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imply HAVE_VBT
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imply ENABLE_MRC_CACHE
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imply AHCI_PCI
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imply ICH_SPI
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imply MMC
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imply MMC_PCI
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imply MMC_SDHCI
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imply MMC_SDHCI_SDMA
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imply SCSI
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imply SCSI_AHCI
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imply SPI_FLASH
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imply SYS_NS16550
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imply USB
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imply USB_XHCI_HCD
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imply VIDEO_FSP
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if INTEL_BRASWELL
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config FSP_ADDR
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hex
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default 0xfff20000
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endif
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@@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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obj-y += braswell.o early_uart.o fsp_configs.o
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <asm/mrccache.h>
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#include <asm/post.h>
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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return x86_cpu_init_f();
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}
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int arch_misc_init(void)
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{
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#ifdef CONFIG_ENABLE_MRC_CACHE
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/*
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* We intend not to check any return value here, as even MRC cache
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* is not saved successfully, it is not a severe error that will
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* prevent system from continuing to boot.
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*/
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mrccache_save();
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#endif
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return 0;
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}
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@@ -0,0 +1,81 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
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(((segbus) & 0xfff) << 20) | \
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(((dev) & 0x1f) << 15) | \
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(((fn) & 0x07) << 12))
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/* Platform Controller Unit */
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#define LPC_DEV 0x1f
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#define LPC_FUNC 0
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/* Enable UART */
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#define UART_CONT 0x80
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/* UART PAD definitions */
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#define UART_RXD_COMMUITY 1
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#define UART_TXD_COMMUITY 1
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#define UART_RXD_FAMILY 4
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#define UART_TXD_FAMILY 4
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#define UART_RXD_PAD 2
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#define UART_TXD_PAD 7
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#define UART_RXD_FUNC 3
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#define UART_TXD_FUNC 3
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/* IO Memory */
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#define IO_BASE_ADDRESS 0xfed80000
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static inline uint32_t gpio_pconf0(int community, int family, int pad)
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{
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return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +
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family * 0x400 + pad * 8;
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}
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static void gpio_select_func(int community, int family, int pad, int func)
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{
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uint32_t pconf0_addr = gpio_pconf0(community, family, pad);
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clrsetbits_le32(pconf0_addr, 0xf << 16, func << 16);
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}
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static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
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{
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unsigned long addr;
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addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
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writel(value, addr);
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}
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/* This can be called after memory-mapped PCI is working */
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int setup_internal_uart(int enable)
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{
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/* Enable or disable the legacy UART hardware */
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x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
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enable);
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/* All done for the disable part, so just return */
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if (!enable)
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return 0;
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/*
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* Set up the pads to the UART function. This allows the signals to
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* leave the chip
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*/
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gpio_select_func(UART_RXD_COMMUITY, UART_RXD_FAMILY,
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UART_RXD_PAD, UART_RXD_FUNC);
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gpio_select_func(UART_TXD_COMMUITY, UART_TXD_FAMILY,
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UART_TXD_PAD, UART_TXD_FUNC);
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return 0;
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}
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void board_debug_uart_init(void)
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{
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setup_internal_uart(1);
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}
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@@ -0,0 +1,163 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/fsp1/fsp_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* Override the FSP's Azalia configuration data
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*
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* @azalia: pointer to be updated to point to a ROM address where Azalia
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* configuration data is stored
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*/
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__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
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{
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*azalia = NULL;
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}
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/**
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* Override the FSP's GPIO configuration data
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*
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* @family: pointer to be updated to point to a ROM address where GPIO
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* family configuration data is stored
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* @pad: pointer to be updated to point to a ROM address where GPIO
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* pad configuration data is stored
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*/
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__weak void update_fsp_gpio_configs(struct gpio_family **family,
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struct gpio_pad **pad)
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{
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*family = NULL;
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*pad = NULL;
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}
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/**
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* Override the FSP's configuration data.
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* If the device tree does not specify an integer setting, use the default
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* provided in Intel's Braswell release FSP/BraswellFsp.bsf file.
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*/
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void fsp_update_configs(struct fsp_config_data *config,
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struct fspinit_rtbuf *rt_buf)
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{
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struct upd_region *fsp_upd = &config->fsp_upd;
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struct memory_upd *memory_upd = &fsp_upd->memory_upd;
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struct silicon_upd *silicon_upd = &fsp_upd->silicon_upd;
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const void *blob = gd->fdt_blob;
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int node;
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/* Initialize runtime buffer for fsp_init() */
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rt_buf->common.stack_top = config->common.stack_top - 32;
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rt_buf->common.boot_mode = config->common.boot_mode;
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rt_buf->common.upd_data = &config->fsp_upd;
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node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp");
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if (node < 0) {
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debug("%s: Cannot find FSP node\n", __func__);
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return;
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}
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node = fdt_node_offset_by_compatible(blob, node,
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"intel,braswell-fsp-memory");
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if (node < 0) {
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debug("%s: Cannot find FSP memory node\n", __func__);
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return;
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}
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/* Override memory UPD contents */
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memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
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"fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB);
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memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
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"fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB);
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memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
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"fsp,mrc-init-spd-addr1", 0xa0);
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memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
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"fsp,mrc-init-spd-addr2", 0xa2);
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memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
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"fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB);
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memory_upd->aperture_size = fdtdec_get_int(blob, node,
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"fsp,aperture-size", APERTURE_SIZE_256MB);
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memory_upd->gtt_size = fdtdec_get_int(blob, node,
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"fsp,gtt-size", GTT_SIZE_1MB);
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memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node,
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"fsp,legacy-seg-decode");
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memory_upd->enable_dvfs = fdtdec_get_bool(blob, node,
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"fsp,enable-dvfs");
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memory_upd->memory_type = fdtdec_get_int(blob, node,
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"fsp,memory-type", DRAM_TYPE_DDR3);
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memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node,
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"fsp,enable-ca-mirror");
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node = fdt_node_offset_by_compatible(blob, node,
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"intel,braswell-fsp-silicon");
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if (node < 0) {
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debug("%s: Cannot find FSP silicon node\n", __func__);
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return;
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}
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/* Override silicon UPD contents */
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silicon_upd->sdcard_mode = fdtdec_get_int(blob, node,
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"fsp,sdcard-mode", SDCARD_MODE_PCI);
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silicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
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"fsp,enable-hsuart0");
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silicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
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"fsp,enable-hsuart1");
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silicon_upd->enable_azalia = fdtdec_get_bool(blob, node,
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"fsp,enable-azalia");
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if (silicon_upd->enable_azalia)
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update_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr);
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silicon_upd->enable_sata = fdtdec_get_bool(blob, node,
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"fsp,enable-sata");
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silicon_upd->enable_xhci = fdtdec_get_bool(blob, node,
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"fsp,enable-xhci");
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silicon_upd->lpe_mode = fdtdec_get_int(blob, node,
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"fsp,lpe-mode", LPE_MODE_PCI);
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silicon_upd->enable_dma0 = fdtdec_get_bool(blob, node,
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"fsp,enable-dma0");
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silicon_upd->enable_dma1 = fdtdec_get_bool(blob, node,
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"fsp,enable-dma1");
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silicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c0");
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silicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c1");
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silicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c2");
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silicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c3");
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silicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c4");
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silicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c5");
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silicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node,
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"fsp,enable-i2c6");
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#ifdef CONFIG_HAVE_VBT
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silicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR;
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#endif
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update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr,
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&silicon_upd->gpio_pad_ptr);
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/*
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* For Braswell B0 stepping, disable_punit_pwr_config must be set to 1
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* otherwise it just hangs in fsp_init().
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*/
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if (gd->arch.x86_mask == 2)
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silicon_upd->disable_punit_pwr_config = 1;
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silicon_upd->emmc_mode = fdtdec_get_int(blob, node,
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"fsp,emmc-mode", EMMC_MODE_PCI);
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silicon_upd->sata_speed = fdtdec_get_int(blob, node,
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"fsp,sata-speed", SATA_SPEED_GEN3);
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silicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node,
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"fsp,pmic-i2c-bus", 0);
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silicon_upd->enable_isp = fdtdec_get_bool(blob, node,
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"fsp,enable-isp");
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silicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node,
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"fsp,isp-pci-dev-config", ISP_PCI_DEV_CONFIG_2);
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silicon_upd->turbo_mode = fdtdec_get_bool(blob, node,
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"fsp,turbo-mode");
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silicon_upd->pnp_settings = fdtdec_get_int(blob, node,
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"fsp,pnp-settings", PNP_SETTING_POWER_AND_PERF);
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silicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node,
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"fsp,sd-detect-chk");
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}
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