GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,9 @@
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#
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# (C) Copyright 2016 Google, Inc
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# Written by Simon Glass <sjg@chromium.org>
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#
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obj-y += call64.o
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obj-y += cpu.o
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obj-y += interrupt.o
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obj-y += setjmp.o
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@@ -0,0 +1,99 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014 Google, Inc
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* Copyright (C) 1991, 1992, 1993 Linus Torvalds
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*
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* Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
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*/
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#include <asm/global_data.h>
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#include <asm/msr-index.h>
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#include <asm/processor-flags.h>
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.code32
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.globl cpu_call64
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cpu_call64:
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/*
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* cpu_call64(ulong pgtable, ulong setup_base, ulong target)
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*
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* eax - pgtable
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* edx - setup_base
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* ecx - target
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*/
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cli
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push %ecx /* arg2 = target */
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push %edx /* arg1 = setup_base */
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mov %eax, %ebx
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/* Load new GDT with the 64bit segments using 32bit descriptor */
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leal gdt, %eax
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movl %eax, gdt+2
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lgdt gdt
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/* Enable PAE mode */
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movl $(X86_CR4_PAE), %eax
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movl %eax, %cr4
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/* Enable the boot page tables */
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leal (%ebx), %eax
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movl %eax, %cr3
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/* Enable Long mode in EFER (Extended Feature Enable Register) */
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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wrmsr
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/* After gdt is loaded */
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xorl %eax, %eax
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lldt %ax
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movl $0x20, %eax
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ltr %ax
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/*
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* Setup for the jump to 64bit mode
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*
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* When the jump is performed we will be in long mode but
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* in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
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* (and in turn EFER.LMA = 1). To jump into 64bit mode we use
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* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
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* We place all of the values on our mini stack so lret can
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* used to perform that far jump. See the gdt below.
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*/
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pop %esi /* setup_base */
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pushl $0x10
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leal lret_target, %eax
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pushl %eax
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/* Enter paged protected Mode, activating Long Mode */
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movl $(X86_CR0_PG | X86_CR0_PE), %eax
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movl %eax, %cr0
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/* Jump from 32bit compatibility mode into 64bit mode. */
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lret
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code64:
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lret_target:
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pop %eax /* target */
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mov %eax, %eax /* Clear bits 63:32 */
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jmp *%eax /* Jump to the 64-bit target */
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.globl call64_stub_size
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call64_stub_size:
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.long . - cpu_call64
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.data
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.align 16
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.globl gdt64
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gdt64:
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gdt:
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.word gdt_end - gdt - 1
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.long gdt /* Fixed up by code above */
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.word 0
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.quad 0x0000000000000000 /* NULL descriptor */
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.quad 0x00af9a000000ffff /* __KERNEL_CS */
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.quad 0x00cf92000000ffff /* __KERNEL_DS */
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.quad 0x0080890000000000 /* TS descriptor */
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.quad 0x0000000000000000 /* TS continued */
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gdt_end:
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@@ -0,0 +1,620 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2008-2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* Part of this file is adapted from coreboot
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* src/arch/x86/lib/cpu.c
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <malloc.h>
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#include <asm/control_regs.h>
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#include <asm/cpu.h>
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#include <asm/mp.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/processor-flags.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Constructor for a conventional segment GDT (or LDT) entry
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* This is a macro so it can be used in initialisers
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*/
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#define GDT_ENTRY(flags, base, limit) \
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((((base) & 0xff000000ULL) << (56-24)) | \
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(((flags) & 0x0000f0ffULL) << 40) | \
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(((limit) & 0x000f0000ULL) << (48-16)) | \
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(((base) & 0x00ffffffULL) << 16) | \
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(((limit) & 0x0000ffffULL)))
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struct gdt_ptr {
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u16 len;
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u32 ptr;
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} __packed;
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struct cpu_device_id {
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unsigned vendor;
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unsigned device;
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};
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struct cpuinfo_x86 {
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uint8_t x86; /* CPU family */
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uint8_t x86_vendor; /* CPU vendor */
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uint8_t x86_model;
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uint8_t x86_mask;
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};
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/*
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* List of cpu vendor strings along with their normalized
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* id values.
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*/
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static const struct {
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int vendor;
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const char *name;
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} x86_vendors[] = {
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{ X86_VENDOR_INTEL, "GenuineIntel", },
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{ X86_VENDOR_CYRIX, "CyrixInstead", },
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{ X86_VENDOR_AMD, "AuthenticAMD", },
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{ X86_VENDOR_UMC, "UMC UMC UMC ", },
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{ X86_VENDOR_NEXGEN, "NexGenDriven", },
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{ X86_VENDOR_CENTAUR, "CentaurHauls", },
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{ X86_VENDOR_RISE, "RiseRiseRise", },
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{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
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{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
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{ X86_VENDOR_NSC, "Geode by NSC", },
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{ X86_VENDOR_SIS, "SiS SiS SiS ", },
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};
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static void load_ds(u32 segment)
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{
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asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
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}
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static void load_es(u32 segment)
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{
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asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
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}
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static void load_fs(u32 segment)
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{
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asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
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}
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static void load_gs(u32 segment)
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{
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asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
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}
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static void load_ss(u32 segment)
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{
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asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
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}
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static void load_gdt(const u64 *boot_gdt, u16 num_entries)
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{
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struct gdt_ptr gdt;
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gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
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gdt.ptr = (ulong)boot_gdt;
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asm volatile("lgdtl %0\n" : : "m" (gdt));
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}
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void arch_setup_gd(gd_t *new_gd)
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{
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u64 *gdt_addr;
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gdt_addr = new_gd->arch.gdt;
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/*
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* CS: code, read/execute, 4 GB, base 0
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*
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* Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
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*/
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gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
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gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
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/* DS: data, read/write, 4 GB, base 0 */
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gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
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/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
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new_gd->arch.gd_addr = new_gd;
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gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
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(ulong)&new_gd->arch.gd_addr, 0xfffff);
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/* 16-bit CS: code, read/execute, 64 kB, base 0 */
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gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
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/* 16-bit DS: data, read/write, 64 kB, base 0 */
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gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
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gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
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gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
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load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
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load_ds(X86_GDT_ENTRY_32BIT_DS);
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load_es(X86_GDT_ENTRY_32BIT_DS);
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load_gs(X86_GDT_ENTRY_32BIT_DS);
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load_ss(X86_GDT_ENTRY_32BIT_DS);
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load_fs(X86_GDT_ENTRY_32BIT_FS);
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}
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#ifdef CONFIG_HAVE_FSP
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/*
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* Setup FSP execution environment GDT
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*
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* Per Intel FSP external architecture specification, before calling any FSP
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* APIs, we need make sure the system is in flat 32-bit mode and both the code
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* and data selectors should have full 4GB access range. Here we reuse the one
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* we used in arch/x86/cpu/start16.S, and reload the segement registers.
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*/
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void setup_fsp_gdt(void)
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{
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load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
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load_ds(X86_GDT_ENTRY_32BIT_DS);
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load_ss(X86_GDT_ENTRY_32BIT_DS);
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load_es(X86_GDT_ENTRY_32BIT_DS);
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load_fs(X86_GDT_ENTRY_32BIT_DS);
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load_gs(X86_GDT_ENTRY_32BIT_DS);
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}
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#endif
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/*
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* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
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* by the fact that they preserve the flags across the division of 5/2.
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* PII and PPro exhibit this behavior too, but they have cpuid available.
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*/
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/*
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* Perform the Cyrix 5/2 test. A Cyrix won't change
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* the flags, while other 486 chips will.
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*/
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static inline int test_cyrix_52div(void)
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{
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unsigned int test;
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__asm__ __volatile__(
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"sahf\n\t" /* clear flags (%eax = 0x0005) */
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"div %b2\n\t" /* divide 5 by 2 */
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"lahf" /* store flags into %ah */
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: "=a" (test)
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: "0" (5), "q" (2)
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: "cc");
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/* AH is 0x02 on Cyrix after the divide.. */
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return (unsigned char) (test >> 8) == 0x02;
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}
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/*
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* Detect a NexGen CPU running without BIOS hypercode new enough
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* to have CPUID. (Thanks to Herbert Oppmann)
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*/
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static int deep_magic_nexgen_probe(void)
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{
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int ret;
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__asm__ __volatile__ (
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" movw $0x5555, %%ax\n"
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" xorw %%dx,%%dx\n"
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" movw $2, %%cx\n"
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" divw %%cx\n"
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" movl $0, %%eax\n"
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" jnz 1f\n"
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" movl $1, %%eax\n"
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"1:\n"
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: "=a" (ret) : : "cx", "dx");
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return ret;
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}
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static bool has_cpuid(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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static bool has_mtrr(void)
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{
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return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
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}
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static int build_vendor_name(char *vendor_name)
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{
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struct cpuid_result result;
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result = cpuid(0x00000000);
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unsigned int *name_as_ints = (unsigned int *)vendor_name;
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name_as_ints[0] = result.ebx;
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name_as_ints[1] = result.edx;
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name_as_ints[2] = result.ecx;
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return result.eax;
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}
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static void identify_cpu(struct cpu_device_id *cpu)
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{
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char vendor_name[16];
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int i;
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vendor_name[0] = '\0'; /* Unset */
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cpu->device = 0; /* fix gcc 4.4.4 warning */
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/* Find the id and vendor_name */
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if (!has_cpuid()) {
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/* Its a 486 if we can modify the AC flag */
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if (flag_is_changeable_p(X86_EFLAGS_AC))
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cpu->device = 0x00000400; /* 486 */
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else
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cpu->device = 0x00000300; /* 386 */
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if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
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memcpy(vendor_name, "CyrixInstead", 13);
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/* If we ever care we can enable cpuid here */
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}
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/* Detect NexGen with old hypercode */
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else if (deep_magic_nexgen_probe())
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memcpy(vendor_name, "NexGenDriven", 13);
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}
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if (has_cpuid()) {
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int cpuid_level;
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cpuid_level = build_vendor_name(vendor_name);
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vendor_name[12] = '\0';
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/* Intel-defined flags: level 0x00000001 */
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if (cpuid_level >= 0x00000001) {
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cpu->device = cpuid_eax(0x00000001);
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} else {
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/* Have CPUID level 0 only unheard of */
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cpu->device = 0x00000400;
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}
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}
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cpu->vendor = X86_VENDOR_UNKNOWN;
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for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
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if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
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cpu->vendor = x86_vendors[i].vendor;
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break;
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}
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}
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}
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static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
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{
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c->x86 = (tfms >> 8) & 0xf;
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c->x86_model = (tfms >> 4) & 0xf;
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c->x86_mask = tfms & 0xf;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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}
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u32 cpu_get_family_model(void)
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{
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return gd->arch.x86_device & 0x0fff0ff0;
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}
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u32 cpu_get_stepping(void)
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{
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return gd->arch.x86_mask;
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}
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/* initialise FPU, reset EM, set MP and NE */
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static void setup_cpu_features(void)
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{
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const u32 em_rst = ~X86_CR0_EM;
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const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
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asm ("fninit\n" \
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"movl %%cr0, %%eax\n" \
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"andl %0, %%eax\n" \
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"orl %1, %%eax\n" \
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"movl %%eax, %%cr0\n" \
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: : "i" (em_rst), "i" (mp_ne_set) : "eax");
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}
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static void setup_identity(void)
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||||
{
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/* identify CPU via cpuid and store the decoded info into gd->arch */
|
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if (has_cpuid()) {
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struct cpu_device_id cpu;
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||||
struct cpuinfo_x86 c;
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||||
|
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identify_cpu(&cpu);
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get_fms(&c, cpu.device);
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gd->arch.x86 = c.x86;
|
||||
gd->arch.x86_vendor = cpu.vendor;
|
||||
gd->arch.x86_model = c.x86_model;
|
||||
gd->arch.x86_mask = c.x86_mask;
|
||||
gd->arch.x86_device = cpu.device;
|
||||
|
||||
gd->arch.has_mtrr = has_mtrr();
|
||||
}
|
||||
}
|
||||
|
||||
/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
|
||||
static void setup_pci_ram_top(void)
|
||||
{
|
||||
gd->pci_ram_top = 0x80000000U;
|
||||
}
|
||||
|
||||
static void setup_mtrr(void)
|
||||
{
|
||||
u64 mtrr_cap;
|
||||
|
||||
/* Configure fixed range MTRRs for some legacy regions */
|
||||
if (!gd->arch.has_mtrr)
|
||||
return;
|
||||
|
||||
mtrr_cap = native_read_msr(MTRR_CAP_MSR);
|
||||
if (mtrr_cap & MTRR_CAP_FIX) {
|
||||
/* Mark the VGA RAM area as uncacheable */
|
||||
native_write_msr(MTRR_FIX_16K_A0000_MSR,
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
|
||||
|
||||
/*
|
||||
* Mark the PCI ROM area as cacheable to improve ROM
|
||||
* execution performance.
|
||||
*/
|
||||
native_write_msr(MTRR_FIX_4K_C0000_MSR,
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
|
||||
native_write_msr(MTRR_FIX_4K_C8000_MSR,
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
|
||||
native_write_msr(MTRR_FIX_4K_D0000_MSR,
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
|
||||
native_write_msr(MTRR_FIX_4K_D8000_MSR,
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
|
||||
MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
|
||||
|
||||
/* Enable the fixed range MTRRs */
|
||||
msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
|
||||
}
|
||||
}
|
||||
|
||||
int x86_cpu_init_tpl(void)
|
||||
{
|
||||
setup_cpu_features();
|
||||
setup_identity();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int x86_cpu_init_f(void)
|
||||
{
|
||||
if (ll_boot_init())
|
||||
setup_cpu_features();
|
||||
setup_identity();
|
||||
setup_mtrr();
|
||||
setup_pci_ram_top();
|
||||
|
||||
/* Set up the i8254 timer if required */
|
||||
if (IS_ENABLED(CONFIG_I8254_TIMER))
|
||||
i8254_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int x86_cpu_reinit_f(void)
|
||||
{
|
||||
setup_identity();
|
||||
setup_pci_ram_top();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void x86_enable_caches(void)
|
||||
{
|
||||
unsigned long cr0;
|
||||
|
||||
cr0 = read_cr0();
|
||||
cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
|
||||
write_cr0(cr0);
|
||||
wbinvd();
|
||||
}
|
||||
void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
|
||||
|
||||
void x86_disable_caches(void)
|
||||
{
|
||||
unsigned long cr0;
|
||||
|
||||
cr0 = read_cr0();
|
||||
cr0 |= X86_CR0_NW | X86_CR0_CD;
|
||||
wbinvd();
|
||||
write_cr0(cr0);
|
||||
wbinvd();
|
||||
}
|
||||
void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
|
||||
|
||||
int dcache_status(void)
|
||||
{
|
||||
return !(read_cr0() & X86_CR0_CD);
|
||||
}
|
||||
|
||||
void cpu_enable_paging_pae(ulong cr3)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
/* Load the page table address */
|
||||
"movl %0, %%cr3\n"
|
||||
/* Enable pae */
|
||||
"movl %%cr4, %%eax\n"
|
||||
"orl $0x00000020, %%eax\n"
|
||||
"movl %%eax, %%cr4\n"
|
||||
/* Enable paging */
|
||||
"movl %%cr0, %%eax\n"
|
||||
"orl $0x80000000, %%eax\n"
|
||||
"movl %%eax, %%cr0\n"
|
||||
:
|
||||
: "r" (cr3)
|
||||
: "eax");
|
||||
}
|
||||
|
||||
void cpu_disable_paging_pae(void)
|
||||
{
|
||||
/* Turn off paging */
|
||||
__asm__ __volatile__ (
|
||||
/* Disable paging */
|
||||
"movl %%cr0, %%eax\n"
|
||||
"andl $0x7fffffff, %%eax\n"
|
||||
"movl %%eax, %%cr0\n"
|
||||
/* Disable pae */
|
||||
"movl %%cr4, %%eax\n"
|
||||
"andl $0xffffffdf, %%eax\n"
|
||||
"movl %%eax, %%cr4\n"
|
||||
:
|
||||
:
|
||||
: "eax");
|
||||
}
|
||||
|
||||
static bool can_detect_long_mode(void)
|
||||
{
|
||||
return cpuid_eax(0x80000000) > 0x80000000UL;
|
||||
}
|
||||
|
||||
static bool has_long_mode(void)
|
||||
{
|
||||
return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
|
||||
}
|
||||
|
||||
int cpu_has_64bit(void)
|
||||
{
|
||||
return has_cpuid() && can_detect_long_mode() &&
|
||||
has_long_mode();
|
||||
}
|
||||
|
||||
#define PAGETABLE_BASE 0x80000
|
||||
#define PAGETABLE_SIZE (6 * 4096)
|
||||
|
||||
/**
|
||||
* build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
|
||||
*
|
||||
* @pgtable: Pointer to a 24iKB block of memory
|
||||
*/
|
||||
static void build_pagetable(uint32_t *pgtable)
|
||||
{
|
||||
uint i;
|
||||
|
||||
memset(pgtable, '\0', PAGETABLE_SIZE);
|
||||
|
||||
/* Level 4 needs a single entry */
|
||||
pgtable[0] = (ulong)&pgtable[1024] + 7;
|
||||
|
||||
/* Level 3 has one 64-bit entry for each GiB of memory */
|
||||
for (i = 0; i < 4; i++)
|
||||
pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
|
||||
|
||||
/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
|
||||
for (i = 0; i < 2048; i++)
|
||||
pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
|
||||
}
|
||||
|
||||
int cpu_jump_to_64bit(ulong setup_base, ulong target)
|
||||
{
|
||||
uint32_t *pgtable;
|
||||
|
||||
pgtable = memalign(4096, PAGETABLE_SIZE);
|
||||
if (!pgtable)
|
||||
return -ENOMEM;
|
||||
|
||||
build_pagetable(pgtable);
|
||||
cpu_call64((ulong)pgtable, setup_base, target);
|
||||
free(pgtable);
|
||||
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/*
|
||||
* Jump from SPL to U-Boot
|
||||
*
|
||||
* This function is work-in-progress with many issues to resolve.
|
||||
*
|
||||
* It works by setting up several regions:
|
||||
* ptr - a place to put the code that jumps into 64-bit mode
|
||||
* gdt - a place to put the global descriptor table
|
||||
* pgtable - a place to put the page tables
|
||||
*
|
||||
* The cpu_call64() code is copied from ROM and then manually patched so that
|
||||
* it has the correct GDT address in RAM. U-Boot is copied from ROM into
|
||||
* its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
|
||||
* which changes to 64-bit mode and starts U-Boot.
|
||||
*/
|
||||
int cpu_jump_to_64bit_uboot(ulong target)
|
||||
{
|
||||
typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
|
||||
uint32_t *pgtable;
|
||||
func_t func;
|
||||
char *ptr;
|
||||
|
||||
pgtable = (uint32_t *)PAGETABLE_BASE;
|
||||
|
||||
build_pagetable(pgtable);
|
||||
|
||||
extern long call64_stub_size;
|
||||
ptr = malloc(call64_stub_size);
|
||||
if (!ptr) {
|
||||
printf("Failed to allocate the cpu_call64 stub\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
memcpy(ptr, cpu_call64, call64_stub_size);
|
||||
|
||||
func = (func_t)ptr;
|
||||
|
||||
/*
|
||||
* Copy U-Boot from ROM
|
||||
* TODO(sjg@chromium.org): Figure out a way to get the text base
|
||||
* correctly here, and in the device-tree binman definition.
|
||||
*
|
||||
* Also consider using FIT so we get the correct image length and
|
||||
* parameters.
|
||||
*/
|
||||
memcpy((char *)target, (char *)0xfff00000, 0x100000);
|
||||
|
||||
/* Jump to U-Boot */
|
||||
func((ulong)pgtable, 0, (ulong)target);
|
||||
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int enable_smis(struct udevice *cpu, void *unused)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct mp_flight_record mp_steps[] = {
|
||||
MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
|
||||
/* Wait for APs to finish initialization before proceeding */
|
||||
MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
|
||||
};
|
||||
|
||||
int x86_mp_init(void)
|
||||
{
|
||||
struct mp_params mp_params;
|
||||
|
||||
mp_params.parallel_microcode_load = 0,
|
||||
mp_params.flight_plan = &mp_steps[0];
|
||||
mp_params.num_records = ARRAY_SIZE(mp_steps);
|
||||
mp_params.microcode_pointer = 0;
|
||||
|
||||
if (mp_init(&mp_params)) {
|
||||
printf("Warning: MP init failure\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,631 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2008-2011
|
||||
* Graeme Russ, <graeme.russ@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
|
||||
*
|
||||
* Portions of this file are derived from the Linux kernel source
|
||||
* Copyright (C) 1991, 1992 Linus Torvalds
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <efi_loader.h>
|
||||
#include <irq_func.h>
|
||||
#include <asm/control_regs.h>
|
||||
#include <asm/i8259.h>
|
||||
#include <asm/interrupt.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/lapic.h>
|
||||
#include <asm/processor-flags.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define DECLARE_INTERRUPT(x) \
|
||||
".globl irq_"#x"\n" \
|
||||
".hidden irq_"#x"\n" \
|
||||
".type irq_"#x", @function\n" \
|
||||
"irq_"#x":\n" \
|
||||
"pushl $"#x"\n" \
|
||||
"jmp.d32 irq_common_entry\n"
|
||||
|
||||
static char *exceptions[] = {
|
||||
"Divide Error",
|
||||
"Debug",
|
||||
"NMI Interrupt",
|
||||
"Breakpoint",
|
||||
"Overflow",
|
||||
"BOUND Range Exceeded",
|
||||
"Invalid Opcode (Undefined Opcode)",
|
||||
"Device Not Available (No Math Coprocessor)",
|
||||
"Double Fault",
|
||||
"Coprocessor Segment Overrun",
|
||||
"Invalid TSS",
|
||||
"Segment Not Present",
|
||||
"Stack Segment Fault",
|
||||
"General Protection",
|
||||
"Page Fault",
|
||||
"Reserved",
|
||||
"x87 FPU Floating-Point Error",
|
||||
"Alignment Check",
|
||||
"Machine Check",
|
||||
"SIMD Floating-Point Exception",
|
||||
"Virtualization Exception",
|
||||
"Reserved",
|
||||
"Reserved",
|
||||
"Reserved",
|
||||
"Reserved",
|
||||
"Reserved",
|
||||
"Reserved",
|
||||
"Reserved",
|
||||
"Reserved",
|
||||
"Reserved",
|
||||
"Reserved",
|
||||
"Reserved"
|
||||
};
|
||||
|
||||
/**
|
||||
* show_efi_loaded_images() - show loaded UEFI images
|
||||
*
|
||||
* List all loaded UEFI images.
|
||||
*
|
||||
* @eip: instruction pointer
|
||||
*/
|
||||
static void show_efi_loaded_images(uintptr_t eip)
|
||||
{
|
||||
efi_print_image_infos((void *)eip);
|
||||
}
|
||||
|
||||
static void dump_regs(struct irq_regs *regs)
|
||||
{
|
||||
unsigned long cs, eip, eflags;
|
||||
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
|
||||
unsigned long d0, d1, d2, d3, d6, d7;
|
||||
unsigned long sp;
|
||||
|
||||
/*
|
||||
* Some exceptions cause an error code to be saved on the current stack
|
||||
* after the EIP value. We should extract CS/EIP/EFLAGS from different
|
||||
* position on the stack based on the exception number.
|
||||
*/
|
||||
switch (regs->irq_id) {
|
||||
case EXC_DF:
|
||||
case EXC_TS:
|
||||
case EXC_NP:
|
||||
case EXC_SS:
|
||||
case EXC_GP:
|
||||
case EXC_PF:
|
||||
case EXC_AC:
|
||||
cs = regs->context.ctx2.xcs;
|
||||
eip = regs->context.ctx2.eip;
|
||||
eflags = regs->context.ctx2.eflags;
|
||||
/* We should fix up the ESP due to error code */
|
||||
regs->esp += 4;
|
||||
break;
|
||||
default:
|
||||
cs = regs->context.ctx1.xcs;
|
||||
eip = regs->context.ctx1.eip;
|
||||
eflags = regs->context.ctx1.eflags;
|
||||
break;
|
||||
}
|
||||
|
||||
printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
|
||||
(u16)cs, eip, eflags);
|
||||
if (gd->flags & GD_FLG_RELOC)
|
||||
printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
|
||||
|
||||
printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
|
||||
regs->eax, regs->ebx, regs->ecx, regs->edx);
|
||||
printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
|
||||
regs->esi, regs->edi, regs->ebp, regs->esp);
|
||||
printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
|
||||
(u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
|
||||
(u16)regs->xgs, (u16)regs->xss);
|
||||
|
||||
cr0 = read_cr0();
|
||||
cr2 = read_cr2();
|
||||
cr3 = read_cr3();
|
||||
cr4 = read_cr4();
|
||||
|
||||
printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
|
||||
cr0, cr2, cr3, cr4);
|
||||
|
||||
d0 = get_debugreg(0);
|
||||
d1 = get_debugreg(1);
|
||||
d2 = get_debugreg(2);
|
||||
d3 = get_debugreg(3);
|
||||
|
||||
printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
|
||||
d0, d1, d2, d3);
|
||||
|
||||
d6 = get_debugreg(6);
|
||||
d7 = get_debugreg(7);
|
||||
printf("DR6: %08lx DR7: %08lx\n",
|
||||
d6, d7);
|
||||
|
||||
printf("Stack:\n");
|
||||
sp = regs->esp;
|
||||
|
||||
sp += 64;
|
||||
|
||||
while (sp > (regs->esp - 16)) {
|
||||
if (sp == regs->esp)
|
||||
printf("--->");
|
||||
else
|
||||
printf(" ");
|
||||
printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
|
||||
sp -= 4;
|
||||
}
|
||||
show_efi_loaded_images(eip);
|
||||
}
|
||||
|
||||
static void do_exception(struct irq_regs *regs)
|
||||
{
|
||||
printf("%s\n", exceptions[regs->irq_id]);
|
||||
dump_regs(regs);
|
||||
hang();
|
||||
}
|
||||
|
||||
struct idt_entry {
|
||||
u16 base_low;
|
||||
u16 selector;
|
||||
u8 res;
|
||||
u8 access;
|
||||
u16 base_high;
|
||||
} __packed;
|
||||
|
||||
struct desc_ptr {
|
||||
unsigned short size;
|
||||
unsigned long address;
|
||||
} __packed;
|
||||
|
||||
struct idt_entry idt[256] __aligned(16);
|
||||
|
||||
struct desc_ptr idt_ptr;
|
||||
|
||||
static inline void load_idt(const struct desc_ptr *dtr)
|
||||
{
|
||||
asm volatile("cs lidt %0" : : "m" (*dtr));
|
||||
}
|
||||
|
||||
void set_vector(u8 intnum, void *routine)
|
||||
{
|
||||
idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
|
||||
idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ideally these would be defined static to avoid a checkpatch warning, but
|
||||
* the compiler cannot see them in the inline asm and complains that they
|
||||
* aren't defined
|
||||
*/
|
||||
void irq_0(void);
|
||||
void irq_1(void);
|
||||
|
||||
int cpu_init_interrupts(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
int irq_entry_size = irq_1 - irq_0;
|
||||
void *irq_entry = (void *)irq_0;
|
||||
|
||||
/* Setup the IDT */
|
||||
for (i = 0; i < 256; i++) {
|
||||
idt[i].access = 0x8e;
|
||||
idt[i].res = 0;
|
||||
idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
|
||||
set_vector(i, irq_entry);
|
||||
irq_entry += irq_entry_size;
|
||||
}
|
||||
|
||||
idt_ptr.size = 256 * 8 - 1;
|
||||
idt_ptr.address = (unsigned long) idt;
|
||||
|
||||
load_idt(&idt_ptr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *x86_get_idt(void)
|
||||
{
|
||||
return &idt_ptr;
|
||||
}
|
||||
|
||||
void __do_irq(int irq)
|
||||
{
|
||||
printf("Unhandled IRQ : %d\n", irq);
|
||||
}
|
||||
void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
|
||||
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
asm("sti\n");
|
||||
}
|
||||
|
||||
int disable_interrupts(void)
|
||||
{
|
||||
long flags;
|
||||
|
||||
#if CONFIG_IS_ENABLED(X86_64)
|
||||
asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
|
||||
#else
|
||||
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
|
||||
#endif
|
||||
return flags & X86_EFLAGS_IF;
|
||||
}
|
||||
|
||||
int interrupt_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
/* Try to set up the interrupt router, but don't require one */
|
||||
ret = uclass_first_device_err(UCLASS_IRQ, &dev);
|
||||
if (ret && ret != -ENODEV)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* When running as an EFI application we are not in control of
|
||||
* interrupts and should leave them alone.
|
||||
*/
|
||||
#ifndef CONFIG_EFI_APP
|
||||
/* Just in case... */
|
||||
disable_interrupts();
|
||||
|
||||
#ifdef CONFIG_I8259_PIC
|
||||
/* Initialize the master/slave i8259 pic */
|
||||
i8259_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_APIC
|
||||
lapic_setup();
|
||||
#endif
|
||||
|
||||
/* Initialize core interrupt and exception functionality of CPU */
|
||||
cpu_init_interrupts();
|
||||
|
||||
/*
|
||||
* It is now safe to enable interrupts.
|
||||
*
|
||||
* TODO(sjg@chromium.org): But we don't handle these correctly when
|
||||
* booted from EFI.
|
||||
*/
|
||||
if (ll_boot_init())
|
||||
enable_interrupts();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* IRQ Low-Level Service Routine */
|
||||
void irq_llsr(struct irq_regs *regs)
|
||||
{
|
||||
/*
|
||||
* For detailed description of each exception, refer to:
|
||||
* Intel® 64 and IA-32 Architectures Software Developer's Manual
|
||||
* Volume 1: Basic Architecture
|
||||
* Order Number: 253665-029US, November 2008
|
||||
* Table 6-1. Exceptions and Interrupts
|
||||
*/
|
||||
if (regs->irq_id < 32) {
|
||||
/* Architecture defined exception */
|
||||
do_exception(regs);
|
||||
} else {
|
||||
/* Hardware or User IRQ */
|
||||
do_irq(regs->irq_id);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* OK - This looks really horrible, but it serves a purpose - It helps create
|
||||
* fully relocatable code.
|
||||
* - The call to irq_llsr will be a relative jump
|
||||
* - The IRQ entries will be guaranteed to be in order
|
||||
* Interrupt entries are now very small (a push and a jump) but they are
|
||||
* now slower (all registers pushed on stack which provides complete
|
||||
* crash dumps in the low level handlers
|
||||
*
|
||||
* Interrupt Entry Point:
|
||||
* - Interrupt has caused eflags, CS and EIP to be pushed
|
||||
* - Interrupt Vector Handler has pushed orig_eax
|
||||
* - pt_regs.esp needs to be adjusted by 40 bytes:
|
||||
* 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
|
||||
* 4 bytes pushed by vector handler (irq_id)
|
||||
* 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
|
||||
* NOTE: Only longs are pushed on/popped off the stack!
|
||||
*/
|
||||
asm(".globl irq_common_entry\n" \
|
||||
".hidden irq_common_entry\n" \
|
||||
".type irq_common_entry, @function\n" \
|
||||
"irq_common_entry:\n" \
|
||||
"cld\n" \
|
||||
"pushl %ss\n" \
|
||||
"pushl %gs\n" \
|
||||
"pushl %fs\n" \
|
||||
"pushl %es\n" \
|
||||
"pushl %ds\n" \
|
||||
"pushl %eax\n" \
|
||||
"movl %esp, %eax\n" \
|
||||
"addl $40, %eax\n" \
|
||||
"pushl %eax\n" \
|
||||
"pushl %ebp\n" \
|
||||
"pushl %edi\n" \
|
||||
"pushl %esi\n" \
|
||||
"pushl %edx\n" \
|
||||
"pushl %ecx\n" \
|
||||
"pushl %ebx\n" \
|
||||
"mov %esp, %eax\n" \
|
||||
"call irq_llsr\n" \
|
||||
"popl %ebx\n" \
|
||||
"popl %ecx\n" \
|
||||
"popl %edx\n" \
|
||||
"popl %esi\n" \
|
||||
"popl %edi\n" \
|
||||
"popl %ebp\n" \
|
||||
"popl %eax\n" \
|
||||
"popl %eax\n" \
|
||||
"popl %ds\n" \
|
||||
"popl %es\n" \
|
||||
"popl %fs\n" \
|
||||
"popl %gs\n" \
|
||||
"popl %ss\n" \
|
||||
"add $4, %esp\n" \
|
||||
"iret\n" \
|
||||
DECLARE_INTERRUPT(0) \
|
||||
DECLARE_INTERRUPT(1) \
|
||||
DECLARE_INTERRUPT(2) \
|
||||
DECLARE_INTERRUPT(3) \
|
||||
DECLARE_INTERRUPT(4) \
|
||||
DECLARE_INTERRUPT(5) \
|
||||
DECLARE_INTERRUPT(6) \
|
||||
DECLARE_INTERRUPT(7) \
|
||||
DECLARE_INTERRUPT(8) \
|
||||
DECLARE_INTERRUPT(9) \
|
||||
DECLARE_INTERRUPT(10) \
|
||||
DECLARE_INTERRUPT(11) \
|
||||
DECLARE_INTERRUPT(12) \
|
||||
DECLARE_INTERRUPT(13) \
|
||||
DECLARE_INTERRUPT(14) \
|
||||
DECLARE_INTERRUPT(15) \
|
||||
DECLARE_INTERRUPT(16) \
|
||||
DECLARE_INTERRUPT(17) \
|
||||
DECLARE_INTERRUPT(18) \
|
||||
DECLARE_INTERRUPT(19) \
|
||||
DECLARE_INTERRUPT(20) \
|
||||
DECLARE_INTERRUPT(21) \
|
||||
DECLARE_INTERRUPT(22) \
|
||||
DECLARE_INTERRUPT(23) \
|
||||
DECLARE_INTERRUPT(24) \
|
||||
DECLARE_INTERRUPT(25) \
|
||||
DECLARE_INTERRUPT(26) \
|
||||
DECLARE_INTERRUPT(27) \
|
||||
DECLARE_INTERRUPT(28) \
|
||||
DECLARE_INTERRUPT(29) \
|
||||
DECLARE_INTERRUPT(30) \
|
||||
DECLARE_INTERRUPT(31) \
|
||||
DECLARE_INTERRUPT(32) \
|
||||
DECLARE_INTERRUPT(33) \
|
||||
DECLARE_INTERRUPT(34) \
|
||||
DECLARE_INTERRUPT(35) \
|
||||
DECLARE_INTERRUPT(36) \
|
||||
DECLARE_INTERRUPT(37) \
|
||||
DECLARE_INTERRUPT(38) \
|
||||
DECLARE_INTERRUPT(39) \
|
||||
DECLARE_INTERRUPT(40) \
|
||||
DECLARE_INTERRUPT(41) \
|
||||
DECLARE_INTERRUPT(42) \
|
||||
DECLARE_INTERRUPT(43) \
|
||||
DECLARE_INTERRUPT(44) \
|
||||
DECLARE_INTERRUPT(45) \
|
||||
DECLARE_INTERRUPT(46) \
|
||||
DECLARE_INTERRUPT(47) \
|
||||
DECLARE_INTERRUPT(48) \
|
||||
DECLARE_INTERRUPT(49) \
|
||||
DECLARE_INTERRUPT(50) \
|
||||
DECLARE_INTERRUPT(51) \
|
||||
DECLARE_INTERRUPT(52) \
|
||||
DECLARE_INTERRUPT(53) \
|
||||
DECLARE_INTERRUPT(54) \
|
||||
DECLARE_INTERRUPT(55) \
|
||||
DECLARE_INTERRUPT(56) \
|
||||
DECLARE_INTERRUPT(57) \
|
||||
DECLARE_INTERRUPT(58) \
|
||||
DECLARE_INTERRUPT(59) \
|
||||
DECLARE_INTERRUPT(60) \
|
||||
DECLARE_INTERRUPT(61) \
|
||||
DECLARE_INTERRUPT(62) \
|
||||
DECLARE_INTERRUPT(63) \
|
||||
DECLARE_INTERRUPT(64) \
|
||||
DECLARE_INTERRUPT(65) \
|
||||
DECLARE_INTERRUPT(66) \
|
||||
DECLARE_INTERRUPT(67) \
|
||||
DECLARE_INTERRUPT(68) \
|
||||
DECLARE_INTERRUPT(69) \
|
||||
DECLARE_INTERRUPT(70) \
|
||||
DECLARE_INTERRUPT(71) \
|
||||
DECLARE_INTERRUPT(72) \
|
||||
DECLARE_INTERRUPT(73) \
|
||||
DECLARE_INTERRUPT(74) \
|
||||
DECLARE_INTERRUPT(75) \
|
||||
DECLARE_INTERRUPT(76) \
|
||||
DECLARE_INTERRUPT(77) \
|
||||
DECLARE_INTERRUPT(78) \
|
||||
DECLARE_INTERRUPT(79) \
|
||||
DECLARE_INTERRUPT(80) \
|
||||
DECLARE_INTERRUPT(81) \
|
||||
DECLARE_INTERRUPT(82) \
|
||||
DECLARE_INTERRUPT(83) \
|
||||
DECLARE_INTERRUPT(84) \
|
||||
DECLARE_INTERRUPT(85) \
|
||||
DECLARE_INTERRUPT(86) \
|
||||
DECLARE_INTERRUPT(87) \
|
||||
DECLARE_INTERRUPT(88) \
|
||||
DECLARE_INTERRUPT(89) \
|
||||
DECLARE_INTERRUPT(90) \
|
||||
DECLARE_INTERRUPT(91) \
|
||||
DECLARE_INTERRUPT(92) \
|
||||
DECLARE_INTERRUPT(93) \
|
||||
DECLARE_INTERRUPT(94) \
|
||||
DECLARE_INTERRUPT(95) \
|
||||
DECLARE_INTERRUPT(97) \
|
||||
DECLARE_INTERRUPT(96) \
|
||||
DECLARE_INTERRUPT(98) \
|
||||
DECLARE_INTERRUPT(99) \
|
||||
DECLARE_INTERRUPT(100) \
|
||||
DECLARE_INTERRUPT(101) \
|
||||
DECLARE_INTERRUPT(102) \
|
||||
DECLARE_INTERRUPT(103) \
|
||||
DECLARE_INTERRUPT(104) \
|
||||
DECLARE_INTERRUPT(105) \
|
||||
DECLARE_INTERRUPT(106) \
|
||||
DECLARE_INTERRUPT(107) \
|
||||
DECLARE_INTERRUPT(108) \
|
||||
DECLARE_INTERRUPT(109) \
|
||||
DECLARE_INTERRUPT(110) \
|
||||
DECLARE_INTERRUPT(111) \
|
||||
DECLARE_INTERRUPT(112) \
|
||||
DECLARE_INTERRUPT(113) \
|
||||
DECLARE_INTERRUPT(114) \
|
||||
DECLARE_INTERRUPT(115) \
|
||||
DECLARE_INTERRUPT(116) \
|
||||
DECLARE_INTERRUPT(117) \
|
||||
DECLARE_INTERRUPT(118) \
|
||||
DECLARE_INTERRUPT(119) \
|
||||
DECLARE_INTERRUPT(120) \
|
||||
DECLARE_INTERRUPT(121) \
|
||||
DECLARE_INTERRUPT(122) \
|
||||
DECLARE_INTERRUPT(123) \
|
||||
DECLARE_INTERRUPT(124) \
|
||||
DECLARE_INTERRUPT(125) \
|
||||
DECLARE_INTERRUPT(126) \
|
||||
DECLARE_INTERRUPT(127) \
|
||||
DECLARE_INTERRUPT(128) \
|
||||
DECLARE_INTERRUPT(129) \
|
||||
DECLARE_INTERRUPT(130) \
|
||||
DECLARE_INTERRUPT(131) \
|
||||
DECLARE_INTERRUPT(132) \
|
||||
DECLARE_INTERRUPT(133) \
|
||||
DECLARE_INTERRUPT(134) \
|
||||
DECLARE_INTERRUPT(135) \
|
||||
DECLARE_INTERRUPT(136) \
|
||||
DECLARE_INTERRUPT(137) \
|
||||
DECLARE_INTERRUPT(138) \
|
||||
DECLARE_INTERRUPT(139) \
|
||||
DECLARE_INTERRUPT(140) \
|
||||
DECLARE_INTERRUPT(141) \
|
||||
DECLARE_INTERRUPT(142) \
|
||||
DECLARE_INTERRUPT(143) \
|
||||
DECLARE_INTERRUPT(144) \
|
||||
DECLARE_INTERRUPT(145) \
|
||||
DECLARE_INTERRUPT(146) \
|
||||
DECLARE_INTERRUPT(147) \
|
||||
DECLARE_INTERRUPT(148) \
|
||||
DECLARE_INTERRUPT(149) \
|
||||
DECLARE_INTERRUPT(150) \
|
||||
DECLARE_INTERRUPT(151) \
|
||||
DECLARE_INTERRUPT(152) \
|
||||
DECLARE_INTERRUPT(153) \
|
||||
DECLARE_INTERRUPT(154) \
|
||||
DECLARE_INTERRUPT(155) \
|
||||
DECLARE_INTERRUPT(156) \
|
||||
DECLARE_INTERRUPT(157) \
|
||||
DECLARE_INTERRUPT(158) \
|
||||
DECLARE_INTERRUPT(159) \
|
||||
DECLARE_INTERRUPT(160) \
|
||||
DECLARE_INTERRUPT(161) \
|
||||
DECLARE_INTERRUPT(162) \
|
||||
DECLARE_INTERRUPT(163) \
|
||||
DECLARE_INTERRUPT(164) \
|
||||
DECLARE_INTERRUPT(165) \
|
||||
DECLARE_INTERRUPT(166) \
|
||||
DECLARE_INTERRUPT(167) \
|
||||
DECLARE_INTERRUPT(168) \
|
||||
DECLARE_INTERRUPT(169) \
|
||||
DECLARE_INTERRUPT(170) \
|
||||
DECLARE_INTERRUPT(171) \
|
||||
DECLARE_INTERRUPT(172) \
|
||||
DECLARE_INTERRUPT(173) \
|
||||
DECLARE_INTERRUPT(174) \
|
||||
DECLARE_INTERRUPT(175) \
|
||||
DECLARE_INTERRUPT(176) \
|
||||
DECLARE_INTERRUPT(177) \
|
||||
DECLARE_INTERRUPT(178) \
|
||||
DECLARE_INTERRUPT(179) \
|
||||
DECLARE_INTERRUPT(180) \
|
||||
DECLARE_INTERRUPT(181) \
|
||||
DECLARE_INTERRUPT(182) \
|
||||
DECLARE_INTERRUPT(183) \
|
||||
DECLARE_INTERRUPT(184) \
|
||||
DECLARE_INTERRUPT(185) \
|
||||
DECLARE_INTERRUPT(186) \
|
||||
DECLARE_INTERRUPT(187) \
|
||||
DECLARE_INTERRUPT(188) \
|
||||
DECLARE_INTERRUPT(189) \
|
||||
DECLARE_INTERRUPT(190) \
|
||||
DECLARE_INTERRUPT(191) \
|
||||
DECLARE_INTERRUPT(192) \
|
||||
DECLARE_INTERRUPT(193) \
|
||||
DECLARE_INTERRUPT(194) \
|
||||
DECLARE_INTERRUPT(195) \
|
||||
DECLARE_INTERRUPT(196) \
|
||||
DECLARE_INTERRUPT(197) \
|
||||
DECLARE_INTERRUPT(198) \
|
||||
DECLARE_INTERRUPT(199) \
|
||||
DECLARE_INTERRUPT(200) \
|
||||
DECLARE_INTERRUPT(201) \
|
||||
DECLARE_INTERRUPT(202) \
|
||||
DECLARE_INTERRUPT(203) \
|
||||
DECLARE_INTERRUPT(204) \
|
||||
DECLARE_INTERRUPT(205) \
|
||||
DECLARE_INTERRUPT(206) \
|
||||
DECLARE_INTERRUPT(207) \
|
||||
DECLARE_INTERRUPT(208) \
|
||||
DECLARE_INTERRUPT(209) \
|
||||
DECLARE_INTERRUPT(210) \
|
||||
DECLARE_INTERRUPT(211) \
|
||||
DECLARE_INTERRUPT(212) \
|
||||
DECLARE_INTERRUPT(213) \
|
||||
DECLARE_INTERRUPT(214) \
|
||||
DECLARE_INTERRUPT(215) \
|
||||
DECLARE_INTERRUPT(216) \
|
||||
DECLARE_INTERRUPT(217) \
|
||||
DECLARE_INTERRUPT(218) \
|
||||
DECLARE_INTERRUPT(219) \
|
||||
DECLARE_INTERRUPT(220) \
|
||||
DECLARE_INTERRUPT(221) \
|
||||
DECLARE_INTERRUPT(222) \
|
||||
DECLARE_INTERRUPT(223) \
|
||||
DECLARE_INTERRUPT(224) \
|
||||
DECLARE_INTERRUPT(225) \
|
||||
DECLARE_INTERRUPT(226) \
|
||||
DECLARE_INTERRUPT(227) \
|
||||
DECLARE_INTERRUPT(228) \
|
||||
DECLARE_INTERRUPT(229) \
|
||||
DECLARE_INTERRUPT(230) \
|
||||
DECLARE_INTERRUPT(231) \
|
||||
DECLARE_INTERRUPT(232) \
|
||||
DECLARE_INTERRUPT(233) \
|
||||
DECLARE_INTERRUPT(234) \
|
||||
DECLARE_INTERRUPT(235) \
|
||||
DECLARE_INTERRUPT(236) \
|
||||
DECLARE_INTERRUPT(237) \
|
||||
DECLARE_INTERRUPT(238) \
|
||||
DECLARE_INTERRUPT(239) \
|
||||
DECLARE_INTERRUPT(240) \
|
||||
DECLARE_INTERRUPT(241) \
|
||||
DECLARE_INTERRUPT(242) \
|
||||
DECLARE_INTERRUPT(243) \
|
||||
DECLARE_INTERRUPT(244) \
|
||||
DECLARE_INTERRUPT(245) \
|
||||
DECLARE_INTERRUPT(246) \
|
||||
DECLARE_INTERRUPT(247) \
|
||||
DECLARE_INTERRUPT(248) \
|
||||
DECLARE_INTERRUPT(249) \
|
||||
DECLARE_INTERRUPT(250) \
|
||||
DECLARE_INTERRUPT(251) \
|
||||
DECLARE_INTERRUPT(252) \
|
||||
DECLARE_INTERRUPT(253) \
|
||||
DECLARE_INTERRUPT(254) \
|
||||
DECLARE_INTERRUPT(255));
|
||||
@@ -0,0 +1,60 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Written by H. Peter Anvin <hpa@zytor.com>
|
||||
* Brought in from Linux v4.4 and modified for U-Boot
|
||||
* From Linux arch/um/sys-i386/setjmp.S
|
||||
*/
|
||||
|
||||
#define _REGPARM
|
||||
|
||||
/*
|
||||
* The jmp_buf is assumed to contain the following, in order:
|
||||
* %ebx
|
||||
* %esp
|
||||
* %ebp
|
||||
* %esi
|
||||
* %edi
|
||||
* <return address>
|
||||
*/
|
||||
|
||||
.text
|
||||
.align 4
|
||||
.globl setjmp
|
||||
.type setjmp, @function
|
||||
setjmp:
|
||||
#ifdef _REGPARM
|
||||
movl %eax, %edx
|
||||
#else
|
||||
movl 4(%esp), %edx
|
||||
#endif
|
||||
popl %ecx /* Return address, and adjust the stack */
|
||||
xorl %eax, %eax /* Return value */
|
||||
movl %ebx, (%edx)
|
||||
movl %esp, 4(%edx) /* Post-return %esp! */
|
||||
pushl %ecx /* Make the call/return stack happy */
|
||||
movl %ebp, 8(%edx)
|
||||
movl %esi, 12(%edx)
|
||||
movl %edi, 16(%edx)
|
||||
movl %ecx, 20(%edx) /* Return address */
|
||||
ret
|
||||
|
||||
/* Provide function size if needed */
|
||||
.size setjmp, .-setjmp
|
||||
|
||||
.align 4
|
||||
.globl longjmp
|
||||
.type longjmp, @function
|
||||
longjmp:
|
||||
#ifdef _REGPARM
|
||||
xchgl %eax, %edx
|
||||
#else
|
||||
movl 4(%esp), %edx /* jmp_ptr address */
|
||||
#endif
|
||||
movl (%edx), %ebx
|
||||
movl 4(%edx), %esp
|
||||
movl 8(%edx), %ebp
|
||||
movl 12(%edx), %esi
|
||||
movl 16(%edx), %edi
|
||||
jmp *20(%edx)
|
||||
|
||||
.size longjmp, .-longjmp
|
||||
Reference in New Issue
Block a user