GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/arch/x86/cpu/queensbay/Kconfig

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+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+
+config INTEL_QUEENSBAY
+	bool
+	select HAVE_FSP
+	select HAVE_CMC
+	select ARCH_EARLY_INIT_R
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply PCH_GBE
+	imply SCSI
+	imply SCSI_AHCI
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
+
+if INTEL_QUEENSBAY
+
+config HAVE_CMC
+	bool "Add a Chipset Micro Code state machine binary"
+	help
+	  Select this option to add a Chipset Micro Code state machine binary
+	  to the resulting U-Boot image. It is a 64K data block of machine
+	  specific code which must be put in the flash for the processor to
+	  access when powered up before system BIOS is executed.
+
+config CMC_FILE
+	string "Chipset Micro Code state machine filename"
+	depends on HAVE_CMC
+	default "cmc.bin"
+	help
+	  The filename of the file to use as Chipset Micro Code state machine
+	  binary in the board directory.
+
+config CMC_ADDR
+	hex "Chipset Micro Code state machine binary location"
+	depends on HAVE_CMC
+	default 0xfffb0000
+	help
+	  The location of the CMC binary is determined by a strap. It must be
+	  put in flash at a location matching the strap-determined base address.
+
+	  The default base address of 0xfffb0000 indicates that the binary must
+	  be located at offset 0xb0000 from the beginning of a 1MB flash device.
+
+config CPU_ADDR_BITS
+	int
+	default 32
+
+config DISABLE_IGD
+	bool "Disable Integrated Graphics Device (IGD)"
+	help
+	  Disable the Integrated Graphics Device (IGD) so that it does not
+	  show in the PCI configuration space as a VGA disaplay controller.
+	  This gives a chance for U-Boot to run PCI/PCIe based graphics
+	  card's VGA BIOS and use that card for the graphics console.
+
+endif

source/bootloader/u-boot-2020.01/arch/x86/cpu/queensbay/Makefile

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+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y += fsp_configs.o
+obj-y += tnc.o

source/bootloader/u-boot-2020.01/arch/x86/cpu/queensbay/fsp_configs.c

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+// SPDX-License-Identifier: Intel
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/fsp1/fsp_support.h>
+
+void fsp_update_configs(struct fsp_config_data *config,
+			struct fspinit_rtbuf *rt_buf)
+{
+	/* Initialize runtime buffer for fsp_init() */
+	rt_buf->common.stack_top = config->common.stack_top - 32;
+	rt_buf->common.boot_mode = config->common.boot_mode;
+	rt_buf->common.upd_data = &config->fsp_upd;
+
+	/* Override any UPD setting if required */
+}

source/bootloader/u-boot-2020.01/arch/x86/cpu/queensbay/tnc.c

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+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/post.h>
+#include <asm/arch/device.h>
+#include <asm/arch/tnc.h>
+#include <asm/fsp1/fsp_support.h>
+#include <asm/processor.h>
+
+static int __maybe_unused disable_igd(void)
+{
+	struct udevice *igd, *sdvo;
+	int ret;
+
+	ret = dm_pci_bus_find_bdf(TNC_IGD, &igd);
+	if (ret)
+		return ret;
+	if (!igd)
+		return 0;
+
+	ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
+	if (ret)
+		return ret;
+	if (!sdvo)
+		return 0;
+
+	/*
+	 * According to Atom E6xx datasheet, setting VGA Disable (bit17)
+	 * of Graphics Controller register (offset 0x50) prevents IGD
+	 * (D2:F0) from reporting itself as a VGA display controller
+	 * class in the PCI configuration space, and should also prevent
+	 * it from responding to VGA legacy memory range and I/O addresses.
+	 *
+	 * However test result shows that with just VGA Disable bit set and
+	 * a PCIe graphics card connected to one of the PCIe controllers on
+	 * the E6xx, accessing the VGA legacy space still causes system hang.
+	 * After a number of attempts, it turns out besides VGA Disable bit,
+	 * the SDVO (D3:F0) device should be disabled to make it work.
+	 *
+	 * To simplify, use the Function Disable register (offset 0xc4)
+	 * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
+	 * two devices will be completely disabled (invisible in the PCI
+	 * configuration space) unless a system reset is performed.
+	 */
+	dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
+	dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
+
+	/*
+	 * After setting the function disable bit, IGD and SDVO devices will
+	 * disappear in the PCI configuration space. This however creates an
+	 * inconsistent state from a driver model PCI controller point of view,
+	 * as these two PCI devices are still attached to its parent's child
+	 * device list as maintained by the driver model. Some driver model PCI
+	 * APIs like dm_pci_find_class(), are referring to the list to speed up
+	 * the finding process instead of re-enumerating the whole PCI bus, so
+	 * it gets the stale cached data which is wrong.
+	 *
+	 * Note x86 PCI enueration normally happens twice, in pre-relocation
+	 * phase and post-relocation. One option might be to call disable_igd()
+	 * in one of the pre-relocation initialization hooks so that it gets
+	 * disabled in the first round, and when it comes to the second round
+	 * driver model PCI will construct a correct list. Unfortunately this
+	 * does not work as Intel FSP is used on this platform to perform low
+	 * level initialization, and fsp_init_phase_pci() is called only once
+	 * in the post-relocation phase. If we disable IGD and SDVO devices,
+	 * fsp_init_phase_pci() simply hangs and never returns.
+	 *
+	 * So the only option we have is to manually remove these two devices.
+	 */
+	ret = device_remove(igd, DM_REMOVE_NORMAL);
+	if (ret)
+		return ret;
+	ret = device_unbind(igd);
+	if (ret)
+		return ret;
+	ret = device_remove(sdvo, DM_REMOVE_NORMAL);
+	if (ret)
+		return ret;
+	ret = device_unbind(sdvo);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+	post_code(POST_CPU_INIT);
+
+	return x86_cpu_init_f();
+}
+
+static void tnc_irq_init(void)
+{
+	struct tnc_rcba *rcba;
+	u32 base;
+
+	pci_read_config32(TNC_LPC, LPC_RCBA, &base);
+	base &= ~MEM_BAR_EN;
+	rcba = (struct tnc_rcba *)base;
+
+	/* Make sure all internal PCI devices are using INTA */
+	writel(INTA, &rcba->d02ip);
+	writel(INTA, &rcba->d03ip);
+	writel(INTA, &rcba->d27ip);
+	writel(INTA, &rcba->d31ip);
+	writel(INTA, &rcba->d23ip);
+	writel(INTA, &rcba->d24ip);
+	writel(INTA, &rcba->d25ip);
+	writel(INTA, &rcba->d26ip);
+
+	/*
+	 * Route TunnelCreek PCI device interrupt pin to PIRQ
+	 *
+	 * Since PCIe downstream ports received INTx are routed to PIRQ
+	 * A/B/C/D directly and not configurable, we have to route PCIe
+	 * root ports' INTx to PIRQ A/B/C/D as well. For other devices
+	 * on TunneCreek, route them to PIRQ E/F/G/H.
+	 */
+	writew(PIRQE, &rcba->d02ir);
+	writew(PIRQF, &rcba->d03ir);
+	writew(PIRQG, &rcba->d27ir);
+	writew(PIRQH, &rcba->d31ir);
+	writew(PIRQA, &rcba->d23ir);
+	writew(PIRQB, &rcba->d24ir);
+	writew(PIRQC, &rcba->d25ir);
+	writew(PIRQD, &rcba->d26ir);
+}
+
+int arch_early_init_r(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_DISABLE_IGD
+	ret = disable_igd();
+#endif
+
+	tnc_irq_init();
+
+	return ret;
+}