GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,135 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/arch/x86/acpi/debug.asl
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*/
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/* POST register region */
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OperationRegion(X80, SystemIO, 0x80, 1)
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Field(X80, ByteAcc, NoLock, Preserve)
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{
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P80, 8
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}
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/* Legacy serial port register region */
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OperationRegion(CREG, SystemIO, 0x3F8, 8)
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Field(CREG, ByteAcc, NoLock, Preserve)
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{
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CDAT, 8,
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CDLM, 8,
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, 8,
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CLCR, 8,
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CMCR, 8,
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CLSR, 8
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}
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/* DINI - Initialize the serial port to 115200 8-N-1 */
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Method(DINI)
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{
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Store(0x83, CLCR)
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Store(0x01, CDAT) /* 115200 baud (low) */
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Store(0x00, CDLM) /* 115200 baud (high) */
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Store(0x03, CLCR) /* word=8 stop=1 parity=none */
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Store(0x03, CMCR) /* DTR=1 RTS=1 out1/2=Off loop=Off */
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Store(0x00, CDLM) /* turn off interrupts */
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}
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/* THRE - Wait for serial port transmitter holding register to go empty */
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Method(THRE)
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{
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And(CLSR, 0x20, Local0)
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While (LEqual(Local0, Zero)) {
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And(CLSR, 0x20, Local0)
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}
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}
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/* OUTX - Send a single raw character */
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Method(OUTX, 1)
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{
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THRE()
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Store(Arg0, CDAT)
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}
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/* OUTC - Send a single character, expanding LF into CR/LF */
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Method(OUTC, 1)
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{
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If (LEqual(Arg0, 0x0a)) {
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OUTX(0x0d)
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}
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OUTX(Arg0)
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}
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/* DBGN - Send a single hex nibble */
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Method(DBGN, 1)
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{
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And(Arg0, 0x0f, Local0)
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If (LLess(Local0, 10)) {
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Add(Local0, 0x30, Local0)
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} Else {
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Add(Local0, 0x37, Local0)
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}
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OUTC(Local0)
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}
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/* DBGB - Send a hex byte */
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Method(DBGB, 1)
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{
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ShiftRight(Arg0, 4, Local0)
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DBGN(Local0)
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DBGN(Arg0)
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}
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/* DBGW - Send a hex word */
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Method(DBGW, 1)
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{
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ShiftRight(Arg0, 8, Local0)
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DBGB(Local0)
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DBGB(Arg0)
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}
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/* DBGD - Send a hex dword */
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Method(DBGD, 1)
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{
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ShiftRight(Arg0, 16, Local0)
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DBGW(Local0)
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DBGW(Arg0)
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}
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/* Get a char from a string */
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Method(GETC, 2)
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{
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CreateByteField(Arg0, Arg1, DBGC)
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Return (DBGC)
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}
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/* DBGO - Send either a string or an integer */
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Method(DBGO, 1, Serialized)
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{
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If (LEqual(ObjectType(Arg0), 1)) {
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If (LGreater(Arg0, 0xffff)) {
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DBGD(Arg0)
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} Else {
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If (LGreater(Arg0, 0xff)) {
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DBGW(Arg0)
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} Else {
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DBGB(Arg0)
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}
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}
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} Else {
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Name(BDBG, Buffer(80) {})
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Store(Arg0, BDBG)
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Store(0, Local1)
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While (One) {
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Store(GETC(BDBG, Local1), Local0)
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If (LEqual(Local0, 0)) {
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Return (Zero)
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}
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OUTC(Local0)
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Increment(Local1)
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}
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}
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Return (Zero)
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}
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@@ -0,0 +1,18 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*/
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#ifndef _ACPI_GNVS_H_
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#define _ACPI_GNVS_H_
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/*
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* This file provides two ACPI global NVS macros: ACPI_GNVS_ADDR and
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* ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file
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* to declare the GNVS OperationRegion, as well as write_acpi_tables()
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* for the GNVS address runtime fix up.
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*/
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#define ACPI_GNVS_ADDR 0xdeadbeef
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#define ACPI_GNVS_SIZE 0x100
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#endif /* _ACPI_GNVS_H_ */
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@@ -0,0 +1,112 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/arch/x86/acpi/globutil.asl
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*/
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Method(MIN, 2)
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{
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If (LLess(Arg0, Arg1)) {
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Return (Arg0)
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} Else {
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Return (Arg1)
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}
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}
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Method(SLEN, 1)
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{
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Store(Arg0, Local0)
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Return (Sizeof(Local0))
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}
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Method(S2BF, 1, Serialized)
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{
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Add(SLEN(Arg0), One, Local0)
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Name(BUFF, Buffer(Local0) {})
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Store(Arg0, BUFF)
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Return (BUFF)
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}
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/*
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* SCMP - Strong string compare
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*
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* Checks both length and content
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*/
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Method(SCMP, 2)
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{
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Store(S2BF(Arg0), Local0)
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Store(S2BF(Arg1), Local1)
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Store(Zero, Local4)
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Store(SLEN(Arg0), Local5)
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Store(SLEN(Arg1), Local6)
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Store(MIN(Local5, Local6), Local7)
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While (LLess(Local4, Local7)) {
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Store(Derefof(Index(Local0, Local4)), Local2)
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Store(Derefof(Index(Local1, Local4)), Local3)
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If (LGreater(Local2, Local3)) {
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Return (One)
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} Else {
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If (LLess(Local2, Local3)) {
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Return (Ones)
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}
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}
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Increment(Local4)
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}
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If (LLess(Local4, Local5)) {
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Return (One)
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} Else {
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If (LLess(Local4, Local6)) {
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Return (Ones)
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} Else {
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Return (Zero)
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}
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}
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}
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/*
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* WCMP - Weak string compare
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*
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* Checks to find Arg1 at beginning of Arg0.
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* Fails if length(Arg0) < length(Arg1).
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* Returns 0 on fail, 1 on pass.
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*/
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Method(WCMP, 2)
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{
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Store(S2BF(Arg0), Local0)
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Store(S2BF(Arg1), Local1)
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If (LLess(SLEN(Arg0), SLEN(Arg1))) {
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Return (Zero)
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}
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Store(Zero, Local2)
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Store(SLEN(Arg1), Local3)
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While (LLess(Local2, Local3)) {
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If (LNotEqual(Derefof(Index(Local0, Local2)),
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Derefof(Index(Local1, Local2)))) {
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Return (Zero)
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}
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Increment(Local2)
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}
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Return (One)
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}
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/*
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* I2BM - Returns Bit Map
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*
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* Arg0 = IRQ Number (0-15)
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*/
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Method(I2BM, 1)
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{
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Store(0, Local0)
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If (LNotEqual(Arg0, 0)) {
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Store(1, Local1)
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ShiftLeft(Local1, Arg0, Local0)
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}
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Return (Local0)
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}
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@@ -0,0 +1,110 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2014 Sage Electronics Engineering, LLC.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
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*/
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/*
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* This file intentionally gets included multiple times, to set pic and apic
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* modes, so should not have guard statements added.
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*/
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/*
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* This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
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* routing for the platform being compiled.
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*
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* This method uses #defines in irqroute.h along with the macros contained
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* in this file to generate an IRQ routing for each PCI device in the system.
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*/
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#undef PCI_DEV_PIRQ_ROUTES
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#undef PCI_DEV_PIRQ_ROUTE
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#undef ACPI_DEV_IRQ
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#undef PCIE_BRIDGE_DEV
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#undef RP_IRQ_ROUTES
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#undef ROOTPORT_METHODS
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#undef ROOTPORT_IRQ_ROUTES
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#undef RP_METHOD
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#if defined(PIC_MODE)
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#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
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Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
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#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
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Name(prefix_ ## func_ ## P, Package() \
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{ \
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ACPI_DEV_IRQ(0x0000, 0, a_), \
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ACPI_DEV_IRQ(0x0000, 1, b_), \
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ACPI_DEV_IRQ(0x0000, 2, c_), \
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ACPI_DEV_IRQ(0x0000, 3, d_), \
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})
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/* define as blank so ROOTPORT_METHODS only gets inserted once */
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#define ROOTPORT_METHODS(prefix_, dev_)
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#else /* defined(PIC_MODE) */
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#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
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Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
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#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
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Name(prefix_ ## func_ ## A, Package() \
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{ \
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ACPI_DEV_IRQ(0x0000, 0, a_), \
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ACPI_DEV_IRQ(0x0000, 1, b_), \
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ACPI_DEV_IRQ(0x0000, 2, c_), \
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ACPI_DEV_IRQ(0x0000, 3, d_), \
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})
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#define ROOTPORT_METHODS(prefix_, dev_) \
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RP_METHOD(prefix_, dev_, 0) \
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RP_METHOD(prefix_, dev_, 1) \
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RP_METHOD(prefix_, dev_, 2) \
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RP_METHOD(prefix_, dev_, 3) \
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RP_METHOD(prefix_, dev_, 4) \
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RP_METHOD(prefix_, dev_, 5) \
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RP_METHOD(prefix_, dev_, 6) \
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RP_METHOD(prefix_, dev_, 7)
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#endif /* defined(PIC_MODE) */
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#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
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ACPI_DEV_IRQ(dev_, 0, a_), \
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ACPI_DEV_IRQ(dev_, 1, b_), \
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ACPI_DEV_IRQ(dev_, 2, c_), \
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ACPI_DEV_IRQ(dev_, 3, d_)
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#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
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ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
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ROOTPORT_METHODS(prefix_, dev_)
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#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
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RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
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RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
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RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
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RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
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RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
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RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
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RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
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RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
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#define RP_METHOD(prefix_, dev_, func_)\
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Device (prefix_ ## 0 ## func_) \
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{ \
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Name(_ADR, dev_ ## 000 ## func_) \
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Name(_PRW, Package() { 0, 0 }) \
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Method(_PRT) { \
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If (PICM) { \
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Return (prefix_ ## func_ ## A) \
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} Else { \
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Return (prefix_ ## func_ ## P) \
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} \
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} \
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||||
}
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/* SoC specific PIRQ route configuration */
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#include <asm/arch/acpi/irqroute.h>
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@@ -0,0 +1,485 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
|
||||
*/
|
||||
|
||||
/*
|
||||
* Intel chipset PIRQ routing control ASL description
|
||||
*
|
||||
* The programming interface is common to most Intel chipsets. But the PRTx
|
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* registers may be mapped to different blocks. Some chipsets map them to LPC
|
||||
* device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
|
||||
* some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
|
||||
* Block (ILB) memory space.
|
||||
*
|
||||
* This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
|
||||
* PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
|
||||
* defined somewhere else in the platform's ASL files.
|
||||
*/
|
||||
|
||||
Device (LNKA)
|
||||
{
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 1)
|
||||
|
||||
/* Disable method */
|
||||
Method(_DIS, 0, Serialized)
|
||||
{
|
||||
Store(0x80, PRTA)
|
||||
}
|
||||
|
||||
/* Possible Resource Settings for this Link */
|
||||
Name(_PRS, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
|
||||
})
|
||||
|
||||
/* Current Resource Settings for this link */
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
Name(RTLA, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateWordField(RTLA, 1, IRQ0)
|
||||
|
||||
/* Clear the WordField */
|
||||
Store(Zero, IRQ0)
|
||||
|
||||
/* Set the bit from PRTA */
|
||||
ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
|
||||
|
||||
Return (RTLA)
|
||||
}
|
||||
|
||||
/* Set Resource Setting for this IRQ link */
|
||||
Method(_SRS, 1, Serialized)
|
||||
{
|
||||
CreateWordField(Arg0, 1, IRQ0)
|
||||
|
||||
/* Which bit is set? */
|
||||
FindSetRightBit(IRQ0, Local0)
|
||||
|
||||
Decrement(Local0)
|
||||
Store(Local0, PRTA)
|
||||
}
|
||||
|
||||
/* Status */
|
||||
Method(_STA, 0, Serialized)
|
||||
{
|
||||
If (And(PRTA, 0x80)) {
|
||||
Return (STA_DISABLED)
|
||||
} Else {
|
||||
Return (STA_INVISIBLE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKB)
|
||||
{
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 2)
|
||||
|
||||
/* Disable method */
|
||||
Method(_DIS, 0, Serialized)
|
||||
{
|
||||
Store(0x80, PRTB)
|
||||
}
|
||||
|
||||
/* Possible Resource Settings for this Link */
|
||||
Name(_PRS, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
|
||||
})
|
||||
|
||||
/* Current Resource Settings for this link */
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
Name(RTLB, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateWordField(RTLB, 1, IRQ0)
|
||||
|
||||
/* Clear the WordField */
|
||||
Store(Zero, IRQ0)
|
||||
|
||||
/* Set the bit from PRTB */
|
||||
ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
|
||||
|
||||
Return (RTLB)
|
||||
}
|
||||
|
||||
/* Set Resource Setting for this IRQ link */
|
||||
Method(_SRS, 1, Serialized)
|
||||
{
|
||||
CreateWordField(Arg0, 1, IRQ0)
|
||||
|
||||
/* Which bit is set? */
|
||||
FindSetRightBit(IRQ0, Local0)
|
||||
|
||||
Decrement(Local0)
|
||||
Store(Local0, PRTB)
|
||||
}
|
||||
|
||||
/* Status */
|
||||
Method(_STA, 0, Serialized)
|
||||
{
|
||||
If (And(PRTB, 0x80)) {
|
||||
Return (STA_DISABLED)
|
||||
} Else {
|
||||
Return (STA_INVISIBLE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKC)
|
||||
{
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 3)
|
||||
|
||||
/* Disable method */
|
||||
Method(_DIS, 0, Serialized)
|
||||
{
|
||||
Store(0x80, PRTC)
|
||||
}
|
||||
|
||||
/* Possible Resource Settings for this Link */
|
||||
Name(_PRS, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
|
||||
})
|
||||
|
||||
/* Current Resource Settings for this link */
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
Name(RTLC, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateWordField(RTLC, 1, IRQ0)
|
||||
|
||||
/* Clear the WordField */
|
||||
Store(Zero, IRQ0)
|
||||
|
||||
/* Set the bit from PRTC */
|
||||
ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
|
||||
|
||||
Return (RTLC)
|
||||
}
|
||||
|
||||
/* Set Resource Setting for this IRQ link */
|
||||
Method(_SRS, 1, Serialized)
|
||||
{
|
||||
CreateWordField(Arg0, 1, IRQ0)
|
||||
|
||||
/* Which bit is set? */
|
||||
FindSetRightBit(IRQ0, Local0)
|
||||
|
||||
Decrement(Local0)
|
||||
Store(Local0, PRTC)
|
||||
}
|
||||
|
||||
/* Status */
|
||||
Method(_STA, 0, Serialized)
|
||||
{
|
||||
If (And(PRTC, 0x80)) {
|
||||
Return (STA_DISABLED)
|
||||
} Else {
|
||||
Return (STA_INVISIBLE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKD)
|
||||
{
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 4)
|
||||
|
||||
/* Disable method */
|
||||
Method(_DIS, 0, Serialized)
|
||||
{
|
||||
Store(0x80, PRTD)
|
||||
}
|
||||
|
||||
/* Possible Resource Settings for this Link */
|
||||
Name(_PRS, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
|
||||
})
|
||||
|
||||
/* Current Resource Settings for this link */
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
Name(RTLD, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateWordField(RTLD, 1, IRQ0)
|
||||
|
||||
/* Clear the WordField */
|
||||
Store(Zero, IRQ0)
|
||||
|
||||
/* Set the bit from PRTD */
|
||||
ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
|
||||
|
||||
Return (RTLD)
|
||||
}
|
||||
|
||||
/* Set Resource Setting for this IRQ link */
|
||||
Method(_SRS, 1, Serialized)
|
||||
{
|
||||
CreateWordField(Arg0, 1, IRQ0)
|
||||
|
||||
/* Which bit is set? */
|
||||
FindSetRightBit(IRQ0, Local0)
|
||||
|
||||
Decrement(Local0)
|
||||
Store(Local0, PRTD)
|
||||
}
|
||||
|
||||
/* Status */
|
||||
Method(_STA, 0, Serialized)
|
||||
{
|
||||
If (And(PRTD, 0x80)) {
|
||||
Return (STA_DISABLED)
|
||||
} Else {
|
||||
Return (STA_INVISIBLE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKE)
|
||||
{
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 5)
|
||||
|
||||
/* Disable method */
|
||||
Method(_DIS, 0, Serialized)
|
||||
{
|
||||
Store(0x80, PRTE)
|
||||
}
|
||||
|
||||
/* Possible Resource Settings for this Link */
|
||||
Name(_PRS, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
|
||||
})
|
||||
|
||||
/* Current Resource Settings for this link */
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
Name(RTLE, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateWordField(RTLE, 1, IRQ0)
|
||||
|
||||
/* Clear the WordField */
|
||||
Store(Zero, IRQ0)
|
||||
|
||||
/* Set the bit from PRTE */
|
||||
ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
|
||||
|
||||
Return (RTLE)
|
||||
}
|
||||
|
||||
/* Set Resource Setting for this IRQ link */
|
||||
Method(_SRS, 1, Serialized)
|
||||
{
|
||||
CreateWordField(Arg0, 1, IRQ0)
|
||||
|
||||
/* Which bit is set? */
|
||||
FindSetRightBit(IRQ0, Local0)
|
||||
|
||||
Decrement(Local0)
|
||||
Store(Local0, PRTE)
|
||||
}
|
||||
|
||||
/* Status */
|
||||
Method(_STA, 0, Serialized)
|
||||
{
|
||||
If (And(PRTE, 0x80)) {
|
||||
Return (STA_DISABLED)
|
||||
} Else {
|
||||
Return (STA_INVISIBLE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKF)
|
||||
{
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 6)
|
||||
|
||||
/* Disable method */
|
||||
Method(_DIS, 0, Serialized)
|
||||
{
|
||||
Store(0x80, PRTF)
|
||||
}
|
||||
|
||||
/* Possible Resource Settings for this Link */
|
||||
Name(_PRS, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
|
||||
})
|
||||
|
||||
/* Current Resource Settings for this link */
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
Name(RTLF, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateWordField(RTLF, 1, IRQ0)
|
||||
|
||||
/* Clear the WordField */
|
||||
Store(Zero, IRQ0)
|
||||
|
||||
/* Set the bit from PRTF */
|
||||
ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
|
||||
|
||||
Return (RTLF)
|
||||
}
|
||||
|
||||
/* Set Resource Setting for this IRQ link */
|
||||
Method(_SRS, 1, Serialized)
|
||||
{
|
||||
CreateWordField(Arg0, 1, IRQ0)
|
||||
|
||||
/* Which bit is set? */
|
||||
FindSetRightBit(IRQ0, Local0)
|
||||
|
||||
Decrement(Local0)
|
||||
Store(Local0, PRTF)
|
||||
}
|
||||
|
||||
/* Status */
|
||||
Method(_STA, 0, Serialized)
|
||||
{
|
||||
If (And(PRTF, 0x80)) {
|
||||
Return (STA_DISABLED)
|
||||
} Else {
|
||||
Return (STA_INVISIBLE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKG)
|
||||
{
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 7)
|
||||
|
||||
/* Disable method */
|
||||
Method(_DIS, 0, Serialized)
|
||||
{
|
||||
Store(0x80, PRTG)
|
||||
}
|
||||
|
||||
/* Possible Resource Settings for this Link */
|
||||
Name(_PRS, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
|
||||
})
|
||||
|
||||
/* Current Resource Settings for this link */
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
Name(RTLG, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateWordField(RTLG, 1, IRQ0)
|
||||
|
||||
/* Clear the WordField */
|
||||
Store(Zero, IRQ0)
|
||||
|
||||
/* Set the bit from PRTG */
|
||||
ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
|
||||
|
||||
Return (RTLG)
|
||||
}
|
||||
|
||||
/* Set Resource Setting for this IRQ link */
|
||||
Method(_SRS, 1, Serialized)
|
||||
{
|
||||
CreateWordField(Arg0, 1, IRQ0)
|
||||
|
||||
/* Which bit is set? */
|
||||
FindSetRightBit(IRQ0, Local0)
|
||||
|
||||
Decrement(Local0)
|
||||
Store(Local0, PRTG)
|
||||
}
|
||||
|
||||
/* Status */
|
||||
Method(_STA, 0, Serialized)
|
||||
{
|
||||
If (And(PRTG, 0x80)) {
|
||||
Return (STA_DISABLED)
|
||||
} Else {
|
||||
Return (STA_INVISIBLE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (LNKH)
|
||||
{
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 8)
|
||||
|
||||
/* Disable method */
|
||||
Method(_DIS, 0, Serialized)
|
||||
{
|
||||
Store(0x80, PRTH)
|
||||
}
|
||||
|
||||
/* Possible Resource Settings for this Link */
|
||||
Name(_PRS, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
|
||||
})
|
||||
|
||||
/* Current Resource Settings for this link */
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
Name(RTLH, ResourceTemplate()
|
||||
{
|
||||
IRQ(Level, ActiveLow, Shared) {}
|
||||
})
|
||||
CreateWordField(RTLH, 1, IRQ0)
|
||||
|
||||
/* Clear the WordField */
|
||||
Store(Zero, IRQ0)
|
||||
|
||||
/* Set the bit from PRTH */
|
||||
ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
|
||||
|
||||
Return (RTLH)
|
||||
}
|
||||
|
||||
/* Set Resource Setting for this IRQ link */
|
||||
Method(_SRS, 1, Serialized)
|
||||
{
|
||||
CreateWordField(Arg0, 1, IRQ0)
|
||||
|
||||
/* Which bit is set? */
|
||||
FindSetRightBit(IRQ0, Local0)
|
||||
|
||||
Decrement(Local0)
|
||||
Store(Local0, PRTH)
|
||||
}
|
||||
|
||||
/* Status */
|
||||
Method(_STA, 0, Serialized)
|
||||
{
|
||||
If (And(PRTH, 0x80)) {
|
||||
Return (STA_DISABLED)
|
||||
} Else {
|
||||
Return (STA_INVISIBLE)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,47 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
|
||||
*/
|
||||
|
||||
Name(\PICM, 0)
|
||||
|
||||
/*
|
||||
* The _PIC method is called by the OS to choose between interrupt
|
||||
* routing via the i8259 interrupt controller or the APIC.
|
||||
*
|
||||
* _PIC is called with a parameter of 0 for i8259 configuration and
|
||||
* with a parameter of 1 for Local APIC/IOAPIC configuration.
|
||||
*/
|
||||
Method(\_PIC, 1)
|
||||
{
|
||||
/* Remember the OS' IRQ routing choice */
|
||||
Store(Arg0, PICM)
|
||||
}
|
||||
|
||||
/* PCI interrupt routing */
|
||||
Method(_PRT) {
|
||||
If (PICM) {
|
||||
Return (Package() {
|
||||
#undef PIC_MODE
|
||||
#include "irq_helper.h"
|
||||
PCI_DEV_PIRQ_ROUTES
|
||||
})
|
||||
} Else {
|
||||
Return (Package() {
|
||||
#define PIC_MODE
|
||||
#include "irq_helper.h"
|
||||
PCI_DEV_PIRQ_ROUTES
|
||||
})
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* PCIe downstream ports interrupt routing */
|
||||
PCIE_BRIDGE_IRQ_ROUTES
|
||||
#undef PIC_MODE
|
||||
#include "irq_helper.h"
|
||||
PCIE_BRIDGE_IRQ_ROUTES
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
|
||||
*/
|
||||
|
||||
Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
|
||||
#ifdef CONFIG_HAVE_ACPI_RESUME
|
||||
Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
|
||||
#endif
|
||||
Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
|
||||
Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
|
||||
@@ -0,0 +1,81 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Modified from coreboot src/arch/x86/acpi/statdef.asl
|
||||
*/
|
||||
|
||||
/* Status and notification definitions */
|
||||
|
||||
#define STA_MISSING 0x00
|
||||
#define STA_PRESENT 0x01
|
||||
#define STA_ENABLED 0x03
|
||||
#define STA_DISABLED 0x09
|
||||
#define STA_INVISIBLE 0x0b
|
||||
#define STA_UNAVAILABLE 0x0d
|
||||
#define STA_VISIBLE 0x0f
|
||||
|
||||
/* SMBus status codes */
|
||||
#define SMB_OK 0x00
|
||||
#define SMB_UNKNOWN_FAIL 0x07
|
||||
#define SMB_DEV_ADDR_NAK 0x10
|
||||
#define SMB_DEVICE_ERROR 0x11
|
||||
#define SMB_DEV_CMD_DENIED 0x12
|
||||
#define SMB_UNKNOWN_ERR 0x13
|
||||
#define SMB_DEV_ACC_DENIED 0x17
|
||||
#define SMB_TIMEOUT 0x18
|
||||
#define SMB_HST_UNSUPP_PROTOCOL 0x19
|
||||
#define SMB_BUSY 0x1a
|
||||
#define SMB_PKT_CHK_ERROR 0x1f
|
||||
|
||||
/* Device Object Notification Values */
|
||||
#define NOTIFY_BUS_CHECK 0x00
|
||||
#define NOTIFY_DEVICE_CHECK 0x01
|
||||
#define NOTIFY_DEVICE_WAKE 0x02
|
||||
#define NOTIFY_EJECT_REQUEST 0x03
|
||||
#define NOTIFY_DEVICE_CHECK_JR 0x04
|
||||
#define NOTIFY_FREQUENCY_ERROR 0x05
|
||||
#define NOTIFY_BUS_MODE 0x06
|
||||
#define NOTIFY_POWER_FAULT 0x07
|
||||
#define NOTIFY_CAPABILITIES 0x08
|
||||
#define NOTIFY_PLD_CHECK 0x09
|
||||
#define NOTIFY_SLIT_UPDATE 0x0b
|
||||
#define NOTIFY_SRA_UPDATE 0x0d
|
||||
|
||||
/* Battery Device Notification Values */
|
||||
#define NOTIFY_BAT_STATUSCHG 0x80
|
||||
#define NOTIFY_BAT_INFOCHG 0x81
|
||||
#define NOTIFY_BAT_MAINTDATA 0x82
|
||||
|
||||
/* Power Source Object Notification Values */
|
||||
#define NOTIFY_PWR_STATUSCHG 0x80
|
||||
#define NOTIFY_PWR_INFOCHG 0x81
|
||||
|
||||
/* Thermal Zone Object Notification Values */
|
||||
#define NOTIFY_TZ_STATUSCHG 0x80
|
||||
#define NOTIFY_TZ_TRIPPTCHG 0x81
|
||||
#define NOTIFY_TZ_DEVLISTCHG 0x82
|
||||
#define NOTIFY_TZ_RELTBLCHG 0x83
|
||||
|
||||
/* Power Button Notification Values */
|
||||
#define NOTIFY_POWER_BUTTON 0x80
|
||||
|
||||
/* Sleep Button Notification Values */
|
||||
#define NOTIFY_SLEEP_BUTTON 0x80
|
||||
|
||||
/* Lid Notification Values */
|
||||
#define NOTIFY_LID_STATUSCHG 0x80
|
||||
|
||||
/* Processor Device Notification Values */
|
||||
#define NOTIFY_CPU_PPCCHG 0x80
|
||||
#define NOTIFY_CPU_CSTATECHG 0x81
|
||||
#define NOTIFY_CPU_THROTLCHG 0x82
|
||||
|
||||
/* User Presence Device Notification Values */
|
||||
#define NOTIFY_USR_PRESNCECHG 0x80
|
||||
|
||||
/* Ambient Light Sensor Notification Values */
|
||||
#define NOTIFY_ALS_ILLUMCHG 0x80
|
||||
#define NOTIFY_ALS_COLORTMPCHG 0x81
|
||||
#define NOTIFY_ALS_RESPCHG 0x82
|
||||
Reference in New Issue
Block a user