GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
+13
@@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <asm/acpi/global_nvs.h>
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OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
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Field(GNVS, ByteAcc, NoLock, Preserve)
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{
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PCNT, 8, /* processor count */
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IURE, 8, /* internal UART enabled */
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}
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@@ -0,0 +1,94 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
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*/
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/* SouthCluster GPIO */
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Device (GPSC)
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{
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Name(_HID, "INT33FC")
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Name(_CID, "INT33FC")
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Name(_UID, 1)
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Name(RBUF, ResourceTemplate()
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{
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Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
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{
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GPIO_SC_IRQ
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}
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})
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Method(_CRS)
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{
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CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
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Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
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Return (^RBUF)
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}
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Method(_STA)
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{
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Return (STA_VISIBLE)
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}
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}
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/* NorthCluster GPIO */
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Device (GPNC)
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{
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Name(_HID, "INT33FC")
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Name(_CID, "INT33FC")
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Name(_UID, 2)
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Name(RBUF, ResourceTemplate()
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{
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Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
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{
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GPIO_NC_IRQ
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}
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})
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Method(_CRS)
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{
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CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
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Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
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Return (^RBUF)
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}
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Method(_STA)
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{
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Return (STA_VISIBLE)
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}
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}
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/* SUS GPIO */
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Device (GPSS)
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{
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Name(_HID, "INT33FC")
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Name(_CID, "INT33FC")
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Name(_UID, 3)
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Name(RBUF, ResourceTemplate()
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{
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Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
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{
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GPIO_SUS_IRQ
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}
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})
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Method(_CRS)
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{
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CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
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Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
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Return (^RBUF)
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}
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Method(_STA)
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{
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Return (STA_VISIBLE)
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}
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}
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@@ -0,0 +1,26 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <asm/arch/device.h>
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#define PCI_DEV_PIRQ_ROUTES \
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PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(EMMC_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SD_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(MMC45_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
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#define PCIE_BRIDGE_IRQ_ROUTES \
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PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D)
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@@ -0,0 +1,198 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
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*/
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/* Intel LPC Bus Device - 0:1f.0 */
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Scope (\)
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{
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/* Intel Legacy Block */
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OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
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Field(ILBS, AnyAcc, NoLock, Preserve) {
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Offset (0x8),
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PRTA, 8,
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PRTB, 8,
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PRTC, 8,
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PRTD, 8,
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PRTE, 8,
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PRTF, 8,
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PRTG, 8,
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PRTH, 8,
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Offset (0x88),
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, 3,
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UI3E, 1,
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UI4E, 1
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}
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}
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Device (LPCB)
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{
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Name(_ADR, 0x001f0000)
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OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
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Field(LPC0, AnyAcc, NoLock, Preserve) {
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Offset(0x08),
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SRID, 8,
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Offset(0x80),
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C1EN, 1,
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Offset(0x84)
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}
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#include <asm/acpi/irqlinks.asl>
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/* Firmware Hub */
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Device (FWH)
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{
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Name(_HID, EISAID("INT0800"))
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Name(_CRS, ResourceTemplate()
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{
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Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
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})
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}
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/* 8259 Interrupt Controller */
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Device (PIC)
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{
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Name(_HID, EISAID("PNP0000"))
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Name(_CRS, ResourceTemplate()
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{
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IO(Decode16, 0x20, 0x20, 0x01, 0x02)
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IO(Decode16, 0x24, 0x24, 0x01, 0x02)
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IO(Decode16, 0x28, 0x28, 0x01, 0x02)
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IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
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IO(Decode16, 0x30, 0x30, 0x01, 0x02)
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IO(Decode16, 0x34, 0x34, 0x01, 0x02)
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IO(Decode16, 0x38, 0x38, 0x01, 0x02)
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IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
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IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
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IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
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IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
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IO(Decode16, 0xac, 0xac, 0x01, 0x02)
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IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
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IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
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IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
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IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
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IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
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IRQNoFlags () { 2 }
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})
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}
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/* 8254 timer */
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Device (TIMR)
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{
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Name(_HID, EISAID("PNP0100"))
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Name(_CRS, ResourceTemplate()
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{
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IO(Decode16, 0x40, 0x40, 0x01, 0x04)
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IO(Decode16, 0x50, 0x50, 0x10, 0x04)
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IRQNoFlags() { 0 }
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})
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}
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/* HPET */
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Device (HPET)
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{
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Name(_HID, EISAID("PNP0103"))
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Name(_CID, 0x010CD041)
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Name(_CRS, ResourceTemplate()
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{
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Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
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})
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Method(_STA)
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{
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Return (STA_VISIBLE)
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}
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}
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/* Internal UART */
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Device (IURT)
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{
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Name(_HID, EISAID("PNP0501"))
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Name(_UID, 1)
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Method(_STA, 0, Serialized)
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{
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If (LEqual(IURE, 1)) {
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Store(1, UI3E)
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Store(1, UI4E)
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Store(1, C1EN)
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Return (STA_VISIBLE)
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} Else {
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Return (STA_MISSING)
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}
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}
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Method(_DIS, 0, Serialized)
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{
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Store(0, UI3E)
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Store(0, UI4E)
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Store(0, C1EN)
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}
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Method(_CRS, 0, Serialized)
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{
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Name(BUF0, ResourceTemplate()
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{
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IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
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IRQNoFlags() { 3 }
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})
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Name(BUF1, ResourceTemplate()
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{
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IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
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IRQNoFlags() { 4 }
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})
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If (LLessEqual(SRID, 0x04)) {
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Return (BUF0)
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} Else {
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Return (BUF1)
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}
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}
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}
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/* Real Time Clock */
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Device (RTC)
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{
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Name(_HID, EISAID("PNP0B00"))
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Name(_CRS, ResourceTemplate()
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{
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IO(Decode16, 0x70, 0x70, 1, 8)
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/*
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* Disable as Windows doesn't like it, and systems
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* don't seem to use it
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*/
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/* IRQNoFlags() { 8 } */
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})
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}
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/* LPC device: Resource consumption */
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Device (LDRC)
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{
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Name(_HID, EISAID("PNP0C02"))
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Name(_UID, 2)
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Name(RBUF, ResourceTemplate()
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{
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IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
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IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
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IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
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})
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Method(_CRS, 0, NotSerialized)
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{
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Return (RBUF)
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}
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}
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}
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@@ -0,0 +1,38 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <asm/acpi/statdef.asl>
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#include <asm/arch/iomap.h>
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#include <asm/arch/irq.h>
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0.
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*/
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Method(_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK, 1)
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{
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Return (Package() {0, 0})
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}
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/* ACPI global NVS */
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#include "global_nvs.asl"
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/* TODO: add CPU ASL support */
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Scope (\_SB)
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{
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#include "southcluster.asl"
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/* ACPI devices */
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#include "gpio.asl"
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}
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/* Chipset specific sleep states */
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#include <asm/acpi/sleepstates.asl>
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+210
@@ -0,0 +1,210 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Google Inc.
|
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
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*
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* Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
|
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*/
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Device (PCI0)
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{
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Name(_HID, EISAID("PNP0A08")) /* PCIe */
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Name(_CID, EISAID("PNP0A03")) /* PCI */
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Name(_ADR, 0)
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Name(_BBN, 0)
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Name(MCRS, ResourceTemplate()
|
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{
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/* Bus Numbers */
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WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
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/* IO Region 0 */
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
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/* PCI Config Space */
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IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
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/* IO Region 1 */
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
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/* VGA memory (0xa0000-0xbffff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
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0x00020000, , , ASEG)
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|
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/* OPROM reserved (0xc0000-0xc3fff) */
|
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
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Cacheable, ReadWrite,
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0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
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0x00004000, , , OPR0)
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/* OPROM reserved (0xc4000-0xc7fff) */
|
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
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Cacheable, ReadWrite,
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0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
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0x00004000, , , OPR1)
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||||
/* OPROM reserved (0xc8000-0xcbfff) */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
|
||||
0x00004000, , , OPR2)
|
||||
|
||||
/* OPROM reserved (0xcc000-0xcffff) */
|
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
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Cacheable, ReadWrite,
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0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
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||||
0x00004000, , , OPR3)
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||||
|
||||
/* OPROM reserved (0xd0000-0xd3fff) */
|
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
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||||
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
|
||||
0x00004000, , , OPR4)
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||||
|
||||
/* OPROM reserved (0xd4000-0xd7fff) */
|
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
|
||||
0x00004000, , , OPR5)
|
||||
|
||||
/* OPROM reserved (0xd8000-0xdbfff) */
|
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
|
||||
0x00004000, , , OPR6)
|
||||
|
||||
/* OPROM reserved (0xdc000-0xdffff) */
|
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
|
||||
0x00004000, , , OPR7)
|
||||
|
||||
/* BIOS Extension (0xe0000-0xe3fff) */
|
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
|
||||
0x00004000, , , ESG0)
|
||||
|
||||
/* BIOS Extension (0xe4000-0xe7fff) */
|
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
|
||||
0x00004000, , , ESG1)
|
||||
|
||||
/* BIOS Extension (0xe8000-0xebfff) */
|
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
|
||||
0x00004000, , , ESG2)
|
||||
|
||||
/* BIOS Extension (0xec000-0xeffff) */
|
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x000ec000, 0x000effff, 0x00000000,
|
||||
0x00004000, , , ESG3)
|
||||
|
||||
/* System BIOS (0xf0000-0xfffff) */
|
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
|
||||
0x00010000, , , FSEG)
|
||||
|
||||
/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
|
||||
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, , , PMEM)
|
||||
|
||||
/* High PCI Memory Region */
|
||||
QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, , , UMEM)
|
||||
})
|
||||
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
/* Update PCI resource area */
|
||||
CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
|
||||
CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
|
||||
CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
|
||||
|
||||
/*
|
||||
* Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
|
||||
*
|
||||
* TODO: for generic usage, read TOLM value from register, or
|
||||
* from global NVS (not implemented by U-Boot yet).
|
||||
*/
|
||||
Store(0x80000000, PMIN)
|
||||
Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
|
||||
Add(Subtract(PMAX, PMIN), 1, PLEN)
|
||||
|
||||
/* Update High PCI resource area */
|
||||
CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
|
||||
CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
|
||||
CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
|
||||
|
||||
/* Set base address to 16GB and allocate 48GB for PCI space */
|
||||
Store(0x400000000, UMIN)
|
||||
Store(0xc00000000, ULEN)
|
||||
Add(UMIN, Subtract(ULEN, 1), UMAX)
|
||||
|
||||
Return (MCRS)
|
||||
}
|
||||
|
||||
/* Device Resource Consumption */
|
||||
Device (PDRC)
|
||||
{
|
||||
Name(_HID, EISAID("PNP0C02"))
|
||||
Name(_UID, 1)
|
||||
|
||||
Name(PDRS, ResourceTemplate() {
|
||||
Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
|
||||
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
|
||||
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
|
||||
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
|
||||
Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
|
||||
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
|
||||
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
|
||||
Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
|
||||
})
|
||||
|
||||
/* Current Resource Settings */
|
||||
Method(_CRS, 0, Serialized)
|
||||
{
|
||||
Return (PDRS)
|
||||
}
|
||||
}
|
||||
|
||||
Method(_OSC, 4)
|
||||
{
|
||||
/* Check for proper GUID */
|
||||
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
|
||||
/* Let OS control everything */
|
||||
Return (Arg3)
|
||||
} Else {
|
||||
/* Unrecognized UUID */
|
||||
CreateDWordField(Arg3, 0, CDW1)
|
||||
Or(CDW1, 4, CDW1)
|
||||
Return (Arg3)
|
||||
}
|
||||
}
|
||||
|
||||
/* LPC Bridge 0:1f.0 */
|
||||
#include "lpc.asl"
|
||||
|
||||
/* USB EHCI 0:1d.0 */
|
||||
#include "usb.asl"
|
||||
|
||||
/* USB XHCI 0:14.0 */
|
||||
#include "xhci.asl"
|
||||
|
||||
/* IRQ routing for each PCI device */
|
||||
#include <asm/acpi/irqroute.asl>
|
||||
}
|
||||
@@ -0,0 +1,33 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
|
||||
*/
|
||||
|
||||
/* EHCI Controller 0:1d.0 */
|
||||
|
||||
Device (EHC1)
|
||||
{
|
||||
Name(_ADR, 0x001d0000)
|
||||
|
||||
/* Power Resources for Wake */
|
||||
Name(_PRW, Package() { 13, 4 })
|
||||
|
||||
/* Highest D state in S3 state */
|
||||
Name(_S3D, 2)
|
||||
|
||||
/* Highest D state in S4 state */
|
||||
Name(_S4D, 2)
|
||||
|
||||
Device (HUB7)
|
||||
{
|
||||
Name(_ADR, 0x00000000)
|
||||
|
||||
Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */
|
||||
Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */
|
||||
Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */
|
||||
Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
|
||||
*/
|
||||
|
||||
/* XHCI Controller 0:14.0 */
|
||||
|
||||
Device (XHCI)
|
||||
{
|
||||
Name(_ADR, 0x00140000)
|
||||
|
||||
/* Power Resources for Wake */
|
||||
Name(_PRW, Package() { 13, 3 })
|
||||
|
||||
/* Highest D state in S3 state */
|
||||
Name(_S3D, 3)
|
||||
|
||||
Device (RHUB)
|
||||
{
|
||||
Name(_ADR, 0x00000000)
|
||||
|
||||
Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */
|
||||
Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */
|
||||
Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */
|
||||
Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,73 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
|
||||
*/
|
||||
|
||||
#ifndef _DEVICE_H_
|
||||
#define _DEVICE_H_
|
||||
|
||||
/*
|
||||
* Internal PCI device numbers within the SoC.
|
||||
*
|
||||
* Note it must start with 0x_ prefix, as the device number macro will be
|
||||
* included in the ACPI ASL files (see irq_helper.h and irq_route.h).
|
||||
*/
|
||||
|
||||
/* SoC transaction router */
|
||||
#define SOC_DEV 0x00
|
||||
|
||||
/* Graphics and Display */
|
||||
#define GFX_DEV 0x02
|
||||
|
||||
/* MIPI */
|
||||
#define MIPI_DEV 0x03
|
||||
|
||||
/* EMMC Port */
|
||||
#define EMMC_DEV 0x10
|
||||
|
||||
/* SDIO Port */
|
||||
#define SDIO_DEV 0x11
|
||||
|
||||
/* SD Port */
|
||||
#define SD_DEV 0x12
|
||||
|
||||
/* SATA */
|
||||
#define SATA_DEV 0x13
|
||||
|
||||
/* xHCI */
|
||||
#define XHCI_DEV 0x14
|
||||
|
||||
/* LPE Audio */
|
||||
#define LPE_DEV 0x15
|
||||
|
||||
/* OTG */
|
||||
#define OTG_DEV 0x16
|
||||
|
||||
/* MMC45 Port */
|
||||
#define MMC45_DEV 0x17
|
||||
|
||||
/* Serial IO 1 */
|
||||
#define SIO1_DEV 0x18
|
||||
|
||||
/* Trusted Execution Engine */
|
||||
#define TXE_DEV 0x1a
|
||||
|
||||
/* HD Audio */
|
||||
#define HDA_DEV 0x1b
|
||||
|
||||
/* PCIe Ports */
|
||||
#define PCIE_DEV 0x1c
|
||||
|
||||
/* EHCI */
|
||||
#define EHCI_DEV 0x1d
|
||||
|
||||
/* Serial IO 2 */
|
||||
#define SIO2_DEV 0x1e
|
||||
|
||||
/* Platform Controller Unit */
|
||||
#define PCU_DEV 0x1f
|
||||
|
||||
#endif /* _DEVICE_H_ */
|
||||
+105
@@ -0,0 +1,105 @@
|
||||
/* SPDX-License-Identifier: Intel */
|
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __FSP_CONFIGS_H__
|
||||
#define __FSP_CONFIGS_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct fsp_config_data {
|
||||
struct fsp_cfg_common common;
|
||||
struct upd_region fsp_upd;
|
||||
};
|
||||
|
||||
struct fspinit_rtbuf {
|
||||
struct common_buf common; /* FSP common runtime data structure */
|
||||
};
|
||||
#endif
|
||||
|
||||
/* FSP user configuration settings */
|
||||
|
||||
#define MRC_INIT_TSEG_SIZE_1MB 1
|
||||
#define MRC_INIT_TSEG_SIZE_2MB 2
|
||||
#define MRC_INIT_TSEG_SIZE_4MB 4
|
||||
#define MRC_INIT_TSEG_SIZE_8MB 8
|
||||
|
||||
#define MRC_INIT_MMIO_SIZE_1024MB 0x400
|
||||
#define MRC_INIT_MMIO_SIZE_1536MB 0x600
|
||||
#define MRC_INIT_MMIO_SIZE_2048MB 0x800
|
||||
|
||||
#define EMMC_BOOT_MODE_DISABLED 0
|
||||
#define EMMC_BOOT_MODE_AUTO 1
|
||||
#define EMMC_BOOT_MODE_EMMC41 2
|
||||
#define EMMC_BOOT_MODE_EMCC45 3
|
||||
|
||||
#define SATA_MODE_IDE 0
|
||||
#define SATA_MODE_AHCI 1
|
||||
|
||||
#define IGD_DVMT50_PRE_ALLOC_32MB 0x01
|
||||
#define IGD_DVMT50_PRE_ALLOC_64MB 0x02
|
||||
#define IGD_DVMT50_PRE_ALLOC_96MB 0x03
|
||||
#define IGD_DVMT50_PRE_ALLOC_128MB 0x04
|
||||
#define IGD_DVMT50_PRE_ALLOC_160MB 0x05
|
||||
#define IGD_DVMT50_PRE_ALLOC_192MB 0x06
|
||||
#define IGD_DVMT50_PRE_ALLOC_224MB 0x07
|
||||
#define IGD_DVMT50_PRE_ALLOC_256MB 0x08
|
||||
#define IGD_DVMT50_PRE_ALLOC_288MB 0x09
|
||||
#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a
|
||||
#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b
|
||||
#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c
|
||||
#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d
|
||||
#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e
|
||||
#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f
|
||||
#define IGD_DVMT50_PRE_ALLOC_512MB 0x10
|
||||
|
||||
#define APERTURE_SIZE_128MB 1
|
||||
#define APERTURE_SIZE_256MB 2
|
||||
#define APERTURE_SIZE_512MB 3
|
||||
|
||||
#define GTT_SIZE_1MB 1
|
||||
#define GTT_SIZE_2MB 2
|
||||
|
||||
#define OS_SELECTION_ANDROID 1
|
||||
#define OS_SELECTION_LINUX 4
|
||||
|
||||
#define DRAM_SPEED_800MTS 0
|
||||
#define DRAM_SPEED_1066MTS 1
|
||||
#define DRAM_SPEED_1333MTS 2
|
||||
#define DRAM_SPEED_1600MTS 3
|
||||
|
||||
#define DRAM_TYPE_DDR3 0
|
||||
#define DRAM_TYPE_DDR3L 1
|
||||
#define DRAM_TYPE_DDR3ECC 2
|
||||
#define DRAM_TYPE_LPDDR2 4
|
||||
#define DRAM_TYPE_LPDDR3 5
|
||||
#define DRAM_TYPE_DDR4 6
|
||||
|
||||
#define DIMM_WIDTH_X8 0
|
||||
#define DIMM_WIDTH_X16 1
|
||||
#define DIMM_WIDTH_X32 2
|
||||
|
||||
#define DIMM_DENSITY_1GBIT 0
|
||||
#define DIMM_DENSITY_2GBIT 1
|
||||
#define DIMM_DENSITY_4GBIT 2
|
||||
#define DIMM_DENSITY_8GBIT 3
|
||||
|
||||
#define DIMM_BUS_WIDTH_8BITS 0
|
||||
#define DIMM_BUS_WIDTH_16BITS 1
|
||||
#define DIMM_BUS_WIDTH_32BITS 2
|
||||
#define DIMM_BUS_WIDTH_64BITS 3
|
||||
|
||||
#define DIMM_SIDES_1RANKS 0
|
||||
#define DIMM_SIDES_2RANKS 1
|
||||
|
||||
#define LPE_MODE_DISABLED 0
|
||||
#define LPE_MODE_PCI 1
|
||||
#define LPE_MODE_ACPI 2
|
||||
|
||||
#define LPSS_SIO_MODE_ACPI 0
|
||||
#define LPSS_SIO_MODE_PCI 1
|
||||
|
||||
#define SCC_MODE_ACPI 0
|
||||
#define SCC_MODE_PCI 1
|
||||
|
||||
#endif /* __FSP_CONFIGS_H__ */
|
||||
@@ -0,0 +1,93 @@
|
||||
/* SPDX-License-Identifier: Intel */
|
||||
/*
|
||||
* Copyright (C) 2013, Intel Corporation
|
||||
* Copyright (C) 2015 Google, Inc
|
||||
*/
|
||||
|
||||
#ifndef __FSP_VPD_H
|
||||
#define __FSP_VPD_H
|
||||
|
||||
struct memory_down_data {
|
||||
uint8_t enable_memory_down;
|
||||
uint8_t dram_speed;
|
||||
uint8_t dram_type;
|
||||
uint8_t dimm_0_enable;
|
||||
uint8_t dimm_1_enable;
|
||||
uint8_t dimm_width;
|
||||
uint8_t dimm_density;
|
||||
uint8_t dimm_bus_width;
|
||||
uint8_t dimm_sides; /* Ranks Per dimm_ */
|
||||
uint8_t dimm_tcl; /* tCL */
|
||||
/* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
|
||||
uint8_t dimm_trpt_rcd;
|
||||
uint8_t dimm_twr; /* tWR in DRAM clk */
|
||||
uint8_t dimm_twtr; /* tWTR in DRAM clk */
|
||||
uint8_t dimm_trrd; /* tRRD in DRAM clk */
|
||||
uint8_t dimm_trtp; /* tRTP in DRAM clk */
|
||||
uint8_t dimm_tfaw; /* tFAW in DRAM clk */
|
||||
};
|
||||
|
||||
struct __packed upd_region {
|
||||
uint64_t signature; /* Offset 0x0000 */
|
||||
uint8_t reserved0[24]; /* Offset 0x0008 */
|
||||
uint16_t mrc_init_tseg_size; /* Offset 0x0020 */
|
||||
uint16_t mrc_init_mmio_size; /* Offset 0x0022 */
|
||||
uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */
|
||||
uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */
|
||||
uint8_t emmc_boot_mode; /* Offset 0x0026 */
|
||||
uint8_t enable_sdio; /* Offset 0x0027 */
|
||||
uint8_t enable_sdcard; /* Offset 0x0028 */
|
||||
uint8_t enable_hsuart0; /* Offset 0x0029 */
|
||||
uint8_t enable_hsuart1; /* Offset 0x002a */
|
||||
uint8_t enable_spi; /* Offset 0x002b */
|
||||
uint8_t reserved1; /* Offset 0x002c */
|
||||
uint8_t enable_sata; /* Offset 0x002d */
|
||||
uint8_t sata_mode; /* Offset 0x002e */
|
||||
uint8_t enable_azalia; /* Offset 0x002f */
|
||||
struct azalia_config *azalia_cfg_ptr; /* Offset 0x0030 */
|
||||
uint8_t enable_xhci; /* Offset 0x0034 */
|
||||
uint8_t lpe_mode; /* Offset 0x0035 */
|
||||
uint8_t lpss_sio_mode; /* Offset 0x0036 */
|
||||
uint8_t enable_dma0; /* Offset 0x0037 */
|
||||
uint8_t enable_dma1; /* Offset 0x0038 */
|
||||
uint8_t enable_i2_c0; /* Offset 0x0039 */
|
||||
uint8_t enable_i2_c1; /* Offset 0x003a */
|
||||
uint8_t enable_i2_c2; /* Offset 0x003b */
|
||||
uint8_t enable_i2_c3; /* Offset 0x003c */
|
||||
uint8_t enable_i2_c4; /* Offset 0x003d */
|
||||
uint8_t enable_i2_c5; /* Offset 0x003e */
|
||||
uint8_t enable_i2_c6; /* Offset 0x003f */
|
||||
uint8_t enable_pwm0; /* Offset 0x0040 */
|
||||
uint8_t enable_pwm1; /* Offset 0x0041 */
|
||||
uint8_t enable_hsi; /* Offset 0x0042 */
|
||||
uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */
|
||||
uint8_t aperture_size; /* Offset 0x0044 */
|
||||
uint8_t gtt_size; /* Offset 0x0045 */
|
||||
uint8_t reserved2[5]; /* Offset 0x0046 */
|
||||
uint8_t mrc_debug_msg; /* Offset 0x004b */
|
||||
uint8_t isp_enable; /* Offset 0x004c */
|
||||
uint8_t scc_mode; /* Offset 0x004d */
|
||||
uint8_t igd_render_standby; /* Offset 0x004e */
|
||||
uint8_t txe_uma_enable; /* Offset 0x004f */
|
||||
uint8_t os_selection; /* Offset 0x0050 */
|
||||
uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */
|
||||
uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */
|
||||
uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */
|
||||
uint8_t enable_igd; /* Offset 0x0054 */
|
||||
uint8_t unused_upd_space1[155]; /* Offset 0x0055 */
|
||||
struct memory_down_data memory_params; /* Offset 0x00f0 */
|
||||
uint16_t terminator; /* Offset 0x0100 */
|
||||
};
|
||||
|
||||
#define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */
|
||||
|
||||
struct __packed vpd_region {
|
||||
uint64_t sign; /* Offset 0x0000 */
|
||||
uint32_t img_rev; /* Offset 0x0008 */
|
||||
uint32_t upd_offset; /* Offset 0x000c */
|
||||
uint8_t unused[16]; /* Offset 0x0010 */
|
||||
uint32_t fsp_res_memlen; /* Offset 0x0020 */
|
||||
uint8_t platform_type; /* Offset 0x0024 */
|
||||
uint8_t enable_secure_boot; /* Offset 0x0025 */
|
||||
};
|
||||
#endif
|
||||
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _GLOBAL_NVS_H_
|
||||
#define _GLOBAL_NVS_H_
|
||||
|
||||
struct __packed acpi_global_nvs {
|
||||
u8 pcnt; /* processor count */
|
||||
u8 iuart_en; /* internal UART enabled */
|
||||
|
||||
/*
|
||||
* Add padding so sizeof(struct acpi_global_nvs) == 0x100.
|
||||
* This must match the size defined in the global_nvs.asl.
|
||||
*/
|
||||
u8 rsvd[254];
|
||||
};
|
||||
|
||||
#endif /* _GLOBAL_NVS_H_ */
|
||||
@@ -0,0 +1,93 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
|
||||
*/
|
||||
|
||||
#ifndef _BAYTRAIL_IOMAP_H_
|
||||
#define _BAYTRAIL_IOMAP_H_
|
||||
|
||||
/* Memory Mapped IO bases */
|
||||
|
||||
/* PCI Configuration Space */
|
||||
#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
|
||||
#define MCFG_BASE_SIZE 0x10000000
|
||||
|
||||
/* Temporary Base Address */
|
||||
#define TEMP_BASE_ADDRESS 0xfd000000
|
||||
|
||||
/* Transactions in this range will abort */
|
||||
#define ABORT_BASE_ADDRESS 0xfeb00000
|
||||
#define ABORT_BASE_SIZE 0x00100000
|
||||
|
||||
/* High Performance Event Timer */
|
||||
#define HPET_BASE_ADDRESS 0xfed00000
|
||||
#define HPET_BASE_SIZE 0x400
|
||||
|
||||
/* SPI Bus */
|
||||
#define SPI_BASE_ADDRESS 0xfed01000
|
||||
#define SPI_BASE_SIZE 0x400
|
||||
|
||||
/* Power Management Controller */
|
||||
#define PMC_BASE_ADDRESS 0xfed03000
|
||||
#define PMC_BASE_SIZE 0x400
|
||||
|
||||
#define GEN_PMCON1 0x20
|
||||
#define UART_EN (1 << 24)
|
||||
#define DISB (1 << 23)
|
||||
#define MEM_SR (1 << 21)
|
||||
#define SRS (1 << 20)
|
||||
#define CTS (1 << 19)
|
||||
#define MS4V (1 << 18)
|
||||
#define PWR_FLR (1 << 16)
|
||||
#define PME_B0_S5_DIS (1 << 15)
|
||||
#define SUS_PWR_FLR (1 << 14)
|
||||
#define WOL_EN_OVRD (1 << 13)
|
||||
#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
|
||||
#define GEN_RST_STS (1 << 9)
|
||||
#define RPS (1 << 2)
|
||||
#define AFTERG3_EN (1 << 0)
|
||||
#define GEN_PMCON2 0x24
|
||||
#define SLPSX_STR_POL_LOCK (1 << 18)
|
||||
#define BIOS_PCI_EXP_EN (1 << 10)
|
||||
#define PWRBTN_LVL (1 << 9)
|
||||
#define SMI_LOCK (1 << 4)
|
||||
|
||||
/* Power Management Unit */
|
||||
#define PUNIT_BASE_ADDRESS 0xfed05000
|
||||
#define PUNIT_BASE_SIZE 0x800
|
||||
|
||||
/* Intel Legacy Block */
|
||||
#define ILB_BASE_ADDRESS 0xfed08000
|
||||
#define ILB_BASE_SIZE 0x400
|
||||
|
||||
/* IO Memory */
|
||||
#define IO_BASE_ADDRESS 0xfed0c000
|
||||
#define IO_BASE_OFFSET_GPSCORE 0x0000
|
||||
#define IO_BASE_OFFSET_GPNCORE 0x1000
|
||||
#define IO_BASE_OFFSET_GPSSUS 0x2000
|
||||
#define IO_BASE_SIZE 0x4000
|
||||
|
||||
/* Root Complex Base Address */
|
||||
#define RCBA_BASE_ADDRESS 0xfed1c000
|
||||
#define RCBA_BASE_SIZE 0x400
|
||||
|
||||
/* MODPHY */
|
||||
#define MPHY_BASE_ADDRESS 0xfef00000
|
||||
#define MPHY_BASE_SIZE 0x100000
|
||||
|
||||
/* IO Port bases */
|
||||
#define ACPI_BASE_ADDRESS 0x0400
|
||||
#define ACPI_BASE_SIZE 0x80
|
||||
|
||||
#define PM1_STS 0x00
|
||||
#define PM1_CNT 0x04
|
||||
|
||||
#define GPIO_BASE_ADDRESS 0x0500
|
||||
#define GPIO_BASE_SIZE 0x100
|
||||
|
||||
#define SMBUS_BASE_ADDRESS 0xefa0
|
||||
|
||||
#endif /* _BAYTRAIL_IOMAP_H_ */
|
||||
@@ -0,0 +1,85 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
|
||||
*
|
||||
* Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
|
||||
*/
|
||||
|
||||
#ifndef _BAYTRAIL_IRQ_H_
|
||||
#define _BAYTRAIL_IRQ_H_
|
||||
|
||||
#define PIRQA_APIC_IRQ 16
|
||||
#define PIRQB_APIC_IRQ 17
|
||||
#define PIRQC_APIC_IRQ 18
|
||||
#define PIRQD_APIC_IRQ 19
|
||||
#define PIRQE_APIC_IRQ 20
|
||||
#define PIRQF_APIC_IRQ 21
|
||||
#define PIRQG_APIC_IRQ 22
|
||||
#define PIRQH_APIC_IRQ 23
|
||||
|
||||
/* The below IRQs are for when devices are in ACPI mode */
|
||||
#define LPE_DMA0_IRQ 24
|
||||
#define LPE_DMA1_IRQ 25
|
||||
#define LPE_SSP0_IRQ 26
|
||||
#define LPE_SSP1_IRQ 27
|
||||
#define LPE_SSP2_IRQ 28
|
||||
#define LPE_IPC2HOST_IRQ 29
|
||||
#define LPSS_I2C1_IRQ 32
|
||||
#define LPSS_I2C2_IRQ 33
|
||||
#define LPSS_I2C3_IRQ 34
|
||||
#define LPSS_I2C4_IRQ 35
|
||||
#define LPSS_I2C5_IRQ 36
|
||||
#define LPSS_I2C6_IRQ 37
|
||||
#define LPSS_I2C7_IRQ 38
|
||||
#define LPSS_HSUART1_IRQ 39
|
||||
#define LPSS_HSUART2_IRQ 40
|
||||
#define LPSS_SPI_IRQ 41
|
||||
#define LPSS_DMA1_IRQ 42
|
||||
#define LPSS_DMA2_IRQ 43
|
||||
#define SCC_EMMC_IRQ 44
|
||||
#define SCC_SDIO_IRQ 46
|
||||
#define SCC_SD_IRQ 47
|
||||
#define GPIO_NC_IRQ 48
|
||||
#define GPIO_SC_IRQ 49
|
||||
#define GPIO_SUS_IRQ 50
|
||||
/* GPIO direct / dedicated IRQs */
|
||||
#define GPIO_S0_DED_IRQ_0 51
|
||||
#define GPIO_S0_DED_IRQ_1 52
|
||||
#define GPIO_S0_DED_IRQ_2 53
|
||||
#define GPIO_S0_DED_IRQ_3 54
|
||||
#define GPIO_S0_DED_IRQ_4 55
|
||||
#define GPIO_S0_DED_IRQ_5 56
|
||||
#define GPIO_S0_DED_IRQ_6 57
|
||||
#define GPIO_S0_DED_IRQ_7 58
|
||||
#define GPIO_S0_DED_IRQ_8 59
|
||||
#define GPIO_S0_DED_IRQ_9 60
|
||||
#define GPIO_S0_DED_IRQ_10 61
|
||||
#define GPIO_S0_DED_IRQ_11 62
|
||||
#define GPIO_S0_DED_IRQ_12 63
|
||||
#define GPIO_S0_DED_IRQ_13 64
|
||||
#define GPIO_S0_DED_IRQ_14 65
|
||||
#define GPIO_S0_DED_IRQ_15 66
|
||||
#define GPIO_S5_DED_IRQ_0 67
|
||||
#define GPIO_S5_DED_IRQ_1 68
|
||||
#define GPIO_S5_DED_IRQ_2 69
|
||||
#define GPIO_S5_DED_IRQ_3 70
|
||||
#define GPIO_S5_DED_IRQ_4 71
|
||||
#define GPIO_S5_DED_IRQ_5 72
|
||||
#define GPIO_S5_DED_IRQ_6 73
|
||||
#define GPIO_S5_DED_IRQ_7 74
|
||||
#define GPIO_S5_DED_IRQ_8 75
|
||||
#define GPIO_S5_DED_IRQ_9 76
|
||||
#define GPIO_S5_DED_IRQ_10 77
|
||||
#define GPIO_S5_DED_IRQ_11 78
|
||||
#define GPIO_S5_DED_IRQ_12 79
|
||||
#define GPIO_S5_DED_IRQ_13 80
|
||||
#define GPIO_S5_DED_IRQ_14 81
|
||||
#define GPIO_S5_DED_IRQ_15 82
|
||||
/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
|
||||
#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot
|
||||
#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot
|
||||
#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot)
|
||||
#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot)
|
||||
|
||||
#endif /* _BAYTRAIL_IRQ_H_ */
|
||||
Reference in New Issue
Block a user