GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/* SPDX-License-Identifier: Intel */
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*/
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#ifndef __FSP_CONFIGS_H__
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#define __FSP_CONFIGS_H__
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#ifndef __ASSEMBLY__
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struct fsp_config_data {
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struct fsp_cfg_common common;
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struct upd_region fsp_upd;
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};
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struct fspinit_rtbuf {
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struct common_buf common; /* FSP common runtime data structure */
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};
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#endif
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/* FSP user configuration settings */
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#define MRC_INIT_TSEG_SIZE_1MB 1
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#define MRC_INIT_TSEG_SIZE_2MB 2
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#define MRC_INIT_TSEG_SIZE_4MB 4
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#define MRC_INIT_TSEG_SIZE_8MB 8
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#define MRC_INIT_MMIO_SIZE_1024MB 0x400
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#define MRC_INIT_MMIO_SIZE_1536MB 0x600
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#define MRC_INIT_MMIO_SIZE_2048MB 0x800
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#define EMMC_BOOT_MODE_DISABLED 0
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#define EMMC_BOOT_MODE_AUTO 1
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#define EMMC_BOOT_MODE_EMMC41 2
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#define EMMC_BOOT_MODE_EMCC45 3
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#define SATA_MODE_IDE 0
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#define SATA_MODE_AHCI 1
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#define IGD_DVMT50_PRE_ALLOC_32MB 0x01
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#define IGD_DVMT50_PRE_ALLOC_64MB 0x02
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#define IGD_DVMT50_PRE_ALLOC_96MB 0x03
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#define IGD_DVMT50_PRE_ALLOC_128MB 0x04
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#define IGD_DVMT50_PRE_ALLOC_160MB 0x05
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#define IGD_DVMT50_PRE_ALLOC_192MB 0x06
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#define IGD_DVMT50_PRE_ALLOC_224MB 0x07
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#define IGD_DVMT50_PRE_ALLOC_256MB 0x08
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#define IGD_DVMT50_PRE_ALLOC_288MB 0x09
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#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a
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#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b
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#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c
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#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d
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#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e
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#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f
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#define IGD_DVMT50_PRE_ALLOC_512MB 0x10
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#define APERTURE_SIZE_128MB 1
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#define APERTURE_SIZE_256MB 2
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#define APERTURE_SIZE_512MB 3
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#define GTT_SIZE_1MB 1
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#define GTT_SIZE_2MB 2
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#define OS_SELECTION_ANDROID 1
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#define OS_SELECTION_LINUX 4
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#define DRAM_SPEED_800MTS 0
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#define DRAM_SPEED_1066MTS 1
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#define DRAM_SPEED_1333MTS 2
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#define DRAM_SPEED_1600MTS 3
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#define DRAM_TYPE_DDR3 0
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#define DRAM_TYPE_DDR3L 1
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#define DRAM_TYPE_DDR3ECC 2
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#define DRAM_TYPE_LPDDR2 4
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#define DRAM_TYPE_LPDDR3 5
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#define DRAM_TYPE_DDR4 6
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#define DIMM_WIDTH_X8 0
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#define DIMM_WIDTH_X16 1
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#define DIMM_WIDTH_X32 2
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#define DIMM_DENSITY_1GBIT 0
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#define DIMM_DENSITY_2GBIT 1
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#define DIMM_DENSITY_4GBIT 2
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#define DIMM_DENSITY_8GBIT 3
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#define DIMM_BUS_WIDTH_8BITS 0
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#define DIMM_BUS_WIDTH_16BITS 1
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#define DIMM_BUS_WIDTH_32BITS 2
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#define DIMM_BUS_WIDTH_64BITS 3
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#define DIMM_SIDES_1RANKS 0
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#define DIMM_SIDES_2RANKS 1
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#define LPE_MODE_DISABLED 0
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#define LPE_MODE_PCI 1
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#define LPE_MODE_ACPI 2
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#define LPSS_SIO_MODE_ACPI 0
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#define LPSS_SIO_MODE_PCI 1
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#define SCC_MODE_ACPI 0
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#define SCC_MODE_PCI 1
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#endif /* __FSP_CONFIGS_H__ */
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@@ -0,0 +1,93 @@
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/* SPDX-License-Identifier: Intel */
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/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2015 Google, Inc
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*/
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#ifndef __FSP_VPD_H
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#define __FSP_VPD_H
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struct memory_down_data {
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uint8_t enable_memory_down;
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uint8_t dram_speed;
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uint8_t dram_type;
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uint8_t dimm_0_enable;
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uint8_t dimm_1_enable;
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uint8_t dimm_width;
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uint8_t dimm_density;
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uint8_t dimm_bus_width;
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uint8_t dimm_sides; /* Ranks Per dimm_ */
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uint8_t dimm_tcl; /* tCL */
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/* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
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uint8_t dimm_trpt_rcd;
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uint8_t dimm_twr; /* tWR in DRAM clk */
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uint8_t dimm_twtr; /* tWTR in DRAM clk */
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uint8_t dimm_trrd; /* tRRD in DRAM clk */
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uint8_t dimm_trtp; /* tRTP in DRAM clk */
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uint8_t dimm_tfaw; /* tFAW in DRAM clk */
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};
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struct __packed upd_region {
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uint64_t signature; /* Offset 0x0000 */
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uint8_t reserved0[24]; /* Offset 0x0008 */
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uint16_t mrc_init_tseg_size; /* Offset 0x0020 */
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uint16_t mrc_init_mmio_size; /* Offset 0x0022 */
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uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */
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uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */
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uint8_t emmc_boot_mode; /* Offset 0x0026 */
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uint8_t enable_sdio; /* Offset 0x0027 */
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uint8_t enable_sdcard; /* Offset 0x0028 */
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uint8_t enable_hsuart0; /* Offset 0x0029 */
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uint8_t enable_hsuart1; /* Offset 0x002a */
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uint8_t enable_spi; /* Offset 0x002b */
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uint8_t reserved1; /* Offset 0x002c */
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uint8_t enable_sata; /* Offset 0x002d */
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uint8_t sata_mode; /* Offset 0x002e */
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uint8_t enable_azalia; /* Offset 0x002f */
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struct azalia_config *azalia_cfg_ptr; /* Offset 0x0030 */
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uint8_t enable_xhci; /* Offset 0x0034 */
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uint8_t lpe_mode; /* Offset 0x0035 */
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uint8_t lpss_sio_mode; /* Offset 0x0036 */
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uint8_t enable_dma0; /* Offset 0x0037 */
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uint8_t enable_dma1; /* Offset 0x0038 */
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uint8_t enable_i2_c0; /* Offset 0x0039 */
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uint8_t enable_i2_c1; /* Offset 0x003a */
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uint8_t enable_i2_c2; /* Offset 0x003b */
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uint8_t enable_i2_c3; /* Offset 0x003c */
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uint8_t enable_i2_c4; /* Offset 0x003d */
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uint8_t enable_i2_c5; /* Offset 0x003e */
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uint8_t enable_i2_c6; /* Offset 0x003f */
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uint8_t enable_pwm0; /* Offset 0x0040 */
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uint8_t enable_pwm1; /* Offset 0x0041 */
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uint8_t enable_hsi; /* Offset 0x0042 */
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uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */
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uint8_t aperture_size; /* Offset 0x0044 */
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uint8_t gtt_size; /* Offset 0x0045 */
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uint8_t reserved2[5]; /* Offset 0x0046 */
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uint8_t mrc_debug_msg; /* Offset 0x004b */
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uint8_t isp_enable; /* Offset 0x004c */
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uint8_t scc_mode; /* Offset 0x004d */
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uint8_t igd_render_standby; /* Offset 0x004e */
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uint8_t txe_uma_enable; /* Offset 0x004f */
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uint8_t os_selection; /* Offset 0x0050 */
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uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */
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uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */
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uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */
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uint8_t enable_igd; /* Offset 0x0054 */
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uint8_t unused_upd_space1[155]; /* Offset 0x0055 */
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struct memory_down_data memory_params; /* Offset 0x00f0 */
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uint16_t terminator; /* Offset 0x0100 */
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};
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#define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */
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struct __packed vpd_region {
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uint64_t sign; /* Offset 0x0000 */
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uint32_t img_rev; /* Offset 0x0008 */
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uint32_t upd_offset; /* Offset 0x000c */
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uint8_t unused[16]; /* Offset 0x0010 */
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uint32_t fsp_res_memlen; /* Offset 0x0020 */
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uint8_t platform_type; /* Offset 0x0024 */
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uint8_t enable_secure_boot; /* Offset 0x0025 */
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};
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#endif
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