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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/bootloader/u-boot-2020.01/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
*/
#ifndef __FSP_CONFIGS_H__
#define __FSP_CONFIGS_H__
#ifndef __ASSEMBLY__
struct fsp_config_data {
struct fsp_cfg_common common;
struct upd_region fsp_upd;
};
struct fspinit_rtbuf {
struct common_buf common; /* FSP common runtime data structure */
};
#endif
/* FSP user configuration settings */
#define MRC_INIT_TSEG_SIZE_1MB 1
#define MRC_INIT_TSEG_SIZE_2MB 2
#define MRC_INIT_TSEG_SIZE_4MB 4
#define MRC_INIT_TSEG_SIZE_8MB 8
#define MRC_INIT_MMIO_SIZE_1024MB 0x400
#define MRC_INIT_MMIO_SIZE_1536MB 0x600
#define MRC_INIT_MMIO_SIZE_2048MB 0x800
#define IGD_DVMT50_PRE_ALLOC_32MB 0x01
#define IGD_DVMT50_PRE_ALLOC_64MB 0x02
#define IGD_DVMT50_PRE_ALLOC_96MB 0x03
#define IGD_DVMT50_PRE_ALLOC_128MB 0x04
#define IGD_DVMT50_PRE_ALLOC_160MB 0x05
#define IGD_DVMT50_PRE_ALLOC_192MB 0x06
#define IGD_DVMT50_PRE_ALLOC_224MB 0x07
#define IGD_DVMT50_PRE_ALLOC_256MB 0x08
#define IGD_DVMT50_PRE_ALLOC_288MB 0x09
#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a
#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b
#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c
#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d
#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e
#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f
#define IGD_DVMT50_PRE_ALLOC_512MB 0x10
#define APERTURE_SIZE_128MB 1
#define APERTURE_SIZE_256MB 2
#define APERTURE_SIZE_512MB 3
#define GTT_SIZE_1MB 1
#define GTT_SIZE_2MB 2
#define DRAM_TYPE_DDR3 0
#define DRAM_TYPE_LPDDR3 1
#define SDCARD_MODE_DISABLED 0
#define SDCARD_MODE_PCI 1
#define SDCARD_MODE_ACPI 2
#define LPE_MODE_DISABLED 0
#define LPE_MODE_PCI 1
#define LPE_MODE_ACPI 2
#define CHV_SVID_CONFIG_0 0
#define CHV_SVID_CONFIG_1 1
#define CHV_SVID_CONFIG_2 2
#define CHV_SVID_CONFIG_3 3
#define EMMC_MODE_DISABLED 0
#define EMMC_MODE_PCI 1
#define EMMC_MODE_ACPI 2
#define SATA_SPEED_GEN1 1
#define SATA_SPEED_GEN2 2
#define SATA_SPEED_GEN3 3
#define ISP_PCI_DEV_CONFIG_1 1
#define ISP_PCI_DEV_CONFIG_2 2
#define ISP_PCI_DEV_CONFIG_3 3
#define PNP_SETTING_DISABLED 0
#define PNP_SETTING_POWER 1
#define PNP_SETTING_PERF 2
#define PNP_SETTING_POWER_AND_PERF 3
#endif /* __FSP_CONFIGS_H__ */
source/bootloader/u-boot-2020.01/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
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/* SPDX-License-Identifier: Intel */
/*
* Copyright (C) 2015, Intel Corporation
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
*/
#ifndef __FSP_VPD_H__
#define __FSP_VPD_H__
struct __packed memory_upd {
u64 signature; /* Offset 0x0020 */
u8 revision; /* Offset 0x0028 */
u8 unused2[7]; /* Offset 0x0029 */
u16 mrc_init_tseg_size; /* Offset 0x0030 */
u16 mrc_init_mmio_size; /* Offset 0x0032 */
u8 mrc_init_spd_addr1; /* Offset 0x0034 */
u8 mrc_init_spd_addr2; /* Offset 0x0035 */
u8 mem_ch0_config; /* Offset 0x0036 */
u8 mem_ch1_config; /* Offset 0x0037 */
u32 memory_spd_ptr; /* Offset 0x0038 */
u8 igd_dvmt50_pre_alloc; /* Offset 0x003c */
u8 aperture_size; /* Offset 0x003d */
u8 gtt_size; /* Offset 0x003e */
u8 legacy_seg_decode; /* Offset 0x003f */
u8 enable_dvfs; /* Offset 0x0040 */
u8 memory_type; /* Offset 0x0041 */
u8 enable_ca_mirror; /* Offset 0x0042 */
u8 reserved[189]; /* Offset 0x0043 */
};
struct gpio_family {
u32 confg;
u32 confg_changes;
u32 misc;
u32 mmio_addr;
wchar_t *name;
};
struct gpio_pad {
u32 confg0;
u32 confg0_changes;
u32 confg1;
u32 confg1_changes;
u32 community;
u32 mmio_addr;
wchar_t *name;
u32 misc;
};
struct __packed silicon_upd {
u64 signature; /* Offset 0x0100 */
u8 revision; /* Offset 0x0108 */
u8 unused3[7]; /* Offset 0x0109 */
u8 sdcard_mode; /* Offset 0x0110 */
u8 enable_hsuart0; /* Offset 0x0111 */
u8 enable_hsuart1; /* Offset 0x0112 */
u8 enable_azalia; /* Offset 0x0113 */
struct azalia_config *azalia_cfg_ptr; /* Offset 0x0114 */
u8 enable_sata; /* Offset 0x0118 */
u8 enable_xhci; /* Offset 0x0119 */
u8 lpe_mode; /* Offset 0x011a */
u8 enable_dma0; /* Offset 0x011b */
u8 enable_dma1; /* Offset 0x011c */
u8 enable_i2c0; /* Offset 0x011d */
u8 enable_i2c1; /* Offset 0x011e */
u8 enable_i2c2; /* Offset 0x011f */
u8 enable_i2c3; /* Offset 0x0120 */
u8 enable_i2c4; /* Offset 0x0121 */
u8 enable_i2c5; /* Offset 0x0122 */
u8 enable_i2c6; /* Offset 0x0123 */
u32 graphics_config_ptr; /* Offset 0x0124 */
struct gpio_family *gpio_familiy_ptr; /* Offset 0x0128 */
struct gpio_pad *gpio_pad_ptr; /* Offset 0x012c */
u8 disable_punit_pwr_config; /* Offset 0x0130 */
u8 chv_svid_config; /* Offset 0x0131 */
u8 disable_dptf; /* Offset 0x0132 */
u8 emmc_mode; /* Offset 0x0133 */
u8 usb3_clk_ssc; /* Offset 0x0134 */
u8 disp_clk_ssc; /* Offset 0x0135 */
u8 sata_clk_ssc; /* Offset 0x0136 */
u8 usb2_port0_pe_txi_set; /* Offset 0x0137 */
u8 usb2_port0_txi_set; /* Offset 0x0138 */
u8 usb2_port0_tx_emphasis_en; /* Offset 0x0139 */
u8 usb2_port0_tx_pe_half; /* Offset 0x013a */
u8 usb2_port1_pe_txi_set; /* Offset 0x013b */
u8 usb2_port1_txi_set; /* Offset 0x013c */
u8 usb2_port1_tx_emphasis_en; /* Offset 0x013d */
u8 usb2_port1_tx_pe_half; /* Offset 0x013e */
u8 usb2_port2_pe_txi_set; /* Offset 0x013f */
u8 usb2_port2_txi_set; /* Offset 0x0140 */
u8 usb2_port2_tx_emphasis_en; /* Offset 0x0141 */
u8 usb2_port2_tx_pe_half; /* Offset 0x0142 */
u8 usb2_port3_pe_txi_set; /* Offset 0x0143 */
u8 usb2_port3_txi_set; /* Offset 0x0144 */
u8 usb2_port3_tx_emphasis_en; /* Offset 0x0145 */
u8 usb2_port3_tx_pe_half; /* Offset 0x0146 */
u8 usb2_port4_pe_txi_set; /* Offset 0x0147 */
u8 usb2_port4_txi_set; /* Offset 0x0148 */
u8 usb2_port4_tx_emphasis_en; /* Offset 0x0149 */
u8 usb2_port4_tx_pe_half; /* Offset 0x014a */
u8 usb3_lane0_ow2tap_gen2_deemph3p5; /* Offset 0x014b */
u8 usb3_lane1_ow2tap_gen2_deemph3p5; /* Offset 0x014c */
u8 usb3_lane2_ow2tap_gen2_deemph3p5; /* Offset 0x014d */
u8 usb3_lane3_ow2tap_gen2_deemph3p5; /* Offset 0x014e */
u8 sata_speed; /* Offset 0x014f */
u8 usb_ssic_port; /* Offset 0x0150 */
u8 usb_hsic_port; /* Offset 0x0151 */
u8 pcie_rootport_speed; /* Offset 0x0152 */
u8 enable_ssic; /* Offset 0x0153 */
u32 logo_ptr; /* Offset 0x0154 */
u32 logo_size; /* Offset 0x0158 */
u8 rtc_lock; /* Offset 0x015c */
u8 pmic_i2c_bus; /* Offset 0x015d */
u8 enable_isp; /* Offset 0x015e */
u8 isp_pci_dev_config; /* Offset 0x015f */
u8 turbo_mode; /* Offset 0x0160 */
u8 pnp_settings; /* Offset 0x0161 */
u8 sd_detect_chk; /* Offset 0x0162 */
u8 reserved[411]; /* Offset 0x0163 */
};
#define MEMORY_UPD_ID 0x244450554d454d24 /* '$MEMUPD$' */
#define SILICON_UPD_ID 0x244450555f495324 /* '$SI_UPD$' */
struct __packed upd_region {
u64 signature; /* Offset 0x0000 */
u8 revision; /* Offset 0x0008 */
u8 unused0[7]; /* Offset 0x0009 */
u32 memory_upd_offset; /* Offset 0x0010 */
u32 silicon_upd_offset; /* Offset 0x0014 */
u64 unused1; /* Offset 0x0018 */
struct memory_upd memory_upd; /* Offset 0x0020 */
struct silicon_upd silicon_upd; /* Offset 0x0100 */
u16 terminator; /* Offset 0x02fe */
};
#define VPD_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */
struct __packed vpd_region {
u64 sign; /* Offset 0x0000 */
u32 img_rev; /* Offset 0x0008 */
u32 upd_offset; /* Offset 0x000c */
};
#endif /* __FSP_VPD_H__ */
source/bootloader/u-boot-2020.01/arch/x86/include/asm/arch-braswell/gpio.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
*
* From coreboot src/soc/intel/braswell/include/soc/gpio.h
*/
#ifndef _BRASWELL_GPIO_H_
#define _BRASWELL_GPIO_H_
#include <asm/arch/iomap.h>
enum mode_list {
M0,
M1,
M2,
M3,
M4,
M5,
M6,
M7,
M8,
M9,
M10,
M11,
M12,
M13,
};
enum int_select {
L0,
L1,
L2,
L3,
L4,
L5,
L6,
L7,
L8,
L9,
L10,
L11,
L12,
L13,
L14,
L15,
};
enum gpio_en {
NATIVE = 0xff,
GPIO = 0, /* Native, no need to set PAD_VALUE */
GPO = 1, /* GPO, output only in PAD_VALUE */
GPI = 2, /* GPI, input only in PAD_VALUE */
HI_Z = 3,
NA_GPO = 0,
};
enum gpio_state {
LOW,
HIGH,
};
enum en_dis {
DISABLE, /* Disable */
ENABLE, /* Enable */
};
enum int_type {
INT_DIS,
TRIG_EDGE_LOW,
TRIG_EDGE_HIGH,
TRIG_EDGE_BOTH,
TRIG_LEVEL,
};
enum mask {
MASKABLE,
NON_MASKABLE,
};
enum glitch_cfg {
GLITCH_DISABLE,
EN_EDGE_DETECT,
EN_RX_DATA,
EN_EDGE_RX_DATA,
};
enum inv_rx_tx {
NO_INVERSION = 0,
INV_RX_ENABLE = 1,
INV_TX_ENABLE = 2,
INV_RX_TX_ENABLE = 3,
INV_RX_DATA = 4,
INV_TX_DATA = 8,
};
enum voltage {
VOLT_3_3, /* Working on 3.3 Volts */
VOLT_1_8, /* Working on 1.8 Volts */
};
enum hs_mode {
DISABLE_HS, /* Disable high speed mode */
ENABLE_HS, /* Enable high speed mode */
};
enum odt_up_dn {
PULL_UP, /* On Die Termination Up */
PULL_DOWN, /* On Die Termination Down */
};
enum odt_en {
DISABLE_OD, /* On Die Termination Disable */
ENABLE_OD, /* On Die Termination Enable */
};
enum pull_type {
P_NONE = 0, /* Pull None */
P_20K_L = 1, /* Pull Down 20K */
P_5K_L = 2, /* Pull Down 5K */
P_1K_L = 4, /* Pull Down 1K */
P_20K_H = 9, /* Pull Up 20K */
P_5K_H = 10, /* Pull Up 5K */
P_1K_H = 12 /* Pull Up 1K */
};
enum bit {
ONE_BIT = 1,
TWO_BIT = 3,
THREE_BIT = 7,
FOUR_BIT = 15,
FIVE_BIT = 31,
SIX_BIT = 63,
SEVEN_BIT = 127,
EIGHT_BIT = 255
};
enum gpe_config {
GPE,
SMI,
SCI,
};
enum community {
SOUTHWEST = 0x0000,
NORTH = 0x8000,
EAST = 0x10000,
SOUTHEAST = 0x18000,
VIRTUAL = 0x20000,
};
#define NA 0xff
#define TERMINATOR 0xffffffff
#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \
odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \
.confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
(((hysctl) != NA) ? hysctl << 24 : 0) | \
(((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
(((hs_mode) != NA) ? hs_mode << 19 : 0) | \
(((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
(((odt_en) != NA) ? odt_en << 17 : 0) | \
(curr_src_str)), \
.confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
(((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
(((vp18_mode) != NA) ? ONE_BIT << 21 : 0) | \
(((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
(((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
(((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
(THREE_BIT)), \
.misc = ((rcomp == ENABLE) ? 1 : 0) , \
.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
(0x80 * family_no) + 0x1080) : 0) , \
.name = 0 \
}
#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \
gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\
int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \
mmio_offset, community_offset) { \
.confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
(((glitch) != NA) ? (glitch << 26) : 0) | \
(((term) != NA) ? (term << 20) : 0) | \
(((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \
((mode << 16))) | \
(((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
(((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
(((gpio_state) == HIGH) ? 2 : 0)), \
.confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
(((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
(((term) != NA) ? (FOUR_BIT << 20) : 0) | \
(FIVE_BIT << 15) | \
(((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
(((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
(((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
.confg1 = ((((current_source) != NA) ? (current_source << 27) : 0) | \
(((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
(((open_drain) != NA) ? open_drain << 3 : 0) | \
(((int_type) != NA) ? int_type : 0)), \
.confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
(((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
(((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
(((int_type) != NA) ? THREE_BIT : 0)), \
.community = community_offset, \
.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
community_offset + mmio_offset) : 0), \
.name = 0, \
.misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
(((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
(((int_mask) != NA) ? (int_mask << 3) : 0)) | \
(((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \
}
#endif /* _BRASWELL_GPIO_H_ */
source/bootloader/u-boot-2020.01/arch/x86/include/asm/arch-braswell/iomap.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
*/
#ifndef _BRASWELL_IOMAP_H_
#define _BRASWELL_IOMAP_H_
/* Memory Mapped IO bases */
/* Power Management Controller */
#define PMC_BASE_ADDRESS 0xfed03000
#define PMC_BASE_SIZE 0x400
/* Power Management Unit */
#define PUNIT_BASE_ADDRESS 0xfed05000
#define PUNIT_BASE_SIZE 0x800
/* Intel Legacy Block */
#define ILB_BASE_ADDRESS 0xfed08000
#define ILB_BASE_SIZE 0x400
/* SPI Bus */
#define SPI_BASE_ADDRESS 0xfed01000
#define SPI_BASE_SIZE 0x400
/* Root Complex Base Address */
#define RCBA_BASE_ADDRESS 0xfed1c000
#define RCBA_BASE_SIZE 0x400
/* IO Memory */
#define IO_BASE_ADDRESS 0xfed80000
#define IO_BASE_SIZE 0x4000
/* MODPHY */
#define MPHY_BASE_ADDRESS 0xfef00000
#define MPHY_BASE_SIZE 0x100000
/* IO Port bases */
#define ACPI_BASE_ADDRESS 0x400
#define ACPI_BASE_SIZE 0x80
#define GPIO_BASE_ADDRESS 0x500
#define GPIO_BASE_SIZE 0x100
#define SMBUS_BASE_ADDRESS 0xefa0
#endif /* _BRASWELL_IOMAP_H_ */