GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/arch/x86/lib/fsp/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-y += fsp_common.o
+obj-y += fsp_dram.o
+obj-y += fsp_support.o

source/bootloader/u-boot-2020.01/arch/x86/lib/fsp/fsp_common.c

@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <acpi_s3.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <rtc.h>
+#include <asm/cmos_layout.h>
+#include <asm/early_cmos.h>
+#include <asm/io.h>
+#include <asm/mrccache.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkcpu(void)
+{
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	post_code(POST_CPU_INFO);
+	return default_print_cpuinfo();
+}
+
+int fsp_init_phase_pci(void)
+{
+	u32 status;
+
+	/* call into FspNotify */
+	debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
+	status = fsp_notify(NULL, INIT_PHASE_PCI);
+	if (status)
+		debug("fail, error code %x\n", status);
+	else
+		debug("OK\n");
+
+	return status ? -EPERM : 0;
+}
+
+void board_final_cleanup(void)
+{
+	u32 status;
+
+	/* call into FspNotify */
+	debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
+	status = fsp_notify(NULL, INIT_PHASE_BOOT);
+	if (status)
+		debug("fail, error code %x\n", status);
+	else
+		debug("OK\n");
+}
+
+void *fsp_prepare_mrc_cache(void)
+{
+	struct mrc_data_container *cache;
+	struct mrc_region entry;
+	int ret;
+
+	ret = mrccache_get_region(NULL, &entry);
+	if (ret)
+		return NULL;
+
+	cache = mrccache_find_current(&entry);
+	if (!cache)
+		return NULL;
+
+	debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
+	      cache->data, cache->data_size, cache->checksum);
+
+	return cache->data;
+}
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+int fsp_save_s3_stack(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (gd->arch.prev_sleep_state == ACPI_S3)
+		return 0;
+
+	ret = uclass_get_device(UCLASS_RTC, 0, &dev);
+	if (ret) {
+		debug("Cannot find RTC: err=%d\n", ret);
+		return -ENODEV;
+	}
+
+	/* Save the stack address to CMOS */
+	ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
+	if (ret) {
+		debug("Save stack address to CMOS: err=%d\n", ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+#endif

source/bootloader/u-boot-2020.01/arch/x86/lib/fsp/fsp_dram.c

@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <handoff.h>
+#include <init.h>
+#include <asm/fsp/fsp_support.h>
+#include <asm/e820.h>
+#include <asm/mrccache.h>
+#include <asm/post.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsp_scan_for_ram_size(void)
+{
+	phys_size_t ram_size = 0;
+	const struct hob_header *hdr;
+	struct hob_res_desc *res_desc;
+
+	hdr = gd->arch.hob_list;
+	while (!end_of_hob(hdr)) {
+		if (hdr->type == HOB_TYPE_RES_DESC) {
+			res_desc = (struct hob_res_desc *)hdr;
+			if (res_desc->type == RES_SYS_MEM ||
+			    res_desc->type == RES_MEM_RESERVED)
+				ram_size += res_desc->len;
+		}
+		hdr = get_next_hob(hdr);
+	}
+
+	gd->ram_size = ram_size;
+	post_code(POST_DRAM);
+
+	return 0;
+};
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = 0;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+unsigned int install_e820_map(unsigned int max_entries,
+			      struct e820_entry *entries)
+{
+	unsigned int num_entries = 0;
+	const struct hob_header *hdr;
+	struct hob_res_desc *res_desc;
+
+	hdr = gd->arch.hob_list;
+
+	while (!end_of_hob(hdr)) {
+		if (hdr->type == HOB_TYPE_RES_DESC) {
+			res_desc = (struct hob_res_desc *)hdr;
+			entries[num_entries].addr = res_desc->phys_start;
+			entries[num_entries].size = res_desc->len;
+
+			if (res_desc->type == RES_SYS_MEM)
+				entries[num_entries].type = E820_RAM;
+			else if (res_desc->type == RES_MEM_RESERVED)
+				entries[num_entries].type = E820_RESERVED;
+
+			num_entries++;
+		}
+		hdr = get_next_hob(hdr);
+	}
+
+	/* Mark PCIe ECAM address range as reserved */
+	entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
+	entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
+	entries[num_entries].type = E820_RESERVED;
+	num_entries++;
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+	/*
+	 * Everything between U-Boot's stack and ram top needs to be
+	 * reserved in order for ACPI S3 resume to work.
+	 */
+	entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
+	entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
+		CONFIG_STACK_SIZE;
+	entries[num_entries].type = E820_RESERVED;
+	num_entries++;
+#endif
+
+	return num_entries;
+}
+
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
+int handoff_arch_save(struct spl_handoff *ho)
+{
+	ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
+	ho->arch.hob_list = gd->arch.hob_list;
+
+	return 0;
+}
+#endif

source/bootloader/u-boot-2020.01/arch/x86/lib/fsp/fsp_support.c

@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: Intel
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/fsp1/fsp_support.h>
+#include <asm/post.h>
+
+u32 fsp_get_usable_lowmem_top(const void *hob_list)
+{
+	const struct hob_header *hdr;
+	struct hob_res_desc *res_desc;
+	phys_addr_t phys_start;
+	u32 top;
+#ifdef CONFIG_FSP_BROKEN_HOB
+	struct hob_mem_alloc *res_mem;
+	phys_addr_t mem_base = 0;
+#endif
+
+	/* Get the HOB list for processing */
+	hdr = hob_list;
+
+	/* * Collect memory ranges */
+	top = FSP_LOWMEM_BASE;
+	while (!end_of_hob(hdr)) {
+		if (hdr->type == HOB_TYPE_RES_DESC) {
+			res_desc = (struct hob_res_desc *)hdr;
+			if (res_desc->type == RES_SYS_MEM) {
+				phys_start = res_desc->phys_start;
+				/* Need memory above 1MB to be collected here */
+				if (phys_start >= FSP_LOWMEM_BASE &&
+				    phys_start < (phys_addr_t)FSP_HIGHMEM_BASE)
+					top += (u32)(res_desc->len);
+			}
+		}
+
+#ifdef CONFIG_FSP_BROKEN_HOB
+		/*
+		 * Find out the lowest memory base address allocated by FSP
+		 * for the boot service data
+		 */
+		if (hdr->type == HOB_TYPE_MEM_ALLOC) {
+			res_mem = (struct hob_mem_alloc *)hdr;
+			if (!mem_base)
+				mem_base = res_mem->mem_base;
+			if (res_mem->mem_base < mem_base)
+				mem_base = res_mem->mem_base;
+		}
+#endif
+
+		hdr = get_next_hob(hdr);
+	}
+
+#ifdef CONFIG_FSP_BROKEN_HOB
+	/*
+	 * Check whether the memory top address is below the FSP HOB list.
+	 * If not, use the lowest memory base address allocated by FSP as
+	 * the memory top address. This is to prevent U-Boot relocation
+	 * overwrites the important boot service data which is used by FSP,
+	 * otherwise the subsequent call to fsp_notify() will fail.
+	 */
+	if (top > (u32)hob_list) {
+		debug("Adjust memory top address due to a buggy FSP\n");
+		top = (u32)mem_base;
+	}
+#endif
+
+	return top;
+}
+
+u64 fsp_get_usable_highmem_top(const void *hob_list)
+{
+	const struct hob_header *hdr;
+	struct hob_res_desc *res_desc;
+	phys_addr_t phys_start;
+	u64 top;
+
+	/* Get the HOB list for processing */
+	hdr = hob_list;
+
+	/* Collect memory ranges */
+	top = FSP_HIGHMEM_BASE;
+	while (!end_of_hob(hdr)) {
+		if (hdr->type == HOB_TYPE_RES_DESC) {
+			res_desc = (struct hob_res_desc *)hdr;
+			if (res_desc->type == RES_SYS_MEM) {
+				phys_start = res_desc->phys_start;
+				/* Need memory above 4GB to be collected here */
+				if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE)
+					top += (u32)(res_desc->len);
+			}
+		}
+		hdr = get_next_hob(hdr);
+	}
+
+	return top;
+}
+
+u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
+				   const efi_guid_t *guid)
+{
+	const struct hob_header *hdr;
+	struct hob_res_desc *res_desc;
+
+	/* Get the HOB list for processing */
+	hdr = hob_list;
+
+	/* Collect memory ranges */
+	while (!end_of_hob(hdr)) {
+		if (hdr->type == HOB_TYPE_RES_DESC) {
+			res_desc = (struct hob_res_desc *)hdr;
+			if (res_desc->type == RES_MEM_RESERVED) {
+				if (!guidcmp(&res_desc->owner, guid)) {
+					if (len)
+						*len = (u32)(res_desc->len);
+
+					return (u64)(res_desc->phys_start);
+				}
+			}
+		}
+		hdr = get_next_hob(hdr);
+	}
+
+	return 0;
+}
+
+u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len)
+{
+	const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
+	u64 length;
+	u32 base;
+
+	base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
+			&length, &guid);
+	if (len && base)
+		*len = (u32)length;
+
+	return base;
+}
+
+u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len)
+{
+	const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
+	u64 length;
+	u32 base;
+
+	base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
+			&length, &guid);
+	if (len && base)
+		*len = (u32)length;
+
+	return base;
+}
+
+void *fsp_get_nvs_data(const void *hob_list, u32 *len)
+{
+	const efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+
+	return hob_get_guid_hob_data(hob_list, len, &guid);
+}
+
+void *fsp_get_var_nvs_data(const void *hob_list, u32 *len)
+{
+	const efi_guid_t guid = FSP_VARIABLE_NV_DATA_HOB_GUID;
+
+	return hob_get_guid_hob_data(hob_list, len, &guid);
+}
+
+void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)
+{
+	const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
+
+	return hob_get_guid_hob_data(hob_list, len, &guid);
+}
+
+void *fsp_get_graphics_info(const void *hob_list, u32 *len)
+{
+	const efi_guid_t guid = FSP_GRAPHICS_INFO_HOB_GUID;
+
+	return hob_get_guid_hob_data(hob_list, len, &guid);
+}