GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
@@ -0,0 +1,18 @@
+if TARGET_ADP_AE3XX
+
+config SYS_CPU
+	default "n1213"
+
+config SYS_BOARD
+	default "adp-ae3xx"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ae3xx"
+
+config SYS_CONFIG_NAME
+	default "adp-ae3xx"
+
+endif
@@ -0,0 +1,6 @@
+ADP-AG101P BOARD
+M:	Andes <uboot@andestech.com>
+S:	Maintained
+F:	board/AndesTech/adp-ae3xx/
+F:	include/configs/adp-ae3xx.h
+F:	configs/adp-ae3xx_defconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+obj-y	:= adp-ae3xx.o
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#include <asm/mach-types.h>
+#include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	printf("Board: %s\n" , CONFIG_SYS_BOARD);
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+	gd->ram_size = actual_size;
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
@@ -0,0 +1,18 @@
+if TARGET_ADP_AG101P
+
+config SYS_CPU
+	default "n1213"
+
+config SYS_BOARD
+	default "adp-ag101p"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ag101"
+
+config SYS_CONFIG_NAME
+	default "adp-ag101p"
+
+endif
@@ -0,0 +1,6 @@
+ADP-AG101P BOARD
+M:	Andes <uboot@andestech.com>
+S:	Maintained
+F:	board/AndesTech/adp-ag101p/
+F:	include/configs/adp-ag101p.h
+F:	configs/adp-ag101p_defconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+
+obj-y	:= adp-ag101p.o
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	printf("Board: %s\n" , CONFIG_SYS_BOARD);
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
@@ -0,0 +1,38 @@
+if TARGET_AX25_AE350
+
+config SYS_CPU
+	default "ax25"
+
+config SYS_BOARD
+	default "ax25-ae350"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ae350"
+
+config SYS_CONFIG_NAME
+	default "ax25-ae350"
+
+config ENV_SIZE
+	default 0x2000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x140000 if ENV_IS_IN_SPI_FLASH
+
+config SPL_TEXT_BASE
+	default 0x800000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x01000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select RISCV_NDS
+	select SUPPORT_SPL
+	imply SMP
+	imply SPL_RAM_SUPPORT
+	imply SPL_RAM_DEVICE
+
+endif
@@ -0,0 +1,13 @@
+AX25-AE350 BOARD
+M:	Rick Chen <rick@andestech.com>
+S:	Maintained
+F:	board/AndesTech/ax25-ae350/
+F:	include/configs/ax25-ae350.h
+F:	configs/ae350_rv32_defconfig
+F:	configs/ae350_rv64_defconfig
+F:	configs/ae350_rv32_xip_defconfig
+F:	configs/ae350_rv64_xip_defconfig
+F:	configs/ae350_rv32_spl_defconfig
+F:	configs/ae350_rv64_spl_defconfig
+F:	configs/ae350_rv32_spl_xip_defconfig
+F:	configs/ae350_rv64_spl_xip_defconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Andes Technology Corporation.
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+obj-y	:= ax25-ae350.o
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <faraday/ftsmc020.h>
+#include <fdtdec.h>
+#include <dm.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern phys_addr_t prior_stage_fdt_address;
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	return 0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+	return (void *)CONFIG_SYS_FDT_BASE;
+}
+
+int smc_init(void)
+{
+	int node = -1;
+	const char *compat = "andestech,atfsmc020";
+	void *blob = (void *)gd->fdt_blob;
+	fdt_addr_t addr;
+	struct ftsmc020_bank *regs;
+
+	node = fdt_node_offset_by_compatible(blob, -1, compat);
+	if (node < 0)
+		return -FDT_ERR_NOTFOUND;
+
+	addr = fdtdec_get_addr(blob, node, "reg");
+
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	regs = (struct ftsmc020_bank *)addr;
+	regs->cr &= ~FTSMC020_BANK_WPROT;
+
+	return 0;
+}
+
+static void v5l2_init(void)
+{
+	struct udevice *dev;
+
+	uclass_get_device(UCLASS_CACHE, 0, &dev);
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	smc_init();
+	v5l2_init();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+	u8 i;
+	u32 boot_devices[] = {
+#ifdef CONFIG_SPL_RAM_SUPPORT
+		BOOT_DEVICE_RAM,
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+		BOOT_DEVICE_MMC1,
+#endif
+	};
+
+	for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+		spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
@@ -0,0 +1,36 @@
+if TARGET_UCP1020
+
+config SYS_BOARD
+	string
+	default "ucp1020"
+
+config SYS_VENDOR
+	string
+	default "Arcturus"
+
+config SYS_CONFIG_NAME
+	string
+	default "UCP1020"
+
+choice
+	prompt "Target image select"
+
+config TARGET_UCP1020_NOR
+	bool "NOR flash u-boot image"
+
+config TARGET_UCP1020_SPIFLASH
+	bool "SPI flash u-boot image"
+
+endchoice
+
+if TARGET_UCP1020_SPIFLASH
+config UCBOOT
+	bool
+	default y
+
+config SPIFLASH
+	bool
+	default y
+endif
+
+endif
@@ -0,0 +1,7 @@
+UCP1020 BOARD
+M:	Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
+S:	Maintained
+F:	board/Arcturus/ucp1020/
+F:	include/configs/UCP1020.h
+F:	configs/UCP1020_defconfig
+F:	configs/UCP1020_SPIFLASH_defconfig
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2013-2015 Arcturus Networks, Inc.
+# based on board/freescale/p1_p2_rdb_pc/Makefile
+# original copyright follows:
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y	+= spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
+obj-y        += ucp1020.o
+obj-y        += ddr.o
+obj-y        += law.o
+obj-y        += tlb.o
+obj-y        += cmd_arc.o
+
+endif
@@ -0,0 +1,54 @@
+The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
+product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
+DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
+
+Information on the generic product family can be found here:
+	http://www.arcturusnetworks.com/products/ucp1020
+
+The UCP1020 several configurable options
+========================================
+
+- the selection of populated phy(s):
+	KSZ9031 (current default for eTSEC 1 and 3)
+
+- the selection of boot location:
+	SPI Flash or NOR flash
+
+The UCP1020 includes 2 default configurations
+=============================================
+NOR boot image:
+	configs/UCP1020_defconfig
+SPI boot image:
+	configs/UCP1020_SPIFLASH_defconfig
+
+The UCP1020 adds an additional command in cmd_arc.c to access and program
+SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
+HW Addresses.
+
+
+Build example
+=============
+
+make distclean
+make UCP1020_defconfig
+make
+
+Default Scripts
+===============
+A default upgrade scripts is included in the default environment variable example:
+
+B$ run tftpflash
+
+Dual Environment
+================
+
+This build enables dual / failover environment environment.
+
+NOR Flash Partition declarations and scripts
+============================================
+Several scripts are available to allow TFTP of images and programming directly
+into defined NOR flash partitions. Examples:
+
+B$ run program0
+B$ run program1
+B$ run program2
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Command for accessing Arcturus factory environment.
+ *
+ * Copyright 2013-2019 Arcturus Networks Inc.
+ *           https://www.arcturusnetworks.com/products/
+ *           by Oleksandr G Zhadan et al.
+ *
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <div64.h>
+#include <env.h>
+#include <malloc.h>
+#include <spi_flash.h>
+#include <mmc.h>
+#include <version.h>
+#include <asm/io.h>
+
+static ulong fwenv_addr[MAX_FWENV_ADDR];
+const char mystrerr[] = "ERROR: Failed to save factory info";
+
+static int ishwaddr(char *hwaddr)
+{
+	if (strlen(hwaddr) == MAX_HWADDR_SIZE)
+		if (hwaddr[2] == ':' &&
+		    hwaddr[5] == ':' &&
+		    hwaddr[8] == ':' &&
+		    hwaddr[11] == ':' &&
+		    hwaddr[14] == ':')
+			return 0;
+	return -1;
+}
+
+#if (FWENV_TYPE == FWENV_MMC)
+
+static char smac[29][18] __attribute__ ((aligned(0x200)));	/* 1 MMC block is 512 bytes */
+
+int set_mmc_arc_product(int argc, char *const argv[])
+{
+	struct mmc *mmc;
+	u32 blk, cnt, n;
+	int i, err = 1;
+	void *addr;
+	const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
+
+	mmc = find_mmc_device(mmc_dev_num);
+	if (!mmc) {
+		printf("No SD/MMC/eMMC card found\n");
+		return 0;
+	}
+	if (mmc_init(mmc)) {
+		printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
+		       mmc_dev_num);
+		return 0;
+	}
+	if (mmc_getwp(mmc) == 1) {
+		printf("Error: card is write protected!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/* Save factory defaults */
+	addr = (void *)smac;
+	cnt = 1;		/* One 512 bytes block */
+
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1) {
+			blk = fwenv_addr[i] / 512;
+			n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
+			if (n != cnt)
+				printf("%s: %s [%d]\n", __func__, mystrerr, i);
+			else
+				err = 0;
+		}
+	if (err)
+		return -2;
+
+	return err;
+}
+
+static int read_mmc_arc_info(void)
+{
+	struct mmc *mmc;
+	u32 blk, cnt, n;
+	int i;
+	void *addr;
+	const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
+
+	mmc = find_mmc_device(mmc_dev_num);
+	if (!mmc) {
+		printf("No SD/MMC/eMMC card found\n");
+		return 0;
+	}
+	if (mmc_init(mmc)) {
+		printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
+		       mmc_dev_num);
+		return 0;
+	}
+
+	addr = (void *)smac;
+	cnt = 1;		/* One 512 bytes block */
+
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1) {
+			blk = fwenv_addr[i] / 512;
+			n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
+			flush_cache((ulong) addr, 512);
+			if (n == cnt)
+				return (i + 1);
+		}
+	return 0;
+}
+#endif
+
+#if (FWENV_TYPE == FWENV_SPI_FLASH)
+
+static struct spi_flash *flash;
+static char smac[4][18];
+
+int set_spi_arc_product(int argc, char *const argv[])
+{
+	int i, err = 1;
+
+	flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+				CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+	if (!flash) {
+		printf("Failed to initialize SPI flash at %u:%u\n",
+		       CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
+		return -1;
+	}
+
+	/* Save factory defaults */
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1)
+			if (spi_flash_write
+			    (flash, fwenv_addr[i], sizeof(smac), smac))
+				printf("%s: %s [%d]\n", __func__, mystrerr, i);
+			else
+				err = 0;
+	if (err)
+		return -2;
+
+	return err;
+}
+
+static int read_spi_arc_info(void)
+{
+	int i;
+
+	flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+				CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+	if (!flash) {
+		printf("Failed to initialize SPI flash at %u:%u\n",
+		       CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
+		return 0;
+	}
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1)
+			if (!spi_flash_read
+			    (flash, fwenv_addr[i], sizeof(smac), smac))
+				return (i + 1);
+	return 0;
+}
+#endif
+
+#if (FWENV_TYPE == FWENV_NOR_FLASH)
+
+static char smac[4][18];
+
+int set_nor_arc_product(int argc, char *const argv[])
+{
+	int i, err = 1;
+
+	/* Save factory defaults */
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1) {
+			ulong fwenv_end = fwenv_addr[i] + 4;
+
+			flash_sect_roundb(&fwenv_end);
+			flash_sect_protect(0, fwenv_addr[i], fwenv_end);
+			if (flash_write
+			    ((char *)smac, fwenv_addr[i], sizeof(smac)))
+				printf("%s: %s [%d]\n", __func__, mystrerr, i);
+			else
+				err = 0;
+			flash_sect_protect(1, fwenv_addr[i], fwenv_end);
+		}
+	if (err)
+		return -2;
+
+	return err;
+}
+
+static int read_nor_arc_info(void)
+{
+	int i;
+
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1) {
+			memcpy(smac, (void *)fwenv_addr[i], sizeof(smac));
+			return (i + 1);
+		}
+
+	return 0;
+}
+#endif
+
+int set_arc_product(int argc, char *const argv[])
+{
+	if (argc != 5)
+		return -1;
+
+	/* Check serial number */
+	if (strlen(argv[1]) != MAX_SERIAL_SIZE)
+		return -1;
+
+	/* Check HWaddrs */
+	if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
+		return -1;
+
+	strcpy(smac[0], argv[1]);
+	strcpy(smac[1], argv[2]);
+	strcpy(smac[2], argv[3]);
+	strcpy(smac[3], argv[4]);
+
+#if (FWENV_TYPE == FWENV_NOR_FLASH)
+	return set_nor_arc_product(argc, argv);
+#endif
+#if (FWENV_TYPE == FWENV_SPI_FLASH)
+	return set_spi_arc_product(argc, argv);
+#endif
+#if (FWENV_TYPE == FWENV_MMC)
+	return set_mmc_arc_product(argc, argv);
+#endif
+	return -2;
+}
+
+static int read_arc_info(void)
+{
+#if (FWENV_TYPE == FWENV_NOR_FLASH)
+	return read_nor_arc_info();
+#endif
+#if (FWENV_TYPE == FWENV_SPI_FLASH)
+	return read_spi_arc_info();
+#endif
+#if (FWENV_TYPE == FWENV_MMC)
+	return read_mmc_arc_info();
+#endif
+	return 0;
+}
+
+static int do_get_arc_info(void)
+{
+	int l = read_arc_info();
+	char *oldserial = env_get("SERIAL");
+	char *oldversion = env_get("VERSION");
+
+	if (oldversion != NULL)
+		if (strcmp(oldversion, U_BOOT_VERSION) != 0)
+			oldversion = NULL;
+
+	if (l == 0) {
+		printf("%s: failed to read factory info\n", __func__);
+		return -2;
+	}
+
+	printf("\rSERIAL:  ");
+	if (smac[0][0] == EMPY_CHAR) {
+		printf("<not found>\n");
+	} else {
+		printf("%s\n", smac[0]);
+		env_set("SERIAL", smac[0]);
+	}
+
+	if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
+		env_set("ethaddr", NULL);
+		env_set("eth1addr", NULL);
+		env_set("eth2addr", NULL);
+		goto done;
+	}
+
+	printf("HWADDR0: ");
+	if (smac[1][0] == EMPY_CHAR) {
+		printf("<not found>\n");
+	} else {
+		char *ret = env_get("ethaddr");
+
+		if (ret == NULL) {
+			env_set("ethaddr", smac[1]);
+			printf("%s\n", smac[1]);
+		} else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
+			env_set("ethaddr", smac[1]);
+			printf("%s (factory)\n", smac[1]);
+		} else {
+			printf("%s\n", ret);
+		}
+	}
+
+	if (strcmp(smac[2], "00:00:00:00:00:00") == 0) {
+		env_set("eth1addr", NULL);
+		env_set("eth2addr", NULL);
+		goto done;
+	}
+
+	printf("HWADDR1: ");
+	if (smac[2][0] == EMPY_CHAR) {
+		printf("<not found>\n");
+	} else {
+		char *ret = env_get("eth1addr");
+
+		if (ret == NULL) {
+			env_set("ethaddr", smac[2]);
+			printf("%s\n", smac[2]);
+		} else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
+			env_set("eth1addr", smac[2]);
+			printf("%s (factory)\n", smac[2]);
+		} else {
+			printf("%s\n", ret);
+		}
+	}
+
+	if (strcmp(smac[3], "00:00:00:00:00:00") == 0) {
+		env_set("eth2addr", NULL);
+		goto done;
+	}
+
+	printf("HWADDR2: ");
+	if (smac[3][0] == EMPY_CHAR) {
+		printf("<not found>\n");
+	} else {
+		char *ret = env_get("eth2addr");
+
+		if (ret == NULL) {
+			env_set("ethaddr", smac[3]);
+			printf("%s\n", smac[3]);
+		} else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
+			env_set("eth2addr", smac[3]);
+			printf("%s (factory)\n", smac[3]);
+		} else {
+			printf("%s\n", ret);
+		}
+	}
+done:
+	if (oldserial == NULL || oldversion == NULL) {
+		if (oldversion == NULL)
+			env_set("VERSION", U_BOOT_VERSION);
+		env_save();
+	}
+
+	return 0;
+}
+
+static int init_fwenv(void)
+{
+	int i, ret = -1;
+
+	fwenv_addr[0] = FWENV_ADDR1;
+	fwenv_addr[1] = FWENV_ADDR2;
+	fwenv_addr[2] = FWENV_ADDR3;
+	fwenv_addr[3] = FWENV_ADDR4;
+
+	for (i = 0; i < MAX_FWENV_ADDR; i++)
+		if (fwenv_addr[i] != -1)
+			ret = 0;
+	if (ret)
+		printf("%s: No firmfare info storage address is defined\n",
+		       __func__);
+	return ret;
+}
+
+void get_arc_info(void)
+{
+	if (!init_fwenv())
+		do_get_arc_info();
+}
+
+static int do_arc_cmd(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	const char *cmd;
+	int ret = -1;
+
+	cmd = argv[1];
+	--argc;
+	++argv;
+
+	if (init_fwenv())
+		return ret;
+
+	if (strcmp(cmd, "product") == 0)
+		ret = set_arc_product(argc, argv);
+	else if (strcmp(cmd, "info") == 0)
+		ret = do_get_arc_info();
+
+	if (ret == -1)
+		return CMD_RET_USAGE;
+
+	return ret;
+}
+
+U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
+	   "Arcturus product command sub-system",
+	   "product serial hwaddr0 hwaddr1 hwaddr2    - save Arcturus factory env\n"
+	   "info                                      - show Arcturus factory env\n\n");
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
+/*
+ * Micron MT41J128M16HA-15E
+ * */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 536870912u,
+	.capacity = 536870912u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 2,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 1650,
+	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.taa_ps = 14050,
+	.twr_ps = 15000,
+	.trcd_ps = 13500,
+	.trrd_ps = 75000,
+	.trp_ps = 13500,
+	.tras_ps = 40000,
+	.trc_ps = 49500,
+	.trfc_ps = 160000,
+	.twtr_ps = 75000,
+	.trtp_ps = 75000,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 30000,
+};
+
+#else
+#error Missing raw timing data for this board
+#endif
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
+
+#ifdef CONFIG_SYS_DDR_CS0_BNDS
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+	size_t ddr_size;
+	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+		.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+	};
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+	       strmhz(buf, sysinfo.freq_ddrbus));
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+			 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	};
+
+	return ddr_size;
+}
+#endif
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	int i;
+
+	popts->clk_adjust = 6;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 2;
+	popts->half_strength_driver_enable = 1;
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x8;
+	popts->trwt_override = 1;
+	popts->trwt = 0;
+
+	if (pdimm->primary_sdram_width == 64)
+		popts->data_bus_width = 0;
+	else if (pdimm->primary_sdram_width == 32)
+		popts->data_bus_width = 1;
+	else
+		printf("Error in DDR bus width configuration!\n");
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+	}
+}
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_VSC7385_ENET
+	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <console.h>
+#include <env.h>
+#include <env_internal.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+	66666000, 7499900, 83332500, 8999900,
+	99999000, 11111000, 12499800, 13333200
+};
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = bus_clk;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+	gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = ENV_VALID;
+#else
+	env_relocate();
+#endif
+
+#ifdef CONFIG_SYS_I2C
+	i2c_init_all();
+#else
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dram_init();
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
+	puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
+ * original copyright follows:
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("\nSecond program loader running in sram...");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc
+ *           http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/tlb.c
+ * original copyright follows:
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+	/* *I*G* - PCI memory 1.5G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O effective: 192K  */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+	/* *I*G - VSC7385 Switch */
+	SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
+#endif /* not SPL */
+
+#ifdef CONFIG_SYS_NAND_BASE
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+	/* *I*G - eSDHC/eSPI/NAND boot */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
+		      0, 8, BOOKE_PAGESZ_1G, 1),
+
+#endif /* RAMBOOT/SPL */
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2019 Arcturus Networks, Inc.
+ *           https://www.arcturusnetworks.com/products/ucp1020/
+ *           by Oleksandr G Zhadan et al.
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <pci.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <ioports.h>
+#include <netdev.h>
+#include <micrel.h>
+#include <spi_flash.h>
+#include <mmc.h>
+#include <linux/ctype.h>
+#include <asm/fsl_serdes.h>
+#include <asm/gpio.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include "ucp1020.h"
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+	/* TO DO: It's actially have to be in spi/ */
+}
+
+/*
+ * To be compatible with cmd_gpio
+ */
+int name_to_gpio(const char *name)
+{
+	int gpio = 31 - simple_strtoul(name, NULL, 10);
+
+	if (gpio < 16)
+		gpio = -1;
+
+	return gpio;
+}
+
+void board_gpio_init(void)
+{
+	int i;
+	char envname[8], *val;
+
+	for (i = 0; i < GPIO_MAX_NUM; i++) {
+		sprintf(envname, "GPIO%d", i);
+		val = env_get(envname);
+		if (val) {
+			char direction = toupper(val[0]);
+			char level = toupper(val[1]);
+
+			if (direction == 'I') {
+				gpio_direction_input(i);
+			} else {
+				if (direction == 'O') {
+					if (level == '1')
+						gpio_direction_output(i, 1);
+					else
+						gpio_direction_output(i, 0);
+				}
+			}
+		}
+	}
+
+	val = env_get("PCIE_OFF");
+	if (val) {
+		gpio_direction_input(GPIO_PCIE1_EN);
+		gpio_direction_input(GPIO_PCIE2_EN);
+	} else {
+		gpio_direction_output(GPIO_PCIE1_EN, 1);
+		gpio_direction_output(GPIO_PCIE2_EN, 1);
+	}
+
+	val = env_get("SDHC_CDWP_OFF");
+	if (!val) {
+		ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+		setbits_be32(&gur->pmuxcr,
+			     (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+	}
+}
+
+int board_early_init_f(void)
+{
+	return 0;	/* Just in case. Could be disable in config file */
+}
+
+int checkboard(void)
+{
+	printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
+	board_gpio_init();
+#ifdef CONFIG_MMC
+	printf("SD/MMC: 4-bit Mode\n");
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+		MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
+		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+#if defined(CONFIG_PHY_MICREL_KSZ9021)
+	int regval;
+	static int cnt;
+
+	if (cnt++ == 0)
+		printf("PHYs address [");
+
+	if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
+		regval =
+		    ksz9021_phy_extended_read(phydev,
+					      MII_KSZ9021_EXT_STRAP_STATUS);
+		/*
+		 * min rx data delay
+		 */
+		ksz9021_phy_extended_write(phydev,
+					   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+					   0x6666);
+		/*
+		 * max rx/tx clock delay, min rx/tx control
+		 */
+		ksz9021_phy_extended_write(phydev,
+					   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+					   0xf6f6);
+		printf("0x%x", (regval & 0x1f));
+	} else {
+		printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
+	}
+	if (cnt == 3)
+		printf("] ");
+	else
+		printf(",");
+#endif
+
+#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
+	regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
+	if (regval >= 0)
+		printf(" (ADDR 0x%x) ", regval & 0x1f);
+#endif
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	static char newkernelargs[256];
+	static u8 id1[16];
+	static u8 id2;
+#ifdef CONFIG_MMC
+	struct mmc *mmc;
+#endif
+	char *sval, *kval;
+
+	if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
+		printf("Error reading i2c IDT6V49205B information!\n");
+	} else {
+		printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
+		i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
+		if (!(id1[1] & 0x02)) {
+			id1[1] |= 0x02;
+			i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
+			asm("nop; nop");
+		}
+	}
+
+	if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
+		printf("Error reading i2c NCT72 information!\n");
+	else
+		printf("NCT72(0x%x): ready\n", id2);
+
+	kval = env_get("kernelargs");
+
+#ifdef CONFIG_MMC
+	mmc = find_mmc_device(0);
+	if (mmc)
+		if (!mmc_init(mmc)) {
+			printf("MMC/SD card detected\n");
+			if (kval) {
+				int n = strlen(defkargs);
+				char *tmp = strstr(kval, defkargs);
+
+				*tmp = 0;
+				strcpy(newkernelargs, kval);
+				strcat(newkernelargs, " ");
+				strcat(newkernelargs, mmckargs);
+				strcat(newkernelargs, " ");
+				strcat(newkernelargs, &tmp[n]);
+				env_set("kernelargs", newkernelargs);
+			} else {
+				env_set("kernelargs", mmckargs);
+			}
+		}
+#endif
+	get_arc_info();
+
+	if (kval) {
+		sval = env_get("SERIAL");
+		if (sval) {
+			strcpy(newkernelargs, "SN=");
+			strcat(newkernelargs, sval);
+			strcat(newkernelargs, " ");
+			strcat(newkernelargs, kval);
+			env_set("kernelargs", newkernelargs);
+		}
+	} else {
+		printf("Error reading kernelargs env variable!\n");
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+#ifdef CONFIG_TSEC2
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
+			puts("eTSEC2 is in sgmii mode.\n");
+			tsec_info[num].flags |= TSEC_SGMII;
+			tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
+		}
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+	const char *soc_usb_compat = "fsl-usb2-dr";
+	int err, usb1_off, usb2_off;
+
+	ft_cpu_setup(blob, bd);
+
+	base = env_get_bootm_low();
+	size = env_get_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+	/* Delete eLBC node as it is muxed with USB2 controller */
+	if (hwconfig("usb2")) {
+		const char *soc_elbc_compat = "fsl,p1020-elbc";
+		int off = fdt_node_offset_by_compatible(blob, -1,
+							soc_elbc_compat);
+		if (off < 0) {
+			printf
+			    ("WARNING: could not find compatible node %s: %s\n",
+			     soc_elbc_compat, fdt_strerror(off));
+			return off;
+		}
+		err = fdt_del_node(blob, off);
+		if (err < 0) {
+			printf("WARNING: could not remove %s: %s\n",
+			       soc_elbc_compat, fdt_strerror(err));
+		}
+		return err;
+	}
+#endif
+
+/* Delete USB2 node as it is muxed with eLBC */
+	usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
+	if (usb1_off < 0) {
+		printf("WARNING: could not find compatible node %s: %s.\n",
+		       soc_usb_compat, fdt_strerror(usb1_off));
+		return usb1_off;
+	}
+	usb2_off =
+	    fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
+	if (usb2_off < 0) {
+		printf("WARNING: could not find compatible node %s: %s.\n",
+		       soc_usb_compat, fdt_strerror(usb2_off));
+		return usb2_off;
+	}
+	err = fdt_del_node(blob, usb2_off);
+	if (err < 0) {
+		printf("WARNING: could not remove %s: %s.\n",
+		       soc_usb_compat, fdt_strerror(err));
+	}
+	return 0;
+}
+#endif
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2019 Arcturus Networks, Inc.
+ *           https://www.arcturusnetworks.com/products/ucp1020/
+ *           by Oleksandr G Zhadan et al.
+ */
+
+#ifndef __UCP1020_H__
+#define __UCP1020_H__
+
+#define GPIO0		31
+#define GPIO1		30
+#define GPIO2		29
+#define GPIO3		28
+#define GPIO4		27
+#define GPIO5		26
+#define GPIO6		25
+#define GPIO7		24
+#define GPIO8		23
+#define GPIO9		22
+#define GPIO10		21
+#define GPIO11		20
+#define GPIO12		19
+#define GPIO13		18
+#define GPIO14		17
+#define GPIO15		16
+#define GPIO_MAX_NUM	16
+
+#define GPIO_SDHC_CD	GPIO8
+#define GPIO_SDHC_WP	GPIO9
+#define GPIO_USB_PCTL0	GPIO10
+#define GPIO_PCIE1_EN	GPIO11
+#define GPIO_PCIE2_EN	GPIO10
+#define GPIO_USB_PCTL1	GPIO11
+
+#define GPIO_WD		GPIO15
+
+#ifdef CONFIG_MMC
+static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
+static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
+#endif
+
+int get_arc_info(void);
+
+#endif
@@ -0,0 +1,15 @@
+if TARGET_BRPPT1
+
+config SYS_BOARD
+	default "brppt1"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "brppt1"
+
+endif
@@ -0,0 +1,8 @@
+BRPPT1 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brppt1/
+F:	include/configs/brppt1.h
+F:	configs/brppt1_mmc_defconfig
+F:	configs/brppt1_nand_defconfig
+F:	configs/brppt1_spi_defconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y	:= mux.o
+endif
+obj-y	+= ../common/common.o
+obj-y	+= board.o
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for B&R BRPPT1
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <common.h>
+#include <bootcount.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* --------------------------------------------------------------------------*/
+/* -- defines for GPIO -- */
+#define	REPSWITCH	(0+20)	/* GPIO0_20 */
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC	(V_OSCK/1000000)
+static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int rc;
+
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	/*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
+	struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+
+	/*
+	 * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
+	 * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
+	 * the source of timer6 clk to CLK_M_OSC
+	 */
+	writel(0x01, &cmdpll->clktimer6clk);
+
+	/* enable additional clocks of modules which are accessed later */
+	u32 *const clk_domains[] = {
+		&cmper->lcdcclkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_tsspecific[] = {
+		&cmper->lcdclkctrl,
+		&cmper->timer5clkctrl,
+		&cmper->timer6clkctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
+
+	/* setup I2C */
+	enable_i2c_pin_mux();
+
+	pmicsetup(0, 0);
+
+	/* peripheral reset */
+	rc = gpio_request(64 + 29, "GPMC_WAIT1");
+	if (rc != 0)
+		printf("cannot request GPMC_WAIT1 GPIO!\n");
+	rc = gpio_direction_output(64 + 29, 1);
+	if (rc != 0)
+		printf("cannot set GPMC_WAIT1 GPIO!\n");
+
+	rc = gpio_request(64 + 28, "GPMC_WAIT0");
+	if (rc != 0)
+		printf("cannot request GPMC_WAIT0 GPIO!\n");
+	rc = gpio_direction_output(64 + 28, 1);
+	if (rc != 0)
+		printf("cannot set GPMC_WAIT0 GPIO!\n");
+
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/* Basic board specific setup.  Pinmux has been handled already. */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_MTD_RAW_NAND
+	gpmc_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static char *bootmodeascii[16] = {
+	"BOOT",		"reserved",	"reserved",	"reserved",
+	"RUN",		"reserved",	"reserved",	"reserved",
+	"reserved",	"reserved",	"reserved",	"reserved",
+	"PME",		"reserved",	"reserved",	"DIAG",
+};
+
+int board_late_init(void)
+{
+	unsigned char bmode = 0;
+	ulong bootcount = 0;
+	int rc;
+
+	bootcount = bootcount_load() & 0xF;
+
+	rc = gpio_request(REPSWITCH, "REPSWITCH");
+
+	if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
+		bmode = 12;
+	else if (bootcount > 0)
+		bmode = 0;
+	else
+		bmode = 4;
+
+	printf("Mode:  %s\n", bootmodeascii[bmode & 0x0F]);
+	env_set_ulong("b_mode", bmode);
+
+	/* get sure that bootcmd isn't affected by any bootcount value */
+	env_set_ulong("bootlimit", 0);
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
@@ -0,0 +1,36 @@
+#
+# Copyright (C) 2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
+
+payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
+
+quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
+cmd_prodbin =								\
+	dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
+	dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
+	dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
+
+quiet_cmd_prodzip = SAPZIP  $@
+cmd_prodzip =					\
+	test -d misc && rm -r misc;		\
+	mkdir misc &&				\
+	cp MLO.byteswap misc/ &&		\
+	cp spl/u-boot-spl.bin misc/ &&		\
+	cp u-boot-dtb.img misc/ &&		\
+	zip -9 -r $@ misc/* >/dev/null $<
+
+ifeq ($(hw-platform-y),brppt1-spi)
+ALL-y += $(hw-platform-y)_prog.bin
+ALL-y += $(hw-platform-y)_prod.zip
+endif
+
+$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
+	$(call if_changed,prodbin)
+
+$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
+	$(call if_changed,prodzip)
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R BRPPT1 Board(s)
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_RTS */
+	{OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+static struct module_pin_mux uart1_pin_mux[] = {
+	/* UART1_RTS as I2C2-SCL */
+	{OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART1_CTS as I2C2-SDA */
+	{OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART1_RXD */
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART1_TXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+	{-1},
+};
+#endif
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI0_SCLK */
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_D0 */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |	PULLUDEN | PULLUP_EN)},
+	/* SPI0_D1 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_CS0 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mii2_pin_mux[] = {
+	{OFFSET(gpmc_a0), MODE(1)},		/* MII2_TXEN */
+	{OFFSET(gpmc_a1), MODE(1) | RXACTIVE},	/* MII2_RXDV */
+	{OFFSET(gpmc_a2), MODE(1)},		/* MII2_TXD3 */
+	{OFFSET(gpmc_a3), MODE(1)},		/* MII2_TXD2 */
+	{OFFSET(gpmc_a4), MODE(1)},		/* MII2_TXD1 */
+	{OFFSET(gpmc_a5), MODE(1)},		/* MII2_TXD0 */
+	{OFFSET(gpmc_a6), MODE(1) | RXACTIVE},	/* MII2_TXCLK */
+	{OFFSET(gpmc_a7), MODE(1) | RXACTIVE},	/* MII2_RXCLK */
+	{OFFSET(gpmc_a8), MODE(1) | RXACTIVE},	/* MII2_RXD3 */
+	{OFFSET(gpmc_a9), MODE(1) | RXACTIVE},	/* MII2_RXD2 */
+	{OFFSET(gpmc_a10), MODE(1) | RXACTIVE},	/* MII2_RXD1 */
+	{OFFSET(gpmc_a11), MODE(1) | RXACTIVE},	/* MII2_RXD0 */
+	{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+	{OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
+						/*
+						 * MII2_CRS is shared with
+						 * NAND_WAIT0
+						 */
+	{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
+	{-1},
+};
+#ifdef CONFIG_MTD_RAW_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+static struct module_pin_mux gpIOs[] = {
+	/* GPIO0_6  (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
+	{OFFSET(spi0_cs1),  (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* TIMER5   (MMC0_DAT3) - TIMER5 (Buzzer) */
+	{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
+	/* TIMER6   (MMC0_DAT2) - PWM_BACK_3V3 */
+	{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_28 (MMC0_DAT1)	 - MII_nNAND */
+	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_29 (MMC0_DAT0)	 - NAND_1n0 */
+	{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
+	{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN  | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
+	{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
+	{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO2_0  (GPMC_nCS3) - DCOK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/*
+	 * GPIO0_7 (PWW0 OUT)
+	 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
+	 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
+	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - REP-Switch */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
+	{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
+	{OFFSET(mcasp0_fsx),   (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
+	{OFFSET(mcasp0_axr0),  (MODE(7) | PULLUDDIS) },
+	/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
+#ifndef CONFIG_MTD_RAW_NAND
+	/* GPIO2_3 - NAND_OE */
+	{OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+	/* GPIO2_4 - NAND_WEN */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+	/* GPIO2_5 - NAND_BE_CLE */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+#endif
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(mii2_pin_mux);
+#ifdef CONFIG_MTD_RAW_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_MMC)
+	configure_module_pin_mux(mmc1_pin_mux);
+#endif
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(uart1_pin_mux);
+	configure_module_pin_mux(gpIOs);
+}
@@ -0,0 +1,18 @@
+if TARGET_BRPPT2
+
+config SYS_BOARD
+	default "brppt2"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "brppt2"
+
+config SPL_DM_SPI
+	def_bool y
+
+endif
@@ -0,0 +1,6 @@
+BUR_PPT2 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brppt2/
+F:	include/configs/brppt2.h
+F:	configs/brppt2_defconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+# Copyright (C) 2019
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+obj-y := ../common/common.o
+obj-y += board.o
@@ -0,0 +1,542 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for BuR BRPPT2 board
+ *
+ * Copyright (C) 2019
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/
+ *
+ */
+#include <common.h>
+#include <spl.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#ifdef CONFIG_SPL_BUILD
+# include <asm/arch/mx6-ddr.h>
+#endif
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define USBHUB_RSTN	IMX_GPIO_NR(1, 16)
+#define BKLT_EN		IMX_GPIO_NR(1, 15)
+#define CAPT_INT	IMX_GPIO_NR(4, 9)
+#define CAPT_RESETN	IMX_GPIO_NR(4, 11)
+#define SW_INTN		IMX_GPIO_NR(3, 26)
+#define VCCDISP_EN	IMX_GPIO_NR(5, 18)
+#define EMMC_RSTN	IMX_GPIO_NR(6, 8)
+#define PMIC_IRQN	IMX_GPIO_NR(5, 22)
+#define TASTER		IMX_GPIO_NR(5, 23)
+
+#define ETH0_LINK	IMX_GPIO_NR(1, 27)
+#define ETH1_LINK	IMX_GPIO_NR(1, 28)
+
+#define UART_PAD_CTRL		(PAD_CTL_PUS_47K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL		(PAD_CTL_PUS_47K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ECSPI_PAD_CTRL		(PAD_CTL_PUS_100K_DOWN |		\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL		(PAD_CTL_PUS_47K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP |			\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL1		(PAD_CTL_PUS_100K_UP |			\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PU	(PAD_CTL_PUS_100K_UP |		\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK	((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) |	\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm |	\
+				PAD_CTL_SRE_FAST)
+
+#define GPIO_PAD_CTRL_PU	(PAD_CTL_PUS_100K_UP |			\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define GPIO_PAD_CTRL_PD	(PAD_CTL_PUS_100K_DOWN |		\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define LCDCMOS_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN |		\
+				PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
+				PAD_CTL_SRE_SLOW  | PAD_CTL_HYS)
+
+#define MUXDESC(pad, ctrl)	IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
+
+#if !defined(CONFIG_SPL_BUILD)
+static iomux_v3_cfg_t const eth_pads[] = {
+	/*
+	 * Gigabit Ethernet
+	 */
+	/* CLKs */
+	MUXDESC(PAD_GPIO_16__ENET_REF_CLK,	ENET_PAD_CTRL_CLK),
+	MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK,	ENET_PAD_CTRL_CLK),
+	/* MDIO */
+	MUXDESC(PAD_ENET_MDIO__ENET_MDIO,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_ENET_MDC__ENET_MDC,		ENET_PAD_CTRL_PU),
+	/* RGMII */
+	MUXDESC(PAD_RGMII_TXC__RGMII_TXC,	ENET_PAD_CTRL1),
+	MUXDESC(PAD_RGMII_TD0__RGMII_TD0,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TD1__RGMII_TD1,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TD2__RGMII_TD2,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TD3__RGMII_TD3,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL,	ENET_PAD_CTRL),
+	MUXDESC(PAD_RGMII_RXC__RGMII_RXC,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD0__RGMII_RD0,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD1__RGMII_RD1,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD2__RGMII_RD2,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RD3__RGMII_RD3,	ENET_PAD_CTRL_PU),
+	MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL,	ENET_PAD_CTRL_PU),
+	/* ETH0_LINK */
+	MUXDESC(PAD_ENET_RXD0__GPIO1_IO27,	GPIO_PAD_CTRL_PD),
+	/* ETH1_LINK */
+	MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28,	GPIO_PAD_CTRL_PD),
+};
+
+static iomux_v3_cfg_t const board_pads[] = {
+	/*
+	 * I2C #3, #4
+	 */
+	MUXDESC(PAD_GPIO_3__I2C3_SCL,		I2C_PAD_CTRL),
+	MUXDESC(PAD_GPIO_6__I2C3_SDA,		I2C_PAD_CTRL),
+
+	/*
+	 * UART#4 PADS
+	 * UART_Tasten
+	 */
+	MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B,	UART_PAD_CTRL),
+	/*
+	 * ESCPI#1
+	 * M25P32 NOR-Flash
+	 */
+	MUXDESC(PAD_EIM_D16__ECSPI1_SCLK,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D17__ECSPI1_MISO,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D18__ECSPI1_MOSI,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D19__GPIO3_IO19,	ECSPI_PAD_CTRL),
+	/*
+	 * ESCPI#2
+	 * resTouch SPI ADC
+	 */
+	MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_OE__ECSPI2_MISO,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D24__GPIO3_IO24,	ECSPI_PAD_CTRL),
+	/*
+	 * USDHC#4
+	 */
+	MUXDESC(PAD_SD4_CLK__SD4_CLK,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_CMD__SD4_CMD,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT0__SD4_DATA0,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT1__SD4_DATA1,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT2__SD4_DATA2,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT3__SD4_DATA3,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT4__SD4_DATA4,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT5__SD4_DATA5,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT6__SD4_DATA6,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT7__SD4_DATA7,	USDHC_PAD_CTRL),
+	/*
+	 * USB OTG power & ID
+	 */
+	/* USB_OTG_5V_EN */
+	MUXDESC(PAD_EIM_D22__GPIO3_IO22,	GPIO_PAD_CTRL_PD),
+	MUXDESC(PAD_EIM_D31__GPIO3_IO31,	GPIO_PAD_CTRL_PD),
+	/* USB_OTG_JUMPER */
+	MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID,	GPIO_PAD_CTRL_PD),
+	/*
+	 * PWM-Pins
+	 */
+	/* BKLT_CTL */
+	MUXDESC(PAD_SD1_CMD__PWM4_OUT,		GPIO_PAD_CTRL_PD),
+	/* SPEAKER */
+	MUXDESC(PAD_SD1_DAT1__PWM3_OUT,		GPIO_PAD_CTRL_PD),
+	/*
+	 * GPIOs
+	 */
+	/* USB_HUB_nRESET */
+	MUXDESC(PAD_SD1_DAT0__GPIO1_IO16,	GPIO_PAD_CTRL_PD),
+	/* BKLT_EN */
+	MUXDESC(PAD_SD2_DAT0__GPIO1_IO15,	GPIO_PAD_CTRL_PD),
+	/* capTouch_INT */
+	MUXDESC(PAD_KEY_ROW1__GPIO4_IO09,	GPIO_PAD_CTRL_PD),
+	/* capTouch_nRESET */
+	MUXDESC(PAD_KEY_ROW2__GPIO4_IO11,	GPIO_PAD_CTRL_PD),
+	/* SW_nINT */
+	MUXDESC(PAD_EIM_D26__GPIO3_IO26,	GPIO_PAD_CTRL_PU),
+	/* VCC_DISP_EN */
+	MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18,	GPIO_PAD_CTRL_PD),
+	/* eMMC_nRESET */
+	MUXDESC(PAD_NANDF_ALE__GPIO6_IO08,	GPIO_PAD_CTRL_PD),
+	/* HWID*/
+	MUXDESC(PAD_NANDF_D0__GPIO2_IO00,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D1__GPIO2_IO01,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D2__GPIO2_IO02,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D3__GPIO2_IO03,	GPIO_PAD_CTRL_PU),
+	/* PMIC_nIRQ */
+	MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22,	GPIO_PAD_CTRL_PU),
+	/* nTASTER */
+	MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23,	GPIO_PAD_CTRL_PU),
+	/* RGB LCD Display */
+	MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15,		LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22,	LCDCMOS_PAD_CTRL),
+	MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23,	LCDCMOS_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+	gpio_direction_output(USBHUB_RSTN, 1);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	ulong b_mode = 4;
+
+	if (gpio_get_value(TASTER) == 0)
+		b_mode = 12;
+
+	env_set_ulong("b_mode", b_mode);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	if (gpio_request(BKLT_EN, "BKLT_EN"))
+		printf("Warning: BKLT_EN setup failed\n");
+	gpio_direction_output(BKLT_EN, 0);
+
+	if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
+		printf("Warning: USBHUB_nRST setup failed\n");
+	gpio_direction_output(USBHUB_RSTN, 0);
+
+	if (gpio_request(TASTER, "TASTER"))
+		printf("Warning: TASTER setup failed\n");
+	gpio_direction_input(TASTER);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	SETUP_IOMUX_PADS(board_pads);
+	SETUP_IOMUX_PADS(eth_pads);
+
+	/* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
+	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+	enable_fec_anatop_clock(0, ENET_25MHZ);
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+#else
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0		= 0x00020030,
+	.dram_sdclk_1		= 0x00020030,
+	.dram_cas		= 0x00020030,
+	.dram_ras		= 0x00020030,
+	.dram_reset		= 0x00020030,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0		= 0x00003000,
+	.dram_sdcke1		= 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2		= 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0		= 0x00003030,
+	.dram_sdodt1		= 0x00003030,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0		= 0x00000030,
+	.dram_sdqs1		= 0x00000030,
+	.dram_sdqs2		= 0x00000030,
+	.dram_sdqs3		= 0x00000030,
+	.dram_sdqs4		= 0x00000030,
+	.dram_sdqs5		= 0x00000030,
+	.dram_sdqs6		= 0x00000030,
+	.dram_sdqs7		= 0x00000030,
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0		= 0x00020030,
+	.dram_dqm1		= 0x00020030,
+	.dram_dqm2		= 0x00020030,
+	.dram_dqm3		= 0x00020030,
+	.dram_dqm4		= 0x00020030,
+	.dram_dqm5		= 0x00020030,
+	.dram_dqm6		= 0x00020030,
+	.dram_dqm7		= 0x00020030,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
+	/* DDR3 */
+	.grp_ddr_type		= 0x000c0000,
+	.grp_ddrmode_ctl	= 0x00020000,
+	/* disable DDR pullups */
+	.grp_ddrpke		= 0x00000000,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds		= 0x00000030,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds		= 0x00000030,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode		= 0x00020000,
+	.grp_b0ds		= 0x00000030,
+	.grp_b1ds		= 0x00000030,
+	.grp_b2ds		= 0x00000030,
+	.grp_b3ds		= 0x00000030,
+	.grp_b4ds		= 0x00000030,
+	.grp_b5ds		= 0x00000030,
+	.grp_b6ds		= 0x00000030,
+	.grp_b7ds		= 0x00000030,
+};
+
+/*
+ * DDR3 desriptions - these are the memory chips we support
+ */
+
+/* NT5CC128M16FP-DII */
+static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
+	.mem_speed      = 1600,
+	.density        = 2,
+	.width          = 16,
+	.banks          = 8,
+	.rowaddr        = 14,
+	.coladdr        = 10,
+	.pagesz         = 2,
+	.trcd           = 1375,
+	.trcmin         = 4875,
+	.trasmin        = 3500,
+};
+
+/* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
+static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
+	/* write leveling calibration determine, MR1-value = 0x0002 */
+	.p0_mpwldectrl0 = 0x003F003E,
+	.p0_mpwldectrl1 = 0x003A003A,
+	.p1_mpwldectrl0 = 0x001B001C,
+	.p1_mpwldectrl1 = 0x00190031,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x02640264,
+	.p0_mpdgctrl1   = 0x02440250,
+	.p1_mpdgctrl0   = 0x02400250,
+	.p1_mpdgctrl1   = 0x0238023C,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x40464644,
+	.p1_mprddlctl   = 0x464A4842,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x38343034,
+	.p1_mpwrdlctl   = 0x36323830,
+};
+
+/* measured on board TSERIES_ARM/1 V_LVDS_S32 */
+static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
+	/* write leveling calibration determine, MR1-value = 0x0002 */
+	.p0_mpwldectrl0 = 0x00410043,
+	.p0_mpwldectrl1 = 0x003A003C,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x023C0244,
+	.p0_mpdgctrl1   = 0x02240230,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x484C4A48,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x3C363434,
+};
+
+static void spl_dram_init(void)
+{
+	struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
+	u32 val, dram_strap = 0;
+	struct mx6_ddr3_cfg *mem = NULL;
+	struct mx6_mmdc_calibration *calib = NULL;
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize		= -1,	/* CPU type specific (overwritten) */
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density	= 32,	/* 32Gb per CS */
+		.ncs		= 1,	/* single chip select */
+		.cs1_mirror	= 0,
+		.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+		.rtt_nom	= 1,	/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+		.walat		= 1,	/* Write additional latency */
+		.ralat		= 5,	/* Read additional latency */
+		.mif3_mode	= 3,	/* Command prediction working mode */
+		.bi_on		= 1,	/* Bank interleaving enabled */
+		.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type	= 0,	/* DDR3 */
+	};
+
+	/*
+	 * MMDC Calibration requires the following data:
+	 *  mx6_mmdc_calibration - board-specific calibration (routing delays)
+	 *     these calibration values depend on board routing, SoC, and DDR
+	 *  mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
+	 *  mx6_ddr_cfg - chip specific timing/layout details
+	 */
+
+	/* setup HWID3-2 to input */
+	val = readl(&gpio->gpio_dir);
+	val &= ~(0x1 << 0 | 0x1 << 1);
+	writel(val, &gpio->gpio_dir);
+
+	/* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
+	dram_strap = readl(&gpio->gpio_psr) & 0x3;
+
+	switch (dram_strap) {
+	/* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
+	case 0:
+		puts("DRAM strap 00\n");
+		mem = &cfg_nt5cc128m16fp_dii;
+		sysinfo.dsize = 2;
+		calib = &cal_nt5cc128m16fp_dii_128x64_s;
+		break;
+	/* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
+	case 1:
+		puts("DRAM strap 01\n");
+		mem = &cfg_nt5cc128m16fp_dii;
+		sysinfo.dsize = 1;
+		calib = &cal_nt5cc128m16fp_dii_128x32_s;
+		break;
+	default:
+		printf("DRAM strap 0x%x (invalid)\n", dram_strap);
+		break;
+	}
+
+	if (!mem) {
+		puts("Error: Invalid Memory Configuration\n");
+		hang();
+	}
+	if (!calib) {
+		puts("Error: Invalid Board Calibration Configuration\n");
+		hang();
+	}
+
+	mx6sdl_dram_iocfg(16 << sysinfo.dsize,
+			  &ddr_iomux_s,
+			  &grp_iomux_s);
+
+	mx6_dram_cfg(&sysinfo, calib, mem);
+}
+
+static iomux_v3_cfg_t const board_pads_spl[] = {
+	/* UART#1 PADS */
+	MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA,	UART_PAD_CTRL),
+	MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA,	UART_PAD_CTRL),
+	/* ESCPI#1 PADS */
+	MUXDESC(PAD_EIM_D16__ECSPI1_SCLK,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D17__ECSPI1_MISO,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D18__ECSPI1_MOSI,	ECSPI_PAD_CTRL),
+	MUXDESC(PAD_EIM_D19__GPIO3_IO19,	ECSPI_PAD_CTRL),
+	/* USDHC#4 PADS */
+	MUXDESC(PAD_SD4_CLK__SD4_CLK,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_CMD__SD4_CMD,		USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT0__SD4_DATA0,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT1__SD4_DATA1,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT2__SD4_DATA2,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT3__SD4_DATA3,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT4__SD4_DATA4,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT5__SD4_DATA5,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT6__SD4_DATA6,	USDHC_PAD_CTRL),
+	MUXDESC(PAD_SD4_DAT7__SD4_DATA7,	USDHC_PAD_CTRL),
+	/* HWID*/
+	MUXDESC(PAD_NANDF_D0__GPIO2_IO00,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D1__GPIO2_IO01,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D2__GPIO2_IO02,	GPIO_PAD_CTRL_PU),
+	MUXDESC(PAD_NANDF_D3__GPIO2_IO03,	GPIO_PAD_CTRL_PU),
+};
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*
+	 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
+	 * initializes DMA very early (before all board code), so the only
+	 * opportunity we have to initialize APBHDMA clocks is in SPL.
+	 * setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+	 */
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x00F0FC03, &ccm->CCGR1);
+	writel(0x0FFFF000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0030C3, &ccm->CCGR5);
+	writel(0x000003F0, &ccm->CCGR6);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+	arch_cpu_init();
+	timer_init();
+	gpr_init();
+
+	SETUP_IOMUX_PADS(board_pads_spl);
+	spl_dram_init();
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif /* CONFIG_SPL_BUILD */
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/imx6dl-//')
+
+payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
+
+quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
+cmd_prodbin =								\
+	dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
+	dd conv=notrunc bs=1 if=SPL of=$@ seek=1024 2>/dev/null && \
+	dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
+
+quiet_cmd_prodzip = SAPZIP  $@
+cmd_prodzip =					\
+	test -d misc && rm -r misc;		\
+	mkdir misc &&				\
+	cp SPL misc/ &&				\
+	cp u-boot-dtb.img misc/ &&		\
+	zip -9 -r $@ misc/* >/dev/null $<
+
+ifeq ($(hw-platform-y),brppt2)
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-y += $(hw-platform-y)_prog.bin
+ALL-y += $(hw-platform-y)_prod.zip
+endif
+endif
+
+$(hw-platform-y)_prog.bin: u-boot-dtb.img spl SPL
+	$(call if_changed,prodbin)
+
+$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
+	$(call if_changed,prodzip)
@@ -0,0 +1,15 @@
+if TARGET_BRSMARC1
+
+config SYS_BOARD
+	default "brsmarc1"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "brsmarc1"
+
+endif
@@ -0,0 +1,6 @@
+BRSMARC1 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brsmarc1/
+F:	include/configs/brsmarc1.h
+F:	configs/brsmarc1_defconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com/
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y	+= ../common/br_resetc.o
+obj-y	+= ../common/common.o
+obj-y	+= board.o
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for B&R BRSMARC1 Board
+ *
+ * Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/emif.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+#include "../common/br_resetc.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define PER_RESET		(2 * 32 + 0)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+
+	int rc;
+	/*
+	 * enable additional clocks of modules which are accessed later from
+	 * VxWorks OS
+	 */
+	u32 *const clk_domains[] = { 0 };
+	u32 *const clk_modules_specific[] = {
+		&cmwkup->wkup_adctscctrl,
+		&cmper->spi1clkctrl,
+		&cmper->dcan0clkctrl,
+		&cmper->dcan1clkctrl,
+		&cmper->timer4clkctrl,
+		&cmper->timer5clkctrl,
+		&cmper->lcdclkctrl,
+		&cmper->lcdcclkstctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_specific, 1);
+
+	/* setup I2C */
+	enable_i2c_pin_mux();
+
+	/* peripheral reset */
+	rc = gpio_request(PER_RESET, "PER_RESET");
+	if (rc != 0)
+		printf("cannot request PER_RESET GPIO!\n");
+
+	rc = gpio_direction_output(PER_RESET, 0);
+	if (rc != 0)
+		printf("cannot set PER_RESET GPIO!\n");
+
+	/* setup pmic */
+	pmicsetup(0, 0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+#if !defined(CONFIG_SPL_BUILD)
+
+/* decision if backlight is switched on or not on powerup */
+int board_backlightstate(void)
+{
+	u8 bklmask, rstcause;
+	int rc = 0;
+
+	rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
+	rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
+
+	if (rc != 0) {
+		printf("%s: read rstctrl failed!\n", __func__);
+		return 1;
+	}
+
+	if ((rstcause & bklmask) != 0)
+		return 0;
+
+	return 1;
+}
+
+/* Basic board specific setup. run quite after relocation */
+int board_init(void)
+{
+	if (power_tps65217_init(0))
+		printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_BOARD_LATE_INIT)
+
+int board_late_init(void)
+{
+	br_resetc_bmode();
+
+	return 0;
+}
+
+#endif /* CONFIG_BOARD_LATE_INIT */
+#endif /* !CONFIG_SPL_BUILD */
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
+
+payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
+
+quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
+cmd_prodbin =								\
+	dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
+	dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
+	dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
+
+quiet_cmd_prodzip = SAPZIP  $@
+cmd_prodzip =					\
+	test -d misc && rm -r misc;		\
+	mkdir misc &&				\
+	cp MLO.byteswap misc/ &&		\
+	cp spl/u-boot-spl.bin misc/ &&		\
+	cp u-boot-dtb.img misc/ &&		\
+	zip -9 -r $@ misc/* >/dev/null $<
+
+ALL-y += $(hw-platform-y)_prog.bin
+ALL-y += $(hw-platform-y)_prod.zip
+
+$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
+	$(call if_changed,prodbin)
+
+$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
+	$(call if_changed,prodzip)
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
+ *
+ * Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI0_SCLK */
+	{OFFSET(spi0_sclk),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI0_D0 */
+	{OFFSET(spi0_d0),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI0_D1 */
+	{OFFSET(spi0_d1),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI0_CS0 */
+	{OFFSET(spi0_cs0),	MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	/* SPI0_CS1 */
+	{OFFSET(spi0_cs1),	MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+	/* SPI1_SCLK */
+	{OFFSET(mcasp0_aclkx),	MODE(3) | PULLUDEN | RXACTIVE},
+	/* SPI1_D0 */
+	{OFFSET(mcasp0_fsx),	MODE(3) | PULLUDEN | RXACTIVE},
+	/* SPI1_D1 */
+	{OFFSET(mcasp0_axr0),	MODE(3) | PULLUDEN | RXACTIVE},
+	/* SPI1_CS0 */
+	{OFFSET(mcasp0_ahclkr),	MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	/* SPI1_CS1 */
+	{OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+	/* DCAN0 TX */
+	{OFFSET(uart1_ctsn),	MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN0 RX */
+	{OFFSET(uart1_rtsn),	MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+	/* DCAN1 TX */
+	{OFFSET(uart0_ctsn),	MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN1 RX */
+	{OFFSET(uart0_rtsn),	MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux gpios[] = {
+	/* GPIO0_7 - LVDS_EN */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO0_20 - BKLT_PWM (timer7) */
+	{OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO2_4 - DISON */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO1_24 - RGB_EN */
+	{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO1_28 - nPD */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
+	/* GPIO2_5 - Watchdog */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO2_0 - ResetOut */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
+	/* GPIO2_2 - BKLT_EN */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+	/* GPIO1_17 - GPIO0 */
+	{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_18 - GPIO1 */
+	{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_19 - GPIO2 */
+	{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_22 - GPIO3 */
+	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_23 - GPIO4 */
+	{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_25 - GPIO5 */
+	{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_7 - GPIO6 */
+	{OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_8 - GPIO7 */
+	{OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_18 - GPIO8 */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_19 - GPIO9 */
+	{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_20 - GPIO10 */
+	{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_21 - GPIO11 */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO2_28 - DRAM-strapping */
+	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+	/* GPIO2_4 - not routed (Pin U6) */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO2_5 - not routed (Pin T6) */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO2_28 - not routed (Pin G15) */
+	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_18 - not routed (Pin B12) */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux uart234_pin_mux[] = {
+	/* UART2_RXD */
+	{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART2_TXD */
+	{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
+
+	/* UART3_RXD */
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART3_TXD */
+	{OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
+	/* UART3_RTS */
+	{OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
+	/* UART3_CTS */
+	{OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+
+	/* UART4_RXD */
+	{OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART4_TXD */
+	{OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
+	/* UART4_RTS */
+	{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
+	/* UART4_CTS */
+	{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+
+	{-1},
+};
+
+static struct module_pin_mux i2c_pin_mux[] = {
+	/* I2C0_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C0_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C1_DATA */
+	{OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C1_SCLK */
+	{OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux eth_pin_mux[] = {
+	/* ETH1 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* ETH1_REFCLK */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRSDV */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXER */
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+
+	/* ETH2 */
+	{OFFSET(mii1_col), MODE(1) | RXACTIVE},		/* ETH2_REFCLK */
+	{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE},	/* RMII2_CRSDV */
+	{OFFSET(gpmc_wpn), MODE(3) | RXACTIVE},		/* RMII2_RXER */
+	{OFFSET(gpmc_a0), MODE(3)},			/* RMII2_TXEN */
+	{OFFSET(gpmc_a11), MODE(3) | RXACTIVE},		/* RMII2_RXD0 */
+	{OFFSET(gpmc_a10), MODE(3) | RXACTIVE},		/* RMII2_RXD1 */
+	{OFFSET(gpmc_a5), MODE(3)},			/* RMII2_TXD0 */
+	{OFFSET(gpmc_a4), MODE(3)},			/* RMII2_TXD1 */
+
+	/* gpio2_19, gpio 3_4, not connected on board */
+	{OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+
+	/* ETH Management */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},	/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},		/* MDIO_CLK */
+
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c_pin_mux(void)
+{
+	configure_module_pin_mux(i2c_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(eth_pin_mux);
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(spi1_pin_mux);
+	configure_module_pin_mux(dcan0_pin_mux);
+	configure_module_pin_mux(dcan1_pin_mux);
+	configure_module_pin_mux(uart234_pin_mux);
+	configure_module_pin_mux(mmc1_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(gpios);
+}
@@ -0,0 +1,15 @@
+if TARGET_BRXRE1
+
+config SYS_BOARD
+	default "brxre1"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "brxre1"
+
+endif
@@ -0,0 +1,7 @@
+BRXRE1 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brxre1/
+F:	include/configs/brxre1.h
+F:	configs/brxre1_defconfig
+F:	arch/arm/dts/am335x-brxre1.dts
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y	+= ../common/br_resetc.o
+obj-y	+= ../common/common.o
+obj-y	+= board.o
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for B&R BRXRE1 Board
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ */
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <dm.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+#include "../common/br_resetc.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define ESC_KEY					(0 + 19)
+#define LCD_PWR					(0 + 5)
+
+#define	RSTCTRL_FORCE_PWR_NEN			0x04
+#define	RSTCTRL_CAN_STB				0x40
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int rc;
+
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+	/*
+	 * enable additional clocks of modules which are accessed later from
+	 * VxWorks OS
+	 */
+	u32 *const clk_domains[] = { 0 };
+
+	u32 *const clk_modules_xre1specific[] = {
+		&cmwkup->wkup_adctscctrl,
+		&cmper->spi1clkctrl,
+		&cmper->dcan0clkctrl,
+		&cmper->dcan1clkctrl,
+		&cmper->epwmss0clkctrl,
+		&cmper->epwmss1clkctrl,
+		&cmper->epwmss2clkctrl,
+		&cmper->lcdclkctrl,
+		&cmper->lcdcclkstctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
+	/* power-OFF LCD-Display */
+	if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
+		printf("cannot request gpio for LCD_PWR!\n");
+	else if (gpio_direction_output(LCD_PWR, 0) != 0)
+		printf("cannot set direction output on LCD_PWR!\n");
+
+	/* setup I2C */
+	enable_i2c_pin_mux();
+
+	/* power-ON 3V3 via Resetcontroller */
+	rc = br_resetc_regset(RSTCTRL_CTRLREG,
+			      RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB);
+	if (rc != 0)
+		printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");
+
+	pmicsetup(0, 0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	/* request common used gpios */
+	gpio_request(ESC_KEY, "boot-key");
+
+	if (power_tps65217_init(0))
+		printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+
+int board_boot_key(void)
+{
+	return gpio_get_value(ESC_KEY);
+}
+
+int board_late_init(void)
+{
+	char othbootargs[128];
+
+	br_resetc_bmode();
+
+	/* setup othbootargs for bootvx-command (vxWorks bootline) */
+	snprintf(othbootargs, sizeof(othbootargs),
+		 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
+		 (u32)gd->fb_base - 0x20,
+		 (u32)env_get_ulong("vx_memtop", 16, gd->fb_base - 0x20),
+		 (u32)env_get_ulong("vx_romfsbase", 16, 0),
+		 (u32)env_get_ulong("vx_romfssize", 16, 0));
+	env_set("othbootargs", othbootargs);
+	/*
+	 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
+	 * expect that vectors are there, original u-boot moves them to _start
+	 */
+	__asm__("ldr r0,=0x20000");
+	__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI1_SCLK */
+	{OFFSET(spi0_sclk),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI1_D0 */
+	{OFFSET(spi0_d0),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI1_D1 */
+	{OFFSET(spi0_d1),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI1_CS0 */
+	{OFFSET(spi0_cs0),	MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	/* SPI1_CS1 */
+	{OFFSET(spi0_cs1),	MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+	/* DCAN0 TX */
+	{OFFSET(uart1_ctsn),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN0 RX */
+	{OFFSET(uart1_rtsn),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+	/* DCAN1 TX */
+	{OFFSET(uart1_rxd),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN1 RX */
+	{OFFSET(uart1_txd),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux gpios[] = {
+	/* GPIO0_7  (PWW0 OUT) - CAN TERM */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - TA602 */
+	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
+	/* GPIO0_30 (GPMC_WAIT0) - TA601 */
+	{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+	/* GPIO1_29 (gpmc_csn0) - MMC nRST */
+	{OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
+	/* GPIO2_0  (GPMC_nCS3)	- VBAT_OK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO2_2  (GPMC_nADV_ALE) - DCOK */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO2_4  (GPMC_nWE) - TST_BAST */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+	/* GPIO2_5  (gpmc_be0n_cle) - DISPLAY_ON_OFF */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
+	/* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
+	{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
+	{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
+	{OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
+	{OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(dcan0_pin_mux);
+	configure_module_pin_mux(dcan1_pin_mux);
+	configure_module_pin_mux(mmc1_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(gpios);
+}
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * common reset-controller functions for B&R boards
+ *
+ * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/ *
+ */
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <i2c.h>
+#include <dm/uclass.h>
+#include "br_resetc.h"
+
+/* I2C Address of controller */
+#define	RSTCTRL_ADDR_PSOC	0x75
+#define	RSTCTRL_ADDR_STM32	0x60
+
+#define BMODE_DEFAULTAR		0
+#define BMODE_SERVICE		2
+#define BMODE_RUN		4
+#define BMODE_PME		12
+#define BMODE_DIAG		15
+
+#ifdef CONFIG_LCD
+#include <lcd.h>
+#define LCD_SETCURSOR(x, y)	lcd_position_cursor(x, y)
+#define LCD_PUTS(x)		lcd_puts(x)
+#else
+#define LCD_SETCURSOR(x, y)
+#define LCD_PUTS(x)
+#endif /* CONFIG_LCD */
+
+static const char *bootmodeascii[16] = {
+	"BOOT",		"reserved",	"reserved",	"reserved",
+	"RUN",		"reserved",	"reserved",	"reserved",
+	"reserved",	"reserved",	"reserved",	"reserved",
+	"PME",		"reserved",	"reserved",	"DIAG",
+};
+
+struct br_reset_t {
+	struct udevice *i2cdev;
+	u8 is_psoc;
+};
+
+static struct br_reset_t resetc;
+
+__weak int board_boot_key(void)
+{
+	return 0;
+}
+
+__weak void board_boot_led(unsigned int on)
+{
+}
+
+static int resetc_init(void)
+{
+	struct udevice *i2cbus;
+	int rc;
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus);
+	if (rc) {
+		printf("Cannot find I2C bus #0!\n");
+		return -1;
+	}
+
+	resetc.is_psoc = 1;
+	rc = dm_i2c_probe(i2cbus,
+			  RSTCTRL_ADDR_PSOC, 0, &resetc.i2cdev);
+	if (rc) {
+		resetc.is_psoc = 0;
+		rc = dm_i2c_probe(i2cbus,
+				  RSTCTRL_ADDR_STM32, 0, &resetc.i2cdev);
+	}
+
+	if (rc)
+		printf("Warning: cannot probe BuR resetcontroller!\n");
+
+	return rc;
+}
+
+int br_resetc_regget(u8 reg, u8 *dst)
+{
+	int rc = 0;
+
+	if (!resetc.i2cdev)
+		rc = resetc_init();
+
+	if (rc != 0)
+		return rc;
+
+	return dm_i2c_read(resetc.i2cdev, reg, dst, 1);
+}
+
+int br_resetc_regset(u8 reg, u8 val)
+{
+	int rc = 0;
+	u16 regw = (val << 8) | val;
+
+	if (!resetc.i2cdev)
+		rc = resetc_init();
+
+	if (rc != 0)
+		return rc;
+
+	if (resetc.is_psoc)
+		return dm_i2c_write(resetc.i2cdev, reg, (u8 *)&regw, 2);
+
+	return dm_i2c_write(resetc.i2cdev, reg, (u8 *)&regw, 1);
+}
+
+int br_resetc_bmode(void)
+{
+	int rc = 0;
+	u16 regw;
+	u8 regb, scr;
+	int cnt;
+	unsigned int bmode = 0;
+
+	if (!resetc.i2cdev)
+		rc = resetc_init();
+
+	if (rc != 0)
+		return rc;
+
+	rc = dm_i2c_read(resetc.i2cdev, RSTCTRL_ENHSTATUS, &regb, 1);
+	if (rc != 0) {
+		printf("WARN: cannot read ENHSTATUS from resetcontroller!\n");
+		return -1;
+	}
+
+	rc = dm_i2c_read(resetc.i2cdev, RSTCTRL_SCRATCHREG0, &scr, 1);
+	if (rc != 0) {
+		printf("WARN: cannot read SCRATCHREG from resetcontroller!\n");
+		return -1;
+	}
+
+	board_boot_led(1);
+
+	/* special bootmode from resetcontroller */
+	if (regb & 0x4) {
+		bmode = BMODE_DIAG;
+	} else if (regb & 0x8) {
+		bmode = BMODE_DEFAULTAR;
+	} else if (board_boot_key() != 0) {
+		cnt = 4;
+		do {
+			LCD_SETCURSOR(1, 8);
+			switch (cnt) {
+			case 4:
+				LCD_PUTS
+				("release KEY to enter SERVICE-mode.     ");
+				break;
+			case 3:
+				LCD_PUTS
+				("release KEY to enter DIAGNOSE-mode.    ");
+				break;
+			case 2:
+				LCD_PUTS
+				("release KEY to enter BOOT-mode.        ");
+				break;
+			}
+			mdelay(1000);
+			cnt--;
+			if (board_boot_key() == 0)
+				break;
+		} while (cnt);
+
+		switch (cnt) {
+		case 0:
+			bmode = BMODE_PME;
+			break;
+		case 1:
+			bmode = BMODE_DEFAULTAR;
+			break;
+		case 2:
+			bmode = BMODE_DIAG;
+			break;
+		case 3:
+			bmode = BMODE_SERVICE;
+			break;
+		}
+	} else if ((regb & 0x1) || scr == 0xCC) {
+		bmode = BMODE_PME;
+	} else {
+		bmode = BMODE_RUN;
+	}
+
+	LCD_SETCURSOR(1, 8);
+
+	switch (bmode) {
+	case BMODE_PME:
+		LCD_PUTS("entering PME-Mode (netscript).         ");
+		regw = 0x0C0C;
+		break;
+	case BMODE_DEFAULTAR:
+		LCD_PUTS("entering BOOT-mode.                    ");
+		regw = 0x0000;
+		break;
+	case BMODE_DIAG:
+		LCD_PUTS("entering DIAGNOSE-mode.                ");
+		regw = 0x0F0F;
+		break;
+	case BMODE_SERVICE:
+		LCD_PUTS("entering SERVICE mode.                 ");
+		regw = 0xB4B4;
+		break;
+	case BMODE_RUN:
+		LCD_PUTS("loading OS...                          ");
+		regw = 0x0404;
+		break;
+	}
+
+	board_boot_led(0);
+
+	if (resetc.is_psoc)
+		rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+				  (u8 *)&regw, 2);
+	else
+		rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+				  (u8 *)&regw, 1);
+
+	if (rc != 0)
+		printf("WARN: cannot write into resetcontroller!\n");
+
+	if (resetc.is_psoc)
+		printf("Reset: PSOC controller\n");
+	else
+		printf("Reset: STM32 controller\n");
+
+	printf("Mode:  %s\n", bootmodeascii[regw & 0x0F]);
+	env_set_ulong("b_mode", regw & 0x0F);
+
+	return rc;
+}
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * common reset-controller functions for B&R boards
+ *
+ * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/ *
+ */
+#ifndef __CONFIG_BRRESETC_H__
+#define __CONFIG_BRRESETC_H__
+#include <common.h>
+
+int br_resetc_regget(u8 reg, u8 *dst);
+int br_resetc_regset(u8 reg, u8 val);
+int br_resetc_bmode(void);
+
+/* reset controller register defines */
+#define RSTCTRL_CTRLREG		0x01
+#define RSTCTRL_SCRATCHREG0	0x04
+#define RSTCTRL_ENHSTATUS	0x07
+#define RSTCTRL_SCRATCHREG1	0x08
+#define RSTCTRL_RSTCAUSE	0x00
+#define RSTCTRL_ERSTCAUSE	0x09
+#define RSTCTRL_SPECGPIO_I	0x0A
+#define RSTCTRL_SPECGPIO_O	0x0B
+
+#endif /* __CONFIG_BRRESETC_H__ */
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * bur_comon.h
+ *
+ * common board information header for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#ifndef _BUR_COMMON_H_
+#define _BUR_COMMON_H_
+
+#include <../../../drivers/video/am335x-fb.h>
+
+int load_lcdtiming(struct am335x_lcdpanel *panel);
+void br_summaryscreen(void);
+void pmicsetup(u32 mpupll, unsigned int bus);
+void enable_uart0_pin_mux(void);
+void enable_i2c_pin_mux(void);
+void enable_board_pin_mux(void);
+int board_eth_init(bd_t *bis);
+
+int brdefaultip_setup(int bus, int chip);
+
+#endif
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * common.c
+ *
+ * common board functions for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ */
+#include <version.h>
+#include <common.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <lcd.h>
+#include "bur_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* --------------------------------------------------------------------------*/
+#if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \
+	!defined(CONFIG_SPL_BUILD)
+#include <asm/arch/hardware.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#include <power/tps65217.h>
+#include "../../../drivers/video/am335x-fb.h"
+
+void lcdbacklight(int on)
+{
+	unsigned int driver = env_get_ulong("ds1_bright_drv", 16, 0UL);
+	unsigned int bright = env_get_ulong("ds1_bright_def", 10, 50);
+	unsigned int pwmfrq = env_get_ulong("ds1_pwmfreq", 10, ~0UL);
+	unsigned int tmp;
+	struct gptimer *timerhw;
+
+	if (on)
+		bright = bright != ~0UL ? bright : 50;
+	else
+		bright = 0;
+
+	switch (driver) {
+	case 2:
+		timerhw = (struct gptimer *)DM_TIMER5_BASE;
+		break;
+	default:
+		timerhw = (struct gptimer *)DM_TIMER6_BASE;
+	}
+
+	switch (driver) {
+	case 0:	/* PMIC LED-Driver */
+		/* brightness level */
+		tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+				   TPS65217_WLEDCTRL2, bright, 0xFF);
+		/* current sink */
+		tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+				   TPS65217_WLEDCTRL1,
+				   bright != 0 ? 0x0A : 0x02,
+				   0xFF);
+		break;
+	case 1:
+	case 2: /* PWM using timer */
+		if (pwmfrq != ~0UL) {
+			timerhw->tiocp_cfg = TCFG_RESET;
+			udelay(10);
+			while (timerhw->tiocp_cfg & TCFG_RESET)
+				;
+			tmp = ~0UL-(V_OSCK/pwmfrq);	/* bottom value */
+			timerhw->tldr = tmp;
+			timerhw->tcrr = tmp;
+			tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright;
+			timerhw->tmar = tmp;
+			timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) |
+					TCLR_CE | TCLR_AR | TCLR_ST);
+		} else {
+			puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n");
+		}
+		break;
+	default:
+		puts("no suitable backlightdriver in env/dtb!\n");
+		break;
+	}
+}
+
+int load_lcdtiming(struct am335x_lcdpanel *panel)
+{
+	struct am335x_lcdpanel pnltmp;
+
+	pnltmp.hactive = env_get_ulong("ds1_hactive", 10, ~0UL);
+	pnltmp.vactive = env_get_ulong("ds1_vactive", 10, ~0UL);
+	pnltmp.bpp = env_get_ulong("ds1_bpp", 10, ~0UL);
+	pnltmp.hfp = env_get_ulong("ds1_hfp", 10, ~0UL);
+	pnltmp.hbp = env_get_ulong("ds1_hbp", 10, ~0UL);
+	pnltmp.hsw = env_get_ulong("ds1_hsw", 10, ~0UL);
+	pnltmp.vfp = env_get_ulong("ds1_vfp", 10, ~0UL);
+	pnltmp.vbp = env_get_ulong("ds1_vbp", 10, ~0UL);
+	pnltmp.vsw = env_get_ulong("ds1_vsw", 10, ~0UL);
+	pnltmp.pxl_clk = env_get_ulong("ds1_pxlclk", 10, ~0UL);
+	pnltmp.pol = env_get_ulong("ds1_pol", 16, ~0UL);
+	pnltmp.pup_delay = env_get_ulong("ds1_pupdelay", 10, ~0UL);
+	pnltmp.pon_delay = env_get_ulong("ds1_tondelay", 10, ~0UL);
+	panel_info.vl_rot = env_get_ulong("ds1_rotation", 10, 0);
+
+	if (
+	   ~0UL == (pnltmp.hactive) ||
+	   ~0UL == (pnltmp.vactive) ||
+	   ~0UL == (pnltmp.bpp) ||
+	   ~0UL == (pnltmp.hfp) ||
+	   ~0UL == (pnltmp.hbp) ||
+	   ~0UL == (pnltmp.hsw) ||
+	   ~0UL == (pnltmp.vfp) ||
+	   ~0UL == (pnltmp.vbp) ||
+	   ~0UL == (pnltmp.vsw) ||
+	   ~0UL == (pnltmp.pxl_clk) ||
+	   ~0UL == (pnltmp.pol) ||
+	   ~0UL == (pnltmp.pup_delay) ||
+	   ~0UL == (pnltmp.pon_delay)
+	   ) {
+		puts("lcd-settings in env/dtb incomplete!\n");
+		printf("display-timings:\n"
+			"================\n"
+			"hactive: %d\n"
+			"vactive: %d\n"
+			"bpp    : %d\n"
+			"hfp    : %d\n"
+			"hbp    : %d\n"
+			"hsw    : %d\n"
+			"vfp    : %d\n"
+			"vbp    : %d\n"
+			"vsw    : %d\n"
+			"pxlclk : %d\n"
+			"pol    : 0x%08x\n"
+			"pondly : %d\n",
+			pnltmp.hactive, pnltmp.vactive, pnltmp.bpp,
+			pnltmp.hfp, pnltmp.hbp, pnltmp.hsw,
+			pnltmp.vfp, pnltmp.vbp, pnltmp.vsw,
+			pnltmp.pxl_clk, pnltmp.pol, pnltmp.pon_delay);
+
+		return -1;
+	}
+	debug("lcd-settings in env complete, taking over.\n");
+	memcpy((void *)panel,
+	       (void *)&pnltmp,
+	       sizeof(struct am335x_lcdpanel));
+
+	return 0;
+}
+
+static void br_summaryscreen_printenv(char *prefix,
+				       char *name, char *altname,
+				       char *suffix)
+{
+	char *envval = env_get(name);
+	if (0 != envval) {
+		lcd_printf("%s %s %s", prefix, envval, suffix);
+	} else if (0 != altname) {
+		envval = env_get(altname);
+		if (0 != envval)
+			lcd_printf("%s %s %s", prefix, envval, suffix);
+	} else {
+		lcd_printf("\n");
+	}
+}
+
+void br_summaryscreen(void)
+{
+	br_summaryscreen_printenv(" - B&R -", "br_orderno", 0, "-\n");
+	br_summaryscreen_printenv(" Serial/Rev :", "br_serial", 0, "\n");
+	br_summaryscreen_printenv(" MAC1       :", "br_mac1", "ethaddr", "\n");
+	br_summaryscreen_printenv(" MAC2       :", "br_mac2", 0, "\n");
+	lcd_puts(" Bootloader : " PLAIN_VERSION "\n");
+	lcd_puts("\n");
+}
+
+void lcdpower(int on)
+{
+	u32 pin, swval, i;
+	char buf[16] = { 0 };
+
+	pin = env_get_ulong("ds1_pwr", 16, ~0UL);
+
+	if (pin == ~0UL) {
+		puts("no pwrpin in dtb/env, cannot powerup display!\n");
+		return;
+	}
+
+	for (i = 0; i < 3; i++) {
+		if (pin != 0) {
+			snprintf(buf, sizeof(buf), "ds1_pwr#%d", i);
+			if (gpio_request(pin & 0x7F, buf) != 0) {
+				printf("%s: not able to request gpio %s",
+				       __func__, buf);
+				continue;
+			}
+			swval = pin & 0x80 ? 0 : 1;
+			if (on)
+				gpio_direction_output(pin & 0x7F, swval);
+			else
+				gpio_direction_output(pin & 0x7F, !swval);
+
+			debug("switched pin %d to %d\n", pin & 0x7F, swval);
+		}
+		pin >>= 8;
+	}
+}
+
+vidinfo_t	panel_info = {
+		.vl_col = 1366,	/*
+				 * give full resolution for allocating enough
+				 * memory
+				 */
+		.vl_row = 768,
+		.vl_bpix = 5,
+		.priv = 0
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	struct am335x_lcdpanel lcd_panel;
+
+	memset(&lcd_panel, 0, sizeof(struct am335x_lcdpanel));
+	if (load_lcdtiming(&lcd_panel) != 0)
+		return;
+
+	lcd_panel.panel_power_ctrl = &lcdpower;
+
+	if (0 != am335xfb_init(&lcd_panel))
+		printf("ERROR: failed to initialize video!");
+	/*
+	 * modifiy panel info to 'real' resolution, to operate correct with
+	 * lcd-framework.
+	 */
+	panel_info.vl_col = lcd_panel.hactive;
+	panel_info.vl_row = lcd_panel.vactive;
+
+	lcd_set_flush_dcache(1);
+}
+
+void lcd_enable(void)
+{
+	br_summaryscreen();
+	lcdbacklight(1);
+}
+#endif /* CONFIG_LCD */
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+
+	nodeoffset = fdt_path_offset(blob, "/factory-settings");
+	if (nodeoffset < 0) {
+		printf("%s: cannot find /factory-settings, trying /fset\n",
+		       __func__);
+		nodeoffset = fdt_path_offset(blob, "/fset");
+		if (nodeoffset < 0) {
+			printf("%s: cannot find /fset.\n", __func__);
+			return 0;
+		}
+	}
+
+	if (fdt_setprop(blob, nodeoffset, "bl-version",
+			PLAIN_VERSION, strlen(PLAIN_VERSION)) != 0) {
+		printf("%s: no 'bl-version' prop in fdt!\n", __func__);
+		return 0;
+	}
+	return 0;
+}
+
+int brdefaultip_setup(int bus, int chip)
+{
+	int rc;
+	struct udevice *i2cdev;
+	u8 u8buf = 0;
+	char defip[256] = { 0 };
+
+	rc = i2c_get_chip_for_busnum(bus, chip, 2, &i2cdev);
+	if (rc != 0) {
+		printf("WARN: cannot probe baseboard EEPROM!\n");
+		return -1;
+	}
+
+	rc = dm_i2c_read(i2cdev, 0, &u8buf, 1);
+	if (rc != 0) {
+		printf("WARN: cannot read baseboard EEPROM!\n");
+		return -1;
+	}
+
+	if (u8buf != 0xFF)
+		snprintf(defip, sizeof(defip),
+			 "if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.%d; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
+			 u8buf);
+	else
+		strncpy(defip,
+			"if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
+			sizeof(defip));
+
+	env_set("brdefaultip", defip);
+	env_set_hex("board_id", u8buf);
+
+	return 0;
+}
+
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_AM33XX)
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <power/tps65217.h>
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+void pmicsetup(u32 mpupll, unsigned int bus)
+{
+	int mpu_vdd;
+	int usb_cur_lim;
+
+	if (power_tps65217_init(bus)) {
+		printf("WARN: cannot setup PMIC 0x24 @ bus #%d, not found!.\n",
+		       bus);
+		return;
+	}
+
+	/* Get the frequency which is defined by device fuses */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
+
+	if (0 != mpupll) {
+		dpll_mpu_opp100.m = mpupll;
+		printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
+	} else {
+		puts("ok.\n");
+	}
+	/*
+	 * Increase USB current limit to 1300mA or 1800mA and set
+	 * the MPU voltage controller as needed.
+	 */
+	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+	} else {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+	}
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+			       usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set DCDC3 (CORE) voltage to 1.125V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set LDO3 to 1.8V */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS1,
+			       TPS65217_LDO_VOLTAGE_OUT_1_8,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+	/* Set LDO4 to 3.3V */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+	/* Set PWR_EN bit in Status Register */
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			   TPS65217_STATUS, TPS65217_PWR_OFF, TPS65217_PWR_OFF);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+#endif /* CONFIG_SPL_BUILD && CONFIG_AM33XX */
@@ -0,0 +1,15 @@
+if TARGET_EB_CPU5282
+
+config SYS_CPU
+	default "mcf52x2"
+
+config SYS_BOARD
+	default "eb_cpu5282"
+
+config SYS_VENDOR
+	default "BuS"
+
+config SYS_CONFIG_NAME
+	default "eb_cpu5282"
+
+endif
@@ -0,0 +1,7 @@
+EB_CPU5282 BOARD
+M:	Jens Scharsig <esw@bus-elektronik.de>
+S:	Maintained
+F:	board/BuS/eb_cpu5282/
+F:	include/configs/eb_cpu5282.h
+F:	configs/eb_cpu5282_defconfig
+F:	configs/eb_cpu5282_internal_defconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= eb_cpu5282.o
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2005-2009
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <command.h>
+#include "asm/m5282.h"
+#include <bmp_layout.h>
+#include <env.h>
+#include <status_led.h>
+#include <bus_vcxk.h>
+
+/*---------------------------------------------------------------------------*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_VIDEO
+unsigned long display_width;
+unsigned long display_height;
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+int checkboard (void)
+{
+	puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n");
+#if (CONFIG_SYS_TEXT_BASE ==  CONFIG_SYS_INT_FLASH_BASE)
+	puts("       Boot from Internal FLASH\n");
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	int size, i;
+
+	size = 0;
+	MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
+			MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
+	asm (" nop");
+#ifdef CONFIG_SYS_SDRAM_BASE0
+	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)|
+		MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
+		MCFSDRAMC_DACR_PS_32;
+	asm (" nop");
+
+	MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
+	asm (" nop");
+
+	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+	asm (" nop");
+	for (i = 0; i < 10; i++)
+		asm (" nop");
+
+	*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
+	asm (" nop");
+	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+	asm (" nop");
+
+	for (i = 0; i < 2000; i++)
+		asm (" nop");
+
+	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
+	asm (" nop");
+	/* write SDRAM mode register */
+	*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
+	asm (" nop");
+	size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024;
+#endif
+#ifdef CONFIG_SYS_SDRAM_BASE1xx
+	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
+			| MCFSDRAMC_DACR_CASL (1)
+			| MCFSDRAMC_DACR_CBM (3)
+			| MCFSDRAMC_DACR_PS_16;
+
+	MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
+
+	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
+
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
+	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
+
+	for (i = 0; i < 2000; i++)
+		asm (" nop");
+
+	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
+	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
+#endif
+	gd->ram_size = size;
+
+	return 0;
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG)
+
+void hw_watchdog_init(void)
+{
+	char *s;
+	int enable;
+
+	enable = 1;
+	s = env_get("watchdog");
+	if (s != NULL)
+		if ((strncmp(s, "off", 3) == 0) || (strncmp(s, "0", 1) == 0))
+			enable = 0;
+	if (enable)
+		MCFGPTA_GPTDDR  |= (1<<2);
+	else
+		MCFGPTA_GPTDDR  &= ~(1<<2);
+}
+
+void hw_watchdog_reset(void)
+{
+	MCFGPTA_GPTPORT  ^= (1<<2);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef	CONFIG_HW_WATCHDOG
+	hw_watchdog_init();
+#endif
+	return 1;
+}
+
+void __led_toggle(led_id_t mask)
+{
+	MCFGPTA_GPTPORT ^= (1 << 3);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+	MCFGPTA_GPTDDR  |= (1 << 3);
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	if (state == CONFIG_LED_STATUS_ON)
+		MCFGPTA_GPTPORT |= (1 << 3);
+	else
+		MCFGPTA_GPTPORT &= ~(1 << 3);
+}
+
+#if defined(CONFIG_VIDEO)
+
+int drv_video_init(void)
+{
+	char *s;
+#ifdef CONFIG_SPLASH_SCREEN
+	unsigned long splash;
+#endif
+	printf("Init Video as ");
+	s = env_get("displaywidth");
+	if (s != NULL)
+		display_width = simple_strtoul(s, NULL, 10);
+	else
+		display_width = 256;
+
+	s = env_get("displayheight");
+	if (s != NULL)
+		display_height = simple_strtoul(s, NULL, 10);
+	else
+		display_height = 256;
+
+	printf("%lu x %lu pixel matrix\n", display_width, display_height);
+
+	MCFCCM_CCR &= ~MCFCCM_CCR_SZEN;
+	MCFGPIO_PEPAR &= ~MCFGPIO_PEPAR_PEPA2;
+
+	vcxk_init(display_width, display_height);
+
+#ifdef CONFIG_SPLASH_SCREEN
+	s = env_get("splashimage");
+	if (s != NULL) {
+		splash = simple_strtoul(s, NULL, 16);
+		vcxk_acknowledge_wait();
+		video_display_bitmap(splash, 0, 0);
+	}
+#endif
+	return 0;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef CONFIG_VIDEO
+int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rcode = 0;
+	ulong side;
+	ulong bright;
+
+	switch (argc) {
+	case 3:
+		side = simple_strtoul(argv[1], NULL, 10);
+		bright = simple_strtoul(argv[2], NULL, 10);
+		if ((side >= 0) && (side <= 3) &&
+			(bright >= 0) && (bright <= 1000)) {
+			vcxk_setbrightness(side, bright);
+			rcode = 0;
+		} else {
+			printf("parameters out of range\n");
+			printf("Usage:\n%s\n", cmdtp->usage);
+			rcode = 1;
+		}
+		break;
+	default:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		rcode = 1;
+		break;
+	}
+	return rcode;
+}
+
+/*---------------------------------------------------------------------------*/
+
+U_BOOT_CMD(
+	bright,	3,	0,	do_brightness,
+	"sets the display brightness\n",
+	" <side> <0..1000>\n        side: 0/3=both; 1=first; 2=second\n"
+);
+
+#endif
+
+/* EOF EB+MCF-EV123.c */
@@ -0,0 +1,6 @@
+TURRIS OMNIA BOARD
+M:	Marek Behún <marek.behun@nic.cz>
+S:	Maintained
+F:	board/CZ.NIC/turris_mox/
+F:	include/configs/turris_mox.h
+F:	configs/turris_mox_defconfig
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+
+obj-y	:= turris_mox.o mox_sp.o
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define RWTM_CMD_PARAM(i)	(size_t)(0xd00b0000 + (i) * 4)
+#define RWTM_CMD		0xd00b0040
+#define RWTM_CMD_RETSTATUS	0xd00b0080
+#define RWTM_CMD_STATUS(i)	(size_t)(0xd00b0084 + (i) * 4)
+
+#define RWTM_HOST_INT_RESET	0xd00b00c8
+#define RWTM_HOST_INT_MASK	0xd00b00cc
+#define SP_CMD_COMPLETE		BIT(0)
+
+#define MBOX_STS_SUCCESS		(0x0 << 30)
+#define MBOX_STS_FAIL			(0x1 << 30)
+#define MBOX_STS_BADCMD			(0x2 << 30)
+#define MBOX_STS_LATER			(0x3 << 30)
+#define MBOX_STS_ERROR(s)		((s) & (3 << 30))
+#define MBOX_STS_VALUE(s)		(((s) >> 10) & 0xfffff)
+#define MBOX_STS_CMD(s)			((s) & 0x3ff)
+
+enum mbox_cmd {
+	MBOX_CMD_GET_RANDOM	= 1,
+	MBOX_CMD_BOARD_INFO,
+	MBOX_CMD_ECDSA_PUB_KEY,
+	MBOX_CMD_HASH,
+	MBOX_CMD_SIGN,
+	MBOX_CMD_VERIFY,
+
+	MBOX_CMD_OTP_READ,
+	MBOX_CMD_OTP_WRITE
+};
+
+static int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout)
+{
+	const int tries = 50;
+	int i;
+	u32 status;
+
+	clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE);
+
+	writel(cmd, RWTM_CMD);
+
+	for (i = 0; i < tries; ++i) {
+		mdelay(10);
+		if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE)
+			break;
+	}
+
+	if (i == tries) {
+		/* if timed out, don't read status */
+		setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
+		return -ETIMEDOUT;
+	}
+
+	for (i = 0; i < nout; ++i)
+		out[i] = readl(RWTM_CMD_STATUS(i));
+	status = readl(RWTM_CMD_RETSTATUS);
+
+	setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
+
+	if (MBOX_STS_CMD(status) != cmd)
+		return -EIO;
+	else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL)
+		return -(int)MBOX_STS_VALUE(status);
+	else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS)
+		return -EIO;
+	else
+		return MBOX_STS_VALUE(status);
+}
+
+const char *mox_sp_get_ecdsa_public_key(void)
+{
+	static char public_key[135];
+	u32 out[16];
+	int res;
+
+	if (public_key[0])
+		return public_key;
+
+	res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, out, 16);
+	if (res < 0)
+		return NULL;
+
+	sprintf(public_key,
+		"%06x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x",
+		(u32)res, out[0], out[1], out[2], out[3], out[4], out[5],
+		out[6], out[7], out[8], out[9], out[10], out[11], out[12],
+		out[13], out[14], out[15]);
+
+	return public_key;
+}
+
+static inline void res_to_mac(u8 *mac, u32 t1, u32 t2)
+{
+	mac[0] = t1 >> 8;
+	mac[1] = t1;
+	mac[2] = t2 >> 24;
+	mac[3] = t2 >> 16;
+	mac[4] = t2 >> 8;
+	mac[5] = t2;
+}
+
+int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram)
+{
+	u32 out[8];
+	int res;
+
+	res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, out, 8);
+	if (res < 0)
+		return res;
+
+	if (sn) {
+		*sn = out[1];
+		*sn <<= 32;
+		*sn |= out[0];
+	}
+
+	if (bv)
+		*bv = out[2];
+
+	if (ram)
+		*ram = out[3];
+
+	if (mac1)
+		res_to_mac(mac1, out[4], out[5]);
+
+	if (mac2)
+		res_to_mac(mac2, out[6], out[7]);
+
+	return 0;
+}
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ */
+
+#ifndef _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_
+#define _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_
+
+#include <common.h>
+
+const char *mox_sp_get_ecdsa_public_key(void);
+int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv,
+			   int *ram);
+
+#endif /* _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ */
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <clk.h>
+#include <env.h>
+#include <spi.h>
+#include <mvebu/comphy.h>
+#include <miiphy.h>
+#include <linux/string.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+#include "mox_sp.h"
+
+#define MAX_MOX_MODULES		10
+
+#define MOX_MODULE_SFP		0x1
+#define MOX_MODULE_PCI		0x2
+#define MOX_MODULE_TOPAZ	0x3
+#define MOX_MODULE_PERIDOT	0x4
+#define MOX_MODULE_USB3		0x5
+#define MOX_MODULE_PASSPCI	0x6
+
+#define ARMADA_37XX_NB_GPIO_SEL	0xd0013830
+#define ARMADA_37XX_SPI_CTRL	0xd0010600
+#define ARMADA_37XX_SPI_CFG	0xd0010604
+#define ARMADA_37XX_SPI_DOUT	0xd0010608
+#define ARMADA_37XX_SPI_DIN	0xd001060c
+
+#define PCIE_PATH	"/soc/pcie@d0070000"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_base = 0;
+	gd->ram_size = (phys_size_t)get_ram_size(0, 0x40000000);
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = (phys_addr_t)0;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+	u8 topology[MAX_MOX_MODULES];
+	int i, size, node;
+	bool enable;
+
+	/*
+	 * SPI driver is not loaded in driver model yet, but we have to find out
+	 * if pcie should be enabled in U-Boot's device tree. Therefore we have
+	 * to read SPI by reading/writing SPI registers directly
+	 */
+
+	writel(0x563fa, ARMADA_37XX_NB_GPIO_SEL);
+	writel(0x10df, ARMADA_37XX_SPI_CFG);
+	writel(0x2005b, ARMADA_37XX_SPI_CTRL);
+
+	while (!(readl(ARMADA_37XX_SPI_CTRL) & 0x2))
+		udelay(1);
+
+	for (i = 0; i < MAX_MOX_MODULES; ++i) {
+		writel(0x0, ARMADA_37XX_SPI_DOUT);
+
+		while (!(readl(ARMADA_37XX_SPI_CTRL) & 0x2))
+			udelay(1);
+
+		topology[i] = readl(ARMADA_37XX_SPI_DIN) & 0xff;
+		if (topology[i] == 0xff)
+			break;
+
+		topology[i] &= 0xf;
+	}
+
+	size = i;
+
+	writel(0x5b, ARMADA_37XX_SPI_CTRL);
+
+	if (size > 1 && (topology[1] == MOX_MODULE_PCI ||
+			 topology[1] == MOX_MODULE_USB3 ||
+			 topology[1] == MOX_MODULE_PASSPCI))
+		enable = true;
+	else
+		enable = false;
+
+	node = fdt_path_offset(blob, PCIE_PATH);
+
+	if (node < 0) {
+		printf("Cannot find PCIe node in U-Boot's device tree!\n");
+		return 0;
+	}
+
+	if (fdt_setprop_string(blob, node, "status",
+			       enable ? "okay" : "disabled") < 0) {
+		printf("Cannot %s PCIe in U-Boot's device tree!\n",
+		       enable ? "enable" : "disable");
+		return 0;
+	}
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+static int mox_do_spi(u8 *in, u8 *out, size_t size)
+{
+	struct spi_slave *slave;
+	struct udevice *dev;
+	int ret;
+
+	ret = spi_get_bus_and_cs(0, 1, 1000000, SPI_CPHA | SPI_CPOL,
+				 "spi_generic_drv", "moxtet@1", &dev,
+				 &slave);
+	if (ret)
+		goto fail;
+
+	ret = spi_claim_bus(slave);
+	if (ret)
+		goto fail_free;
+
+	ret = spi_xfer(slave, size * 8, out, in, SPI_XFER_ONCE);
+
+	spi_release_bus(slave);
+fail_free:
+	spi_free_slave(slave);
+fail:
+	return ret;
+}
+
+static int mox_get_topology(const u8 **ptopology, int *psize, int *pis_sd)
+{
+	static int is_sd;
+	static u8 topology[MAX_MOX_MODULES - 1];
+	static int size;
+	u8 din[MAX_MOX_MODULES], dout[MAX_MOX_MODULES];
+	int ret, i;
+
+	if (size) {
+		if (ptopology)
+			*ptopology = topology;
+		if (psize)
+			*psize = size;
+		if (pis_sd)
+			*pis_sd = is_sd;
+		return 0;
+	}
+
+	memset(din, 0, MAX_MOX_MODULES);
+	memset(dout, 0, MAX_MOX_MODULES);
+
+	ret = mox_do_spi(din, dout, MAX_MOX_MODULES);
+	if (ret)
+		return ret;
+
+	if (din[0] == 0x10)
+		is_sd = 1;
+	else if (din[0] == 0x00)
+		is_sd = 0;
+	else
+		return -ENODEV;
+
+	for (i = 1; i < MAX_MOX_MODULES && din[i] != 0xff; ++i)
+		topology[i - 1] = din[i] & 0xf;
+	size = i - 1;
+
+	if (ptopology)
+		*ptopology = topology;
+	if (psize)
+		*psize = size;
+	if (pis_sd)
+		*pis_sd = is_sd;
+
+	return 0;
+}
+
+int comphy_update_map(struct comphy_map *serdes_map, int count)
+{
+	int ret, i, size, sfpindex = -1, swindex = -1;
+	const u8 *topology;
+
+	ret = mox_get_topology(&topology, &size, NULL);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < size; ++i) {
+		if (topology[i] == MOX_MODULE_SFP && sfpindex == -1)
+			sfpindex = i;
+		else if ((topology[i] == MOX_MODULE_TOPAZ ||
+			  topology[i] == MOX_MODULE_PERIDOT) &&
+			 swindex == -1)
+			swindex = i;
+	}
+
+	if (sfpindex >= 0 && swindex >= 0) {
+		if (sfpindex < swindex)
+			serdes_map[0].speed = PHY_SPEED_1_25G;
+		else
+			serdes_map[0].speed = PHY_SPEED_3_125G;
+	} else if (sfpindex >= 0) {
+		serdes_map[0].speed = PHY_SPEED_1_25G;
+	} else if (swindex >= 0) {
+		serdes_map[0].speed = PHY_SPEED_3_125G;
+	}
+
+	return 0;
+}
+
+#define SW_SMI_CMD_R(d, r)	(0x9800 | (((d) & 0x1f) << 5) | ((r) & 0x1f))
+#define SW_SMI_CMD_W(d, r)	(0x9400 | (((d) & 0x1f) << 5) | ((r) & 0x1f))
+
+static int sw_multi_read(struct mii_dev *bus, int sw, int dev, int reg)
+{
+	bus->write(bus, sw, 0, 0, SW_SMI_CMD_R(dev, reg));
+	mdelay(5);
+	return bus->read(bus, sw, 0, 1);
+}
+
+static void sw_multi_write(struct mii_dev *bus, int sw, int dev, int reg,
+			   u16 val)
+{
+	bus->write(bus, sw, 0, 1, val);
+	bus->write(bus, sw, 0, 0, SW_SMI_CMD_W(dev, reg));
+	mdelay(5);
+}
+
+static int sw_scratch_read(struct mii_dev *bus, int sw, int reg)
+{
+	sw_multi_write(bus, sw, 0x1c, 0x1a, (reg & 0x7f) << 8);
+	return sw_multi_read(bus, sw, 0x1c, 0x1a) & 0xff;
+}
+
+static void sw_led_write(struct mii_dev *bus, int sw, int port, int reg,
+			 u16 val)
+{
+	sw_multi_write(bus, sw, port, 0x16, 0x8000 | ((reg & 7) << 12)
+					    | (val & 0x7ff));
+}
+
+static void sw_blink_leds(struct mii_dev *bus, int peridot, int topaz)
+{
+	int i, p;
+	struct {
+		int port;
+		u16 val;
+		int wait;
+	} regs[] = {
+		{ 2, 0xef, 1 }, { 2, 0xfe, 1 }, { 2, 0x33, 0 },
+		{ 4, 0xef, 1 }, { 4, 0xfe, 1 }, { 4, 0x33, 0 },
+		{ 3, 0xfe, 1 }, { 3, 0xef, 1 }, { 3, 0x33, 0 },
+		{ 1, 0xfe, 1 }, { 1, 0xef, 1 }, { 1, 0x33, 0 }
+	};
+
+	for (i = 0; i < 12; ++i) {
+		for (p = 0; p < peridot; ++p) {
+			sw_led_write(bus, 0x10 + p, regs[i].port, 0,
+				     regs[i].val);
+			sw_led_write(bus, 0x10 + p, regs[i].port + 4, 0,
+				     regs[i].val);
+		}
+		if (topaz) {
+			sw_led_write(bus, 0x2, 0x10 + regs[i].port, 0,
+				     regs[i].val);
+		}
+
+		if (regs[i].wait)
+			mdelay(75);
+	}
+}
+
+static void check_switch_address(struct mii_dev *bus, int addr)
+{
+	if (sw_scratch_read(bus, addr, 0x70) >> 3 != addr)
+		printf("Check of switch MDIO address failed for 0x%02x\n",
+		       addr);
+}
+
+static int sfp, pci, topaz, peridot, usb, passpci;
+static int sfp_pos, peridot_pos[3];
+static int module_count;
+
+static int configure_peridots(struct gpio_desc *reset_gpio)
+{
+	int i, ret;
+	u8 dout[MAX_MOX_MODULES];
+
+	memset(dout, 0, MAX_MOX_MODULES);
+
+	/* set addresses of Peridot modules */
+	for (i = 0; i < peridot; ++i)
+		dout[module_count - peridot_pos[i]] = (~i) & 3;
+
+	/*
+	 * if there is a SFP module connected to the last Peridot module, set
+	 * the P10_SMODE to 1 for the Peridot module
+	 */
+	if (sfp)
+		dout[module_count - peridot_pos[i - 1]] |= 1 << 3;
+
+	dm_gpio_set_value(reset_gpio, 1);
+	mdelay(10);
+
+	ret = mox_do_spi(NULL, dout, module_count + 1);
+
+	mdelay(10);
+	dm_gpio_set_value(reset_gpio, 0);
+
+	mdelay(50);
+
+	return ret;
+}
+
+static int get_reset_gpio(struct gpio_desc *reset_gpio)
+{
+	int node;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "cznic,moxtet");
+	if (node < 0) {
+		printf("Cannot find Moxtet bus device node!\n");
+		return -1;
+	}
+
+	gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpios", 0,
+				   reset_gpio, GPIOD_IS_OUT);
+
+	if (!dm_gpio_is_valid(reset_gpio)) {
+		printf("Cannot find reset GPIO for Moxtet bus!\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	int ret;
+	u8 mac1[6], mac2[6];
+
+	ret = mbox_sp_get_board_info(NULL, mac1, mac2, NULL, NULL);
+	if (ret < 0) {
+		printf("Cannot read data from OTP!\n");
+		return 0;
+	}
+
+	if (is_valid_ethaddr(mac1) && !env_get("ethaddr"))
+		eth_env_set_enetaddr("ethaddr", mac1);
+
+	if (is_valid_ethaddr(mac2) && !env_get("eth1addr"))
+		eth_env_set_enetaddr("eth1addr", mac2);
+
+	return 0;
+}
+
+static void mox_print_info(void)
+{
+	int ret, board_version, ram_size;
+	u64 serial_number;
+	const char *pub_key;
+
+	ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version,
+				     &ram_size);
+	if (ret < 0)
+		return;
+
+	printf("Turris Mox:\n");
+	printf("  Board version: %i\n", board_version);
+	printf("  RAM size: %i MiB\n", ram_size);
+	printf("  Serial Number: %016llX\n", serial_number);
+
+	pub_key = mox_sp_get_ecdsa_public_key();
+	if (pub_key)
+		printf("  ECDSA Public Key: %s\n", pub_key);
+	else
+		printf("Cannot read ECDSA Public Key\n");
+}
+
+int last_stage_init(void)
+{
+	int ret, i;
+	const u8 *topology;
+	int is_sd;
+	struct mii_dev *bus;
+	struct gpio_desc reset_gpio = {};
+
+	mox_print_info();
+
+	ret = mox_get_topology(&topology, &module_count, &is_sd);
+	if (ret) {
+		printf("Cannot read module topology!\n");
+		return 0;
+	}
+
+	printf("  SD/eMMC version: %s\n", is_sd ? "SD" : "eMMC");
+
+	if (module_count)
+		printf("Module Topology:\n");
+
+	for (i = 0; i < module_count; ++i) {
+		switch (topology[i]) {
+		case MOX_MODULE_SFP:
+			printf("% 4i: SFP Module\n", i + 1);
+			break;
+		case MOX_MODULE_PCI:
+			printf("% 4i: Mini-PCIe Module\n", i + 1);
+			break;
+		case MOX_MODULE_TOPAZ:
+			printf("% 4i: Topaz Switch Module (4-port)\n", i + 1);
+			break;
+		case MOX_MODULE_PERIDOT:
+			printf("% 4i: Peridot Switch Module (8-port)\n", i + 1);
+			break;
+		case MOX_MODULE_USB3:
+			printf("% 4i: USB 3.0 Module (4 ports)\n", i + 1);
+			break;
+		case MOX_MODULE_PASSPCI:
+			printf("% 4i: Passthrough Mini-PCIe Module\n", i + 1);
+			break;
+		default:
+			printf("% 4i: unknown (ID %i)\n", i + 1, topology[i]);
+		}
+	}
+
+	/* now check if modules are connected in supported mode */
+
+	for (i = 0; i < module_count; ++i) {
+		switch (topology[i]) {
+		case MOX_MODULE_SFP:
+			if (sfp) {
+				printf("Error: Only one SFP module is supported!\n");
+			} else if (topaz) {
+				printf("Error: SFP module cannot be connected after Topaz Switch module!\n");
+			} else {
+				sfp_pos = i;
+				++sfp;
+			}
+			break;
+		case MOX_MODULE_PCI:
+			if (pci) {
+				printf("Error: Only one Mini-PCIe module is supported!\n");
+			} else if (usb) {
+				printf("Error: Mini-PCIe module cannot come after USB 3.0 module!\n");
+			} else if (i && (i != 1 || !passpci)) {
+				printf("Error: Mini-PCIe module should be the first connected module or come right after Passthrough Mini-PCIe module!\n");
+			} else {
+				++pci;
+			}
+			break;
+		case MOX_MODULE_TOPAZ:
+			if (topaz) {
+				printf("Error: Only one Topaz module is supported!\n");
+			} else if (peridot >= 3) {
+				printf("Error: At most two Peridot modules can come before Topaz module!\n");
+			} else {
+				++topaz;
+			}
+			break;
+		case MOX_MODULE_PERIDOT:
+			if (sfp || topaz) {
+				printf("Error: Peridot module must come before SFP or Topaz module!\n");
+			} else if (peridot >= 3) {
+				printf("Error: At most three Peridot modules are supported!\n");
+			} else {
+				peridot_pos[peridot] = i;
+				++peridot;
+			}
+			break;
+		case MOX_MODULE_USB3:
+			if (pci) {
+				printf("Error: USB 3.0 module cannot come after Mini-PCIe module!\n");
+			} else if (usb) {
+				printf("Error: Only one USB 3.0 module is supported!\n");
+			} else if (i && (i != 1 || !passpci)) {
+				printf("Error: USB 3.0 module should be the first connected module or come right after Passthrough Mini-PCIe module!\n");
+			} else {
+				++usb;
+			}
+			break;
+		case MOX_MODULE_PASSPCI:
+			if (passpci) {
+				printf("Error: Only one Passthrough Mini-PCIe module is supported!\n");
+			} else if (i != 0) {
+				printf("Error: Passthrough Mini-PCIe module should be the first connected module!\n");
+			} else {
+				++passpci;
+			}
+		}
+	}
+
+	/* now configure modules */
+
+	if (get_reset_gpio(&reset_gpio) < 0)
+		return 0;
+
+	if (peridot > 0) {
+		if (configure_peridots(&reset_gpio) < 0) {
+			printf("Cannot configure Peridot modules!\n");
+			peridot = 0;
+		}
+	} else {
+		dm_gpio_set_value(&reset_gpio, 1);
+		mdelay(50);
+		dm_gpio_set_value(&reset_gpio, 0);
+		mdelay(50);
+	}
+
+	if (peridot || topaz) {
+		/*
+		 * now check if the addresses are set by reading Scratch & Misc
+		 * register 0x70 of Peridot (and potentially Topaz) modules
+		 */
+
+		bus = miiphy_get_dev_by_name("neta@30000");
+		if (!bus) {
+			printf("Cannot get MDIO bus device!\n");
+		} else {
+			for (i = 0; i < peridot; ++i)
+				check_switch_address(bus, 0x10 + i);
+
+			if (topaz)
+				check_switch_address(bus, 0x2);
+
+			sw_blink_leds(bus, peridot, topaz);
+		}
+	}
+
+	printf("\n");
+
+	return 0;
+}
@@ -0,0 +1,6 @@
+TURRIS OMNIA BOARD
+M:	Marek Behún <marek.behun@nic.cz>
+S:	Maintained
+F:	board/CZ.NIC/turris_omnia/
+F:	include/configs/turris_omnia.h
+F:	configs/turris_omnia_defconfig
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+
+obj-y	:= turris_omnia.o
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+ * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
+ *
+ * Derived from the code for
+ *   Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <dm/uclass.h>
+#include <fdt_support.h>
+#include <time.h>
+#include <u-boot/crc.h>
+# include <atsha204a-i2c.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OMNIA_I2C_BUS_NAME		"i2c@11000->i2cmux@70->i2c@0"
+
+#define OMNIA_I2C_MCU_CHIP_ADDR		0x2a
+#define OMNIA_I2C_MCU_CHIP_LEN		1
+
+#define OMNIA_I2C_EEPROM_CHIP_ADDR	0x54
+#define OMNIA_I2C_EEPROM_CHIP_LEN	2
+#define OMNIA_I2C_EEPROM_MAGIC		0x0341a034
+
+enum mcu_commands {
+	CMD_GET_STATUS_WORD	= 0x01,
+	CMD_GET_RESET		= 0x09,
+	CMD_WATCHDOG_STATE	= 0x0b,
+};
+
+enum status_word_bits {
+	CARD_DET_STSBIT		= 0x0010,
+	MSATA_IND_STSBIT	= 0x0020,
+};
+
+#define OMNIA_ATSHA204_OTP_VERSION	0
+#define OMNIA_ATSHA204_OTP_SERIAL	1
+#define OMNIA_ATSHA204_OTP_MAC0		3
+#define OMNIA_ATSHA204_OTP_MAC1		4
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T3.0"
+ */
+#define OMNIA_GPP_OUT_ENA_LOW					\
+	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
+	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
+	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define OMNIA_GPP_OUT_ENA_MID					\
+	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
+	   BIT(16) | BIT(17) | BIT(18)))
+
+#define OMNIA_GPP_OUT_VAL_LOW	0x0
+#define OMNIA_GPP_OUT_VAL_MID	0x0
+#define OMNIA_GPP_POL_LOW	0x0
+#define OMNIA_GPP_POL_MID	0x0
+
+static struct serdes_map board_serdes_map_pex[] = {
+	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+static struct serdes_map board_serdes_map_sata[] = {
+	{SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
+					  uint offset_len)
+{
+	struct udevice *bus, *dev;
+	int ret;
+
+	ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
+	if (ret) {
+		printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
+		       OMNIA_I2C_BUS_NAME, ret);
+		return NULL;
+	}
+
+	ret = i2c_get_chip(bus, addr, offset_len, &dev);
+	if (ret) {
+		printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
+		       name, ret);
+		return NULL;
+	}
+
+	return dev;
+}
+
+static int omnia_mcu_read(u8 cmd, void *buf, int len)
+{
+	struct udevice *chip;
+
+	chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
+				  OMNIA_I2C_MCU_CHIP_LEN);
+	if (!chip)
+		return -ENODEV;
+
+	return dm_i2c_read(chip, cmd, buf, len);
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int omnia_mcu_write(u8 cmd, const void *buf, int len)
+{
+	struct udevice *chip;
+
+	chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
+				  OMNIA_I2C_MCU_CHIP_LEN);
+	if (!chip)
+		return -ENODEV;
+
+	return dm_i2c_write(chip, cmd, buf, len);
+}
+
+static bool disable_mcu_watchdog(void)
+{
+	int ret;
+
+	puts("Disabling MCU watchdog... ");
+
+	ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
+	if (ret) {
+		printf("omnia_mcu_write failed: %i\n", ret);
+		return false;
+	}
+
+	puts("disabled\n");
+
+	return true;
+}
+#endif
+
+static bool omnia_detect_sata(void)
+{
+	int ret;
+	u16 stsword;
+
+	puts("MiniPCIe/mSATA card detection... ");
+
+	ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
+	if (ret) {
+		printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
+		       ret);
+		return false;
+	}
+
+	if (!(stsword & CARD_DET_STSBIT)) {
+		puts("none\n");
+		return false;
+	}
+
+	if (stsword & MSATA_IND_STSBIT)
+		puts("mSATA\n");
+	else
+		puts("MiniPCIe\n");
+
+	return stsword & MSATA_IND_STSBIT ? true : false;
+}
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	if (omnia_detect_sata()) {
+		*serdes_map_array = board_serdes_map_sata;
+		*count = ARRAY_SIZE(board_serdes_map_sata);
+	} else {
+		*serdes_map_array = board_serdes_map_pex;
+		*count = ARRAY_SIZE(board_serdes_map_pex);
+	}
+
+	return 0;
+}
+
+struct omnia_eeprom {
+	u32 magic;
+	u32 ramsize;
+	char region[4];
+	u32 crc;
+};
+
+static bool omnia_read_eeprom(struct omnia_eeprom *oep)
+{
+	struct udevice *chip;
+	u32 crc;
+	int ret;
+
+	chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
+				  OMNIA_I2C_EEPROM_CHIP_LEN);
+
+	if (!chip)
+		return false;
+
+	ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
+	if (ret) {
+		printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
+		return false;
+	}
+
+	if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
+		printf("bad EEPROM magic number (%08x, should be %08x)\n",
+		       oep->magic, OMNIA_I2C_EEPROM_MAGIC);
+		return false;
+	}
+
+	crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
+	if (crc != oep->crc) {
+		printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
+		       oep->crc, crc);
+		return false;
+	}
+
+	return true;
+}
+
+static int omnia_get_ram_size_gb(void)
+{
+	static int ram_size;
+	struct omnia_eeprom oep;
+
+	if (!ram_size) {
+		/* Get the board config from EEPROM */
+		if (omnia_read_eeprom(&oep)) {
+			debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
+
+			if (oep.ramsize == 0x2)
+				ram_size = 2;
+			else
+				ram_size = 1;
+		} else {
+			/* Hardcoded fallback */
+			puts("Memory config from EEPROM read failed!\n");
+			puts("Falling back to default 1 GiB!\n");
+			ram_size = 1;
+		}
+	}
+
+	return ram_size;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map_1g = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_4GBIT,			/* mem_size */
+	    MV_DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_NORMAL,		/* temperature */
+	    MV_DDR_TIM_2T} },		/* timing */
+	BUS_MASK_32BIT,			/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+static struct mv_ddr_topology_map board_topology_map_2g = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_8GBIT,			/* mem_size */
+	    MV_DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_NORMAL,		/* temperature */
+	    MV_DDR_TIM_2T} },		/* timing */
+	BUS_MASK_32BIT,			/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	if (omnia_get_ram_size_gb() == 2)
+		return &board_topology_map_2g;
+	else
+		return &board_topology_map_1g;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int set_regdomain(void)
+{
+	struct omnia_eeprom oep;
+	char rd[3] = {' ', ' ', 0};
+
+	if (omnia_read_eeprom(&oep))
+		memcpy(rd, &oep.region, 2);
+	else
+		puts("EEPROM regdomain read failed.\n");
+
+	printf("Regdomain set to %s\n", rd);
+	return env_set("regdomain", rd);
+}
+
+/*
+ * default factory reset bootcommand on Omnia first sets all the front LEDs
+ * to green and then tries to load the rescue image from SPI flash memory and
+ * boot it
+ */
+#define OMNIA_FACTORY_RESET_BOOTCMD \
+	"i2c dev 2; " \
+	"i2c mw 0x2a.1 0x3 0x1c 1; " \
+	"i2c mw 0x2a.1 0x4 0x1c 1; " \
+	"mw.l 0x01000000 0x00ff000c; " \
+	"i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
+	"setenv bootargs \"earlyprintk console=ttyS0,115200" \
+			" omniarescue=$omnia_reset\"; " \
+	"sf probe; " \
+	"sf read 0x1000000 0x100000 0x700000; " \
+	"bootm 0x1000000; " \
+	"bootz 0x1000000"
+
+static void handle_reset_button(void)
+{
+	int ret;
+	u8 reset_status;
+
+	ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
+	if (ret) {
+		printf("omnia_mcu_read failed: %i, reset status unknown!\n",
+		       ret);
+		return;
+	}
+
+	env_set_ulong("omnia_reset", reset_status);
+
+	if (reset_status) {
+		printf("RESET button was pressed, overwriting bootcmd!\n");
+		env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
+	}
+}
+#endif
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
+	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
+	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
+	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
+	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+#ifndef CONFIG_SPL_BUILD
+	disable_mcu_watchdog();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifndef CONFIG_SPL_BUILD
+	set_regdomain();
+	handle_reset_button();
+#endif
+	pci_init();
+
+	return 0;
+}
+
+static struct udevice *get_atsha204a_dev(void)
+{
+	static struct udevice *dev;
+
+	if (dev)
+		return dev;
+
+	if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
+		puts("Cannot find ATSHA204A on I2C bus!\n");
+		dev = NULL;
+	}
+
+	return dev;
+}
+
+int checkboard(void)
+{
+	u32 version_num, serial_num;
+	int err = 1;
+
+	struct udevice *dev = get_atsha204a_dev();
+
+	if (dev) {
+		err = atsha204a_wakeup(dev);
+		if (err)
+			goto out;
+
+		err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+				     OMNIA_ATSHA204_OTP_VERSION,
+				     (u8 *)&version_num);
+		if (err)
+			goto out;
+
+		err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+				     OMNIA_ATSHA204_OTP_SERIAL,
+				     (u8 *)&serial_num);
+		if (err)
+			goto out;
+
+		atsha204a_sleep(dev);
+	}
+
+out:
+	printf("Turris Omnia:\n");
+	printf("  RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
+	if (err)
+		printf("  Serial Number: unknown\n");
+	else
+		printf("  Serial Number: %08X%08X\n", be32_to_cpu(version_num),
+		       be32_to_cpu(serial_num));
+
+	return 0;
+}
+
+static void increment_mac(u8 *mac)
+{
+	int i;
+
+	for (i = 5; i >= 3; i--) {
+		mac[i] += 1;
+		if (mac[i])
+			break;
+	}
+}
+
+int misc_init_r(void)
+{
+	int err;
+	struct udevice *dev = get_atsha204a_dev();
+	u8 mac0[4], mac1[4], mac[6];
+
+	if (!dev)
+		goto out;
+
+	err = atsha204a_wakeup(dev);
+	if (err)
+		goto out;
+
+	err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     OMNIA_ATSHA204_OTP_MAC0, mac0);
+	if (err)
+		goto out;
+
+	err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     OMNIA_ATSHA204_OTP_MAC1, mac1);
+	if (err)
+		goto out;
+
+	atsha204a_sleep(dev);
+
+	mac[0] = mac0[1];
+	mac[1] = mac0[2];
+	mac[2] = mac0[3];
+	mac[3] = mac1[1];
+	mac[4] = mac1[2];
+	mac[5] = mac1[3];
+
+	if (is_valid_ethaddr(mac))
+		eth_env_set_enetaddr("eth1addr", mac);
+
+	increment_mac(mac);
+
+	if (is_valid_ethaddr(mac))
+		eth_env_set_enetaddr("eth2addr", mac);
+
+	increment_mac(mac);
+
+	if (is_valid_ethaddr(mac))
+		eth_env_set_enetaddr("ethaddr", mac);
+
+out:
+	return 0;
+}
+
@@ -0,0 +1,15 @@
+if TARGET_FLEA3
+
+config SYS_BOARD
+	default "flea3"
+
+config SYS_VENDOR
+	default "CarMediaLab"
+
+config SYS_SOC
+	default "mx35"
+
+config SYS_CONFIG_NAME
+	default "flea3"
+
+endif
@@ -0,0 +1,6 @@
+FLEA3 BOARD
+M:	Stefano Babic <sbabic@denx.de>
+S:	Maintained
+F:	board/CarMediaLab/flea3/
+F:	include/configs/flea3.h
+F:	configs/flea3_defconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+
+obj-y	:= flea3.o
+obj-y	+= lowlevel_init.o
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <env.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux-mx35.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG		0x003F4208
+
+#define ESDCTL_DDR2_CONFIG	0x007FFC3F
+
+static inline void dram_wait(unsigned int count)
+{
+	volatile unsigned int wait = count;
+
+	while (wait--)
+		;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+		PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+static void board_setup_sdram(void)
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+	/* Initialize with default values both CSD0/1 */
+	writel(0x2000, &esdc->esdctl0);
+	writel(0x2000, &esdc->esdctl1);
+
+
+	mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+			     13, 10, 2, 0x8080);
+}
+
+static void setup_iomux_uart3(void)
+{
+	static const iomux_v3_cfg_t uart3_pads[] = {
+		MX35_PAD_RTS2__UART3_RXD_MUX,
+		MX35_PAD_CTS2__UART3_TXD_MUX,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c_pads[] = {
+		NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
+
+		NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+
+static void setup_iomux_spi(void)
+{
+	static const iomux_v3_cfg_t spi_pads[] = {
+		MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+		MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+		MX35_PAD_CSPI1_SS0__CSPI1_SS0,
+		MX35_PAD_CSPI1_SS1__CSPI1_SS1,
+		MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+}
+
+static void setup_iomux_fec(void)
+{
+	static const iomux_v3_cfg_t fec_pads[] = {
+		MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+		MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+		MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+		MX35_PAD_FEC_COL__FEC_COL,
+		MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+		MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+		MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+		MX35_PAD_FEC_MDC__FEC_MDC,
+		MX35_PAD_FEC_MDIO__FEC_MDIO,
+		MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+		MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+		MX35_PAD_FEC_CRS__FEC_CRS,
+		MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+		MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+		MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+		MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+		MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+		MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+		/* GPIO used to power off ethernet */
+		MX35_PAD_STXFS4__GPIO2_31,
+	};
+
+	/* setup pins for FEC */
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+int board_early_init_f(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	/* setup GPIO3_1 to set HighVCore signal */
+	imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
+	gpio_direction_output(65, 1);
+
+	/* initialize PLL and clock configuration */
+	writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+	writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+	writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+	/* Set the core to run at 532 Mhz */
+	writel(0x00001000, &ccm->pdr0);
+
+	/* Set-up RAM */
+	board_setup_sdram();
+
+	/* enable clocks */
+	writel(readl(&ccm->cgr0) |
+		MXC_CCM_CGR0_EMI_MASK |
+		MXC_CCM_CGR0_EDIO_MASK |
+		MXC_CCM_CGR0_EPIT1_MASK,
+		&ccm->cgr0);
+
+	writel(readl(&ccm->cgr1) |
+		MXC_CCM_CGR1_FEC_MASK |
+		MXC_CCM_CGR1_GPIO1_MASK |
+		MXC_CCM_CGR1_GPIO2_MASK |
+		MXC_CCM_CGR1_GPIO3_MASK |
+		MXC_CCM_CGR1_I2C1_MASK |
+		MXC_CCM_CGR1_I2C2_MASK |
+		MXC_CCM_CGR1_I2C3_MASK,
+		&ccm->cgr1);
+
+	/* Set-up NAND */
+	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+	/* Set pinmux for the required peripherals */
+	setup_iomux_uart3();
+	setup_iomux_i2c();
+	setup_iomux_fec();
+	setup_iomux_spi();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	/* Enable power for ethernet */
+	gpio_direction_output(63, 0);
+
+	udelay(2000);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	int rev = 0;
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	static const struct node_info nodes[] = {
+		{ "physmap-flash.0", MTD_DEV_TYPE_NOR, },  /* NOR flash */
+		{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+	};
+
+	if (env_get("fdt_noauto")) {
+		puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
+		return 0;
+	}
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+	return 0;
+}
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ */
+
+#include <config.h>
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	core_init
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	mov pc, lr
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+
+#define MII_MARVELL_PHY_PAGE		22
+
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+void mv_phy_88e1116_init(const char *name, u16 phyaddr)
+{
+	u16 reg;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+	miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+	if (miiphy_reset(name, phyaddr) == 0)
+		printf("88E1116 Initialized on %s\n", name);
+}
+
+void mv_phy_88e1318_init(const char *name, u16 phyaddr)
+{
+	u16 reg;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/*
+	 * Set control mode 4 for LED[0].
+	 */
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
+	miiphy_read(name, phyaddr, 16, &reg);
+	reg |= 0xf;
+	miiphy_write(name, phyaddr, 16, reg);
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+	miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
+	miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+	if (miiphy_reset(name, phyaddr) == 0)
+		printf("88E1318 Initialized on %s\n", name);
+}
+#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+int lacie_read_mac_address(uchar *mac_addr)
+{
+	int ret;
+	ushort version;
+
+	/* I2C-0 for on-board EEPROM */
+	i2c_set_bus_num(0);
+
+	/* Check layout version for EEPROM data */
+	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+			CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+			(uchar *) &version, 2);
+	if (ret != 0) {
+		printf("Error: failed to read I2C EEPROM @%02x\n",
+			CONFIG_SYS_I2C_EEPROM_ADDR);
+		return ret;
+	}
+	version = be16_to_cpu(version);
+	if (version < 1 || version > 3) {
+		printf("Error: unknown version %d for EEPROM data\n",
+			version);
+		return -1;
+	}
+
+	/* Read Ethernet MAC address from EEPROM */
+	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
+			CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
+	if (ret != 0)
+		printf("Error: failed to read I2C EEPROM @%02x\n",
+			CONFIG_SYS_I2C_EEPROM_ADDR);
+	return ret;
+}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ */
+
+#ifndef _LACIE_COMMON_H
+#define _LACIE_COMMON_H
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+void mv_phy_88e1116_init(const char *name, u16 phyaddr);
+void mv_phy_88e1318_init(const char *name, u16 phyaddr);
+#endif
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+int lacie_read_mac_address(uchar *mac);
+#endif
+
+#endif /* _LACIE_COMMON_H */
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * cpld-gpio-bus.c: provides support for the CPLD GPIO bus found on some LaCie
+ * boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO
+ * bus exposes two registers (address and data). Each of this register is made
+ * up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that
+ * the registers have been updated.
+ *
+ * Mostly this bus is used to configure the LEDs on LaCie boards.
+ *
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ */
+
+#include <asm/arch/gpio.h>
+#include "cpld-gpio-bus.h"
+
+static void cpld_gpio_bus_set_addr(struct cpld_gpio_bus *bus, unsigned addr)
+{
+	int pin;
+
+	for (pin = 0; pin < bus->num_addr; pin++)
+		kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1);
+}
+
+static void cpld_gpio_bus_set_data(struct cpld_gpio_bus *bus, unsigned data)
+{
+	int pin;
+
+	for (pin = 0; pin < bus->num_data; pin++)
+		kw_gpio_set_value(bus->data[pin], (data >> pin) & 1);
+}
+
+static void cpld_gpio_bus_enable_select(struct cpld_gpio_bus *bus)
+{
+	/* The transfer is enabled on the raising edge. */
+	kw_gpio_set_value(bus->enable, 0);
+	kw_gpio_set_value(bus->enable, 1);
+}
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *bus,
+			 unsigned addr, unsigned value)
+{
+	cpld_gpio_bus_set_addr(bus, addr);
+	cpld_gpio_bus_set_data(bus, value);
+	cpld_gpio_bus_enable_select(bus);
+}
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ */
+
+#ifndef _LACIE_CPLD_GPI0_BUS_H
+#define _LACIE_CPLD_GPI0_BUS_H
+
+struct cpld_gpio_bus {
+	unsigned *addr;
+	unsigned num_addr;
+	unsigned *data;
+	unsigned num_data;
+	unsigned enable;
+};
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus,
+			 unsigned addr, unsigned value);
+
+#endif /* _LACIE_CPLD_GPI0_BUS_H */
@@ -0,0 +1,12 @@
+if TARGET_EDMINIV2
+
+config SYS_BOARD
+	default "edminiv2"
+
+config SYS_VENDOR
+	default "LaCie"
+
+config SYS_CONFIG_NAME
+	default "edminiv2"
+
+endif
@@ -0,0 +1,6 @@
+EDMINIV2 BOARD
+M:	Albert ARIBAUD <albert.u.boot@aribaud.net>
+S:	Maintained
+F:	board/LaCie/edminiv2/
+F:	include/configs/edminiv2.h
+F:	configs/edminiv2_defconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= edminiv2.o ../common/common.o
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+#include "../common/common.h"
+#include <spl.h>
+#include <ns16550.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of board */
+	gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
+
+	/* boot parameter start at 256th byte of RAM base */
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	mv_phy_88e1116_init("egiga0", 8);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+/*
+ * SPL serial setup and NOR boot device selection
+ */
+
+#ifdef CONFIG_SPL_BUILD
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NOR;
+}
+
+#endif /* CONFIG_SPL_BUILD */
@@ -0,0 +1,12 @@
+if TARGET_NET2BIG_V2
+
+config SYS_BOARD
+	default "net2big_v2"
+
+config SYS_VENDOR
+	default "LaCie"
+
+config SYS_CONFIG_NAME
+	default "lacie_kw"
+
+endif
@@ -0,0 +1,7 @@
+NET2BIG_V2 BOARD
+M:	Simon Guinot <simon.guinot@sequanux.org>
+S:	Maintained
+F:	board/LaCie/net2big_v2/
+F:	include/configs/lacie_kw.h
+F:	configs/d2net_v2_defconfig
+F:	configs/net2big_v2_defconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= net2big_v2.o ../common/common.o
+ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
+obj-y	+= ../common/cpld-gpio-bus.o
+endif
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000C30	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x38743000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A32	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000CCCC	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000662	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000044	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00096630	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00009663	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "net2big_v2.h"
+#include "../common/common.h"
+#include "../common/cpld-gpio-bus.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* GPIO configuration */
+	mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
+			  NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,		/* Request power-off */
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP13_GPIO,		/* Rear power switch (on|auto) */
+		MPP14_GPIO,		/* USB fuse alarm */
+		MPP15_GPIO,		/* Rear power switch (auto|off) */
+		MPP16_GPIO,		/* SATA HDD1 power */
+		MPP17_GPIO,		/* SATA HDD2 power */
+		MPP20_SATA1_ACTn,
+		MPP21_SATA0_ACTn,
+		MPP24_GPIO,		/* USB mode select */
+		MPP26_GPIO,		/* USB device vbus */
+		MPP28_GPIO,		/* USB enable host vbus */
+		MPP29_GPIO,		/* CPLD GPIO bus ALE */
+		MPP34_GPIO,		/* Rear Push button 0=on 1=off */
+		MPP35_GPIO,		/* Inhibit switch power-off */
+		MPP36_GPIO,		/* SATA HDD1 presence */
+		MPP37_GPIO,		/* SATA HDD2 presence */
+		MPP40_GPIO,		/* eSATA presence */
+		MPP44_GPIO,		/* CPLD GPIO bus (data 0) */
+		MPP45_GPIO,		/* CPLD GPIO bus (data 1) */
+		MPP46_GPIO,		/* CPLD GPIO bus (data 2) */
+		MPP47_GPIO,		/* CPLD GPIO bus (addr 0) */
+		MPP48_GPIO,		/* CPLD GPIO bus (addr 1) */
+		MPP49_GPIO,		/* CPLD GPIO bus (addr 2) */
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Machine number */
+	gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
+
+	/* Boot parameters address */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
+/*
+ * Start I2C fan (GMT G762 controller)
+ */
+static void init_fan(void)
+{
+	u8 data;
+
+	i2c_set_bus_num(0);
+
+	/* Enable open-loop and PWM modes */
+	data = 0x20;
+	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+		      G762_REG_FAN_CMD1, 1, &data, 1) != 0)
+		goto err;
+	data = 0;
+	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+		      G762_REG_SET_CNT, 1, &data, 1) != 0)
+		goto err;
+	/*
+	 * RPM to PWM (set_out register) fan speed conversion array:
+	 * 0    0x00
+	 * 1500	0x04
+	 * 2800	0x08
+	 * 3400	0x0C
+	 * 3700	0x10
+	 * 4400	0x20
+	 * 4700	0x30
+	 * 4800	0x50
+	 * 5200	0x80
+	 * 5400	0xC0
+	 * 5500	0xFF
+	 *
+	 * Start fan at low speed (2800 RPM):
+	 */
+	data = 0x08;
+	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+		      G762_REG_SET_OUT, 1, &data, 1) != 0)
+		goto err;
+
+	return;
+err:
+	printf("Error: failed to start I2C fan @%02x\n",
+	       CONFIG_SYS_I2C_G762_ADDR);
+}
+#else
+static void init_fan(void) {}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
+
+#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
+/*
+ * CPLD GPIO bus:
+ *
+ * - address register : bit [0-2] -> GPIO [47-49]
+ * - data register    : bit [0-2] -> GPIO [44-46]
+ * - enable register  : GPIO 29
+ */
+static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
+static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
+
+static struct cpld_gpio_bus cpld_gpio_bus = {
+	.addr		= cpld_gpio_bus_addr,
+	.num_addr	= ARRAY_SIZE(cpld_gpio_bus_addr),
+	.data		= cpld_gpio_bus_data,
+	.num_data	= ARRAY_SIZE(cpld_gpio_bus_data),
+	.enable		= 29,
+};
+
+/*
+ * LEDs configuration:
+ *
+ * The LEDs are controlled by a CPLD and can be configured through
+ * the CPLD GPIO bus.
+ *
+ * Address register selection:
+ *
+ * addr | register
+ * ----------------------------
+ *   0  | front LED
+ *   1  | front LED brightness
+ *   2  | SATA LED brightness
+ *   3  | SATA0 LED
+ *   4  | SATA1 LED
+ *   5  | SATA2 LED
+ *   6  | SATA3 LED
+ *   7  | SATA4 LED
+ *
+ * Data register configuration:
+ *
+ * data | LED brightness
+ * -------------------------------------------------
+ *   0  | min (off)
+ *   -  | -
+ *   7  | max
+ *
+ * data | front LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | fix blue on
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *
+ * data | SATA LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | SATA activity blink
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | fix blue on
+ */
+static void init_leds(void)
+{
+	/* Enable the front blue LED */
+	cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
+	cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
+
+	/* Configure SATA LEDs to blink in relation with the SATA activity */
+	cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
+	cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
+	cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
+}
+#else
+static void init_leds(void) {}
+#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
+
+int misc_init_r(void)
+{
+	init_fan();
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+	if (!env_get("ethaddr")) {
+		uchar mac[6];
+		if (lacie_read_mac_address(mac) == 0)
+			eth_env_set_enetaddr("ethaddr", mac);
+	}
+#endif
+	init_leds();
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+	mv_phy_88e1116_init("egiga0", 8);
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO)
+/* Return GPIO push button status */
+static int
+do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
+}
+
+U_BOOT_CMD(button, 1, 1, do_read_push_button,
+	   "Return GPIO push button status 0=off 1=on", "");
+#endif
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef NET2BIG_V2_H
+#define NET2BIG_V2_H
+
+/* GPIO configuration */
+#define NET2BIG_V2_OE_LOW		0x0600E000
+#define NET2BIG_V2_OE_HIGH		0x00000134
+#define NET2BIG_V2_OE_VAL_LOW		0x10030000
+#define NET2BIG_V2_OE_VAL_HIGH		0x00000000
+
+/* Buttons */
+#define NET2BIG_V2_GPIO_PUSH_BUTTON	34
+
+/* GMT G762 registers (I2C fan controller) */
+#define G762_REG_SET_CNT		0x00
+#define G762_REG_SET_OUT		0x03
+#define G762_REG_FAN_CMD1		0x04
+
+#endif /* NET2BIG_V2_H */
@@ -0,0 +1,12 @@
+if TARGET_NETSPACE_V2
+
+config SYS_BOARD
+	default "netspace_v2"
+
+config SYS_VENDOR
+	default "LaCie"
+
+config SYS_CONFIG_NAME
+	default "lacie_kw"
+
+endif
@@ -0,0 +1,14 @@
+NETSPACE_V2 BOARD
+M:	Simon Guinot <simon.guinot@sequanux.org>
+S:	Maintained
+F:	board/LaCie/netspace_v2/
+F:	include/configs/lacie_kw.h
+F:	configs/inetspace_v2_defconfig
+F:	configs/netspace_max_v2_defconfig
+F:	configs/netspace_v2_defconfig
+
+NETSPACE_LITE_V2 BOARD
+#M:	-
+S:	Maintained
+F:	configs/netspace_lite_v2_defconfig
+F:	configs/netspace_mini_v2_defconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	:= netspace_v2.o ../common/common.o
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000008	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   10, Cs0size=512Mb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000632	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x34143000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000DDDD	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   10, Cs0size=512Mb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000632	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000C	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000632	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "netspace_v2.h"
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* Gpio configuration */
+	mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
+			  NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,		/* Fan speed (bit 1) */
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,		/* Red led */
+		MPP14_GPIO,		/* USB fuse */
+		MPP16_GPIO,		/* SATA 0 power */
+		MPP17_GPIO,		/* SATA 1 power */
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_SATA1_ACTn,
+		MPP21_SATA0_ACTn,
+		MPP22_GPIO,		/* Fan speed (bit 0) */
+		MPP23_GPIO,		/* Fan power */
+		MPP24_GPIO,		/* USB mode select */
+		MPP25_GPIO,		/* Fan rotation fail */
+		MPP26_GPIO,		/* USB vbus-in detection */
+		MPP28_GPIO,		/* USB enable vbus-out */
+		MPP29_GPIO,		/* Blue led (slow register) */
+		MPP30_GPIO,		/* Blue led (command register) */
+		MPP31_GPIO,		/* Board power off */
+		MPP32_GPIO,		/* Button (0 = Released, 1 = Pushed) */
+		MPP33_GPIO,		/* Fan speed (bit 2) */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Machine number */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	/* Boot parameters address */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+	if (!env_get("ethaddr")) {
+		uchar mac[6];
+		if (lacie_read_mac_address(mac) == 0)
+			eth_env_set_enetaddr("ethaddr", mac);
+	}
+#endif
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+	mv_phy_88e1318_init("egiga0", 0);
+#else
+	mv_phy_88e1116_init("egiga0", 8);
+#endif
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO)
+/* Return GPIO button status */
+static int
+do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
+}
+
+U_BOOT_CMD(button, 1, 1, do_read_button,
+	   "Return GPIO button status 0=off 1=on", "");
+#endif
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef NETSPACE_V2_H
+#define NETSPACE_V2_H
+
+/* GPIO configuration */
+#define NETSPACE_V2_OE_LOW		0x06004000
+#define NETSPACE_V2_OE_HIGH		0x00000031
+#define NETSPACE_V2_OE_VAL_LOW		0x10030000
+#define NETSPACE_V2_OE_VAL_HIGH		0x00000000
+
+#define NETSPACE_V2_GPIO_BUTTON         32
+
+#endif /* NETSPACE_V2_H */
@@ -0,0 +1,15 @@
+if TARGET_ASPENITE
+
+config SYS_BOARD
+	default "aspenite"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_SOC
+	default "armada100"
+
+config SYS_CONFIG_NAME
+	default "aspenite"
+
+endif
@@ -0,0 +1,6 @@
+ASPENITE BOARD
+M:	Prafulla Wadaskar <prafulla@marvell.com>
+S:	Maintained
+F:	board/Marvell/aspenite/
+F:	include/configs/aspenite.h
+F:	configs/aspenite_defconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+
+obj-y	:= aspenite.o
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* I2C */
+		MFP105_CI2C_SDA,
+		MFP106_CI2C_SCL,
+
+		/* Enable Console on UART1 */
+		MFP107_UART1_RXD,
+		MFP108_UART1_TXD,
+
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of Board */
+	gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+	return 0;
+}
@@ -0,0 +1,12 @@
+if TARGET_DB_88F6281_BP
+
+config SYS_BOARD
+	default "db-88f6281-bp"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_CONFIG_NAME
+	default "db-88f6281-bp"
+
+endif
@@ -0,0 +1,10 @@
+DB_88F6820_AMC BOARD
+M:	Chris Packham <judge.packham@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/kirkwood-db-88f6281.dts
+F:	arch/arm/dts/kirkwood-db-88f6281-spi.dts
+F:	arch/arm/dts/kirkwood-db.dtsi
+F:	board/Marvell/db-88f6281-bp/
+F:	include/configs/db-88f6281-bp.h
+F:	configs/db-88f6281-bp-nand_defconfig
+F:	configs/db-88f6281-bp-spi_defconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	:= db-88f6281-bp.o
+extra-y := kwbimage.cfg
+
+quiet_cmd_sed = SED     $@
+      cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
+
+SEDFLAGS_kwbimage.cfg = -e "s/^\#@BOOT_FROM.*/BOOT_FROM	$(if $(CONFIG_CMD_NAND),nand,spi)/"
+$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+		include/config/auto.conf
+	$(call if_changed,sed)
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <linux/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define DB_88F6281_OE_LOW	~(BIT(7))
+#define DB_88F6281_OE_HIGH	~(BIT(15) | BIT(14) | BIT(13) | BIT(4))
+#define DB_88F6281_OE_VAL_LOW	BIT(7)
+#define DB_88F6281_OE_VAL_HIGH	0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	mvebu_config_gpio(DB_88F6281_OE_VAL_LOW,
+			  DB_88F6281_OE_VAL_HIGH,
+			  DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+#ifdef CONFIG_CMD_NAND
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+#else
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+#endif
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_SATA1_ACTn,
+		MPP21_SATA0_ACTn,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
+void reset_phy(void)
+{
+}
+#endif
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+# Boot Media configurations
+#@BOOT_FROM
+
+DATA 0xd00100e0 0x1b1b1b9b
+DATA 0xd0020134 0xbbbbbbbb
+DATA 0xd0020138 0x00bbbbbb
+DATA 0xd0020154 0x00000200
+DATA 0xd002014c 0x00001c00
+DATA 0xd0020148 0x00000001
+
+DATA 0xd0001400 0x43000c30
+DATA 0xd0001404 0x39543000
+DATA 0xd0001408 0x22125451
+DATA 0xd000140c 0x00000833
+DATA 0xd0001410 0x000000cc
+DATA 0xd0001414 0x00000000
+DATA 0xd0001418 0x00000000
+DATA 0xd000141c 0x00000c52
+DATA 0xd0001420 0x00000044
+DATA 0xd0001424 0x0000f1ff
+DATA 0xd0001428 0x00085520
+DATA 0xd000147c 0x00008552
+DATA 0xd0001504 0x0ffffff1
+DATA 0xd0001508 0x10000000
+DATA 0xd000150c 0x0ffffff5
+DATA 0xd0001514 0x00000000
+DATA 0xd000151c 0x00000000
+DATA 0xd0001494 0x84210000
+DATA 0xd0001498 0x00000000
+DATA 0xd000149c 0x0000f40f
+DATA 0xd0001480 0x00000001
+
+# End of Header extension
+DATA 0x0 0x0
@@ -0,0 +1,6 @@
+DB_88F6720 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/db-88f6720/
+F:	include/configs/db-88f6720.h
+F:	configs/db-88f6720_defconfig
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+
+obj-y	:= db-88f6720.o
--- a/Show More
+++ b/Show More