GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/bootloader/u-boot-2020.01/board/AndesTech/adp-ae3xx/Kconfig

@@ -0,0 +1,18 @@
+if TARGET_ADP_AE3XX
+
+config SYS_CPU
+	default "n1213"
+
+config SYS_BOARD
+	default "adp-ae3xx"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ae3xx"
+
+config SYS_CONFIG_NAME
+	default "adp-ae3xx"
+
+endif

source/bootloader/u-boot-2020.01/board/AndesTech/adp-ae3xx/MAINTAINERS

@@ -0,0 +1,6 @@
+ADP-AG101P BOARD
+M:	Andes <uboot@andestech.com>
+S:	Maintained
+F:	board/AndesTech/adp-ae3xx/
+F:	include/configs/adp-ae3xx.h
+F:	configs/adp-ae3xx_defconfig

source/bootloader/u-boot-2020.01/board/AndesTech/adp-ae3xx/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2016 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+obj-y	:= adp-ae3xx.o

source/bootloader/u-boot-2020.01/board/AndesTech/adp-ae3xx/adp-ae3xx.c

@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#include <asm/mach-types.h>
+#include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	printf("Board: %s\n" , CONFIG_SYS_BOARD);
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+	gd->ram_size = actual_size;
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}

source/bootloader/u-boot-2020.01/board/AndesTech/adp-ag101p/Kconfig

@@ -0,0 +1,18 @@
+if TARGET_ADP_AG101P
+
+config SYS_CPU
+	default "n1213"
+
+config SYS_BOARD
+	default "adp-ag101p"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ag101"
+
+config SYS_CONFIG_NAME
+	default "adp-ag101p"
+
+endif

source/bootloader/u-boot-2020.01/board/AndesTech/adp-ag101p/MAINTAINERS

@@ -0,0 +1,6 @@
+ADP-AG101P BOARD
+M:	Andes <uboot@andestech.com>
+S:	Maintained
+F:	board/AndesTech/adp-ag101p/
+F:	include/configs/adp-ag101p.h
+F:	configs/adp-ag101p_defconfig

source/bootloader/u-boot-2020.01/board/AndesTech/adp-ag101p/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+
+obj-y	:= adp-ag101p.o

source/bootloader/u-boot-2020.01/board/AndesTech/adp-ag101p/adp-ag101p.c

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	printf("Board: %s\n" , CONFIG_SYS_BOARD);
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}

source/bootloader/u-boot-2020.01/board/AndesTech/ax25-ae350/Kconfig

@@ -0,0 +1,38 @@
+if TARGET_AX25_AE350
+
+config SYS_CPU
+	default "ax25"
+
+config SYS_BOARD
+	default "ax25-ae350"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ae350"
+
+config SYS_CONFIG_NAME
+	default "ax25-ae350"
+
+config ENV_SIZE
+	default 0x2000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x140000 if ENV_IS_IN_SPI_FLASH
+
+config SPL_TEXT_BASE
+	default 0x800000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x01000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select RISCV_NDS
+	select SUPPORT_SPL
+	imply SMP
+	imply SPL_RAM_SUPPORT
+	imply SPL_RAM_DEVICE
+
+endif

source/bootloader/u-boot-2020.01/board/AndesTech/ax25-ae350/MAINTAINERS

@@ -0,0 +1,13 @@
+AX25-AE350 BOARD
+M:	Rick Chen <rick@andestech.com>
+S:	Maintained
+F:	board/AndesTech/ax25-ae350/
+F:	include/configs/ax25-ae350.h
+F:	configs/ae350_rv32_defconfig
+F:	configs/ae350_rv64_defconfig
+F:	configs/ae350_rv32_xip_defconfig
+F:	configs/ae350_rv64_xip_defconfig
+F:	configs/ae350_rv32_spl_defconfig
+F:	configs/ae350_rv64_spl_defconfig
+F:	configs/ae350_rv32_spl_xip_defconfig
+F:	configs/ae350_rv64_spl_xip_defconfig

source/bootloader/u-boot-2020.01/board/AndesTech/ax25-ae350/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Andes Technology Corporation.
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+obj-y	:= ax25-ae350.o

source/bootloader/u-boot-2020.01/board/AndesTech/ax25-ae350/ax25-ae350.c

@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <faraday/ftsmc020.h>
+#include <fdtdec.h>
+#include <dm.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern phys_addr_t prior_stage_fdt_address;
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	return 0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+	return (void *)CONFIG_SYS_FDT_BASE;
+}
+
+int smc_init(void)
+{
+	int node = -1;
+	const char *compat = "andestech,atfsmc020";
+	void *blob = (void *)gd->fdt_blob;
+	fdt_addr_t addr;
+	struct ftsmc020_bank *regs;
+
+	node = fdt_node_offset_by_compatible(blob, -1, compat);
+	if (node < 0)
+		return -FDT_ERR_NOTFOUND;
+
+	addr = fdtdec_get_addr(blob, node, "reg");
+
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	regs = (struct ftsmc020_bank *)addr;
+	regs->cr &= ~FTSMC020_BANK_WPROT;
+
+	return 0;
+}
+
+static void v5l2_init(void)
+{
+	struct udevice *dev;
+
+	uclass_get_device(UCLASS_CACHE, 0, &dev);
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	smc_init();
+	v5l2_init();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+	u8 i;
+	u32 boot_devices[] = {
+#ifdef CONFIG_SPL_RAM_SUPPORT
+		BOOT_DEVICE_RAM,
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+		BOOT_DEVICE_MMC1,
+#endif
+	};
+
+	for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+		spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif