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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/bootloader/u-boot-2020.01/board/BuR/brppt1/Kconfig
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if TARGET_BRPPT1
config SYS_BOARD
default "brppt1"
config SYS_VENDOR
default "BuR"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "brppt1"
endif
source/bootloader/u-boot-2020.01/board/BuR/brppt1/MAINTAINERS
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BRPPT1 BOARD
M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
S: Maintained
F: board/BuR/brppt1/
F: include/configs/brppt1.h
F: configs/brppt1_mmc_defconfig
F: configs/brppt1_nand_defconfig
F: configs/brppt1_spi_defconfig
source/bootloader/u-boot-2020.01/board/BuR/brppt1/Makefile
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# SPDX-License-Identifier: GPL-2.0+
#
# Makefile
#
# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
ifeq ($(CONFIG_SPL_BUILD),y)
obj-y := mux.o
endif
obj-y += ../common/common.o
obj-y += board.o
source/bootloader/u-boot-2020.01/board/BuR/brppt1/board.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* board.c
*
* Board functions for B&R BRPPT1
*
* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*
*/
#include <common.h>
#include <bootcount.h>
#include <env.h>
#include <errno.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
/* --------------------------------------------------------------------------*/
/* -- defines for GPIO -- */
#define REPSWITCH (0+20) /* GPIO0_20 */
#if defined(CONFIG_SPL_BUILD)
/* TODO: check ram-timing ! */
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
static const struct ctrl_ioregs ddr3_ioregs = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
#define OSC (V_OSCK/1000000)
static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
int rc;
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
/*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
/*
* in TRM they write a reset value of 1 (=CLK_M_OSC) for the
* CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
* the source of timer6 clk to CLK_M_OSC
*/
writel(0x01, &cmdpll->clktimer6clk);
/* enable additional clocks of modules which are accessed later */
u32 *const clk_domains[] = {
&cmper->lcdcclkstctrl,
0
};
u32 *const clk_modules_tsspecific[] = {
&cmper->lcdclkctrl,
&cmper->timer5clkctrl,
&cmper->timer6clkctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
/* setup I2C */
enable_i2c_pin_mux();
pmicsetup(0, 0);
/* peripheral reset */
rc = gpio_request(64 + 29, "GPMC_WAIT1");
if (rc != 0)
printf("cannot request GPMC_WAIT1 GPIO!\n");
rc = gpio_direction_output(64 + 29, 1);
if (rc != 0)
printf("cannot set GPMC_WAIT1 GPIO!\n");
rc = gpio_request(64 + 28, "GPMC_WAIT0");
if (rc != 0)
printf("cannot request GPMC_WAIT0 GPIO!\n");
rc = gpio_direction_output(64 + 28, 1);
if (rc != 0)
printf("cannot set GPMC_WAIT0 GPIO!\n");
}
const struct dpll_params *get_dpll_ddr_params(void)
{
return &dpll_ddr3;
}
void sdram_init(void)
{
config_ddr(400, &ddr3_ioregs,
&ddr3_data,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
#endif /* CONFIG_SPL_BUILD */
/* Basic board specific setup. Pinmux has been handled already. */
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_MTD_RAW_NAND
gpmc_init();
#endif
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
static char *bootmodeascii[16] = {
"BOOT", "reserved", "reserved", "reserved",
"RUN", "reserved", "reserved", "reserved",
"reserved", "reserved", "reserved", "reserved",
"PME", "reserved", "reserved", "DIAG",
};
int board_late_init(void)
{
unsigned char bmode = 0;
ulong bootcount = 0;
int rc;
bootcount = bootcount_load() & 0xF;
rc = gpio_request(REPSWITCH, "REPSWITCH");
if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
bmode = 12;
else if (bootcount > 0)
bmode = 0;
else
bmode = 4;
printf("Mode: %s\n", bootmodeascii[bmode & 0x0F]);
env_set_ulong("b_mode", bmode);
/* get sure that bootcmd isn't affected by any bootcount value */
env_set_ulong("bootlimit", 0);
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
source/bootloader/u-boot-2020.01/board/BuR/brppt1/config.mk
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#
# Copyright (C) 2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
# B&R Industrial Automation GmbH - http://www.br-automation.com
#
# SPDX-License-Identifier: GPL-2.0+
#
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
cmd_prodbin = \
dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
quiet_cmd_prodzip = SAPZIP $@
cmd_prodzip = \
test -d misc && rm -r misc; \
mkdir misc && \
cp MLO.byteswap misc/ && \
cp spl/u-boot-spl.bin misc/ && \
cp u-boot-dtb.img misc/ && \
zip -9 -r $@ misc/* >/dev/null $<
ifeq ($(hw-platform-y),brppt1-spi)
ALL-y += $(hw-platform-y)_prog.bin
ALL-y += $(hw-platform-y)_prod.zip
endif
$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
$(call if_changed,prodbin)
$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
$(call if_changed,prodzip)
source/bootloader/u-boot-2020.01/board/BuR/brppt1/mux.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* mux.c
*
* Pinmux Setting for B&R BRPPT1 Board(s)
*
* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
static struct module_pin_mux uart0_pin_mux[] = {
/* UART0_RTS */
{OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
/* UART0_CTS */
{OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART0_RXD */
{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART0_TXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux uart1_pin_mux[] = {
/* UART1_RTS as I2C2-SCL */
{OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART1_CTS as I2C2-SDA */
{OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART1_RXD */
{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART1_TXD */
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
{-1},
};
#ifdef CONFIG_MMC
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
{-1},
};
#endif
static struct module_pin_mux i2c0_pin_mux[] = {
/* I2C_DATA */
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C_SCLK */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
static struct module_pin_mux spi0_pin_mux[] = {
/* SPI0_SCLK */
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
/* SPI0_D0 */
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
/* SPI0_D1 */
{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
/* SPI0_CS0 */
{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
{-1},
};
static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
{OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux mii2_pin_mux[] = {
{OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
{OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
{OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
{OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
{OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
{OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
{OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
{OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
{OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
{OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
{OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
{OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
{OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
/*
* MII2_CRS is shared with
* NAND_WAIT0
*/
{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
{-1},
};
#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{-1},
};
#endif
static struct module_pin_mux gpIOs[] = {
/* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
/* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
/* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO2_0 (GPMC_nCS3) - DCOK */
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
/*
* GPIO0_7 (PWW0 OUT)
* DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
*/
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO0_20 (DMA_INTR1) - REP-Switch */
{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
{OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
#ifndef CONFIG_MTD_RAW_NAND
/* GPIO2_3 - NAND_OE */
{OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
/* GPIO2_4 - NAND_WEN */
{OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
/* GPIO2_5 - NAND_BE_CLE */
{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
#endif
{-1},
};
static struct module_pin_mux lcd_pin_mux[] = {
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_i2c_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
void enable_board_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mii2_pin_mux);
#ifdef CONFIG_MTD_RAW_NAND
configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_MMC)
configure_module_pin_mux(mmc1_pin_mux);
#endif
configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(lcd_pin_mux);
configure_module_pin_mux(uart1_pin_mux);
configure_module_pin_mux(gpIOs);
}
source/bootloader/u-boot-2020.01/board/BuR/brppt2/Kconfig
+18
View File
@@ -0,0 +1,18 @@
if TARGET_BRPPT2
config SYS_BOARD
default "brppt2"
config SYS_VENDOR
default "BuR"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "brppt2"
config SPL_DM_SPI
def_bool y
endif
source/bootloader/u-boot-2020.01/board/BuR/brppt2/MAINTAINERS
+6
View File
@@ -0,0 +1,6 @@
BUR_PPT2 BOARD
M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
S: Maintained
F: board/BuR/brppt2/
F: include/configs/brppt2.h
F: configs/brppt2_defconfig
source/bootloader/u-boot-2020.01/board/BuR/brppt2/Makefile
+8
View File
@@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2019
# B&R Industrial Automation GmbH - http://www.br-automation.com
#
obj-y := ../common/common.o
obj-y += board.o
source/bootloader/u-boot-2020.01/board/BuR/brppt2/board.c
+542
View File
@@ -0,0 +1,542 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Board functions for BuR BRPPT2 board
*
* Copyright (C) 2019
* B&R Industrial Automation GmbH - http://www.br-automation.com/
*
*/
#include <common.h>
#include <spl.h>
#include <dm.h>
#include <miiphy.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#ifdef CONFIG_SPL_BUILD
# include <asm/arch/mx6-ddr.h>
#endif
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/gpio.h>
#define USBHUB_RSTN IMX_GPIO_NR(1, 16)
#define BKLT_EN IMX_GPIO_NR(1, 15)
#define CAPT_INT IMX_GPIO_NR(4, 9)
#define CAPT_RESETN IMX_GPIO_NR(4, 11)
#define SW_INTN IMX_GPIO_NR(3, 26)
#define VCCDISP_EN IMX_GPIO_NR(5, 18)
#define EMMC_RSTN IMX_GPIO_NR(6, 8)
#define PMIC_IRQN IMX_GPIO_NR(5, 22)
#define TASTER IMX_GPIO_NR(5, 23)
#define ETH0_LINK IMX_GPIO_NR(1, 27)
#define ETH1_LINK IMX_GPIO_NR(1, 28)
#define UART_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define ECSPI_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
PAD_CTL_SRE_FAST)
#define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define GPIO_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define LCDCMOS_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
#if !defined(CONFIG_SPL_BUILD)
static iomux_v3_cfg_t const eth_pads[] = {
/*
* Gigabit Ethernet
*/
/* CLKs */
MUXDESC(PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL_CLK),
MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL_CLK),
/* MDIO */
MUXDESC(PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL_PU),
MUXDESC(PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL_PU),
/* RGMII */
MUXDESC(PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL1),
MUXDESC(PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
MUXDESC(PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL_PU),
MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL_PU),
/* ETH0_LINK */
MUXDESC(PAD_ENET_RXD0__GPIO1_IO27, GPIO_PAD_CTRL_PD),
/* ETH1_LINK */
MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28, GPIO_PAD_CTRL_PD),
};
static iomux_v3_cfg_t const board_pads[] = {
/*
* I2C #3, #4
*/
MUXDESC(PAD_GPIO_3__I2C3_SCL, I2C_PAD_CTRL),
MUXDESC(PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL),
/*
* UART#4 PADS
* UART_Tasten
*/
MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA, UART_PAD_CTRL),
MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA, UART_PAD_CTRL),
MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B, UART_PAD_CTRL),
MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B, UART_PAD_CTRL),
/*
* ESCPI#1
* M25P32 NOR-Flash
*/
MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
/*
* ESCPI#2
* resTouch SPI ADC
*/
MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_OE__ECSPI2_MISO, ECSPI_PAD_CTRL),
MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D24__GPIO3_IO24, ECSPI_PAD_CTRL),
/*
* USDHC#4
*/
MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
/*
* USB OTG power & ID
*/
/* USB_OTG_5V_EN */
MUXDESC(PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL_PD),
MUXDESC(PAD_EIM_D31__GPIO3_IO31, GPIO_PAD_CTRL_PD),
/* USB_OTG_JUMPER */
MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID, GPIO_PAD_CTRL_PD),
/*
* PWM-Pins
*/
/* BKLT_CTL */
MUXDESC(PAD_SD1_CMD__PWM4_OUT, GPIO_PAD_CTRL_PD),
/* SPEAKER */
MUXDESC(PAD_SD1_DAT1__PWM3_OUT, GPIO_PAD_CTRL_PD),
/*
* GPIOs
*/
/* USB_HUB_nRESET */
MUXDESC(PAD_SD1_DAT0__GPIO1_IO16, GPIO_PAD_CTRL_PD),
/* BKLT_EN */
MUXDESC(PAD_SD2_DAT0__GPIO1_IO15, GPIO_PAD_CTRL_PD),
/* capTouch_INT */
MUXDESC(PAD_KEY_ROW1__GPIO4_IO09, GPIO_PAD_CTRL_PD),
/* capTouch_nRESET */
MUXDESC(PAD_KEY_ROW2__GPIO4_IO11, GPIO_PAD_CTRL_PD),
/* SW_nINT */
MUXDESC(PAD_EIM_D26__GPIO3_IO26, GPIO_PAD_CTRL_PU),
/* VCC_DISP_EN */
MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18, GPIO_PAD_CTRL_PD),
/* eMMC_nRESET */
MUXDESC(PAD_NANDF_ALE__GPIO6_IO08, GPIO_PAD_CTRL_PD),
/* HWID*/
MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
/* PMIC_nIRQ */
MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22, GPIO_PAD_CTRL_PU),
/* nTASTER */
MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23, GPIO_PAD_CTRL_PU),
/* RGB LCD Display */
MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22, LCDCMOS_PAD_CTRL),
MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23, LCDCMOS_PAD_CTRL),
};
int board_ehci_hcd_init(int port)
{
gpio_direction_output(USBHUB_RSTN, 1);
return 0;
}
int board_late_init(void)
{
ulong b_mode = 4;
if (gpio_get_value(TASTER) == 0)
b_mode = 12;
env_set_ulong("b_mode", b_mode);
return 0;
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
if (gpio_request(BKLT_EN, "BKLT_EN"))
printf("Warning: BKLT_EN setup failed\n");
gpio_direction_output(BKLT_EN, 0);
if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
printf("Warning: USBHUB_nRST setup failed\n");
gpio_direction_output(USBHUB_RSTN, 0);
if (gpio_request(TASTER, "TASTER"))
printf("Warning: TASTER setup failed\n");
gpio_direction_input(TASTER);
return 0;
}
int board_early_init_f(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
SETUP_IOMUX_PADS(board_pads);
SETUP_IOMUX_PADS(eth_pads);
/* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
enable_fec_anatop_clock(0, ENET_25MHZ);
enable_enet_clk(1);
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
#else
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
.dram_cas = 0x00020030,
.dram_ras = 0x00020030,
.dram_reset = 0x00020030,
/* SDCKE[0:1]: 100k pull-up */
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
/* SDBA2: pull-up disabled */
.dram_sdba2 = 0x00000000,
/* SDODT[0:1]: 100k pull-up, 40 ohm */
.dram_sdodt0 = 0x00003030,
.dram_sdodt1 = 0x00003030,
/* SDQS[0:7]: Differential input, 40 ohm */
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
/* DQM[0:7]: Differential input, 40 ohm */
.dram_dqm0 = 0x00020030,
.dram_dqm1 = 0x00020030,
.dram_dqm2 = 0x00020030,
.dram_dqm3 = 0x00020030,
.dram_dqm4 = 0x00020030,
.dram_dqm5 = 0x00020030,
.dram_dqm6 = 0x00020030,
.dram_dqm7 = 0x00020030,
};
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
/* DDR3 */
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
/* disable DDR pullups */
.grp_ddrpke = 0x00000000,
/* ADDR[00:16], SDBA[0:1]: 40 ohm */
.grp_addds = 0x00000030,
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
.grp_ctlds = 0x00000030,
/* DATA[00:63]: Differential input, 40 ohm */
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_b2ds = 0x00000030,
.grp_b3ds = 0x00000030,
.grp_b4ds = 0x00000030,
.grp_b5ds = 0x00000030,
.grp_b6ds = 0x00000030,
.grp_b7ds = 0x00000030,
};
/*
* DDR3 desriptions - these are the memory chips we support
*/
/* NT5CC128M16FP-DII */
static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
.mem_speed = 1600,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
/* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
/* write leveling calibration determine, MR1-value = 0x0002 */
.p0_mpwldectrl0 = 0x003F003E,
.p0_mpwldectrl1 = 0x003A003A,
.p1_mpwldectrl0 = 0x001B001C,
.p1_mpwldectrl1 = 0x00190031,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x02640264,
.p0_mpdgctrl1 = 0x02440250,
.p1_mpdgctrl0 = 0x02400250,
.p1_mpdgctrl1 = 0x0238023C,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x40464644,
.p1_mprddlctl = 0x464A4842,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x38343034,
.p1_mpwrdlctl = 0x36323830,
};
/* measured on board TSERIES_ARM/1 V_LVDS_S32 */
static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
/* write leveling calibration determine, MR1-value = 0x0002 */
.p0_mpwldectrl0 = 0x00410043,
.p0_mpwldectrl1 = 0x003A003C,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x023C0244,
.p0_mpdgctrl1 = 0x02240230,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x484C4A48,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x3C363434,
};
static void spl_dram_init(void)
{
struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
u32 val, dram_strap = 0;
struct mx6_ddr3_cfg *mem = NULL;
struct mx6_mmdc_calibration *calib = NULL;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = -1, /* CPU type specific (overwritten) */
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
.ncs = 1, /* single chip select */
.cs1_mirror = 0,
.rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
.rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = 0, /* DDR3 */
};
/*
* MMDC Calibration requires the following data:
* mx6_mmdc_calibration - board-specific calibration (routing delays)
* these calibration values depend on board routing, SoC, and DDR
* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
* mx6_ddr_cfg - chip specific timing/layout details
*/
/* setup HWID3-2 to input */
val = readl(&gpio->gpio_dir);
val &= ~(0x1 << 0 | 0x1 << 1);
writel(val, &gpio->gpio_dir);
/* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
dram_strap = readl(&gpio->gpio_psr) & 0x3;
switch (dram_strap) {
/* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
case 0:
puts("DRAM strap 00\n");
mem = &cfg_nt5cc128m16fp_dii;
sysinfo.dsize = 2;
calib = &cal_nt5cc128m16fp_dii_128x64_s;
break;
/* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
case 1:
puts("DRAM strap 01\n");
mem = &cfg_nt5cc128m16fp_dii;
sysinfo.dsize = 1;
calib = &cal_nt5cc128m16fp_dii_128x32_s;
break;
default:
printf("DRAM strap 0x%x (invalid)\n", dram_strap);
break;
}
if (!mem) {
puts("Error: Invalid Memory Configuration\n");
hang();
}
if (!calib) {
puts("Error: Invalid Board Calibration Configuration\n");
hang();
}
mx6sdl_dram_iocfg(16 << sysinfo.dsize,
&ddr_iomux_s,
&grp_iomux_s);
mx6_dram_cfg(&sysinfo, calib, mem);
}
static iomux_v3_cfg_t const board_pads_spl[] = {
/* UART#1 PADS */
MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA, UART_PAD_CTRL),
MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA, UART_PAD_CTRL),
/* ESCPI#1 PADS */
MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
/* USDHC#4 PADS */
MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
/* HWID*/
MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
};
void spl_board_init(void)
{
preloader_console_init();
}
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/*
* We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
* initializes DMA very early (before all board code), so the only
* opportunity we have to initialize APBHDMA clocks is in SPL.
* setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
*/
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x00F0FC03, &ccm->CCGR1);
writel(0x0FFFF000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0030C3, &ccm->CCGR5);
writel(0x000003F0, &ccm->CCGR6);
}
void board_init_f(ulong dummy)
{
ccgr_init();
arch_cpu_init();
timer_init();
gpr_init();
SETUP_IOMUX_PADS(board_pads_spl);
spl_dram_init();
}
void reset_cpu(ulong addr)
{
}
#endif /* CONFIG_SPL_BUILD */
source/bootloader/u-boot-2020.01/board/BuR/brppt2/config.mk
+36
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@@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
# B&R Industrial Automation GmbH - http://www.br-automation.com
#
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/imx6dl-//')
payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
cmd_prodbin = \
dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
dd conv=notrunc bs=1 if=SPL of=$@ seek=1024 2>/dev/null && \
dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
quiet_cmd_prodzip = SAPZIP $@
cmd_prodzip = \
test -d misc && rm -r misc; \
mkdir misc && \
cp SPL misc/ && \
cp u-boot-dtb.img misc/ && \
zip -9 -r $@ misc/* >/dev/null $<
ifeq ($(hw-platform-y),brppt2)
ifneq ($(CONFIG_SPL_BUILD),y)
ALL-y += $(hw-platform-y)_prog.bin
ALL-y += $(hw-platform-y)_prod.zip
endif
endif
$(hw-platform-y)_prog.bin: u-boot-dtb.img spl SPL
$(call if_changed,prodbin)
$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
$(call if_changed,prodzip)
source/bootloader/u-boot-2020.01/board/BuR/brsmarc1/Kconfig
+15
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@@ -0,0 +1,15 @@
if TARGET_BRSMARC1
config SYS_BOARD
default "brsmarc1"
config SYS_VENDOR
default "BuR"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "brsmarc1"
endif
source/bootloader/u-boot-2020.01/board/BuR/brsmarc1/MAINTAINERS
+6
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@@ -0,0 +1,6 @@
BRSMARC1 BOARD
M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
S: Maintained
F: board/BuR/brsmarc1/
F: include/configs/brsmarc1.h
F: configs/brsmarc1_defconfig
source/bootloader/u-boot-2020.01/board/BuR/brsmarc1/Makefile
+10
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@@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
# B&R Industrial Automation GmbH - http://www.br-automation.com/
#
obj-$(CONFIG_SPL_BUILD) += mux.o
obj-y += ../common/br_resetc.o
obj-y += ../common/common.o
obj-y += board.o
source/bootloader/u-boot-2020.01/board/BuR/brsmarc1/board.c
+169
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@@ -0,0 +1,169 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board.c
*
* Board functions for B&R BRSMARC1 Board
*
* Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
* B&R Industrial Automation GmbH - http://www.br-automation.com
*
*/
#include <common.h>
#include <errno.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/emif.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
#include "../common/br_resetc.h"
/* -------------------------------------------------------------------------*/
/* -- defines for used GPIO Hardware -- */
#define PER_RESET (2 * 32 + 0)
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
static const struct ctrl_ioregs ddr3_ioregs = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
#define OSC (V_OSCK / 1000000)
const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
int rc;
/*
* enable additional clocks of modules which are accessed later from
* VxWorks OS
*/
u32 *const clk_domains[] = { 0 };
u32 *const clk_modules_specific[] = {
&cmwkup->wkup_adctscctrl,
&cmper->spi1clkctrl,
&cmper->dcan0clkctrl,
&cmper->dcan1clkctrl,
&cmper->timer4clkctrl,
&cmper->timer5clkctrl,
&cmper->lcdclkctrl,
&cmper->lcdcclkstctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_specific, 1);
/* setup I2C */
enable_i2c_pin_mux();
/* peripheral reset */
rc = gpio_request(PER_RESET, "PER_RESET");
if (rc != 0)
printf("cannot request PER_RESET GPIO!\n");
rc = gpio_direction_output(PER_RESET, 0);
if (rc != 0)
printf("cannot set PER_RESET GPIO!\n");
/* setup pmic */
pmicsetup(0, 0);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
return &dpll_ddr3;
}
void sdram_init(void)
{
config_ddr(400, &ddr3_ioregs,
&ddr3_data,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
#endif /* CONFIG_SPL_BUILD */
#if !defined(CONFIG_SPL_BUILD)
/* decision if backlight is switched on or not on powerup */
int board_backlightstate(void)
{
u8 bklmask, rstcause;
int rc = 0;
rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
if (rc != 0) {
printf("%s: read rstctrl failed!\n", __func__);
return 1;
}
if ((rstcause & bklmask) != 0)
return 0;
return 1;
}
/* Basic board specific setup. run quite after relocation */
int board_init(void)
{
if (power_tps65217_init(0))
printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
return 0;
}
#if defined(CONFIG_BOARD_LATE_INIT)
int board_late_init(void)
{
br_resetc_bmode();
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
#endif /* !CONFIG_SPL_BUILD */
source/bootloader/u-boot-2020.01/board/BuR/brsmarc1/config.mk
+33
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@@ -0,0 +1,33 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
# B&R Industrial Automation GmbH - http://www.br-automation.com
#
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
cmd_prodbin = \
dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
quiet_cmd_prodzip = SAPZIP $@
cmd_prodzip = \
test -d misc && rm -r misc; \
mkdir misc && \
cp MLO.byteswap misc/ && \
cp spl/u-boot-spl.bin misc/ && \
cp u-boot-dtb.img misc/ && \
zip -9 -r $@ misc/* >/dev/null $<
ALL-y += $(hw-platform-y)_prog.bin
ALL-y += $(hw-platform-y)_prod.zip
$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
$(call if_changed,prodbin)
$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
$(call if_changed,prodzip)
source/bootloader/u-boot-2020.01/board/BuR/brsmarc1/mux.c
+266
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@@ -0,0 +1,266 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* mux.c
*
* Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
*
* Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
* B&R Industrial Automation GmbH - http://www.br-automation.com
*
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
static struct module_pin_mux spi0_pin_mux[] = {
/* SPI0_SCLK */
{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI0_D0 */
{OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI0_D1 */
{OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI0_CS0 */
{OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* SPI0_CS1 */
{OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
static struct module_pin_mux spi1_pin_mux[] = {
/* SPI1_SCLK */
{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
/* SPI1_D0 */
{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
/* SPI1_D1 */
{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
/* SPI1_CS0 */
{OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* SPI1_CS1 */
{OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
static struct module_pin_mux dcan0_pin_mux[] = {
/* DCAN0 TX */
{OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
/* DCAN0 RX */
{OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
{-1},
};
static struct module_pin_mux dcan1_pin_mux[] = {
/* DCAN1 TX */
{OFFSET(uart0_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
/* DCAN1 RX */
{OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
{-1},
};
static struct module_pin_mux gpios[] = {
/* GPIO0_7 - LVDS_EN */
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO0_20 - BKLT_PWM (timer7) */
{OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO2_4 - DISON */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO1_24 - RGB_EN */
{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO1_28 - nPD */
{OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
/* GPIO2_5 - Watchdog */
{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO2_0 - ResetOut */
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
/* GPIO2_2 - BKLT_EN */
{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
/* GPIO1_17 - GPIO0 */
{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_18 - GPIO1 */
{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_19 - GPIO2 */
{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_22 - GPIO3 */
{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_23 - GPIO4 */
{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_25 - GPIO5 */
{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_7 - GPIO6 */
{OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_8 - GPIO7 */
{OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_18 - GPIO8 */
{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_19 - GPIO9 */
{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_20 - GPIO10 */
{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_21 - GPIO11 */
{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO2_28 - DRAM-strapping */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
/* GPIO2_4 - not routed (Pin U6) */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO2_5 - not routed (Pin T6) */
{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO2_28 - not routed (Pin G15) */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO3_18 - not routed (Pin B12) */
{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
{-1},
};
static struct module_pin_mux uart0_pin_mux[] = {
/* UART0_RXD */
{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART0_TXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux uart234_pin_mux[] = {
/* UART2_RXD */
{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART2_TXD */
{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
/* UART3_RXD */
{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART3_TXD */
{OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
/* UART3_RTS */
{OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
/* UART3_CTS */
{OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART4_RXD */
{OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART4_TXD */
{OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
/* UART4_RTS */
{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
/* UART4_CTS */
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
{-1},
};
static struct module_pin_mux i2c_pin_mux[] = {
/* I2C0_DATA */
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C0_SCLK */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C1_DATA */
{OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C1_SCLK */
{OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
static struct module_pin_mux eth_pin_mux[] = {
/* ETH1 */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* ETH1_REFCLK */
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRSDV */
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXER */
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
/* ETH2 */
{OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* ETH2_REFCLK */
{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRSDV */
{OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXER */
{OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
{OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
{OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
{OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
{OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
/* gpio2_19, gpio 3_4, not connected on board */
{OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
{OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* ETH Management */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
{-1},
};
static struct module_pin_mux lcd_pin_mux[] = {
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_i2c_pin_mux(void)
{
configure_module_pin_mux(i2c_pin_mux);
}
void enable_board_pin_mux(void)
{
configure_module_pin_mux(eth_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(spi1_pin_mux);
configure_module_pin_mux(dcan0_pin_mux);
configure_module_pin_mux(dcan1_pin_mux);
configure_module_pin_mux(uart234_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(lcd_pin_mux);
configure_module_pin_mux(gpios);
}
source/bootloader/u-boot-2020.01/board/BuR/brxre1/Kconfig
+15
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if TARGET_BRXRE1
config SYS_BOARD
default "brxre1"
config SYS_VENDOR
default "BuR"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "brxre1"
endif
source/bootloader/u-boot-2020.01/board/BuR/brxre1/MAINTAINERS
+7
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@@ -0,0 +1,7 @@
BRXRE1 BOARD
M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
S: Maintained
F: board/BuR/brxre1/
F: include/configs/brxre1.h
F: configs/brxre1_defconfig
F: arch/arm/dts/am335x-brxre1.dts
source/bootloader/u-boot-2020.01/board/BuR/brxre1/Makefile
+11
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@@ -0,0 +1,11 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Makefile
#
# Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> -
# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
obj-$(CONFIG_SPL_BUILD) += mux.o
obj-y += ../common/br_resetc.o
obj-y += ../common/common.o
obj-y += board.o
source/bootloader/u-boot-2020.01/board/BuR/brxre1/board.c
+182
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@@ -0,0 +1,182 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board.c
*
* Board functions for B&R BRXRE1 Board
*
* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*
*/
#include <common.h>
#include <env.h>
#include <errno.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <dm.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
#include "../common/br_resetc.h"
/* -------------------------------------------------------------------------*/
/* -- defines for used GPIO Hardware -- */
#define ESC_KEY (0 + 19)
#define LCD_PWR (0 + 5)
#define RSTCTRL_FORCE_PWR_NEN 0x04
#define RSTCTRL_CAN_STB 0x40
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
static const struct ctrl_ioregs ddr3_ioregs = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
#define OSC (V_OSCK / 1000000)
const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
int rc;
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
/*
* enable additional clocks of modules which are accessed later from
* VxWorks OS
*/
u32 *const clk_domains[] = { 0 };
u32 *const clk_modules_xre1specific[] = {
&cmwkup->wkup_adctscctrl,
&cmper->spi1clkctrl,
&cmper->dcan0clkctrl,
&cmper->dcan1clkctrl,
&cmper->epwmss0clkctrl,
&cmper->epwmss1clkctrl,
&cmper->epwmss2clkctrl,
&cmper->lcdclkctrl,
&cmper->lcdcclkstctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
/* power-OFF LCD-Display */
if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
printf("cannot request gpio for LCD_PWR!\n");
else if (gpio_direction_output(LCD_PWR, 0) != 0)
printf("cannot set direction output on LCD_PWR!\n");
/* setup I2C */
enable_i2c_pin_mux();
/* power-ON 3V3 via Resetcontroller */
rc = br_resetc_regset(RSTCTRL_CTRLREG,
RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB);
if (rc != 0)
printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");
pmicsetup(0, 0);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
return &dpll_ddr3;
}
void sdram_init(void)
{
config_ddr(400, &ddr3_ioregs,
&ddr3_data,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
#endif /* CONFIG_SPL_BUILD */
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
/* request common used gpios */
gpio_request(ESC_KEY, "boot-key");
if (power_tps65217_init(0))
printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_boot_key(void)
{
return gpio_get_value(ESC_KEY);
}
int board_late_init(void)
{
char othbootargs[128];
br_resetc_bmode();
/* setup othbootargs for bootvx-command (vxWorks bootline) */
snprintf(othbootargs, sizeof(othbootargs),
"u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
(u32)gd->fb_base - 0x20,
(u32)env_get_ulong("vx_memtop", 16, gd->fb_base - 0x20),
(u32)env_get_ulong("vx_romfsbase", 16, 0),
(u32)env_get_ulong("vx_romfssize", 16, 0));
env_set("othbootargs", othbootargs);
/*
* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
* expect that vectors are there, original u-boot moves them to _start
*/
__asm__("ldr r0,=0x20000");
__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
source/bootloader/u-boot-2020.01/board/BuR/brxre1/mux.c
+197
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// SPDX-License-Identifier: GPL-2.0+
/*
* mux.c
*
* Pinmux Setting for B&R LEIT Board(s)
*
* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
static struct module_pin_mux spi0_pin_mux[] = {
/* SPI1_SCLK */
{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_D0 */
{OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_D1 */
{OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
/* SPI1_CS0 */
{OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
/* SPI1_CS1 */
{OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
{-1},
};
static struct module_pin_mux dcan0_pin_mux[] = {
/* DCAN0 TX */
{OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
/* DCAN0 RX */
{OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
{-1},
};
static struct module_pin_mux dcan1_pin_mux[] = {
/* DCAN1 TX */
{OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
/* DCAN1 RX */
{OFFSET(uart1_txd), MODE(2) | RXACTIVE},
{-1},
};
static struct module_pin_mux gpios[] = {
/* GPIO0_7 (PWW0 OUT) - CAN TERM */
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO0_19 (DMA_INTR0) - TA602 */
{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
{OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
/* GPIO0_30 (GPMC_WAIT0) - TA601 */
{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
/* GPIO1_29 (gpmc_csn0) - MMC nRST */
{OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
/* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
/* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO2_4 (GPMC_nWE) - TST_BAST */
{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
/* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */
{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
/* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
{OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
/* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
{OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
{-1},
};
static struct module_pin_mux uart0_pin_mux[] = {
/* UART0_CTS */
{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART0_RXD */
{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* UART0_TXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
/* I2C_DATA */
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C_SCLK */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
{OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
{-1},
};
static struct module_pin_mux lcd_pin_mux[] = {
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_i2c_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
void enable_board_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(dcan0_pin_mux);
configure_module_pin_mux(dcan1_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(lcd_pin_mux);
configure_module_pin_mux(gpios);
}
source/bootloader/u-boot-2020.01/board/BuR/common/br_resetc.c
+236
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// SPDX-License-Identifier: GPL-2.0+
/*
* common reset-controller functions for B&R boards
*
* Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at>
* B&R Industrial Automation GmbH - http://www.br-automation.com/ *
*/
#include <common.h>
#include <env.h>
#include <errno.h>
#include <i2c.h>
#include <dm/uclass.h>
#include "br_resetc.h"
/* I2C Address of controller */
#define RSTCTRL_ADDR_PSOC 0x75
#define RSTCTRL_ADDR_STM32 0x60
#define BMODE_DEFAULTAR 0
#define BMODE_SERVICE 2
#define BMODE_RUN 4
#define BMODE_PME 12
#define BMODE_DIAG 15
#ifdef CONFIG_LCD
#include <lcd.h>
#define LCD_SETCURSOR(x, y) lcd_position_cursor(x, y)
#define LCD_PUTS(x) lcd_puts(x)
#else
#define LCD_SETCURSOR(x, y)
#define LCD_PUTS(x)
#endif /* CONFIG_LCD */
static const char *bootmodeascii[16] = {
"BOOT", "reserved", "reserved", "reserved",
"RUN", "reserved", "reserved", "reserved",
"reserved", "reserved", "reserved", "reserved",
"PME", "reserved", "reserved", "DIAG",
};
struct br_reset_t {
struct udevice *i2cdev;
u8 is_psoc;
};
static struct br_reset_t resetc;
__weak int board_boot_key(void)
{
return 0;
}
__weak void board_boot_led(unsigned int on)
{
}
static int resetc_init(void)
{
struct udevice *i2cbus;
int rc;
rc = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus);
if (rc) {
printf("Cannot find I2C bus #0!\n");
return -1;
}
resetc.is_psoc = 1;
rc = dm_i2c_probe(i2cbus,
RSTCTRL_ADDR_PSOC, 0, &resetc.i2cdev);
if (rc) {
resetc.is_psoc = 0;
rc = dm_i2c_probe(i2cbus,
RSTCTRL_ADDR_STM32, 0, &resetc.i2cdev);
}
if (rc)
printf("Warning: cannot probe BuR resetcontroller!\n");
return rc;
}
int br_resetc_regget(u8 reg, u8 *dst)
{
int rc = 0;
if (!resetc.i2cdev)
rc = resetc_init();
if (rc != 0)
return rc;
return dm_i2c_read(resetc.i2cdev, reg, dst, 1);
}
int br_resetc_regset(u8 reg, u8 val)
{
int rc = 0;
u16 regw = (val << 8) | val;
if (!resetc.i2cdev)
rc = resetc_init();
if (rc != 0)
return rc;
if (resetc.is_psoc)
return dm_i2c_write(resetc.i2cdev, reg, (u8 *)&regw, 2);
return dm_i2c_write(resetc.i2cdev, reg, (u8 *)&regw, 1);
}
int br_resetc_bmode(void)
{
int rc = 0;
u16 regw;
u8 regb, scr;
int cnt;
unsigned int bmode = 0;
if (!resetc.i2cdev)
rc = resetc_init();
if (rc != 0)
return rc;
rc = dm_i2c_read(resetc.i2cdev, RSTCTRL_ENHSTATUS, &regb, 1);
if (rc != 0) {
printf("WARN: cannot read ENHSTATUS from resetcontroller!\n");
return -1;
}
rc = dm_i2c_read(resetc.i2cdev, RSTCTRL_SCRATCHREG0, &scr, 1);
if (rc != 0) {
printf("WARN: cannot read SCRATCHREG from resetcontroller!\n");
return -1;
}
board_boot_led(1);
/* special bootmode from resetcontroller */
if (regb & 0x4) {
bmode = BMODE_DIAG;
} else if (regb & 0x8) {
bmode = BMODE_DEFAULTAR;
} else if (board_boot_key() != 0) {
cnt = 4;
do {
LCD_SETCURSOR(1, 8);
switch (cnt) {
case 4:
LCD_PUTS
("release KEY to enter SERVICE-mode. ");
break;
case 3:
LCD_PUTS
("release KEY to enter DIAGNOSE-mode. ");
break;
case 2:
LCD_PUTS
("release KEY to enter BOOT-mode. ");
break;
}
mdelay(1000);
cnt--;
if (board_boot_key() == 0)
break;
} while (cnt);
switch (cnt) {
case 0:
bmode = BMODE_PME;
break;
case 1:
bmode = BMODE_DEFAULTAR;
break;
case 2:
bmode = BMODE_DIAG;
break;
case 3:
bmode = BMODE_SERVICE;
break;
}
} else if ((regb & 0x1) || scr == 0xCC) {
bmode = BMODE_PME;
} else {
bmode = BMODE_RUN;
}
LCD_SETCURSOR(1, 8);
switch (bmode) {
case BMODE_PME:
LCD_PUTS("entering PME-Mode (netscript). ");
regw = 0x0C0C;
break;
case BMODE_DEFAULTAR:
LCD_PUTS("entering BOOT-mode. ");
regw = 0x0000;
break;
case BMODE_DIAG:
LCD_PUTS("entering DIAGNOSE-mode. ");
regw = 0x0F0F;
break;
case BMODE_SERVICE:
LCD_PUTS("entering SERVICE mode. ");
regw = 0xB4B4;
break;
case BMODE_RUN:
LCD_PUTS("loading OS... ");
regw = 0x0404;
break;
}
board_boot_led(0);
if (resetc.is_psoc)
rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
(u8 *)&regw, 2);
else
rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
(u8 *)&regw, 1);
if (rc != 0)
printf("WARN: cannot write into resetcontroller!\n");
if (resetc.is_psoc)
printf("Reset: PSOC controller\n");
else
printf("Reset: STM32 controller\n");
printf("Mode: %s\n", bootmodeascii[regw & 0x0F]);
env_set_ulong("b_mode", regw & 0x0F);
return rc;
}
source/bootloader/u-boot-2020.01/board/BuR/common/br_resetc.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* common reset-controller functions for B&R boards
*
* Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at>
* B&R Industrial Automation GmbH - http://www.br-automation.com/ *
*/
#ifndef __CONFIG_BRRESETC_H__
#define __CONFIG_BRRESETC_H__
#include <common.h>
int br_resetc_regget(u8 reg, u8 *dst);
int br_resetc_regset(u8 reg, u8 val);
int br_resetc_bmode(void);
/* reset controller register defines */
#define RSTCTRL_CTRLREG 0x01
#define RSTCTRL_SCRATCHREG0 0x04
#define RSTCTRL_ENHSTATUS 0x07
#define RSTCTRL_SCRATCHREG1 0x08
#define RSTCTRL_RSTCAUSE 0x00
#define RSTCTRL_ERSTCAUSE 0x09
#define RSTCTRL_SPECGPIO_I 0x0A
#define RSTCTRL_SPECGPIO_O 0x0B
#endif /* __CONFIG_BRRESETC_H__ */
source/bootloader/u-boot-2020.01/board/BuR/common/bur_common.h
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@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* bur_comon.h
*
* common board information header for B&R boards
*
* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*/
#ifndef _BUR_COMMON_H_
#define _BUR_COMMON_H_
#include <../../../drivers/video/am335x-fb.h>
int load_lcdtiming(struct am335x_lcdpanel *panel);
void br_summaryscreen(void);
void pmicsetup(u32 mpupll, unsigned int bus);
void enable_uart0_pin_mux(void);
void enable_i2c_pin_mux(void);
void enable_board_pin_mux(void);
int board_eth_init(bd_t *bis);
int brdefaultip_setup(int bus, int chip);
#endif
source/bootloader/u-boot-2020.01/board/BuR/common/common.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* common.c
*
* common board functions for B&R boards
*
* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*
*/
#include <version.h>
#include <common.h>
#include <env.h>
#include <fdtdec.h>
#include <i2c.h>
#include <lcd.h>
#include "bur_common.h"
DECLARE_GLOBAL_DATA_PTR;
/* --------------------------------------------------------------------------*/
#if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \
!defined(CONFIG_SPL_BUILD)
#include <asm/arch/hardware.h>
#include <asm/arch/cpu.h>
#include <asm/gpio.h>
#include <power/tps65217.h>
#include "../../../drivers/video/am335x-fb.h"
void lcdbacklight(int on)
{
unsigned int driver = env_get_ulong("ds1_bright_drv", 16, 0UL);
unsigned int bright = env_get_ulong("ds1_bright_def", 10, 50);
unsigned int pwmfrq = env_get_ulong("ds1_pwmfreq", 10, ~0UL);
unsigned int tmp;
struct gptimer *timerhw;
if (on)
bright = bright != ~0UL ? bright : 50;
else
bright = 0;
switch (driver) {
case 2:
timerhw = (struct gptimer *)DM_TIMER5_BASE;
break;
default:
timerhw = (struct gptimer *)DM_TIMER6_BASE;
}
switch (driver) {
case 0: /* PMIC LED-Driver */
/* brightness level */
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
TPS65217_WLEDCTRL2, bright, 0xFF);
/* current sink */
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
TPS65217_WLEDCTRL1,
bright != 0 ? 0x0A : 0x02,
0xFF);
break;
case 1:
case 2: /* PWM using timer */
if (pwmfrq != ~0UL) {
timerhw->tiocp_cfg = TCFG_RESET;
udelay(10);
while (timerhw->tiocp_cfg & TCFG_RESET)
;
tmp = ~0UL-(V_OSCK/pwmfrq); /* bottom value */
timerhw->tldr = tmp;
timerhw->tcrr = tmp;
tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright;
timerhw->tmar = tmp;
timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) |
TCLR_CE | TCLR_AR | TCLR_ST);
} else {
puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n");
}
break;
default:
puts("no suitable backlightdriver in env/dtb!\n");
break;
}
}
int load_lcdtiming(struct am335x_lcdpanel *panel)
{
struct am335x_lcdpanel pnltmp;
pnltmp.hactive = env_get_ulong("ds1_hactive", 10, ~0UL);
pnltmp.vactive = env_get_ulong("ds1_vactive", 10, ~0UL);
pnltmp.bpp = env_get_ulong("ds1_bpp", 10, ~0UL);
pnltmp.hfp = env_get_ulong("ds1_hfp", 10, ~0UL);
pnltmp.hbp = env_get_ulong("ds1_hbp", 10, ~0UL);
pnltmp.hsw = env_get_ulong("ds1_hsw", 10, ~0UL);
pnltmp.vfp = env_get_ulong("ds1_vfp", 10, ~0UL);
pnltmp.vbp = env_get_ulong("ds1_vbp", 10, ~0UL);
pnltmp.vsw = env_get_ulong("ds1_vsw", 10, ~0UL);
pnltmp.pxl_clk = env_get_ulong("ds1_pxlclk", 10, ~0UL);
pnltmp.pol = env_get_ulong("ds1_pol", 16, ~0UL);
pnltmp.pup_delay = env_get_ulong("ds1_pupdelay", 10, ~0UL);
pnltmp.pon_delay = env_get_ulong("ds1_tondelay", 10, ~0UL);
panel_info.vl_rot = env_get_ulong("ds1_rotation", 10, 0);
if (
~0UL == (pnltmp.hactive) ||
~0UL == (pnltmp.vactive) ||
~0UL == (pnltmp.bpp) ||
~0UL == (pnltmp.hfp) ||
~0UL == (pnltmp.hbp) ||
~0UL == (pnltmp.hsw) ||
~0UL == (pnltmp.vfp) ||
~0UL == (pnltmp.vbp) ||
~0UL == (pnltmp.vsw) ||
~0UL == (pnltmp.pxl_clk) ||
~0UL == (pnltmp.pol) ||
~0UL == (pnltmp.pup_delay) ||
~0UL == (pnltmp.pon_delay)
) {
puts("lcd-settings in env/dtb incomplete!\n");
printf("display-timings:\n"
"================\n"
"hactive: %d\n"
"vactive: %d\n"
"bpp : %d\n"
"hfp : %d\n"
"hbp : %d\n"
"hsw : %d\n"
"vfp : %d\n"
"vbp : %d\n"
"vsw : %d\n"
"pxlclk : %d\n"
"pol : 0x%08x\n"
"pondly : %d\n",
pnltmp.hactive, pnltmp.vactive, pnltmp.bpp,
pnltmp.hfp, pnltmp.hbp, pnltmp.hsw,
pnltmp.vfp, pnltmp.vbp, pnltmp.vsw,
pnltmp.pxl_clk, pnltmp.pol, pnltmp.pon_delay);
return -1;
}
debug("lcd-settings in env complete, taking over.\n");
memcpy((void *)panel,
(void *)&pnltmp,
sizeof(struct am335x_lcdpanel));
return 0;
}
static void br_summaryscreen_printenv(char *prefix,
char *name, char *altname,
char *suffix)
{
char *envval = env_get(name);
if (0 != envval) {
lcd_printf("%s %s %s", prefix, envval, suffix);
} else if (0 != altname) {
envval = env_get(altname);
if (0 != envval)
lcd_printf("%s %s %s", prefix, envval, suffix);
} else {
lcd_printf("\n");
}
}
void br_summaryscreen(void)
{
br_summaryscreen_printenv(" - B&R -", "br_orderno", 0, "-\n");
br_summaryscreen_printenv(" Serial/Rev :", "br_serial", 0, "\n");
br_summaryscreen_printenv(" MAC1 :", "br_mac1", "ethaddr", "\n");
br_summaryscreen_printenv(" MAC2 :", "br_mac2", 0, "\n");
lcd_puts(" Bootloader : " PLAIN_VERSION "\n");
lcd_puts("\n");
}
void lcdpower(int on)
{
u32 pin, swval, i;
char buf[16] = { 0 };
pin = env_get_ulong("ds1_pwr", 16, ~0UL);
if (pin == ~0UL) {
puts("no pwrpin in dtb/env, cannot powerup display!\n");
return;
}
for (i = 0; i < 3; i++) {
if (pin != 0) {
snprintf(buf, sizeof(buf), "ds1_pwr#%d", i);
if (gpio_request(pin & 0x7F, buf) != 0) {
printf("%s: not able to request gpio %s",
__func__, buf);
continue;
}
swval = pin & 0x80 ? 0 : 1;
if (on)
gpio_direction_output(pin & 0x7F, swval);
else
gpio_direction_output(pin & 0x7F, !swval);
debug("switched pin %d to %d\n", pin & 0x7F, swval);
}
pin >>= 8;
}
}
vidinfo_t panel_info = {
.vl_col = 1366, /*
* give full resolution for allocating enough
* memory
*/
.vl_row = 768,
.vl_bpix = 5,
.priv = 0
};
void lcd_ctrl_init(void *lcdbase)
{
struct am335x_lcdpanel lcd_panel;
memset(&lcd_panel, 0, sizeof(struct am335x_lcdpanel));
if (load_lcdtiming(&lcd_panel) != 0)
return;
lcd_panel.panel_power_ctrl = &lcdpower;
if (0 != am335xfb_init(&lcd_panel))
printf("ERROR: failed to initialize video!");
/*
* modifiy panel info to 'real' resolution, to operate correct with
* lcd-framework.
*/
panel_info.vl_col = lcd_panel.hactive;
panel_info.vl_row = lcd_panel.vactive;
lcd_set_flush_dcache(1);
}
void lcd_enable(void)
{
br_summaryscreen();
lcdbacklight(1);
}
#endif /* CONFIG_LCD */
int ft_board_setup(void *blob, bd_t *bd)
{
int nodeoffset;
nodeoffset = fdt_path_offset(blob, "/factory-settings");
if (nodeoffset < 0) {
printf("%s: cannot find /factory-settings, trying /fset\n",
__func__);
nodeoffset = fdt_path_offset(blob, "/fset");
if (nodeoffset < 0) {
printf("%s: cannot find /fset.\n", __func__);
return 0;
}
}
if (fdt_setprop(blob, nodeoffset, "bl-version",
PLAIN_VERSION, strlen(PLAIN_VERSION)) != 0) {
printf("%s: no 'bl-version' prop in fdt!\n", __func__);
return 0;
}
return 0;
}
int brdefaultip_setup(int bus, int chip)
{
int rc;
struct udevice *i2cdev;
u8 u8buf = 0;
char defip[256] = { 0 };
rc = i2c_get_chip_for_busnum(bus, chip, 2, &i2cdev);
if (rc != 0) {
printf("WARN: cannot probe baseboard EEPROM!\n");
return -1;
}
rc = dm_i2c_read(i2cdev, 0, &u8buf, 1);
if (rc != 0) {
printf("WARN: cannot read baseboard EEPROM!\n");
return -1;
}
if (u8buf != 0xFF)
snprintf(defip, sizeof(defip),
"if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.%d; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
u8buf);
else
strncpy(defip,
"if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
sizeof(defip));
env_set("brdefaultip", defip);
env_set_hex("board_id", u8buf);
return 0;
}
int overwrite_console(void)
{
return 1;
}
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_AM33XX)
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <power/tps65217.h>
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
void pmicsetup(u32 mpupll, unsigned int bus)
{
int mpu_vdd;
int usb_cur_lim;
if (power_tps65217_init(bus)) {
printf("WARN: cannot setup PMIC 0x24 @ bus #%d, not found!.\n",
bus);
return;
}
/* Get the frequency which is defined by device fuses */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
if (0 != mpupll) {
dpll_mpu_opp100.m = mpupll;
printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
} else {
puts("ok.\n");
}
/*
* Increase USB current limit to 1300mA or 1800mA and set
* the MPU voltage controller as needed.
*/
if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
} else {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
}
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
puts("tps65217_reg_write failure\n");
/* Set DCDC3 (CORE) voltage to 1.125V */
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
TPS65217_DCDC_VOLT_SEL_1125MV)) {
puts("tps65217_voltage_update failure\n");
return;
}
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Set DCDC2 (MPU) voltage */
if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
puts("tps65217_voltage_update failure\n");
return;
}
/* Set LDO3 to 1.8V */
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_1_8,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
/* Set LDO4 to 3.3V */
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS2,
TPS65217_LDO_VOLTAGE_OUT_3_3,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
/* Set PWR_EN bit in Status Register */
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
TPS65217_STATUS, TPS65217_PWR_OFF, TPS65217_PWR_OFF);
}
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
}
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
#endif /* CONFIG_SPL_BUILD && CONFIG_AM33XX */