GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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if TARGET_BRPPT1
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config SYS_BOARD
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default "brppt1"
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config SYS_VENDOR
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default "BuR"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "brppt1"
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endif
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@@ -0,0 +1,8 @@
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BRPPT1 BOARD
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M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
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S: Maintained
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F: board/BuR/brppt1/
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F: include/configs/brppt1.h
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F: configs/brppt1_mmc_defconfig
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F: configs/brppt1_nand_defconfig
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F: configs/brppt1_spi_defconfig
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@@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Makefile
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#
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# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
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# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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ifeq ($(CONFIG_SPL_BUILD),y)
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obj-y := mux.o
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endif
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obj-y += ../common/common.o
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obj-y += board.o
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@@ -0,0 +1,192 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for B&R BRPPT1
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*
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* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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*/
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#include <common.h>
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#include <bootcount.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <power/tps65217.h>
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#include "../common/bur_common.h"
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* --------------------------------------------------------------------------*/
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/* -- defines for GPIO -- */
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#define REPSWITCH (0+20) /* GPIO0_20 */
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#if defined(CONFIG_SPL_BUILD)
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/* TODO: check ram-timing ! */
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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static const struct ctrl_ioregs ddr3_ioregs = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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#define OSC (V_OSCK/1000000)
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static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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int rc;
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
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/*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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/*
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* in TRM they write a reset value of 1 (=CLK_M_OSC) for the
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* CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
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* the source of timer6 clk to CLK_M_OSC
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*/
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writel(0x01, &cmdpll->clktimer6clk);
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/* enable additional clocks of modules which are accessed later */
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u32 *const clk_domains[] = {
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&cmper->lcdcclkstctrl,
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0
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};
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u32 *const clk_modules_tsspecific[] = {
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&cmper->lcdclkctrl,
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&cmper->timer5clkctrl,
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&cmper->timer6clkctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
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/* setup I2C */
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enable_i2c_pin_mux();
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pmicsetup(0, 0);
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/* peripheral reset */
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rc = gpio_request(64 + 29, "GPMC_WAIT1");
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if (rc != 0)
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printf("cannot request GPMC_WAIT1 GPIO!\n");
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rc = gpio_direction_output(64 + 29, 1);
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if (rc != 0)
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printf("cannot set GPMC_WAIT1 GPIO!\n");
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rc = gpio_request(64 + 28, "GPMC_WAIT0");
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if (rc != 0)
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printf("cannot request GPMC_WAIT0 GPIO!\n");
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rc = gpio_direction_output(64 + 28, 1);
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if (rc != 0)
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printf("cannot set GPMC_WAIT0 GPIO!\n");
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr3;
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}
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void sdram_init(void)
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{
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config_ddr(400, &ddr3_ioregs,
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&ddr3_data,
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&ddr3_cmd_ctrl_data,
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&ddr3_emif_reg_data, 0);
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}
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#endif /* CONFIG_SPL_BUILD */
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/* Basic board specific setup. Pinmux has been handled already. */
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_MTD_RAW_NAND
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gpmc_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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static char *bootmodeascii[16] = {
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"BOOT", "reserved", "reserved", "reserved",
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"RUN", "reserved", "reserved", "reserved",
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"reserved", "reserved", "reserved", "reserved",
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"PME", "reserved", "reserved", "DIAG",
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};
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int board_late_init(void)
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{
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unsigned char bmode = 0;
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ulong bootcount = 0;
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int rc;
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bootcount = bootcount_load() & 0xF;
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rc = gpio_request(REPSWITCH, "REPSWITCH");
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if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
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bmode = 12;
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else if (bootcount > 0)
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bmode = 0;
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else
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bmode = 4;
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printf("Mode: %s\n", bootmodeascii[bmode & 0x0F]);
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env_set_ulong("b_mode", bmode);
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/* get sure that bootcmd isn't affected by any bootcount value */
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env_set_ulong("bootlimit", 0);
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return 0;
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}
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#endif /* CONFIG_BOARD_LATE_INIT */
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@@ -0,0 +1,36 @@
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#
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# Copyright (C) 2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
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# B&R Industrial Automation GmbH - http://www.br-automation.com
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
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payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
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quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
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cmd_prodbin = \
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dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
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dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
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dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
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quiet_cmd_prodzip = SAPZIP $@
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cmd_prodzip = \
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test -d misc && rm -r misc; \
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mkdir misc && \
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cp MLO.byteswap misc/ && \
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cp spl/u-boot-spl.bin misc/ && \
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cp u-boot-dtb.img misc/ && \
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zip -9 -r $@ misc/* >/dev/null $<
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ifeq ($(hw-platform-y),brppt1-spi)
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ALL-y += $(hw-platform-y)_prog.bin
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ALL-y += $(hw-platform-y)_prod.zip
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endif
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$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
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$(call if_changed,prodbin)
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$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
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$(call if_changed,prodzip)
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@@ -0,0 +1,253 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* mux.c
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*
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* Pinmux Setting for B&R BRPPT1 Board(s)
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*
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* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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static struct module_pin_mux uart0_pin_mux[] = {
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/* UART0_RTS */
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{OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
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/* UART0_CTS */
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{OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART0_RXD */
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{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART0_TXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
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{-1},
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};
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static struct module_pin_mux uart1_pin_mux[] = {
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/* UART1_RTS as I2C2-SCL */
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{OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART1_CTS as I2C2-SDA */
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{OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART1_RXD */
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{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART1_TXD */
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{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
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{-1},
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};
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#ifdef CONFIG_MMC
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static struct module_pin_mux mmc1_pin_mux[] = {
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{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
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{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
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{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
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{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
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{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
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{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
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{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
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{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
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{-1},
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};
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#endif
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static struct module_pin_mux i2c0_pin_mux[] = {
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/* I2C_DATA */
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C_SCLK */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux spi0_pin_mux[] = {
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/* SPI0_SCLK */
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{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
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/* SPI0_D0 */
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{OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
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/* SPI0_D1 */
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{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
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/* SPI0_CS0 */
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{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
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{-1},
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};
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static struct module_pin_mux mii1_pin_mux[] = {
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{OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
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{OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
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{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
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{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
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{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
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{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
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{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
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{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
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{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
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{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
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{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
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{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
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{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
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{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux mii2_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
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{OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
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{OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
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{OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
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{OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
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{OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
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{OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
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{OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
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{OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
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{OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
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{OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
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{OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
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{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
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{OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
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/*
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* MII2_CRS is shared with
|
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* NAND_WAIT0
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*/
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{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
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{-1},
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};
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#ifdef CONFIG_MTD_RAW_NAND
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static struct module_pin_mux nand_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
|
||||
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
|
||||
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
|
||||
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
|
||||
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
|
||||
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
|
||||
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
|
||||
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
|
||||
{OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
|
||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
|
||||
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
|
||||
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
|
||||
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
|
||||
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
|
||||
{-1},
|
||||
};
|
||||
#endif
|
||||
static struct module_pin_mux gpIOs[] = {
|
||||
/* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
|
||||
{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
|
||||
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
|
||||
/* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
|
||||
/* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
|
||||
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
|
||||
/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
|
||||
{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
|
||||
/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
|
||||
{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
|
||||
{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
|
||||
{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
|
||||
{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
|
||||
{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO2_0 (GPMC_nCS3) - DCOK */
|
||||
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
|
||||
/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
|
||||
{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
|
||||
/*
|
||||
* GPIO0_7 (PWW0 OUT)
|
||||
* DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
|
||||
*/
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
|
||||
/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
|
||||
{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO0_20 (DMA_INTR1) - REP-Switch */
|
||||
{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
|
||||
{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
|
||||
/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
|
||||
{OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
|
||||
/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
|
||||
{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
|
||||
/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
|
||||
{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
|
||||
#ifndef CONFIG_MTD_RAW_NAND
|
||||
/* GPIO2_3 - NAND_OE */
|
||||
{OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
|
||||
/* GPIO2_4 - NAND_WEN */
|
||||
{OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
|
||||
/* GPIO2_5 - NAND_BE_CLE */
|
||||
{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
|
||||
#endif
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux lcd_pin_mux[] = {
|
||||
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
|
||||
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
|
||||
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
|
||||
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
|
||||
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
|
||||
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
|
||||
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
|
||||
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
|
||||
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
|
||||
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
|
||||
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
|
||||
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
|
||||
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
|
||||
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
|
||||
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
|
||||
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
|
||||
|
||||
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
|
||||
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
|
||||
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
|
||||
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
|
||||
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
|
||||
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
|
||||
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
|
||||
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
|
||||
|
||||
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
|
||||
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
|
||||
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
|
||||
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
|
||||
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_board_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(mii2_pin_mux);
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
#elif defined(CONFIG_MMC)
|
||||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
#endif
|
||||
configure_module_pin_mux(spi0_pin_mux);
|
||||
configure_module_pin_mux(lcd_pin_mux);
|
||||
configure_module_pin_mux(uart1_pin_mux);
|
||||
configure_module_pin_mux(gpIOs);
|
||||
}
|
||||
Reference in New Issue
Block a user