GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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if TARGET_BRSMARC1
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config SYS_BOARD
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default "brsmarc1"
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config SYS_VENDOR
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default "BuR"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "brsmarc1"
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endif
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@@ -0,0 +1,6 @@
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BRSMARC1 BOARD
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M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
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S: Maintained
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F: board/BuR/brsmarc1/
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F: include/configs/brsmarc1.h
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F: configs/brsmarc1_defconfig
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@@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
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# B&R Industrial Automation GmbH - http://www.br-automation.com/
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#
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obj-$(CONFIG_SPL_BUILD) += mux.o
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obj-y += ../common/br_resetc.o
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obj-y += ../common/common.o
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obj-y += board.o
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@@ -0,0 +1,169 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for B&R BRSMARC1 Board
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*
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* Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/emif.h>
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#include <power/tps65217.h>
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#include "../common/bur_common.h"
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#include "../common/br_resetc.h"
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/* -------------------------------------------------------------------------*/
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/* -- defines for used GPIO Hardware -- */
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#define PER_RESET (2 * 32 + 0)
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SPL_BUILD)
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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static const struct ctrl_ioregs ddr3_ioregs = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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#define OSC (V_OSCK / 1000000)
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const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
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struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
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int rc;
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/*
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* enable additional clocks of modules which are accessed later from
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* VxWorks OS
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*/
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u32 *const clk_domains[] = { 0 };
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u32 *const clk_modules_specific[] = {
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&cmwkup->wkup_adctscctrl,
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&cmper->spi1clkctrl,
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&cmper->dcan0clkctrl,
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&cmper->dcan1clkctrl,
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&cmper->timer4clkctrl,
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&cmper->timer5clkctrl,
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&cmper->lcdclkctrl,
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&cmper->lcdcclkstctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_specific, 1);
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/* setup I2C */
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enable_i2c_pin_mux();
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/* peripheral reset */
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rc = gpio_request(PER_RESET, "PER_RESET");
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if (rc != 0)
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printf("cannot request PER_RESET GPIO!\n");
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rc = gpio_direction_output(PER_RESET, 0);
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if (rc != 0)
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printf("cannot set PER_RESET GPIO!\n");
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/* setup pmic */
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pmicsetup(0, 0);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr3;
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}
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void sdram_init(void)
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{
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config_ddr(400, &ddr3_ioregs,
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&ddr3_data,
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&ddr3_cmd_ctrl_data,
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&ddr3_emif_reg_data, 0);
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}
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#endif /* CONFIG_SPL_BUILD */
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#if !defined(CONFIG_SPL_BUILD)
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/* decision if backlight is switched on or not on powerup */
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int board_backlightstate(void)
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{
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u8 bklmask, rstcause;
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int rc = 0;
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rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
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rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
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if (rc != 0) {
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printf("%s: read rstctrl failed!\n", __func__);
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return 1;
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}
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if ((rstcause & bklmask) != 0)
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return 0;
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return 1;
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}
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/* Basic board specific setup. run quite after relocation */
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int board_init(void)
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{
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if (power_tps65217_init(0))
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printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
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return 0;
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}
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#if defined(CONFIG_BOARD_LATE_INIT)
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int board_late_init(void)
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{
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br_resetc_bmode();
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return 0;
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}
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#endif /* CONFIG_BOARD_LATE_INIT */
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#endif /* !CONFIG_SPL_BUILD */
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@@ -0,0 +1,33 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
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# B&R Industrial Automation GmbH - http://www.br-automation.com
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#
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hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
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payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
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quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
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cmd_prodbin = \
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dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
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dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
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dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
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quiet_cmd_prodzip = SAPZIP $@
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cmd_prodzip = \
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test -d misc && rm -r misc; \
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mkdir misc && \
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cp MLO.byteswap misc/ && \
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cp spl/u-boot-spl.bin misc/ && \
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cp u-boot-dtb.img misc/ && \
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zip -9 -r $@ misc/* >/dev/null $<
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ALL-y += $(hw-platform-y)_prog.bin
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ALL-y += $(hw-platform-y)_prod.zip
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$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
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$(call if_changed,prodbin)
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$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
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$(call if_changed,prodzip)
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@@ -0,0 +1,266 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* mux.c
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*
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* Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
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*
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* Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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*
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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static struct module_pin_mux spi0_pin_mux[] = {
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/* SPI0_SCLK */
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{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
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/* SPI0_D0 */
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{OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
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/* SPI0_D1 */
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{OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
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/* SPI0_CS0 */
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{OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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/* SPI0_CS1 */
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{OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux spi1_pin_mux[] = {
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/* SPI1_SCLK */
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{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
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/* SPI1_D0 */
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{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
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/* SPI1_D1 */
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{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
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/* SPI1_CS0 */
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{OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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/* SPI1_CS1 */
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{OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux dcan0_pin_mux[] = {
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/* DCAN0 TX */
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{OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
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/* DCAN0 RX */
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{OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux dcan1_pin_mux[] = {
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/* DCAN1 TX */
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{OFFSET(uart0_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
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/* DCAN1 RX */
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{OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux gpios[] = {
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/* GPIO0_7 - LVDS_EN */
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO0_20 - BKLT_PWM (timer7) */
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{OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO2_4 - DISON */
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{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO1_24 - RGB_EN */
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{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO1_28 - nPD */
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{OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
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/* GPIO2_5 - Watchdog */
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{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO2_0 - ResetOut */
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{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
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/* GPIO2_2 - BKLT_EN */
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{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
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/* GPIO1_17 - GPIO0 */
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{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_18 - GPIO1 */
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{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_19 - GPIO2 */
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{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_22 - GPIO3 */
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{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_23 - GPIO4 */
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{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_25 - GPIO5 */
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{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_7 - GPIO6 */
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{OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_8 - GPIO7 */
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{OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_18 - GPIO8 */
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{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_19 - GPIO9 */
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{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_20 - GPIO10 */
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{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_21 - GPIO11 */
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{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO2_28 - DRAM-strapping */
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{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
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/* GPIO2_4 - not routed (Pin U6) */
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{OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO2_5 - not routed (Pin T6) */
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{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO2_28 - not routed (Pin G15) */
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{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO3_18 - not routed (Pin B12) */
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{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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{-1},
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};
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static struct module_pin_mux uart0_pin_mux[] = {
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/* UART0_RXD */
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{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART0_TXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
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{-1},
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};
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static struct module_pin_mux uart234_pin_mux[] = {
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/* UART2_RXD */
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{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART2_TXD */
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{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
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/* UART3_RXD */
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{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART3_TXD */
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{OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
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/* UART3_RTS */
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{OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
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/* UART3_CTS */
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{OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART4_RXD */
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{OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART4_TXD */
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{OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
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/* UART4_RTS */
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{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
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/* UART4_CTS */
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{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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{-1},
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};
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static struct module_pin_mux i2c_pin_mux[] = {
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/* I2C0_DATA */
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C0_SCLK */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C1_DATA */
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{OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C1_SCLK */
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{OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux eth_pin_mux[] = {
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/* ETH1 */
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{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* ETH1_REFCLK */
|
||||
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRSDV */
|
||||
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXER */
|
||||
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
|
||||
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
|
||||
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
|
||||
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
|
||||
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
|
||||
|
||||
/* ETH2 */
|
||||
{OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* ETH2_REFCLK */
|
||||
{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRSDV */
|
||||
{OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXER */
|
||||
{OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
|
||||
{OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
|
||||
{OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
|
||||
{OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
|
||||
{OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
|
||||
|
||||
/* gpio2_19, gpio 3_4, not connected on board */
|
||||
{OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
|
||||
{OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
|
||||
|
||||
/* ETH Management */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc1_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
|
||||
{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
|
||||
{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
|
||||
{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
|
||||
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
|
||||
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
|
||||
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
|
||||
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
|
||||
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
|
||||
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux lcd_pin_mux[] = {
|
||||
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
|
||||
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
|
||||
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
|
||||
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
|
||||
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
|
||||
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
|
||||
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
|
||||
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
|
||||
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
|
||||
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
|
||||
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
|
||||
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
|
||||
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
|
||||
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
|
||||
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
|
||||
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
|
||||
|
||||
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
|
||||
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
|
||||
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
|
||||
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
|
||||
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
|
||||
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
|
||||
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
|
||||
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
|
||||
|
||||
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
|
||||
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
|
||||
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
|
||||
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
|
||||
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c_pin_mux);
|
||||
}
|
||||
|
||||
void enable_board_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(eth_pin_mux);
|
||||
configure_module_pin_mux(spi0_pin_mux);
|
||||
configure_module_pin_mux(spi1_pin_mux);
|
||||
configure_module_pin_mux(dcan0_pin_mux);
|
||||
configure_module_pin_mux(dcan1_pin_mux);
|
||||
configure_module_pin_mux(uart234_pin_mux);
|
||||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
configure_module_pin_mux(lcd_pin_mux);
|
||||
configure_module_pin_mux(gpios);
|
||||
}
|
||||
Reference in New Issue
Block a user