GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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if TARGET_BRXRE1
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config SYS_BOARD
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default "brxre1"
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config SYS_VENDOR
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default "BuR"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "brxre1"
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endif
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@@ -0,0 +1,7 @@
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BRXRE1 BOARD
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M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
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S: Maintained
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F: board/BuR/brxre1/
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F: include/configs/brxre1.h
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F: configs/brxre1_defconfig
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F: arch/arm/dts/am335x-brxre1.dts
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@@ -0,0 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Makefile
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#
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# Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> -
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# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
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obj-$(CONFIG_SPL_BUILD) += mux.o
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obj-y += ../common/br_resetc.o
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obj-y += ../common/common.o
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obj-y += board.o
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@@ -0,0 +1,182 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for B&R BRXRE1 Board
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*
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* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <dm.h>
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#include <power/tps65217.h>
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#include "../common/bur_common.h"
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#include "../common/br_resetc.h"
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/* -------------------------------------------------------------------------*/
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/* -- defines for used GPIO Hardware -- */
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#define ESC_KEY (0 + 19)
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#define LCD_PWR (0 + 5)
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#define RSTCTRL_FORCE_PWR_NEN 0x04
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#define RSTCTRL_CAN_STB 0x40
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SPL_BUILD)
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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static const struct ctrl_ioregs ddr3_ioregs = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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#define OSC (V_OSCK / 1000000)
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const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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int rc;
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
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struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
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/*
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* enable additional clocks of modules which are accessed later from
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* VxWorks OS
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*/
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u32 *const clk_domains[] = { 0 };
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u32 *const clk_modules_xre1specific[] = {
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&cmwkup->wkup_adctscctrl,
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&cmper->spi1clkctrl,
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&cmper->dcan0clkctrl,
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&cmper->dcan1clkctrl,
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&cmper->epwmss0clkctrl,
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&cmper->epwmss1clkctrl,
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&cmper->epwmss2clkctrl,
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&cmper->lcdclkctrl,
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&cmper->lcdcclkstctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
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/* power-OFF LCD-Display */
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if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
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printf("cannot request gpio for LCD_PWR!\n");
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else if (gpio_direction_output(LCD_PWR, 0) != 0)
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printf("cannot set direction output on LCD_PWR!\n");
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/* setup I2C */
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enable_i2c_pin_mux();
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/* power-ON 3V3 via Resetcontroller */
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rc = br_resetc_regset(RSTCTRL_CTRLREG,
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RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB);
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if (rc != 0)
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printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");
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pmicsetup(0, 0);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr3;
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}
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void sdram_init(void)
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{
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config_ddr(400, &ddr3_ioregs,
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&ddr3_data,
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&ddr3_cmd_ctrl_data,
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&ddr3_emif_reg_data, 0);
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}
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#endif /* CONFIG_SPL_BUILD */
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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/* request common used gpios */
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gpio_request(ESC_KEY, "boot-key");
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if (power_tps65217_init(0))
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printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_boot_key(void)
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{
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return gpio_get_value(ESC_KEY);
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}
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int board_late_init(void)
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{
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char othbootargs[128];
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br_resetc_bmode();
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/* setup othbootargs for bootvx-command (vxWorks bootline) */
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snprintf(othbootargs, sizeof(othbootargs),
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"u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
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(u32)gd->fb_base - 0x20,
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(u32)env_get_ulong("vx_memtop", 16, gd->fb_base - 0x20),
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(u32)env_get_ulong("vx_romfsbase", 16, 0),
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(u32)env_get_ulong("vx_romfssize", 16, 0));
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env_set("othbootargs", othbootargs);
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/*
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* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
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* expect that vectors are there, original u-boot moves them to _start
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*/
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__asm__("ldr r0,=0x20000");
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__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
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return 0;
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}
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#endif /* CONFIG_BOARD_LATE_INIT */
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@@ -0,0 +1,197 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* mux.c
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*
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* Pinmux Setting for B&R LEIT Board(s)
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*
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* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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static struct module_pin_mux spi0_pin_mux[] = {
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/* SPI1_SCLK */
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{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
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/* SPI1_D0 */
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{OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
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/* SPI1_D1 */
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{OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
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/* SPI1_CS0 */
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{OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
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/* SPI1_CS1 */
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{OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux dcan0_pin_mux[] = {
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/* DCAN0 TX */
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{OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
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/* DCAN0 RX */
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{OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux dcan1_pin_mux[] = {
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/* DCAN1 TX */
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{OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
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/* DCAN1 RX */
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{OFFSET(uart1_txd), MODE(2) | RXACTIVE},
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{-1},
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};
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static struct module_pin_mux gpios[] = {
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/* GPIO0_7 (PWW0 OUT) - CAN TERM */
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO0_19 (DMA_INTR0) - TA602 */
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{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
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{OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
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{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
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/* GPIO0_30 (GPMC_WAIT0) - TA601 */
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{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
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{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
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/* GPIO1_29 (gpmc_csn0) - MMC nRST */
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{OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
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/* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
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{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
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/* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
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{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO2_4 (GPMC_nWE) - TST_BAST */
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{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
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/* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */
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{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
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/* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
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{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
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{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
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{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
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{OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
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/* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
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{OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
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{-1},
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};
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static struct module_pin_mux uart0_pin_mux[] = {
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/* UART0_CTS */
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{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART0_RXD */
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{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART0_TXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
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{-1},
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};
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static struct module_pin_mux i2c0_pin_mux[] = {
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/* I2C_DATA */
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C_SCLK */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux mii1_pin_mux[] = {
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{OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
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{OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
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{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
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{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
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{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
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{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
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{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
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{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
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{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
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{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
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{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
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{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
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{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
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{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux mmc1_pin_mux[] = {
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{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
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{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
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{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
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{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
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{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
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{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
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{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
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{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
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{-1},
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};
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static struct module_pin_mux lcd_pin_mux[] = {
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{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
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{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
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{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
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{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
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{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
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{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
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{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
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{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
|
||||
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
|
||||
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
|
||||
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
|
||||
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
|
||||
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
|
||||
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
|
||||
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
|
||||
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
|
||||
|
||||
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
|
||||
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
|
||||
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
|
||||
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
|
||||
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
|
||||
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
|
||||
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
|
||||
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
|
||||
|
||||
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
|
||||
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
|
||||
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
|
||||
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
|
||||
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_board_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(spi0_pin_mux);
|
||||
configure_module_pin_mux(dcan0_pin_mux);
|
||||
configure_module_pin_mux(dcan1_pin_mux);
|
||||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
configure_module_pin_mux(lcd_pin_mux);
|
||||
configure_module_pin_mux(gpios);
|
||||
}
|
||||
Reference in New Issue
Block a user