GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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*/
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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#define MII_MARVELL_PHY_PAGE 22
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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void mv_phy_88e1116_init(const char *name, u16 phyaddr)
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{
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u16 reg;
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if (miiphy_set_current_dev(name))
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return;
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
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if (miiphy_reset(name, phyaddr) == 0)
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printf("88E1116 Initialized on %s\n", name);
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}
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void mv_phy_88e1318_init(const char *name, u16 phyaddr)
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{
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u16 reg;
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if (miiphy_set_current_dev(name))
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return;
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/*
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* Set control mode 4 for LED[0].
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*/
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
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miiphy_read(name, phyaddr, 16, ®);
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reg |= 0xf;
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miiphy_write(name, phyaddr, 16, reg);
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
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if (miiphy_reset(name, phyaddr) == 0)
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printf("88E1318 Initialized on %s\n", name);
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}
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#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
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#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
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int lacie_read_mac_address(uchar *mac_addr)
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{
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int ret;
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ushort version;
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/* I2C-0 for on-board EEPROM */
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i2c_set_bus_num(0);
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/* Check layout version for EEPROM data */
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
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(uchar *) &version, 2);
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if (ret != 0) {
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printf("Error: failed to read I2C EEPROM @%02x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return ret;
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}
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version = be16_to_cpu(version);
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if (version < 1 || version > 3) {
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printf("Error: unknown version %d for EEPROM data\n",
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version);
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return -1;
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}
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/* Read Ethernet MAC address from EEPROM */
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
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if (ret != 0)
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printf("Error: failed to read I2C EEPROM @%02x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return ret;
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}
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#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */
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@@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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*/
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#ifndef _LACIE_COMMON_H
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#define _LACIE_COMMON_H
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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void mv_phy_88e1116_init(const char *name, u16 phyaddr);
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void mv_phy_88e1318_init(const char *name, u16 phyaddr);
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#endif
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#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
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int lacie_read_mac_address(uchar *mac);
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#endif
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#endif /* _LACIE_COMMON_H */
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@@ -0,0 +1,46 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* cpld-gpio-bus.c: provides support for the CPLD GPIO bus found on some LaCie
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* boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO
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* bus exposes two registers (address and data). Each of this register is made
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* up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that
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* the registers have been updated.
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*
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* Mostly this bus is used to configure the LEDs on LaCie boards.
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*
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* Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
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*/
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#include <asm/arch/gpio.h>
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#include "cpld-gpio-bus.h"
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static void cpld_gpio_bus_set_addr(struct cpld_gpio_bus *bus, unsigned addr)
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{
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int pin;
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for (pin = 0; pin < bus->num_addr; pin++)
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kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1);
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}
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static void cpld_gpio_bus_set_data(struct cpld_gpio_bus *bus, unsigned data)
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{
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int pin;
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for (pin = 0; pin < bus->num_data; pin++)
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kw_gpio_set_value(bus->data[pin], (data >> pin) & 1);
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}
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static void cpld_gpio_bus_enable_select(struct cpld_gpio_bus *bus)
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{
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/* The transfer is enabled on the raising edge. */
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kw_gpio_set_value(bus->enable, 0);
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kw_gpio_set_value(bus->enable, 1);
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}
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void cpld_gpio_bus_write(struct cpld_gpio_bus *bus,
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unsigned addr, unsigned value)
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{
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cpld_gpio_bus_set_addr(bus, addr);
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cpld_gpio_bus_set_data(bus, value);
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cpld_gpio_bus_enable_select(bus);
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}
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@@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
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*/
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#ifndef _LACIE_CPLD_GPI0_BUS_H
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#define _LACIE_CPLD_GPI0_BUS_H
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struct cpld_gpio_bus {
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unsigned *addr;
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unsigned num_addr;
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unsigned *data;
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unsigned num_data;
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unsigned enable;
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};
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void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus,
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unsigned addr, unsigned value);
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#endif /* _LACIE_CPLD_GPI0_BUS_H */
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@@ -0,0 +1,12 @@
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if TARGET_EDMINIV2
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config SYS_BOARD
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default "edminiv2"
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config SYS_VENDOR
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default "LaCie"
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config SYS_CONFIG_NAME
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default "edminiv2"
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endif
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@@ -0,0 +1,6 @@
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EDMINIV2 BOARD
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M: Albert ARIBAUD <albert.u.boot@aribaud.net>
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S: Maintained
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F: board/LaCie/edminiv2/
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F: include/configs/edminiv2.h
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F: configs/edminiv2_defconfig
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@@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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#
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# Based on original Kirkwood support which is
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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obj-y := edminiv2.o ../common/common.o
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@@ -0,0 +1,55 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/orion5x.h>
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#include "../common/common.h"
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#include <spl.h>
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#include <ns16550.h>
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#include <asm/mach-types.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* arch number of board */
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gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
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/* boot parameter start at 256th byte of RAM base */
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gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
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return 0;
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}
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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/* Configure and enable MV88E1116 PHY */
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void reset_phy(void)
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{
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mv_phy_88e1116_init("egiga0", 8);
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}
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#endif /* CONFIG_RESET_PHY_R */
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/*
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* SPL serial setup and NOR boot device selection
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*/
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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preloader_console_init();
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_NOR;
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}
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#endif /* CONFIG_SPL_BUILD */
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@@ -0,0 +1,12 @@
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if TARGET_NET2BIG_V2
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config SYS_BOARD
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default "net2big_v2"
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config SYS_VENDOR
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default "LaCie"
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config SYS_CONFIG_NAME
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default "lacie_kw"
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endif
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@@ -0,0 +1,7 @@
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NET2BIG_V2 BOARD
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M: Simon Guinot <simon.guinot@sequanux.org>
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S: Maintained
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F: board/LaCie/net2big_v2/
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F: include/configs/lacie_kw.h
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F: configs/d2net_v2_defconfig
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F: configs/net2big_v2_defconfig
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@@ -0,0 +1,13 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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#
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# Based on Kirkwood support:
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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obj-y := net2big_v2.o ../common/common.o
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ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
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obj-y += ../common/cpld-gpio-bus.o
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endif
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@@ -0,0 +1,149 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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#
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# Based on Kirkwood support:
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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# Refer doc/README.kwbimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM spi # Boot from SPI flash
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xFFD100e0 0x1B1B1B9B
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xFFD01400 0x43000C30 # DDR Configuration register
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# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
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# bit23-14: zero
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# bit24: 1= enable exit self refresh mode on DDR access
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# bit25: 1 required
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# bit29-26: zero
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# bit31-30: 01
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DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
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# bit 4: 0=addr/cmd in smame cycle
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# bit 5: 0=clk is driven during self refresh, we don't care for APX
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# bit 6: 0=use recommended falling edge of clk for addr/cmd
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# bit14: 0=input buffer always powered up
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# bit18: 1=cpu lock transaction enabled
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# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 3 required
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# bit31: 0=no additional STARTBURST delay
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DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
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# bit7-4: TRCD
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# bit11- 8: TRP
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# bit15-12: TWR
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# bit19-16: TWTR
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# bit20: TRAS msb
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# bit23-21: 0x0
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# bit27-24: TRRD
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# bit31-28: TRTP
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DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
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# bit6-0: TRFC
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# bit8-7: TR2R
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# bit10-9: TR2W
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# bit12-11: TW2W
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# bit31-13: zero required
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DATA 0xFFD01410 0x0000CCCC # DDR Address Control
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# bit1-0: 01, Cs0width=x16
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# bit3-2: 11, Cs0size=1Gb
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# bit5-4: 00, Cs2width=nonexistent
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# bit7-6: 00, Cs1size =nonexistent
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# bit9-8: 00, Cs2width=nonexistent
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# bit11-10: 00, Cs2size =nonexistent
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# bit13-12: 00, Cs3width=nonexistent
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# bit15-14: 00, Cs3size =nonexistent
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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# bit19: 0, Cs3AddrSel
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# bit31-20: 0 required
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
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# bit0: 0, OpenPage enabled
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# bit31-1: 0 required
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DATA 0xFFD01418 0x00000000 # DDR Operation
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# bit3-0: 0x0, DDR cmd
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# bit31-4: 0 required
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DATA 0xFFD0141C 0x00000662 # DDR Mode
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# bit2-0: 2, BurstLen=2 required
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# bit3: 0, BurstType=0 required
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# bit6-4: 4, CL=5
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# bit7: 0, TestMode=0 normal
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# bit8: 0, DLL reset=0 normal
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# bit11-9: 6, auto-precharge write recovery ????????????
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# bit12: 0, PD must be zero
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# bit31-13: 0 required
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DATA 0xFFD01420 0x00000044 # DDR Extended Mode
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# bit0: 0, DDR DLL enabled
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# bit1: 1, DDR drive strenght reduced
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# bit2: 1, DDR ODT control lsd enabled
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# bit5-3: 000, required
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# bit6: 1, DDR ODT control msb, enabled
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# bit9-7: 000, required
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# bit10: 0, differential DQS enabled
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# bit11: 0, required
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# bit12: 0, DDR output buffer enabled
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# bit31-13: 0 required
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DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
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# bit2-0: 111, required
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# bit3 : 1 , MBUS Burst Chop disabled
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# bit6-4: 111, required
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# bit7 : 1 , D2P Latency enabled
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# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
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# bit9 : 0 , no half clock cycle addition to dataout
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# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
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# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
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# bit15-12: 1111 required
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# bit31-16: 0 required
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DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
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DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
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DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
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# bit0: 1, Window enabled
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# bit1: 0, Write Protect disabled
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# bit3-2: 00, CS0 hit selected
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||||
# bit23-4: ones, required
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||||
# bit31-24: 0x07, Size (i.e. 128MB)
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||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
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||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit11-10:1, DQ_ODTSel. ODT select turned on
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,254 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
*
|
||||
* Based on Kirkwood support:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <env.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
#include "net2big_v2.h"
|
||||
#include "../common/common.h"
|
||||
#include "../common/cpld-gpio-bus.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* GPIO configuration */
|
||||
mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
|
||||
NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
static const u32 kwmpp_config[] = {
|
||||
MPP0_SPI_SCn,
|
||||
MPP1_SPI_MOSI,
|
||||
MPP2_SPI_SCK,
|
||||
MPP3_SPI_MISO,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO, /* Request power-off */
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP13_GPIO, /* Rear power switch (on|auto) */
|
||||
MPP14_GPIO, /* USB fuse alarm */
|
||||
MPP15_GPIO, /* Rear power switch (auto|off) */
|
||||
MPP16_GPIO, /* SATA HDD1 power */
|
||||
MPP17_GPIO, /* SATA HDD2 power */
|
||||
MPP20_SATA1_ACTn,
|
||||
MPP21_SATA0_ACTn,
|
||||
MPP24_GPIO, /* USB mode select */
|
||||
MPP26_GPIO, /* USB device vbus */
|
||||
MPP28_GPIO, /* USB enable host vbus */
|
||||
MPP29_GPIO, /* CPLD GPIO bus ALE */
|
||||
MPP34_GPIO, /* Rear Push button 0=on 1=off */
|
||||
MPP35_GPIO, /* Inhibit switch power-off */
|
||||
MPP36_GPIO, /* SATA HDD1 presence */
|
||||
MPP37_GPIO, /* SATA HDD2 presence */
|
||||
MPP40_GPIO, /* eSATA presence */
|
||||
MPP44_GPIO, /* CPLD GPIO bus (data 0) */
|
||||
MPP45_GPIO, /* CPLD GPIO bus (data 1) */
|
||||
MPP46_GPIO, /* CPLD GPIO bus (data 2) */
|
||||
MPP47_GPIO, /* CPLD GPIO bus (addr 0) */
|
||||
MPP48_GPIO, /* CPLD GPIO bus (addr 1) */
|
||||
MPP49_GPIO, /* CPLD GPIO bus (addr 2) */
|
||||
0
|
||||
};
|
||||
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Machine number */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
|
||||
|
||||
/* Boot parameters address */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MISC_INIT_R)
|
||||
|
||||
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
|
||||
/*
|
||||
* Start I2C fan (GMT G762 controller)
|
||||
*/
|
||||
static void init_fan(void)
|
||||
{
|
||||
u8 data;
|
||||
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
/* Enable open-loop and PWM modes */
|
||||
data = 0x20;
|
||||
if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
|
||||
G762_REG_FAN_CMD1, 1, &data, 1) != 0)
|
||||
goto err;
|
||||
data = 0;
|
||||
if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
|
||||
G762_REG_SET_CNT, 1, &data, 1) != 0)
|
||||
goto err;
|
||||
/*
|
||||
* RPM to PWM (set_out register) fan speed conversion array:
|
||||
* 0 0x00
|
||||
* 1500 0x04
|
||||
* 2800 0x08
|
||||
* 3400 0x0C
|
||||
* 3700 0x10
|
||||
* 4400 0x20
|
||||
* 4700 0x30
|
||||
* 4800 0x50
|
||||
* 5200 0x80
|
||||
* 5400 0xC0
|
||||
* 5500 0xFF
|
||||
*
|
||||
* Start fan at low speed (2800 RPM):
|
||||
*/
|
||||
data = 0x08;
|
||||
if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
|
||||
G762_REG_SET_OUT, 1, &data, 1) != 0)
|
||||
goto err;
|
||||
|
||||
return;
|
||||
err:
|
||||
printf("Error: failed to start I2C fan @%02x\n",
|
||||
CONFIG_SYS_I2C_G762_ADDR);
|
||||
}
|
||||
#else
|
||||
static void init_fan(void) {}
|
||||
#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
|
||||
|
||||
#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
|
||||
/*
|
||||
* CPLD GPIO bus:
|
||||
*
|
||||
* - address register : bit [0-2] -> GPIO [47-49]
|
||||
* - data register : bit [0-2] -> GPIO [44-46]
|
||||
* - enable register : GPIO 29
|
||||
*/
|
||||
static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
|
||||
static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
|
||||
|
||||
static struct cpld_gpio_bus cpld_gpio_bus = {
|
||||
.addr = cpld_gpio_bus_addr,
|
||||
.num_addr = ARRAY_SIZE(cpld_gpio_bus_addr),
|
||||
.data = cpld_gpio_bus_data,
|
||||
.num_data = ARRAY_SIZE(cpld_gpio_bus_data),
|
||||
.enable = 29,
|
||||
};
|
||||
|
||||
/*
|
||||
* LEDs configuration:
|
||||
*
|
||||
* The LEDs are controlled by a CPLD and can be configured through
|
||||
* the CPLD GPIO bus.
|
||||
*
|
||||
* Address register selection:
|
||||
*
|
||||
* addr | register
|
||||
* ----------------------------
|
||||
* 0 | front LED
|
||||
* 1 | front LED brightness
|
||||
* 2 | SATA LED brightness
|
||||
* 3 | SATA0 LED
|
||||
* 4 | SATA1 LED
|
||||
* 5 | SATA2 LED
|
||||
* 6 | SATA3 LED
|
||||
* 7 | SATA4 LED
|
||||
*
|
||||
* Data register configuration:
|
||||
*
|
||||
* data | LED brightness
|
||||
* -------------------------------------------------
|
||||
* 0 | min (off)
|
||||
* - | -
|
||||
* 7 | max
|
||||
*
|
||||
* data | front LED mode
|
||||
* -------------------------------------------------
|
||||
* 0 | fix off
|
||||
* 1 | fix blue on
|
||||
* 2 | fix red on
|
||||
* 3 | blink blue on=1 sec and blue off=1 sec
|
||||
* 4 | blink red on=1 sec and red off=1 sec
|
||||
* 5 | blink blue on=2.5 sec and red on=0.5 sec
|
||||
* 6 | blink blue on=1 sec and red on=1 sec
|
||||
* 7 | blink blue on=0.5 sec and blue off=2.5 sec
|
||||
*
|
||||
* data | SATA LED mode
|
||||
* -------------------------------------------------
|
||||
* 0 | fix off
|
||||
* 1 | SATA activity blink
|
||||
* 2 | fix red on
|
||||
* 3 | blink blue on=1 sec and blue off=1 sec
|
||||
* 4 | blink red on=1 sec and red off=1 sec
|
||||
* 5 | blink blue on=2.5 sec and red on=0.5 sec
|
||||
* 6 | blink blue on=1 sec and red on=1 sec
|
||||
* 7 | fix blue on
|
||||
*/
|
||||
static void init_leds(void)
|
||||
{
|
||||
/* Enable the front blue LED */
|
||||
cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
|
||||
cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
|
||||
|
||||
/* Configure SATA LEDs to blink in relation with the SATA activity */
|
||||
cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
|
||||
cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
|
||||
cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
|
||||
}
|
||||
#else
|
||||
static void init_leds(void) {}
|
||||
#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
init_fan();
|
||||
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
|
||||
if (!env_get("ethaddr")) {
|
||||
uchar mac[6];
|
||||
if (lacie_read_mac_address(mac) == 0)
|
||||
eth_env_set_enetaddr("ethaddr", mac);
|
||||
}
|
||||
#endif
|
||||
init_leds();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_MISC_INIT_R */
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
|
||||
/* Configure and initialize PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
mv_phy_88e1116_init("egiga0", 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KIRKWOOD_GPIO)
|
||||
/* Return GPIO push button status */
|
||||
static int
|
||||
do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(button, 1, 1, do_read_push_button,
|
||||
"Return GPIO push button status 0=off 1=on", "");
|
||||
#endif
|
||||
@@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
*
|
||||
* Based on Kirkwood support:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef NET2BIG_V2_H
|
||||
#define NET2BIG_V2_H
|
||||
|
||||
/* GPIO configuration */
|
||||
#define NET2BIG_V2_OE_LOW 0x0600E000
|
||||
#define NET2BIG_V2_OE_HIGH 0x00000134
|
||||
#define NET2BIG_V2_OE_VAL_LOW 0x10030000
|
||||
#define NET2BIG_V2_OE_VAL_HIGH 0x00000000
|
||||
|
||||
/* Buttons */
|
||||
#define NET2BIG_V2_GPIO_PUSH_BUTTON 34
|
||||
|
||||
/* GMT G762 registers (I2C fan controller) */
|
||||
#define G762_REG_SET_CNT 0x00
|
||||
#define G762_REG_SET_OUT 0x03
|
||||
#define G762_REG_FAN_CMD1 0x04
|
||||
|
||||
#endif /* NET2BIG_V2_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_NETSPACE_V2
|
||||
|
||||
config SYS_BOARD
|
||||
default "netspace_v2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "LaCie"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "lacie_kw"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,14 @@
|
||||
NETSPACE_V2 BOARD
|
||||
M: Simon Guinot <simon.guinot@sequanux.org>
|
||||
S: Maintained
|
||||
F: board/LaCie/netspace_v2/
|
||||
F: include/configs/lacie_kw.h
|
||||
F: configs/inetspace_v2_defconfig
|
||||
F: configs/netspace_max_v2_defconfig
|
||||
F: configs/netspace_v2_defconfig
|
||||
|
||||
NETSPACE_LITE_V2 BOARD
|
||||
#M: -
|
||||
S: Maintained
|
||||
F: configs/netspace_lite_v2_defconfig
|
||||
F: configs/netspace_mini_v2_defconfig
|
||||
@@ -0,0 +1,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
#
|
||||
# Based on Kirkwood support:
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
|
||||
obj-y := netspace_v2.o ../common/common.o
|
||||
@@ -0,0 +1,149 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
#
|
||||
# Based on Kirkwood support:
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
# Refer doc/README.kwbimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1B1B1B9B
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000618 # DDR Configuration register
|
||||
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x00000008 # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
||||
# bit3-2: 10, Cs0size=512Mb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000632 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000004 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strenght reduced
|
||||
# bit2: 1, DDR ODT control lsd enabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, enabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 1 , D2P Latency enabled
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit11-10:1, DQ_ODTSel. ODT select turned on
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,149 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
#
|
||||
# Based on Kirkwood support:
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
# Refer doc/README.kwbimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1B1B1B9B
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000618 # DDR Configuration register
|
||||
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x0000DDDD # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
||||
# bit3-2: 10, Cs0size=512Mb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000632 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000004 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strenght reduced
|
||||
# bit2: 1, DDR ODT control lsd enabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, enabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 1 , D2P Latency enabled
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit11-10:1, DQ_ODTSel. ODT select turned on
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,149 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
#
|
||||
# Based on Kirkwood support:
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
# Refer doc/README.kwbimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi # Boot from SPI flash
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1B1B1B9B
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000618 # DDR Configuration register
|
||||
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x0000000C # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
||||
# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs2width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000632 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000004 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strenght reduced
|
||||
# bit2: 1, DDR ODT control lsd enabled
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, enabled
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 1 , D2P Latency enabled
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
|
||||
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
||||
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
|
||||
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
|
||||
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
|
||||
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
||||
# bit11-10:1, DQ_ODTSel. ODT select turned on
|
||||
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,118 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
*
|
||||
* Based on Kirkwood support:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <env.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
#include "netspace_v2.h"
|
||||
#include "../common/common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Gpio configuration */
|
||||
mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
|
||||
NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
static const u32 kwmpp_config[] = {
|
||||
MPP0_SPI_SCn,
|
||||
MPP1_SPI_MOSI,
|
||||
MPP2_SPI_SCK,
|
||||
MPP3_SPI_MISO,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO, /* Fan speed (bit 1) */
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_GPO, /* Red led */
|
||||
MPP14_GPIO, /* USB fuse */
|
||||
MPP16_GPIO, /* SATA 0 power */
|
||||
MPP17_GPIO, /* SATA 1 power */
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_SATA1_ACTn,
|
||||
MPP21_SATA0_ACTn,
|
||||
MPP22_GPIO, /* Fan speed (bit 0) */
|
||||
MPP23_GPIO, /* Fan power */
|
||||
MPP24_GPIO, /* USB mode select */
|
||||
MPP25_GPIO, /* Fan rotation fail */
|
||||
MPP26_GPIO, /* USB vbus-in detection */
|
||||
MPP28_GPIO, /* USB enable vbus-out */
|
||||
MPP29_GPIO, /* Blue led (slow register) */
|
||||
MPP30_GPIO, /* Blue led (command register) */
|
||||
MPP31_GPIO, /* Board power off */
|
||||
MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
|
||||
MPP33_GPIO, /* Fan speed (bit 2) */
|
||||
0
|
||||
};
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Machine number */
|
||||
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
|
||||
|
||||
/* Boot parameters address */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MISC_INIT_R)
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
|
||||
if (!env_get("ethaddr")) {
|
||||
uchar mac[6];
|
||||
if (lacie_read_mac_address(mac) == 0)
|
||||
eth_env_set_enetaddr("ethaddr", mac);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
|
||||
/* Configure and initialize PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
|
||||
mv_phy_88e1318_init("egiga0", 0);
|
||||
#else
|
||||
mv_phy_88e1116_init("egiga0", 8);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KIRKWOOD_GPIO)
|
||||
/* Return GPIO button status */
|
||||
static int
|
||||
do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(button, 1, 1, do_read_button,
|
||||
"Return GPIO button status 0=off 1=on", "");
|
||||
#endif
|
||||
@@ -0,0 +1,22 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
|
||||
*
|
||||
* Based on Kirkwood support:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef NETSPACE_V2_H
|
||||
#define NETSPACE_V2_H
|
||||
|
||||
/* GPIO configuration */
|
||||
#define NETSPACE_V2_OE_LOW 0x06004000
|
||||
#define NETSPACE_V2_OE_HIGH 0x00000031
|
||||
#define NETSPACE_V2_OE_VAL_LOW 0x10030000
|
||||
#define NETSPACE_V2_OE_VAL_HIGH 0x00000000
|
||||
|
||||
#define NETSPACE_V2_GPIO_BUTTON 32
|
||||
|
||||
#endif /* NETSPACE_V2_H */
|
||||
Reference in New Issue
Block a user