GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,15 @@
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if TARGET_ASPENITE
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config SYS_BOARD
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default "aspenite"
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config SYS_VENDOR
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default "Marvell"
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config SYS_SOC
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default "armada100"
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config SYS_CONFIG_NAME
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default "aspenite"
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endif
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@@ -0,0 +1,6 @@
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ASPENITE BOARD
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M: Prafulla Wadaskar <prafulla@marvell.com>
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S: Maintained
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F: board/Marvell/aspenite/
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F: include/configs/aspenite.h
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F: configs/aspenite_defconfig
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@@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2010
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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# Contributor: Mahavir Jain <mjain@marvell.com>
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obj-y := aspenite.o
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@@ -0,0 +1,43 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*/
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#include <common.h>
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#include <mvmfp.h>
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#include <asm/mach-types.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mfp.h>
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#include <asm/arch/armada100.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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u32 mfp_cfg[] = {
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/* I2C */
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MFP105_CI2C_SDA,
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MFP106_CI2C_SCL,
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/* Enable Console on UART1 */
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MFP107_UART1_RXD,
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MFP108_UART1_TXD,
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MFP_EOC /*End of configureation*/
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};
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/* configure MFP's */
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mfp_config(mfp_cfg);
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return 0;
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}
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int board_init(void)
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{
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/* arch number of Board */
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gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
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return 0;
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}
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@@ -0,0 +1,12 @@
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if TARGET_DB_88F6281_BP
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config SYS_BOARD
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default "db-88f6281-bp"
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config SYS_VENDOR
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default "Marvell"
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config SYS_CONFIG_NAME
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default "db-88f6281-bp"
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endif
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@@ -0,0 +1,10 @@
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DB_88F6820_AMC BOARD
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M: Chris Packham <judge.packham@gmail.com>
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S: Maintained
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F: arch/arm/dts/kirkwood-db-88f6281.dts
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F: arch/arm/dts/kirkwood-db-88f6281-spi.dts
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F: arch/arm/dts/kirkwood-db.dtsi
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F: board/Marvell/db-88f6281-bp/
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F: include/configs/db-88f6281-bp.h
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F: configs/db-88f6281-bp-nand_defconfig
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F: configs/db-88f6281-bp-spi_defconfig
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@@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-y := db-88f6281-bp.o
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extra-y := kwbimage.cfg
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quiet_cmd_sed = SED $@
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cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
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SEDFLAGS_kwbimage.cfg = -e "s/^\#@BOOT_FROM.*/BOOT_FROM $(if $(CONFIG_CMD_NAND),nand,spi)/"
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$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
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include/config/auto.conf
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$(call if_changed,sed)
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@@ -0,0 +1,103 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <linux/io.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/gpio.h>
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#define DB_88F6281_OE_LOW ~(BIT(7))
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#define DB_88F6281_OE_HIGH ~(BIT(15) | BIT(14) | BIT(13) | BIT(4))
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#define DB_88F6281_OE_VAL_LOW BIT(7)
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#define DB_88F6281_OE_VAL_HIGH 0
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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mvebu_config_gpio(DB_88F6281_OE_VAL_LOW,
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DB_88F6281_OE_VAL_HIGH,
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DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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#ifdef CONFIG_CMD_NAND
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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#else
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MPP0_SPI_SCn,
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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#endif
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_SD_CLK,
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_SATA1_ACTn,
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MPP21_SATA0_ACTn,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO,
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MPP35_GPIO,
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_GPIO,
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MPP41_GPIO,
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MPP42_GPIO,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO,
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MPP48_GPIO,
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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/* automatically defined by kirkwood config.h */
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void reset_phy(void)
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{
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}
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#endif
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@@ -0,0 +1,36 @@
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# SPDX-License-Identifier: GPL-2.0+
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# Boot Media configurations
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#@BOOT_FROM
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DATA 0xd00100e0 0x1b1b1b9b
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DATA 0xd0020134 0xbbbbbbbb
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DATA 0xd0020138 0x00bbbbbb
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DATA 0xd0020154 0x00000200
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DATA 0xd002014c 0x00001c00
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DATA 0xd0020148 0x00000001
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DATA 0xd0001400 0x43000c30
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DATA 0xd0001404 0x39543000
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DATA 0xd0001408 0x22125451
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DATA 0xd000140c 0x00000833
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DATA 0xd0001410 0x000000cc
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DATA 0xd0001414 0x00000000
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DATA 0xd0001418 0x00000000
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DATA 0xd000141c 0x00000c52
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DATA 0xd0001420 0x00000044
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DATA 0xd0001424 0x0000f1ff
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DATA 0xd0001428 0x00085520
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DATA 0xd000147c 0x00008552
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DATA 0xd0001504 0x0ffffff1
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DATA 0xd0001508 0x10000000
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DATA 0xd000150c 0x0ffffff5
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DATA 0xd0001514 0x00000000
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DATA 0xd000151c 0x00000000
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DATA 0xd0001494 0x84210000
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DATA 0xd0001498 0x00000000
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DATA 0xd000149c 0x0000f40f
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DATA 0xd0001480 0x00000001
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# End of Header extension
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DATA 0x0 0x0
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@@ -0,0 +1,6 @@
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DB_88F6720 BOARD
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M: Stefan Roese <sr@denx.de>
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S: Maintained
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F: board/Marvell/db-88f6720/
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F: include/configs/db-88f6720.h
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F: configs/db-88f6720_defconfig
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@@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2016 Stefan Roese <sr@denx.de>
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obj-y := db-88f6720.o
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@@ -0,0 +1,90 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
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*/
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#define DB_88F6720_MPP0_7 0x00020020 /* SPI */
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#define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
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#define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
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#define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
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#define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
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#define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
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#define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
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#define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
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#define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
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#define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
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#define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
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#define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
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#define DB_88F6720_GPP_OUT_VAL_LOW 0x0
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#define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
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#define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
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#define DB_88F6720_GPP_POL_LOW 0x0
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#define DB_88F6720_GPP_POL_MID 0x0
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#define DB_88F6720_GPP_POL_HIGH 0x0
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
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writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
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writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
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writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
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writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
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writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
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writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
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writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
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writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
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/* Configure GPIO */
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/* Set GPP Out value */
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writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
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/* Set GPP Polarity */
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writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
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writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
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writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
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||||
|
||||
return 0;
|
||||
}
|
||||
|
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int board_init(void)
|
||||
{
|
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/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
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|
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int checkboard(void)
|
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{
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puts("Board: Marvell DB-88F6720\n");
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||||
return 0;
|
||||
}
|
||||
|
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int board_eth_init(bd_t *bis)
|
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{
|
||||
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
@@ -0,0 +1,6 @@
|
||||
DB_88F6820_AMC BOARD
|
||||
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
||||
S: Maintained
|
||||
F: board/Marvell/db-88f6820-amc/
|
||||
F: include/configs/db-88f6820-amc.h
|
||||
F: configs/db-88f6820-amc_defconfig
|
||||
@@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
|
||||
obj-y := db-88f6820-amc.o
|
||||
@@ -0,0 +1,128 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
|
||||
#include <../serdes/a38x/high_speed_env_spec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Those values and defines are taken from the Marvell U-Boot version
|
||||
* "u-boot-2013.01-2016_T1.0.eng_drop_v10"
|
||||
*/
|
||||
#define DB_AMC_88F68XX_GPP_OUT_ENA_LOW \
|
||||
(~(BIT(29)))
|
||||
#define DB_AMC_88F68XX_GPP_OUT_ENA_MID \
|
||||
(~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
|
||||
#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT(29))
|
||||
#define DB_AMC_88F68XX_GPP_OUT_VAL_MID 0x0
|
||||
#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0
|
||||
#define DB_AMC_88F68XX_GPP_POL_LOW 0x0
|
||||
#define DB_AMC_88F68XX_GPP_POL_MID 0x0
|
||||
|
||||
static struct serdes_map board_serdes_map[] = {
|
||||
{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
|
||||
};
|
||||
|
||||
int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
|
||||
{
|
||||
*serdes_map_array = board_serdes_map;
|
||||
*count = ARRAY_SIZE(board_serdes_map);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the DDR layout / topology here in the board file. This will
|
||||
* be used by the DDR3 init code in the SPL U-Boot version to configure
|
||||
* the DDR3 controller.
|
||||
*/
|
||||
static struct mv_ddr_topology_map board_topology_map = {
|
||||
DEBUG_LEVEL_ERROR,
|
||||
0x1, /* active interfaces */
|
||||
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
|
||||
{ { { {0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0} },
|
||||
SPEED_BIN_DDR_1866L, /* speed_bin */
|
||||
MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
|
||||
MV_DDR_DIE_CAP_2GBIT, /* mem_size */
|
||||
MV_DDR_FREQ_800, /* frequency */
|
||||
0, 0, /* cas_wl cas_l */
|
||||
MV_DDR_TEMP_LOW, /* temperature */
|
||||
MV_DDR_TIM_DEFAULT} }, /* timing */
|
||||
BUS_MASK_32BIT, /* Busses mask */
|
||||
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
|
||||
{ {0} }, /* raw spd data */
|
||||
{0} /* timing parameters */
|
||||
};
|
||||
|
||||
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
|
||||
{
|
||||
/* Return the board topology as defined in the board code */
|
||||
return &board_topology_map;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Configure MPP */
|
||||
writel(0x11111111, MVEBU_MPP_BASE + 0x00);
|
||||
writel(0x11111111, MVEBU_MPP_BASE + 0x04);
|
||||
writel(0x55066011, MVEBU_MPP_BASE + 0x08);
|
||||
writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(0x05055555, MVEBU_MPP_BASE + 0x10);
|
||||
writel(0x01106565, MVEBU_MPP_BASE + 0x14);
|
||||
writel(0x40000000, MVEBU_MPP_BASE + 0x18);
|
||||
writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
|
||||
|
||||
/* Set GPP Out value */
|
||||
writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
|
||||
/* Set GPP Polarity */
|
||||
writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||
writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
||||
writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Marvell DB-88F6820-AMC\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
@@ -0,0 +1,6 @@
|
||||
DB_88F6820_GP BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/Marvell/db-88f6820-gp/
|
||||
F: include/configs/db-88f6820-gp.h
|
||||
F: configs/db-88f6820-gp_defconfig
|
||||
@@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
|
||||
obj-y := db-88f6820-gp.o
|
||||
@@ -0,0 +1,18 @@
|
||||
Update from original Marvell U-Boot to mainline U-Boot:
|
||||
-------------------------------------------------------
|
||||
|
||||
The resulting image including the SPL binary with the
|
||||
full DDR setup is "u-boot-spl.kwb".
|
||||
|
||||
To update the SPI NOR flash, please use the following
|
||||
command:
|
||||
|
||||
=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\
|
||||
sf update 2000000 0 60000
|
||||
|
||||
Note that the original Marvell U-Boot seems to have
|
||||
problems with the "sf update" command. This does not
|
||||
work reliable. So here this command should be used:
|
||||
|
||||
=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\
|
||||
sf erase 0 60000;sf write 2000000 0 60000
|
||||
@@ -0,0 +1,155 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
|
||||
#include <../serdes/a38x/high_speed_env_spec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Those values and defines are taken from the Marvell U-Boot version
|
||||
* "u-boot-2013.01-2014_T3.0"
|
||||
*/
|
||||
#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
|
||||
(~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
|
||||
BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
|
||||
BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
|
||||
#define DB_GP_88F68XX_GPP_OUT_ENA_MID \
|
||||
(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
|
||||
BIT(16) | BIT(17) | BIT(18)))
|
||||
|
||||
#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
|
||||
#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
|
||||
#define DB_GP_88F68XX_GPP_POL_LOW 0x0
|
||||
#define DB_GP_88F68XX_GPP_POL_MID 0x0
|
||||
|
||||
/* IO expander on Marvell GP board includes e.g. fan enabling */
|
||||
struct marvell_io_exp {
|
||||
u8 chip;
|
||||
u8 addr;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
static struct marvell_io_exp io_exp[] = {
|
||||
{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
|
||||
{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
|
||||
{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
|
||||
{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
|
||||
{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
|
||||
{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
|
||||
{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
|
||||
{ 0x21, 3, 0xC0 } /* Output Data, register#1 */
|
||||
};
|
||||
|
||||
static struct serdes_map board_serdes_map[] = {
|
||||
{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
|
||||
{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
|
||||
};
|
||||
|
||||
int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
|
||||
{
|
||||
*serdes_map_array = board_serdes_map;
|
||||
*count = ARRAY_SIZE(board_serdes_map);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the DDR layout / topology here in the board file. This will
|
||||
* be used by the DDR3 init code in the SPL U-Boot version to configure
|
||||
* the DDR3 controller.
|
||||
*/
|
||||
static struct mv_ddr_topology_map board_topology_map = {
|
||||
DEBUG_LEVEL_ERROR,
|
||||
0x1, /* active interfaces */
|
||||
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
|
||||
{ { { {0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0} },
|
||||
SPEED_BIN_DDR_1866L, /* speed_bin */
|
||||
MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
|
||||
MV_DDR_DIE_CAP_4GBIT, /* mem_size */
|
||||
MV_DDR_FREQ_800, /* frequency */
|
||||
0, 0, /* cas_wl cas_l */
|
||||
MV_DDR_TEMP_LOW, /* temperature */
|
||||
MV_DDR_TIM_DEFAULT} }, /* timing */
|
||||
BUS_MASK_32BIT, /* Busses mask */
|
||||
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
|
||||
{ {0} }, /* raw spd data */
|
||||
{0} /* timing parameters */
|
||||
};
|
||||
|
||||
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
|
||||
{
|
||||
/* Return the board topology as defined in the board code */
|
||||
return &board_topology_map;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Configure MPP */
|
||||
writel(0x11111111, MVEBU_MPP_BASE + 0x00);
|
||||
writel(0x11111111, MVEBU_MPP_BASE + 0x04);
|
||||
writel(0x11244011, MVEBU_MPP_BASE + 0x08);
|
||||
writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(0x22200002, MVEBU_MPP_BASE + 0x10);
|
||||
writel(0x30042022, MVEBU_MPP_BASE + 0x14);
|
||||
writel(0x55550555, MVEBU_MPP_BASE + 0x18);
|
||||
writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
|
||||
|
||||
/* Set GPP Out value */
|
||||
writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
|
||||
/* Set GPP Polarity */
|
||||
writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||
writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
||||
writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
/* Init I2C IO expanders */
|
||||
for (i = 0; i < ARRAY_SIZE(io_exp); i++)
|
||||
i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Marvell DB-88F6820-GP\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
@@ -0,0 +1,6 @@
|
||||
DB_MV784MP_GP BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/Marvell/db-mv784mp-gp/
|
||||
F: include/configs/db-mv784mp-gp.h
|
||||
F: configs/db-mv784mp-gp_defconfig
|
||||
@@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
|
||||
obj-y := db-mv784mp-gp.o
|
||||
@@ -0,0 +1,117 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define ETH_PHY_CTRL_REG 0
|
||||
#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
|
||||
#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
|
||||
|
||||
/*
|
||||
* Those values and defines are taken from the Marvell U-Boot version
|
||||
* "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
|
||||
* "RD-AXP-GP rev 1.0".
|
||||
*
|
||||
* GPPs
|
||||
* MPP# NAME IN/OUT
|
||||
* ----------------------------------------------
|
||||
* 21 SW_Reset_ OUT
|
||||
* 25 Phy_Int# IN
|
||||
* 28 SDI_WP IN
|
||||
* 29 SDI_Status IN
|
||||
* 54-61 On GPP Connector ?
|
||||
* 62 Switch Interrupt IN
|
||||
* 63-65 Reserved from SW Board ?
|
||||
* 66 SW_BRD connected IN
|
||||
*/
|
||||
#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
|
||||
#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
|
||||
#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
|
||||
|
||||
#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
|
||||
#define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
|
||||
#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Configure MPP */
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x00);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x04);
|
||||
writel(0x33000000, MVEBU_MPP_BASE + 0x08);
|
||||
writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(0x11111111, MVEBU_MPP_BASE + 0x10);
|
||||
writel(0x00221100, MVEBU_MPP_BASE + 0x14);
|
||||
writel(0x00000003, MVEBU_MPP_BASE + 0x18);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x20);
|
||||
|
||||
/* Configure GPIO */
|
||||
writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
|
||||
writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Marvell DB-MV784MP-GP\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
u16 reg;
|
||||
|
||||
/* Enable QSGMII AN */
|
||||
/* Set page to 4 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
|
||||
/* Enable AN */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
|
||||
/* Set page to 0 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
|
||||
|
||||
/* Phy C_ANEG */
|
||||
reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
|
||||
reg |= 0x1E0;
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
|
||||
|
||||
/* Soft-Reset */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
|
||||
|
||||
/* Power up the phy */
|
||||
reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
|
||||
reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
|
||||
|
||||
printf("88E1545 Initialized\n");
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,7 @@
|
||||
DB-XC3-24G4XG BOARD
|
||||
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
||||
S: Maintained
|
||||
F: board/Marvell/db-xc3-24g4xg/
|
||||
F: include/configs/db-xc3-24g4xg.h
|
||||
F: configs/db-xc3-24g4xg_defconfig
|
||||
F: arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
|
||||
@@ -0,0 +1,14 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
|
||||
obj-y := db-xc3-24g4xg.o
|
||||
extra-y := kwbimage.cfg
|
||||
|
||||
quiet_cmd_sed = SED $@
|
||||
cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
|
||||
|
||||
SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
|
||||
$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
|
||||
include/config/auto.conf
|
||||
$(call if_changed,sed)
|
||||
@@ -0,0 +1,4 @@
|
||||
To generate binary.0 from Marvell's bin_hdr.elf use the following command
|
||||
|
||||
arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
|
||||
board/Marvell/db-xc3-24g4xg/binary.0
|
||||
@@ -0,0 +1,11 @@
|
||||
--------
|
||||
WARNING:
|
||||
--------
|
||||
This file should contain the bin_hdr generated by the original Marvell
|
||||
U-Boot implementation. As this is currently not included in this
|
||||
U-Boot version, we have added this placeholder, so that the U-Boot
|
||||
image can be generated without errors.
|
||||
|
||||
If you have a known to be working bin_hdr for your board, then you
|
||||
just need to replace this text file here with the binary header
|
||||
and recompile U-Boot.
|
||||
@@ -0,0 +1,68 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* These values and defines are taken from the Marvell U-Boot version
|
||||
* "u-boot-2013.01-2016_T1.0.eng_drop_v6"
|
||||
*/
|
||||
#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
|
||||
| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)))
|
||||
#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
|
||||
#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
|
||||
| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))
|
||||
#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
|
||||
#define DB_DX_AC3_GPP_POL_LOW 0x0
|
||||
#define DB_DX_AC3_GPP_POL_MID 0x0
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Configure MPP */
|
||||
writel(0x00142222, MVEBU_MPP_BASE + 0x00);
|
||||
writel(0x11122000, MVEBU_MPP_BASE + 0x04);
|
||||
writel(0x44444004, MVEBU_MPP_BASE + 0x08);
|
||||
writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(0x00000001, MVEBU_MPP_BASE + 0x10);
|
||||
|
||||
/* Set GPP Out value */
|
||||
writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
|
||||
/* Set GPP Polarity */
|
||||
writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||
writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
||||
writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DISPLAY_BOARDINFO
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: " CONFIG_SYS_BOARD "\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,12 @@
|
||||
#
|
||||
# Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
#
|
||||
|
||||
# Armada XP uses version 1 image format
|
||||
VERSION 1
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi
|
||||
|
||||
# Binary Header (bin_hdr) with DDR3 training code
|
||||
BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_DREAMPLUG
|
||||
|
||||
config SYS_BOARD
|
||||
default "dreamplug"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "Marvell"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "dreamplug"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
DREAMPLUG BOARD
|
||||
M: Jason Cooper <u-boot@lakedaemon.net>
|
||||
S: Maintained
|
||||
F: board/Marvell/dreamplug/
|
||||
F: include/configs/dreamplug.h
|
||||
F: configs/dreamplug_defconfig
|
||||
@@ -0,0 +1,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2011
|
||||
# Jason Cooper <u-boot@lakedaemon.net>
|
||||
#
|
||||
# Based on work by:
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Siddarth Gore <gores@marvell.com>
|
||||
|
||||
obj-y := dreamplug.o
|
||||
@@ -0,0 +1,135 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Jason Cooper <u-boot@lakedaemon.net>
|
||||
*
|
||||
* Based on work by:
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Siddarth Gore <gores@marvell.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "dreamplug.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* default gpio configuration
|
||||
* There are maximum 64 gpios controlled through 2 sets of registers
|
||||
* the below configuration configures mainly initial LED status
|
||||
*/
|
||||
mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
|
||||
DREAMPLUG_OE_VAL_HIGH,
|
||||
DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
static const u32 kwmpp_config[] = {
|
||||
MPP0_SPI_SCn, /* SPI Flash */
|
||||
MPP1_SPI_MOSI,
|
||||
MPP2_SPI_SCK,
|
||||
MPP3_SPI_MISO,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO,
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD, /* Serial */
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_SD_CLK, /* SDIO Slot */
|
||||
MPP13_SD_CMD,
|
||||
MPP14_SD_D0,
|
||||
MPP15_SD_D1,
|
||||
MPP16_SD_D2,
|
||||
MPP17_SD_D3,
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_GE1_0, /* Gigabit Ethernet */
|
||||
MPP21_GE1_1,
|
||||
MPP22_GE1_2,
|
||||
MPP23_GE1_3,
|
||||
MPP24_GE1_4,
|
||||
MPP25_GE1_5,
|
||||
MPP26_GE1_6,
|
||||
MPP27_GE1_7,
|
||||
MPP28_GE1_8,
|
||||
MPP29_GE1_9,
|
||||
MPP30_GE1_10,
|
||||
MPP31_GE1_11,
|
||||
MPP32_GE1_12,
|
||||
MPP33_GE1_13,
|
||||
MPP34_GE1_14,
|
||||
MPP35_GE1_15,
|
||||
MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
|
||||
MPP37_GPIO,
|
||||
MPP38_GPIO,
|
||||
MPP39_GPIO,
|
||||
MPP40_TDM_SPI_SCK,
|
||||
MPP41_TDM_SPI_MISO,
|
||||
MPP42_TDM_SPI_MOSI,
|
||||
MPP43_GPIO,
|
||||
MPP44_GPIO,
|
||||
MPP45_GPIO,
|
||||
MPP46_GPIO,
|
||||
MPP47_GPIO, /* Bluetooth LED */
|
||||
MPP48_GPIO, /* Wifi LED */
|
||||
MPP49_GPIO, /* Wifi AP LED */
|
||||
0
|
||||
};
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
void mv_phy_88e1116_init(char *name)
|
||||
{
|
||||
u16 reg;
|
||||
u16 devadr;
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* command to read PHY dev address */
|
||||
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
|
||||
printf("Err..%s could not read PHY dev address\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable RGMII delay on Tx and Rx for CPU port
|
||||
* Ref: sec 4.7.2 of chip datasheet
|
||||
*/
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
|
||||
miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
|
||||
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
|
||||
miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, devadr);
|
||||
|
||||
printf("88E1116 Initialized on %s\n", name);
|
||||
}
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
/* configure and initialize both PHY's */
|
||||
mv_phy_88e1116_init("egiga0");
|
||||
mv_phy_88e1116_init("egiga1");
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Jason Cooper <u-boot@lakedaemon.net>
|
||||
*
|
||||
* Based on work by:
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Siddarth Gore <gores@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef __DREAMPLUG_H
|
||||
#define __DREAMPLUG_H
|
||||
|
||||
#define DREAMPLUG_OE_LOW (~(0))
|
||||
#define DREAMPLUG_OE_HIGH (~(0))
|
||||
#define DREAMPLUG_OE_VAL_LOW 0
|
||||
#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1116_MAC_CTRL2_REG 21
|
||||
#define MV88E1116_PGADR_REG 22
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
#endif /* __DREAMPLUG_H */
|
||||
@@ -0,0 +1,145 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2011
|
||||
# Jason Cooper <u-boot@lakedaemon.net>
|
||||
#
|
||||
# Based on work by:
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Siddarth Gore <gores@marvell.com>
|
||||
# Refer doc/README.kwbimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0/1 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1b1b9b9b
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
|
||||
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x000000cc # DDR Address Control
|
||||
# bit1-0: 01, Cs0width=x8
|
||||
# bit3-2: 10, Cs0size=1Gb
|
||||
# bit5-4: 01, Cs1width=x8
|
||||
# bit7-6: 10, Cs1size=1Gb
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000C52 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 0, DDR ODT control lsd (disabled)
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, (disabled)
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
|
||||
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
|
||||
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,15 @@
|
||||
if TARGET_GPLUGD
|
||||
|
||||
config SYS_BOARD
|
||||
default "gplugd"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "Marvell"
|
||||
|
||||
config SYS_SOC
|
||||
default "armada100"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "gplugd"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
GPLUGD BOARD
|
||||
M: Ajay Bhargav <contact@8051projects.net>
|
||||
S: Maintained
|
||||
F: board/Marvell/gplugd/
|
||||
F: include/configs/gplugd.h
|
||||
F: configs/gplugd_defconfig
|
||||
@@ -0,0 +1,13 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2011
|
||||
# eInfochips Ltd. <www.einfochips.com>
|
||||
# Written-by: Ajay Bhargav <contact@8051projects.net>
|
||||
#
|
||||
# Based on Aspenite:
|
||||
# (C) Copyright 2010
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
# Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
|
||||
obj-y := gplugd.o
|
||||
@@ -0,0 +1,130 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* eInfochips Ltd. <www.einfochips.com>
|
||||
* Written-by: Ajay Bhargav <contact@8051projects.net>
|
||||
*
|
||||
* Based on Aspenite:
|
||||
* (C) Copyright 2010
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
* Contributor: Mahavir Jain <mjain@marvell.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mvmfp.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/mfp.h>
|
||||
#include <asm/arch/armada100.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#ifdef CONFIG_ARMADA100_FEC
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#endif /* CONFIG_ARMADA100_FEC */
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
u32 mfp_cfg[] = {
|
||||
/* I2C */
|
||||
MFP105_CI2C_SDA,
|
||||
MFP106_CI2C_SCL,
|
||||
|
||||
/* Enable Console on UART3 */
|
||||
MFPO8_UART3_TXD,
|
||||
MFPO9_UART3_RXD,
|
||||
|
||||
/* Ethernet PHY Interface */
|
||||
MFP086_ETH_TXCLK,
|
||||
MFP087_ETH_TXEN,
|
||||
MFP088_ETH_TXDQ3,
|
||||
MFP089_ETH_TXDQ2,
|
||||
MFP090_ETH_TXDQ1,
|
||||
MFP091_ETH_TXDQ0,
|
||||
MFP092_ETH_CRS,
|
||||
MFP093_ETH_COL,
|
||||
MFP094_ETH_RXCLK,
|
||||
MFP095_ETH_RXER,
|
||||
MFP096_ETH_RXDQ3,
|
||||
MFP097_ETH_RXDQ2,
|
||||
MFP098_ETH_RXDQ1,
|
||||
MFP099_ETH_RXDQ0,
|
||||
MFP100_ETH_MDC,
|
||||
MFP101_ETH_MDIO,
|
||||
MFP103_ETH_RXDV,
|
||||
|
||||
/* SSP2 */
|
||||
MFP107_SSP2_RXD,
|
||||
MFP108_SSP2_TXD,
|
||||
MFP110_SSP2_CS,
|
||||
MFP111_SSP2_CLK,
|
||||
|
||||
MFP_EOC /*End of configuration*/
|
||||
};
|
||||
/* configure MFP's */
|
||||
mfp_config(mfp_cfg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
struct armd1apb2_registers *apb2_regs =
|
||||
(struct armd1apb2_registers *)ARMD1_APBC2_BASE;
|
||||
|
||||
/* arch number of Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_GPLUGD;
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
|
||||
/* Assert PHY_RST# */
|
||||
gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
|
||||
udelay(10);
|
||||
/* Deassert PHY_RST# */
|
||||
gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
|
||||
|
||||
/* Enable SSP2 clock */
|
||||
writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARMADA100_FEC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
struct armd1apmu_registers *apmu_regs =
|
||||
(struct armd1apmu_registers *)ARMD1_APMU_BASE;
|
||||
|
||||
/* Enable clock of ethernet controller */
|
||||
writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
|
||||
|
||||
return armada100_fec_register(ARMD1_FEC_BASE);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
/* Configure and initialize PHY chip 88E3015 */
|
||||
void reset_phy(void)
|
||||
{
|
||||
u16 phy_adr;
|
||||
const char *name = "armd-fec0";
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* command to read PHY dev address */
|
||||
if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
|
||||
printf("Err..%s could not read PHY dev address\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set Ethernet LED in TX blink mode */
|
||||
miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
|
||||
miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, phy_adr);
|
||||
debug("88E3015 Initialized on %s\n", name);
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
#endif /* CONFIG_ARMADA100_FEC */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_GURUPLUG
|
||||
|
||||
config SYS_BOARD
|
||||
default "guruplug"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "Marvell"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "guruplug"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
GURUPLUG BOARD
|
||||
M: Siddarth Gore <gores@marvell.com>
|
||||
S: Maintained
|
||||
F: board/Marvell/guruplug/
|
||||
F: include/configs/guruplug.h
|
||||
F: configs/guruplug_defconfig
|
||||
@@ -0,0 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Siddarth Gore <gores@marvell.com>
|
||||
|
||||
obj-y := guruplug.o
|
||||
@@ -0,0 +1,138 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Siddarth Gore <gores@marvell.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "guruplug.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* default gpio configuration
|
||||
* There are maximum 64 gpios controlled through 2 sets of registers
|
||||
* the below configuration configures mainly initial LED status
|
||||
*/
|
||||
mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
|
||||
GURUPLUG_OE_VAL_HIGH,
|
||||
GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
static const u32 kwmpp_config[] = {
|
||||
MPP0_NF_IO2,
|
||||
MPP1_NF_IO3,
|
||||
MPP2_NF_IO4,
|
||||
MPP3_NF_IO5,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO, /* GPIO_RST */
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_SD_CLK,
|
||||
MPP13_SD_CMD,
|
||||
MPP14_SD_D0,
|
||||
MPP15_SD_D1,
|
||||
MPP16_SD_D2,
|
||||
MPP17_SD_D3,
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_GE1_0,
|
||||
MPP21_GE1_1,
|
||||
MPP22_GE1_2,
|
||||
MPP23_GE1_3,
|
||||
MPP24_GE1_4,
|
||||
MPP25_GE1_5,
|
||||
MPP26_GE1_6,
|
||||
MPP27_GE1_7,
|
||||
MPP28_GE1_8,
|
||||
MPP29_GE1_9,
|
||||
MPP30_GE1_10,
|
||||
MPP31_GE1_11,
|
||||
MPP32_GE1_12,
|
||||
MPP33_GE1_13,
|
||||
MPP34_GE1_14,
|
||||
MPP35_GE1_15,
|
||||
MPP36_GPIO,
|
||||
MPP37_GPIO,
|
||||
MPP38_GPIO,
|
||||
MPP39_GPIO,
|
||||
MPP40_TDM_SPI_SCK,
|
||||
MPP41_TDM_SPI_MISO,
|
||||
MPP42_TDM_SPI_MOSI,
|
||||
MPP43_GPIO,
|
||||
MPP44_GPIO,
|
||||
MPP45_GPIO,
|
||||
MPP46_GPIO, /* M_RLED */
|
||||
MPP47_GPIO, /* M_GLED */
|
||||
MPP48_GPIO, /* B_RLED */
|
||||
MPP49_GPIO, /* B_GLED */
|
||||
0
|
||||
};
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/*
|
||||
* arch number of board
|
||||
*/
|
||||
gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
void mv_phy_88e1121_init(char *name)
|
||||
{
|
||||
u16 reg;
|
||||
u16 devadr;
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* command to read PHY dev address */
|
||||
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
|
||||
printf("Err..%s could not read PHY dev address\n",
|
||||
__FUNCTION__);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable RGMII delay on Tx and Rx for CPU port
|
||||
* Ref: sec 4.7.2 of chip datasheet
|
||||
*/
|
||||
miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
|
||||
miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®);
|
||||
reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
|
||||
miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
|
||||
miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, devadr);
|
||||
|
||||
printf("88E1121 Initialized on %s\n", name);
|
||||
}
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
/* configure and initialize both PHY's */
|
||||
mv_phy_88e1121_init("egiga0");
|
||||
mv_phy_88e1121_init("egiga1");
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
@@ -0,0 +1,22 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Siddarth Gore <gores@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef __GURUPLUG_H
|
||||
#define __GURUPLUG_H
|
||||
|
||||
#define GURUPLUG_OE_LOW (~(0))
|
||||
#define GURUPLUG_OE_HIGH (~(0))
|
||||
#define GURUPLUG_OE_VAL_LOW 0
|
||||
#define GURUPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1121_MAC_CTRL2_REG 21
|
||||
#define MV88E1121_PGADR_REG 22
|
||||
#define MV88E1121_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1121_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
#endif /* __GURUPLUG_H */
|
||||
@@ -0,0 +1,144 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Siddarth Gore <gores@marvell.com>
|
||||
# Refer doc/README.kwbimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM nand
|
||||
NAND_ECC_MODE default
|
||||
NAND_PAGE_SIZE 0x0800
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0/1 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1b1b9b9b
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
|
||||
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x000000cc # DDR Address Control
|
||||
# bit1-0: 01, Cs0width=x8
|
||||
# bit3-2: 10, Cs0size=1Gb
|
||||
# bit5-4: 01, Cs1width=x8
|
||||
# bit7-6: 10, Cs1size=1Gb
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000C52 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 0, DDR ODT control lsd (disabled)
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, (disabled)
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
|
||||
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
|
||||
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,16 @@
|
||||
MVEBU_DB_88F3720 BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/Marvell/mvebu_armada-37xx/
|
||||
F: include/configs/mvebu_armada-37xx.h
|
||||
F: configs/mvebu_db-88f3720_defconfig
|
||||
|
||||
ESPRESSOBin BOARD
|
||||
M: Konstantin Porotchkin <kostap@marvell.com>
|
||||
S: Maintained
|
||||
F: configs/mvebu_espressobin-88f3720_defconfig
|
||||
|
||||
uDPU BOARD
|
||||
M: Vladimir Vid <vladimir.vid@sartura.hr>
|
||||
S: Maintained
|
||||
F: configs/uDPU_defconfig
|
||||
@@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||
|
||||
obj-y := board.o
|
||||
@@ -0,0 +1,234 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <i2c.h>
|
||||
#include <phy.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* IO expander I2C device */
|
||||
#define I2C_IO_EXP_ADDR 0x22
|
||||
#define I2C_IO_CFG_REG_0 0x6
|
||||
#define I2C_IO_DATA_OUT_REG_0 0x2
|
||||
#define I2C_IO_REG_0_SATA_OFF 2
|
||||
#define I2C_IO_REG_0_USB_H_OFF 1
|
||||
|
||||
/* The pin control values are the same for DB and Espressobin */
|
||||
#define PINCTRL_NB_REG_VALUE 0x000173fa
|
||||
#define PINCTRL_SB_REG_VALUE 0x00007a23
|
||||
|
||||
/* Ethernet switch registers */
|
||||
/* SMI addresses for multi-chip mode */
|
||||
#define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
|
||||
#define MVEBU_SW_G2_SMI_ADDR (28)
|
||||
|
||||
/* Multi-chip mode */
|
||||
#define MVEBU_SW_SMI_DATA_REG (1)
|
||||
#define MVEBU_SW_SMI_CMD_REG (0)
|
||||
#define SW_SMI_CMD_REG_ADDR_OFF 0
|
||||
#define SW_SMI_CMD_DEV_ADDR_OFF 5
|
||||
#define SW_SMI_CMD_SMI_OP_OFF 10
|
||||
#define SW_SMI_CMD_SMI_MODE_OFF 12
|
||||
#define SW_SMI_CMD_SMI_BUSY_OFF 15
|
||||
|
||||
/* Single-chip mode */
|
||||
/* Switch Port Registers */
|
||||
#define MVEBU_SW_LINK_CTRL_REG (1)
|
||||
#define MVEBU_SW_PORT_CTRL_REG (4)
|
||||
|
||||
/* Global 2 Registers */
|
||||
#define MVEBU_G2_SMI_PHY_CMD_REG (24)
|
||||
#define MVEBU_G2_SMI_PHY_DATA_REG (25)
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Board specific AHCI / SATA enable code */
|
||||
int board_ahci_enable(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
u8 buf[8];
|
||||
|
||||
/* Only DB requres this configuration */
|
||||
if (!of_machine_is_compatible("marvell,armada-3720-db"))
|
||||
return 0;
|
||||
|
||||
/* Configure IO exander PCA9555: 7bit address 0x22 */
|
||||
ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find PCA9555: %d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable SATA power via IO expander connected via I2C by setting
|
||||
* the corresponding bit to output mode to enable power for SATA
|
||||
*/
|
||||
buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
|
||||
ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Board specific xHCI enable code */
|
||||
int board_xhci_enable(fdt_addr_t base)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
u8 buf[8];
|
||||
|
||||
/* Only DB requres this configuration */
|
||||
if (!of_machine_is_compatible("marvell,armada-3720-db"))
|
||||
return 0;
|
||||
|
||||
/* Configure IO exander PCA9555: 7bit address 0x22 */
|
||||
ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find PCA9555: %d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
printf("Enable USB VBUS\n");
|
||||
|
||||
/*
|
||||
* Read configuration (direction) and set VBUS pin as output
|
||||
* (reset pin = output)
|
||||
*/
|
||||
ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
|
||||
ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Read VBUS output value and disable it */
|
||||
ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
|
||||
ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/*
|
||||
* Required delay for configuration to settle - must wait for
|
||||
* power on port is disabled in case VBUS signal was high,
|
||||
* required 3 seconds delay to let VBUS signal fully settle down
|
||||
*/
|
||||
mdelay(3000);
|
||||
|
||||
/* Enable VBUS power: Set output value of VBUS pin as enabled */
|
||||
buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
|
||||
ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mdelay(500); /* required delay to let output value settle */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Helper function for accessing switch devices in multi-chip connection mode */
|
||||
static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
|
||||
int smi_addr, int reg, u16 value)
|
||||
{
|
||||
u16 smi_cmd = 0;
|
||||
|
||||
if (bus->write(bus, dev_smi_addr, 0,
|
||||
MVEBU_SW_SMI_DATA_REG, value) != 0) {
|
||||
printf("Error writing to the PHY addr=%02x reg=%02x\n",
|
||||
smi_addr, reg);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
|
||||
(1 << SW_SMI_CMD_SMI_MODE_OFF) |
|
||||
(1 << SW_SMI_CMD_SMI_OP_OFF) |
|
||||
(smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
|
||||
(reg << SW_SMI_CMD_REG_ADDR_OFF);
|
||||
if (bus->write(bus, dev_smi_addr, 0,
|
||||
MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
|
||||
printf("Error writing to the PHY addr=%02x reg=%02x\n",
|
||||
smi_addr, reg);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Bring-up board-specific network stuff */
|
||||
int board_network_enable(struct mii_dev *bus)
|
||||
{
|
||||
if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* FIXME: remove this code once Topaz driver gets available
|
||||
* A3720 Community Board Only
|
||||
* Configure Topaz switch (88E6341)
|
||||
* Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
|
||||
*/
|
||||
mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
|
||||
MVEBU_SW_PORT_CTRL_REG, 0x7f);
|
||||
mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
|
||||
MVEBU_SW_PORT_CTRL_REG, 0x7f);
|
||||
mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
|
||||
MVEBU_SW_PORT_CTRL_REG, 0x7f);
|
||||
mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
|
||||
MVEBU_SW_PORT_CTRL_REG, 0x7f);
|
||||
|
||||
/* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
|
||||
mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
|
||||
MVEBU_SW_LINK_CTRL_REG, 0xe002);
|
||||
|
||||
/* Power up PHY 1, 2, 3 (through Global 2 registers) */
|
||||
mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
|
||||
MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
|
||||
mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
|
||||
MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
|
||||
mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
|
||||
MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
|
||||
mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
|
||||
MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
MVEBU_ARMADA_8K BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/Marvell/mvebu_armada-8k/
|
||||
F: include/configs/mvebu_armada-8k.h
|
||||
F: configs/mvebu_db_armada8k_defconfig
|
||||
|
||||
|
||||
MACCHIATOBin BOARD
|
||||
M: Konstantin Porotchkin <kostap@marvell.com>
|
||||
S: Maintained
|
||||
F: configs/mvebu_mcbin-88f8040_defconfig
|
||||
@@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||
|
||||
obj-y := board.o
|
||||
@@ -0,0 +1,162 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <i2c.h>
|
||||
#include <init.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Information specific to the DB-88F7040 eval board. We strive to use
|
||||
* DT for such platform specfic configurations. At some point, this
|
||||
* might be removed here and implemented via DT.
|
||||
*/
|
||||
/* IO expander I2C device */
|
||||
#define I2C_IO_EXP_ADDR 0x21
|
||||
#define I2C_IO_CFG_REG_0 0x6
|
||||
#define I2C_IO_DATA_OUT_REG_0 0x2
|
||||
/* VBus enable */
|
||||
#define I2C_IO_REG_0_USB_H0_OFF 0
|
||||
#define I2C_IO_REG_0_USB_H1_OFF 1
|
||||
#define I2C_IO_REG_VBUS ((1 << I2C_IO_REG_0_USB_H0_OFF) | \
|
||||
(1 << I2C_IO_REG_0_USB_H1_OFF))
|
||||
/* Current limit */
|
||||
#define I2C_IO_REG_0_USB_H0_CL 4
|
||||
#define I2C_IO_REG_0_USB_H1_CL 5
|
||||
#define I2C_IO_REG_CL ((1 << I2C_IO_REG_0_USB_H0_CL) | \
|
||||
(1 << I2C_IO_REG_0_USB_H1_CL))
|
||||
|
||||
static int usb_enabled = 0;
|
||||
|
||||
/* Board specific xHCI dis-/enable code */
|
||||
|
||||
/*
|
||||
* Set USB VBUS signals (via I2C IO expander/GPIO) as output and set
|
||||
* output value as disabled
|
||||
*
|
||||
* Set USB Current Limit signals (via I2C IO expander/GPIO) as output
|
||||
* and set output value as enabled
|
||||
*/
|
||||
int board_xhci_config(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
u8 buf[8];
|
||||
|
||||
if (of_machine_is_compatible("marvell,armada7040-db")) {
|
||||
/* Configure IO exander PCA9555: 7bit address 0x21 */
|
||||
ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find PCA9555: %d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read configuration (direction) and set VBUS pin as output
|
||||
* (reset pin = output)
|
||||
*/
|
||||
ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
buf[0] &= ~I2C_IO_REG_VBUS;
|
||||
buf[0] &= ~I2C_IO_REG_CL;
|
||||
ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Read output value and configure it */
|
||||
ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
buf[0] &= ~I2C_IO_REG_VBUS;
|
||||
buf[0] |= I2C_IO_REG_CL;
|
||||
ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mdelay(500); /* required delay to let output value settle */
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_xhci_enable(fdt_addr_t base)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
u8 buf[8];
|
||||
|
||||
if (of_machine_is_compatible("marvell,armada7040-db")) {
|
||||
/*
|
||||
* This function enables all USB ports simultaniously,
|
||||
* it only needs to get called once
|
||||
*/
|
||||
if (usb_enabled)
|
||||
return 0;
|
||||
|
||||
/* Configure IO exander PCA9555: 7bit address 0x21 */
|
||||
ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find PCA9555: %d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Read VBUS output value */
|
||||
ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Enable VBUS power: Set output value of VBUS pin as enabled */
|
||||
buf[0] |= I2C_IO_REG_VBUS;
|
||||
ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mdelay(500); /* required delay to let output value settle */
|
||||
usb_enabled = 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Nothing to do (yet), perhaps later some pin-muxing etc */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
/* Pre-configure the USB ports (overcurrent, VBus) */
|
||||
board_xhci_config();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_OPENRD
|
||||
|
||||
config SYS_BOARD
|
||||
default "openrd"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "Marvell"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "openrd"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,8 @@
|
||||
OPENRD / OPENRD_CLIENT BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/Marvell/openrd/
|
||||
F: include/configs/openrd.h
|
||||
F: configs/openrd_base_defconfig
|
||||
F: configs/openrd_client_defconfig
|
||||
F: configs/openrd_ultimate_defconfig
|
||||
@@ -0,0 +1,12 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2009
|
||||
# Net Insight <www.netinsight.net>
|
||||
# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
|
||||
#
|
||||
# Based on sheevaplug:
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
|
||||
obj-y := openrd.o
|
||||
@@ -0,0 +1,150 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
# Refer doc/README.kwbimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM nand
|
||||
NAND_ECC_MODE default
|
||||
NAND_PAGE_SIZE 0x0800
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1b1b1b9b
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
|
||||
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x000000cc # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
||||
# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs1width=x8
|
||||
# bit7-6: 11, Cs1size=1Gb
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000C52 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000042 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 1, DDR drive strength reduced
|
||||
# bit2: 0, DDR ODT control lsd (disabled)
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, (disabled)
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
|
||||
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
|
||||
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
|
||||
# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
|
||||
# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
|
||||
# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
|
||||
# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
|
||||
DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
|
||||
# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
|
||||
# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
|
||||
# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
|
||||
# bit14: 1, M_STARTBURST_IN ODT: Enabled
|
||||
# bit15: 1, DDR IO ODT Unit: Use ODT block
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,160 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Net Insight <www.netinsight.net>
|
||||
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
|
||||
*
|
||||
* Based on sheevaplug.c:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "openrd.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* default gpio configuration
|
||||
* There are maximum 64 gpios controlled through 2 sets of registers
|
||||
* the below configuration configures mainly initial LED status
|
||||
*/
|
||||
mvebu_config_gpio(OPENRD_OE_VAL_LOW,
|
||||
OPENRD_OE_VAL_HIGH,
|
||||
OPENRD_OE_LOW, OPENRD_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
static const u32 kwmpp_config[] = {
|
||||
MPP0_NF_IO2,
|
||||
MPP1_NF_IO3,
|
||||
MPP2_NF_IO4,
|
||||
MPP3_NF_IO5,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO,
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_SD_CLK,
|
||||
MPP13_SD_CMD, /* Alt UART1_TXD */
|
||||
MPP14_SD_D0, /* Alt UART1_RXD */
|
||||
MPP15_SD_D1,
|
||||
MPP16_SD_D2,
|
||||
MPP17_SD_D3,
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_GE1_0,
|
||||
MPP21_GE1_1,
|
||||
MPP22_GE1_2,
|
||||
MPP23_GE1_3,
|
||||
MPP24_GE1_4,
|
||||
MPP25_GE1_5,
|
||||
MPP26_GE1_6,
|
||||
MPP27_GE1_7,
|
||||
MPP28_GPIO,
|
||||
MPP29_TSMP9,
|
||||
MPP30_GE1_10,
|
||||
MPP31_GE1_11,
|
||||
MPP32_GE1_12,
|
||||
MPP33_GE1_13,
|
||||
MPP34_GPIO, /* UART1 / SD sel */
|
||||
MPP35_TDM_CH0_TX_QL,
|
||||
MPP36_TDM_SPI_CS1,
|
||||
MPP37_TDM_CH2_TX_QL,
|
||||
MPP38_TDM_CH2_RX_QL,
|
||||
MPP39_AUDIO_I2SBCLK,
|
||||
MPP40_AUDIO_I2SDO,
|
||||
MPP41_AUDIO_I2SLRC,
|
||||
MPP42_AUDIO_I2SMCLK,
|
||||
MPP43_AUDIO_I2SDI,
|
||||
MPP44_AUDIO_EXTCLK,
|
||||
MPP45_TDM_PCLK,
|
||||
MPP46_TDM_FS,
|
||||
MPP47_TDM_DRX,
|
||||
MPP48_TDM_DTX,
|
||||
MPP49_TDM_CH0_RX_QL,
|
||||
0
|
||||
};
|
||||
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/*
|
||||
* arch number of board
|
||||
*/
|
||||
#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
|
||||
#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
|
||||
#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
|
||||
#endif
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
/* Configure and enable MV88E1116/88E1121 PHY */
|
||||
void mv_phy_init(char *name)
|
||||
{
|
||||
u16 reg;
|
||||
u16 devadr;
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* command to read PHY dev address */
|
||||
if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
|
||||
printf("Err..%s could not read PHY dev address\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable RGMII delay on Tx and Rx for CPU port
|
||||
* Ref: sec 4.7.2 of chip datasheet
|
||||
*/
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
|
||||
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
|
||||
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
|
||||
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, devadr);
|
||||
|
||||
printf(PHY_NO" Initialized on %s\n", name);
|
||||
}
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
mv_phy_init("egiga0");
|
||||
|
||||
#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
|
||||
/* Kirkwood ethernet driver is written with the assumption that in case
|
||||
* of multiple PHYs, their addresses are consecutive. But unfortunately
|
||||
* in case of OpenRD-Client, PHY addresses are not consecutive.*/
|
||||
miiphy_write("egiga1", 0xEE, 0xEE, 24);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
|
||||
defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
|
||||
/* configure and initialize both PHY's */
|
||||
mv_phy_init("egiga1");
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
@@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Net Insight <www.netinsight.net>
|
||||
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
|
||||
*
|
||||
* Based on sheevaplug.h:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef __OPENRD_BASE_H
|
||||
#define __OPENRD_BASE_H
|
||||
|
||||
#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */
|
||||
#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */
|
||||
#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */
|
||||
#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1116_LED_FCTRL_REG 10
|
||||
#define MV88E1116_CPRSP_CR3_REG 21
|
||||
#define MV88E1116_MAC_CTRL_REG 21
|
||||
#define MV88E1116_PGADR_REG 22
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
#endif /* __OPENRD_BASE_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
if TARGET_SHEEVAPLUG
|
||||
|
||||
config SYS_BOARD
|
||||
default "sheevaplug"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "Marvell"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "sheevaplug"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,6 @@
|
||||
SHEEVAPLUG BOARD
|
||||
M: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
S: Maintained
|
||||
F: board/Marvell/sheevaplug/
|
||||
F: include/configs/sheevaplug.h
|
||||
F: configs/sheevaplug_defconfig
|
||||
@@ -0,0 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
|
||||
obj-y := sheevaplug.o
|
||||
@@ -0,0 +1,144 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
# Refer to doc/README.kwbimage for more details about how-to
|
||||
# configure and create kirkwood boot images.
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM nand
|
||||
NAND_ECC_MODE default
|
||||
NAND_PAGE_SIZE 0x0800
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1b1b1b9b
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
|
||||
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x000000cc # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
||||
# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs1width=x8
|
||||
# bit7-6: 11, Cs1size=1Gb
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000C52 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 0, DDR ODT control lsd (disabled)
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, (disabled)
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
|
||||
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
|
||||
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,133 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include "sheevaplug.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* default gpio configuration
|
||||
* There are maximum 64 gpios controlled through 2 sets of registers
|
||||
* the below configuration configures mainly initial LED status
|
||||
*/
|
||||
mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
|
||||
SHEEVAPLUG_OE_VAL_HIGH,
|
||||
SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
static const u32 kwmpp_config[] = {
|
||||
MPP0_NF_IO2,
|
||||
MPP1_NF_IO3,
|
||||
MPP2_NF_IO4,
|
||||
MPP3_NF_IO5,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO,
|
||||
MPP8_UART0_RTS,
|
||||
MPP9_UART0_CTS,
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_SD_CLK,
|
||||
MPP13_SD_CMD,
|
||||
MPP14_SD_D0,
|
||||
MPP15_SD_D1,
|
||||
MPP16_SD_D2,
|
||||
MPP17_SD_D3,
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_GPIO,
|
||||
MPP21_GPIO,
|
||||
MPP22_GPIO,
|
||||
MPP23_GPIO,
|
||||
MPP24_GPIO,
|
||||
MPP25_GPIO,
|
||||
MPP26_GPIO,
|
||||
MPP27_GPIO,
|
||||
MPP28_GPIO,
|
||||
MPP29_TSMP9,
|
||||
MPP30_GPIO,
|
||||
MPP31_GPIO,
|
||||
MPP32_GPIO,
|
||||
MPP33_GPIO,
|
||||
MPP34_GPIO,
|
||||
MPP35_GPIO,
|
||||
MPP36_GPIO,
|
||||
MPP37_GPIO,
|
||||
MPP38_GPIO,
|
||||
MPP39_GPIO,
|
||||
MPP40_GPIO,
|
||||
MPP41_GPIO,
|
||||
MPP42_GPIO,
|
||||
MPP43_GPIO,
|
||||
MPP44_GPIO,
|
||||
MPP45_GPIO,
|
||||
MPP46_GPIO,
|
||||
MPP47_GPIO,
|
||||
MPP48_GPIO,
|
||||
MPP49_GPIO,
|
||||
0
|
||||
};
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/*
|
||||
* arch number of board
|
||||
*/
|
||||
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
/* Configure and enable MV88E1116 PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
u16 reg;
|
||||
u16 devadr;
|
||||
char *name = "egiga0";
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* command to read PHY dev address */
|
||||
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
|
||||
printf("Err..%s could not read PHY dev address\n",
|
||||
__FUNCTION__);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable RGMII delay on Tx and Rx for CPU port
|
||||
* Ref: sec 4.7.2 of chip datasheet
|
||||
*/
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
|
||||
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
|
||||
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
|
||||
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, devadr);
|
||||
|
||||
printf("88E1116 Initialized on %s\n", name);
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef __SHEEVAPLUG_H
|
||||
#define __SHEEVAPLUG_H
|
||||
|
||||
#define SHEEVAPLUG_OE_LOW (~(0))
|
||||
#define SHEEVAPLUG_OE_HIGH (~(0))
|
||||
#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
|
||||
#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1116_LED_FCTRL_REG 10
|
||||
#define MV88E1116_CPRSP_CR3_REG 21
|
||||
#define MV88E1116_MAC_CTRL_REG 21
|
||||
#define MV88E1116_PGADR_REG 22
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
#endif /* __SHEEVAPLUG_H */
|
||||
Reference in New Issue
Block a user