GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

This commit is contained in:
lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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DB-XC3-24G4XG BOARD
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
S: Maintained
F: board/Marvell/db-xc3-24g4xg/
F: include/configs/db-xc3-24g4xg.h
F: configs/db-xc3-24g4xg_defconfig
F: arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
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# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2015 Stefan Roese <sr@denx.de>
obj-y := db-xc3-24g4xg.o
extra-y := kwbimage.cfg
quiet_cmd_sed = SED $@
cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
include/config/auto.conf
$(call if_changed,sed)
@@ -0,0 +1,4 @@
To generate binary.0 from Marvell's bin_hdr.elf use the following command
arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
board/Marvell/db-xc3-24g4xg/binary.0
@@ -0,0 +1,11 @@
--------
WARNING:
--------
This file should contain the bin_hdr generated by the original Marvell
U-Boot implementation. As this is currently not included in this
U-Boot version, we have added this placeholder, so that the U-Boot
image can be generated without errors.
If you have a known to be working bin_hdr for your board, then you
just need to replace this text file here with the binary header
and recompile U-Boot.
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <i2c.h>
#include <asm/gpio.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* These values and defines are taken from the Marvell U-Boot version
* "u-boot-2013.01-2016_T1.0.eng_drop_v6"
*/
#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)))
#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))
#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
#define DB_DX_AC3_GPP_POL_LOW 0x0
#define DB_DX_AC3_GPP_POL_MID 0x0
int board_early_init_f(void)
{
/* Configure MPP */
writel(0x00142222, MVEBU_MPP_BASE + 0x00);
writel(0x11122000, MVEBU_MPP_BASE + 0x04);
writel(0x44444004, MVEBU_MPP_BASE + 0x08);
writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
writel(0x00000001, MVEBU_MPP_BASE + 0x10);
/* Set GPP Out value */
writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
/* Set GPP Polarity */
writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
/* Set GPP Out Enable */
writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board: " CONFIG_SYS_BOARD "\n");
return 0;
}
#endif
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#
# Copyright (C) 2014 Stefan Roese <sr@denx.de>
#
# Armada XP uses version 1 image format
VERSION 1
# Boot Media configurations
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068