GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,14 @@
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if TARGET_IMX8QM_ROM7720_A1
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config SYS_BOARD
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default "imx8qm_rom7720_a1"
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config SYS_VENDOR
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default "advantech"
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config SYS_CONFIG_NAME
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default "imx8qm_rom7720"
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source "board/freescale/common/Kconfig"
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endif
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@@ -0,0 +1,6 @@
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i.MX8QM ROM 7720 a1 BOARD
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M: Oliver Graute <oliver.graute@kococonnector.com>
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S: Maintained
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F: board/advantech/imx8qm_rom7720_a1/
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F: include/configs/imx8qm_rom7720.h
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F: configs/imx8qm_rom7720_a1_4G_defconfig
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@@ -0,0 +1,11 @@
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#
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# Copyright 2017 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += imx8qm_rom7720_a1.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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endif
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@@ -0,0 +1,50 @@
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U-Boot for the NXP i.MX8QM ROM 7720a1 board
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Quick Start
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===========
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- Build the ARM Trusted firmware binary
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- Get scfw_tcm.bin and ahab-container.img
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- Get imx-mkimage
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- Build U-Boot
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- Build imx-mkimage
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- Flash the binary into the SD card
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- Boot
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Get and Build the ARM Trusted firmware
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======================================
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$ git clone https://source.codeaurora.org/external/imx/imx-atf
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$ cd imx-atf/
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$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
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$ make PLAT=imx8qm bl31
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Get scfw_tcm.bin and ahab-container.img
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==============================
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
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$ chmod +x imx-sc-firmware-1.1.bin
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$ ./imx-sc-firmware-1.1.bin
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
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$ chmod +x firmware-imx-8.0.bin
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$ ./firmware-imx-8.0.bin
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Build U-Boot
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============
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$ export ATF_LOAD_ADDR=0x80000000
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$ export BL33_LOAD_ADDR=0x80020000
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$ make imx8qm_rom7720_a1_4G_defconfig
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$ make u-boot.bin
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$ make flash.bin
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Flash the binary into the SD card
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=================================
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Burn the flash.bin binary to SD card offset 32KB:
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$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
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Boot
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====
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Set Boot switch SW2: 1100.
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+141
@@ -0,0 +1,141 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2018 NXP
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* Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
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*/
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#include <common.h>
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#include <errno.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/imx8-pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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static iomux_cfg_t uart0_pads[] = {
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SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
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}
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int board_early_init_f(void)
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{
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sc_pm_clock_rate_t rate = SC_80MHZ;
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int ret;
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/* Set UART0 clock root to 80 MHz */
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ret = sc_pm_setup_uart(SC_R_UART_0, rate);
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if (ret)
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return ret;
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setup_iomux_uart();
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/* This is needed to because Kernel do not Power Up DC_0 */
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sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON);
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sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
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return 0;
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}
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#if IS_ENABLED(CONFIG_FEC_MXC)
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#include <miiphy.h>
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int board_phy_config(struct phy_device *phydev)
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{
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#ifdef CONFIG_FEC_ENABLE_MAX7322
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u8 value;
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/* This is needed to drive the pads to 1.8V instead of 1.5V */
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i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
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if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
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/* Write 0x1 to enable O0 output, this device has no addr */
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/* hence addr length is 0 */
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value = 0x1;
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if (dm_i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
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printf("MAX7322 write failed\n");
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} else {
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printf("MAX7322 Not found\n");
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}
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mdelay(1);
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#endif
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int checkboard(void)
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{
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puts("Board: ROM-7720-A1 4GB\n");
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build_info();
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print_bootinfo();
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return 0;
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}
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int board_init(void)
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{
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/* Power up base board */
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sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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}
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/*
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* Board specific reset that is system reset.
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*/
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void reset_cpu(ulong addr)
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{
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/* TODO */
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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env_set("board_name", "ROM-7720-A1");
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env_set("board_rev", "iMX8QM");
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#endif
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env_set("sec_boot", "no");
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#ifdef CONFIG_AHAB_BOOT
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env_set("sec_boot", "yes");
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#endif
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return 0;
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}
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@@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#define __ASSEMBLY__
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/* Boot from SD, sector size 0x400 */
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BOOT_FROM SD 0x400
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/* SoC type IMX8QM */
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SOC_TYPE IMX8QM
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/* Append seco container image */
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APPEND mx8qm-ahab-container.img
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/* Create the 2nd container */
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CONTAINER
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/* Add scfw image with exec attribute */
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IMAGE SCU mx8qm-val-scfw-tcm.bin
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/* Add ATF image with exec attribute */
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IMAGE A35 bl31.bin 0x80000000
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/* Add U-Boot image with load attribute */
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DATA A35 u-boot-dtb.bin 0x80020000
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@@ -0,0 +1,220 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2018 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <spl.h>
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#include <fsl_esdhc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/imx8-pins.h>
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#include <asm/arch/iomux.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#ifdef CONFIG_FSL_ESDHC
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#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
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#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
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static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
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{USDHC1_BASE_ADDR, 0, 8},
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{USDHC2_BASE_ADDR, 0, 4},
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{USDHC3_BASE_ADDR, 0, 4},
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};
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static iomux_cfg_t emmc0[] = {
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SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
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SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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};
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static iomux_cfg_t usdhc2_sd[] = {
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SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
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SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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};
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 USDHC1
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* mmc1 USDHC2
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* mmc2 USDHC3
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
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if (ret != SC_ERR_NONE)
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return ret;
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imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
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init_clk_usdhc(0);
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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case 1:
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ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
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if (ret != SC_ERR_NONE)
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return ret;
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ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
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if (ret != SC_ERR_NONE)
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return ret;
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imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
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init_clk_usdhc(2);
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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gpio_request(USDHC2_CD_GPIO, "sd2_cd");
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gpio_direction_input(USDHC2_CD_GPIO);
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break;
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default:
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printf("Warning: you configured more USDHC controllers"
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"(%d) than supported by the board\n", i + 1);
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return 0;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret) {
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printf("Warning: failed to initialize mmc dev %d\n", i);
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return ret;
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}
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}
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return 0;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
|
||||
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switch (cfg->esdhc_base) {
|
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case USDHC1_BASE_ADDR:
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ret = 1;
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break;
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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break;
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}
|
||||
|
||||
return ret;
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||||
}
|
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|
||||
#endif /* CONFIG_FSL_ESDHC */
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SPL_SPI_SUPPORT)
|
||||
if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
|
||||
if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
|
||||
puts("Warning: failed to initialize FSPI0\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
puts("Normal Boot\n");
|
||||
}
|
||||
|
||||
void spl_board_prepare_for_boot(void)
|
||||
{
|
||||
#if defined(CONFIG_SPL_SPI_SUPPORT)
|
||||
if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
|
||||
if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
|
||||
puts("Warning: failed to turn off FSPI0\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
timer_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
Reference in New Issue
Block a user