GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_SBx81LIFKW
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config SYS_BOARD
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default "SBx81LIFKW"
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config SYS_VENDOR
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default "alliedtelesis"
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config SYS_CONFIG_NAME
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default "SBx81LIFKW"
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endif
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@@ -0,0 +1,7 @@
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SBx81LIFKW BOARD
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M: Chris Packham <chris.packham@alliedtelesis.co.nz>
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S: Maintained
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F: board/alliedtelesis/SBx81LIFKW/
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F: include/configs/SBx81LIFKW
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F: configs/SBx81LIFKW_defconfig
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F: arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
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@@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2010, 2018
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# Allied Telesis <www.alliedtelesis.com>
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#
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obj-y += sbx81lifkw.o
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@@ -0,0 +1,47 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2018 Allied Telesis
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#
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# Refer docs/README.kwimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM spi # Boot from SPI flash
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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DATA 0xffd100e0 0x1b1b1b1b
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DATA 0xffd20134 0xffffffff
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DATA 0xffd20138 0x009fffff
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DATA 0xffd20154 0x00000000
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DATA 0xffd2014c 0x00000000
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DATA 0xffd20148 0x00000001
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# Dram initalization for 1 x x16
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# DDR II Micron part number MT47H64M16HR-3
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# MClk 333MHz, Size 128MB, ECC disable
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#
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DATA 0xffd01400 0x43000618
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DATA 0xffd01404 0x35143000
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DATA 0xffd01408 0x11012227
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DATA 0xffd0140c 0x00000819
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DATA 0xffd01410 0x0000000d
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DATA 0xffd01414 0x00000000
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DATA 0xffd01418 0x00000000
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DATA 0xffd0141c 0x00000632
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DATA 0xffd01420 0x00000040
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DATA 0xffd01424 0x0000f07f
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DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
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DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
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DATA 0xffd01508 0x10000000
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DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
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DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
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DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
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DATA 0xffd01494 0x00030000
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DATA 0xffd01498 0x00000000
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DATA 0xffd0149c 0x0000e803
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DATA 0xffd01480 0x00000001
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# End of Header extension
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DATA 0x0 0x0
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@@ -0,0 +1,198 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010, 2018
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* Allied Telesis <www.alliedtelesis.com>
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <status_led.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/gpio.h>
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/* Note: GPIO differences between specific boards
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*
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* We're trying to avoid having multiple build targets for all the Kirkwood
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* based boards one area where things tend to differ is GPIO usage. For the
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* most part the GPIOs driven by the bootloader are similar enough in function
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* that there is no harm in driving them.
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*
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* XZ4 XS6 XS16 GS24A GT40 GP24A GT24A
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* GPIO39 - INT(<) NC MUX_RST_N(>) NC POE_DIS_N(>) NC
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*/
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#define SBX81LIFKW_OE_LOW ~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \
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BIT(18) | BIT(17) | BIT(13) | BIT(12) | \
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BIT(10))
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#define SBX81LIFKW_OE_HIGH ~(BIT(0) | BIT(1) | BIT(7))
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#define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27))
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#define SBX81LIFKW_OE_VAL_HIGH (BIT(0) | BIT(1))
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#define MV88E6097_RESET 27
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DECLARE_GLOBAL_DATA_PTR;
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struct led {
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u32 reg;
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u32 value;
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u32 mask;
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};
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struct led amber_solid = {
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MVEBU_GPIO0_BASE,
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BIT(10),
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BIT(18) | BIT(10)
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};
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struct led green_solid = {
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MVEBU_GPIO0_BASE,
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BIT(18) | BIT(10),
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BIT(18) | BIT(10)
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};
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struct led amber_flash = {
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MVEBU_GPIO0_BASE,
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0,
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BIT(18) | BIT(10)
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};
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struct led green_flash = {
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MVEBU_GPIO0_BASE,
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BIT(18),
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BIT(18) | BIT(10)
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};
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static void status_led_set(struct led *led)
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{
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clrsetbits_le32(led->reg, led->mask, led->value);
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}
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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mvebu_config_gpio(SBX81LIFKW_OE_VAL_LOW,
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SBX81LIFKW_OE_VAL_HIGH,
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SBX81LIFKW_OE_LOW, SBX81LIFKW_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_SPI_SCn,
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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MPP4_UART0_RXD,
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MPP5_UART0_TXD,
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MPP6_SYSRST_OUTn,
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MPP7_PEX_RST_OUTn,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_GPO,
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MPP11_GPIO,
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MPP12_GPO,
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MPP13_GPIO,
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MPP14_GPIO,
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MPP15_UART0_RTS,
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MPP16_UART0_CTS,
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MPP17_GPIO,
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MPP18_GPO,
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MPP19_GPO,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO,
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MPP35_GPIO,
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_GPIO,
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MPP41_GPIO,
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MPP42_GPIO,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO,
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MPP48_GPIO,
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/* Power-down unused subsystems. The required
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* subsystems are:
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*
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* GE0 b0
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* PEX0 PHY b1
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* PEX0.0 b2
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* TSU b5
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* SDRAM b6
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* RUNIT b7
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*/
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writel((BIT(0) | BIT(1) | BIT(2) |
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BIT(5) | BIT(6) | BIT(7)),
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KW_CPU_REG_BASE + 0x1c);
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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status_led_set(&amber_solid);
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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/* automatically defined by kirkwood config.h */
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void reset_phy(void)
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{
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}
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#endif
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#ifdef CONFIG_MV88E61XX_SWITCH
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int mv88e61xx_hw_reset(struct phy_device *phydev)
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{
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/* Ensure the 88e6097 gets at least 10ms Reset
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*/
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kw_gpio_set_value(MV88E6097_RESET, 0);
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mdelay(20);
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kw_gpio_set_value(MV88E6097_RESET, 1);
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mdelay(20);
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phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
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return 0;
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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status_led_set(&green_flash);
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return 0;
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}
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#endif
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@@ -0,0 +1,12 @@
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if TARGET_SBx81LIFXCAT
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config SYS_BOARD
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default "SBx81LIFXCAT"
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config SYS_VENDOR
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default "alliedtelesis"
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config SYS_CONFIG_NAME
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default "SBx81LIFXCAT"
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endif
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@@ -0,0 +1,7 @@
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SBx81LIFXCAT BOARD
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M: Chris Packham <chris.packham@alliedtelesis.co.nz>
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S: Maintained
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F: board/alliedtelesis/SBx81LIFXCAT/
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F: include/configs/SBx81LIFXCAT
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F: configs/SBx81LIFXCAT_defconfig
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F: arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts
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@@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2010, 2018
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# Allied Telesis <www.alliedtelesis.com>
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#
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obj-y += sbx81lifxcat.o
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@@ -0,0 +1,49 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2018 Allied Telesis
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#
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||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
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BOOT_FROM spi # Boot from SPI flash
|
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# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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DATA 0xffd100e0 0x1b1b1b1b
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DATA 0xffd20134 0xffffffff
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DATA 0xffd20138 0x009fffff
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DATA 0xffd20154 0x00000000
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DATA 0xffd2014c 0x00000000
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DATA 0xffd20148 0x00000001
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# Dram initalization for 1 x x16
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# DDR II Micron part number MT47H64M16HR-3
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# MClk 333MHz, Size 128MB, ECC disable
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#
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DATA 0xffd01400 0x43000618
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DATA 0xffd01404 0x38543000
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DATA 0xffd01408 0x23125441
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DATA 0xffd0140c 0x00000832
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DATA 0xffd01410 0x0000000D
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DATA 0xffd01414 0x00000000
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DATA 0xffd01418 0x00000000
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DATA 0xffd0141c 0x00000652
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DATA 0xffd01420 0x00000042
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DATA 0xffd01424 0x0000F0FF
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DATA 0xffd01428 0x00074410
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DATA 0xffd0147C 0x00007441
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DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
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DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
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DATA 0xffd01508 0x10000000
|
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DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
|
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DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
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DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
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DATA 0xffd01494 0x84210000
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DATA 0xffd01498 0x00000000
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DATA 0xffd0149c 0x0000F80F
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DATA 0xffd01480 0x00000001
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# End of Header extension
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||||
DATA 0x0 0x0
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@@ -0,0 +1,134 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
|
||||
* (C) Copyright 2010, 2018
|
||||
* Allied Telesis <www.alliedtelesis.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
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#include <miiphy.h>
|
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#include <netdev.h>
|
||||
#include <led.h>
|
||||
#include <linux/io.h>
|
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/gpio.h>
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|
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#define SBX81LIFXCAT_OE_LOW (~0)
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#define SBX81LIFXCAT_OE_HIGH (~BIT(11))
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#define SBX81LIFXCAT_OE_VAL_LOW (0)
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#define SBX81LIFXCAT_OE_VAL_HIGH (BIT(11))
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DECLARE_GLOBAL_DATA_PTR;
|
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|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* default gpio configuration
|
||||
* There are maximum 64 gpios controlled through 2 sets of registers
|
||||
* the below configuration configures mainly initial LED status
|
||||
*/
|
||||
mvebu_config_gpio(SBX81LIFXCAT_OE_VAL_LOW,
|
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SBX81LIFXCAT_OE_VAL_HIGH,
|
||||
SBX81LIFXCAT_OE_LOW, SBX81LIFXCAT_OE_HIGH);
|
||||
|
||||
/* Multi-Purpose Pins Functionality configuration */
|
||||
static const u32 kwmpp_config[] = {
|
||||
MPP0_SPI_SCn,
|
||||
MPP1_SPI_MOSI,
|
||||
MPP2_SPI_SCK,
|
||||
MPP3_SPI_MISO,
|
||||
MPP4_NF_IO6,
|
||||
MPP5_NF_IO7,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO,
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
MPP12_GPO,
|
||||
MPP13_UART1_TXD,
|
||||
MPP14_UART1_RXD,
|
||||
MPP15_GPIO,
|
||||
MPP16_GPIO,
|
||||
MPP17_GPIO,
|
||||
MPP18_NF_IO0,
|
||||
MPP19_NF_IO1,
|
||||
MPP20_GE1_0,
|
||||
MPP21_GE1_1,
|
||||
MPP22_GE1_2,
|
||||
MPP23_GE1_3,
|
||||
MPP24_GE1_4,
|
||||
MPP25_GE1_5,
|
||||
MPP26_GE1_6,
|
||||
MPP27_GE1_7,
|
||||
MPP28_GE1_8,
|
||||
MPP29_GE1_9,
|
||||
MPP30_GE1_10,
|
||||
MPP31_GE1_11,
|
||||
MPP32_GE1_12,
|
||||
MPP33_GE1_13,
|
||||
MPP34_GPIO,
|
||||
MPP35_GPIO,
|
||||
MPP36_GPIO,
|
||||
MPP37_GPIO,
|
||||
MPP38_GPIO,
|
||||
MPP39_GPIO,
|
||||
MPP40_GPIO,
|
||||
MPP41_GPIO,
|
||||
MPP42_GPIO,
|
||||
MPP43_GPIO,
|
||||
MPP44_GPIO,
|
||||
MPP45_GPIO,
|
||||
MPP46_GPIO,
|
||||
MPP47_GPIO,
|
||||
MPP48_GPIO,
|
||||
MPP49_GPIO,
|
||||
0
|
||||
};
|
||||
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
/* automatically defined by kirkwood config.h */
|
||||
void reset_phy(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MV88E61XX_SWITCH
|
||||
int mv88e61xx_hw_reset(struct phy_device *phydev)
|
||||
{
|
||||
phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
int misc_init_r(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = led_get_by_label("status:ledp", &dev);
|
||||
if (!ret)
|
||||
led_set_state(dev, LEDST_ON);
|
||||
|
||||
ret = led_get_by_label("status:ledn", &dev);
|
||||
if (!ret)
|
||||
led_set_state(dev, LEDST_OFF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,36 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Allied Telesis Labs
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int gpio_hog_list(struct gpio_desc *gpiod, int max_count,
|
||||
const char *node_name, const char *gpio_name, int value)
|
||||
{
|
||||
int node;
|
||||
int count;
|
||||
int i;
|
||||
|
||||
node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, node_name);
|
||||
if (node < 0)
|
||||
return -ENODEV;
|
||||
|
||||
if (!dm_gpio_is_valid(gpiod)) {
|
||||
count =
|
||||
gpio_request_list_by_name_nodev(offset_to_ofnode(node),
|
||||
gpio_name, gpiod, max_count,
|
||||
GPIOD_IS_OUT);
|
||||
if (count < 0)
|
||||
return count;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
dm_gpio_set_value(&gpiod[i], value);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,13 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2017 Allied Telesis Labs
|
||||
*/
|
||||
|
||||
int gpio_hog_list(struct gpio_desc *gpiod, int max_count, const char *node_name,
|
||||
const char *gpio_name, int value);
|
||||
|
||||
static inline int gpio_hog(struct gpio_desc *gpiod, const char *node_name,
|
||||
const char *gpio_name, int value)
|
||||
{
|
||||
return gpio_hog_list(gpiod, 1, node_name, gpio_name, value);
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
x530 BOARD
|
||||
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
||||
S: Maintained
|
||||
F: board/alliedtelesis/x530/
|
||||
F: board/alliedtelesis/common/gpio_hog.c
|
||||
F: board/alliedtelesis/common/gpio_hog.h
|
||||
F: arch/arm/dts/armada-385-atl-x530.dts
|
||||
F: arch/arm/dts/armada-385-atl-x530.dtsi
|
||||
F: arch/arm/dts/armada-385-atl-x530DP.dts
|
||||
F: arch/arm/dts/armada-385-atl-x530DP.dtsi
|
||||
F: include/configs/x530.h
|
||||
F: configs/x530_defconfig
|
||||
@@ -0,0 +1,9 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2017 Allied Telesis Labs
|
||||
#
|
||||
|
||||
obj-y := $(BOARD).o
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
obj-y += ../common/gpio_hog.o
|
||||
endif
|
||||
@@ -0,0 +1,12 @@
|
||||
#
|
||||
# Copyright (C) 2017 Allied Telesis Labs
|
||||
#
|
||||
|
||||
# Armada XP uses version 1 image format
|
||||
VERSION 1
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi
|
||||
|
||||
# Binary Header (bin_hdr) with DDR3 training code
|
||||
BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
|
||||
@@ -0,0 +1,176 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Allied Telesis Labs
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <dm.h>
|
||||
#include <env.h>
|
||||
#include <i2c.h>
|
||||
#include <wdt.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include "../common/gpio_hog.h"
|
||||
|
||||
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
|
||||
#include <../serdes/a38x/high_speed_env_spec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
|
||||
|
||||
#define CONFIG_NVS_LOCATION 0xf4800000
|
||||
#define CONFIG_NVS_SIZE (512 << 10)
|
||||
|
||||
static struct serdes_map board_serdes_map[] = {
|
||||
{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
|
||||
};
|
||||
|
||||
int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
|
||||
{
|
||||
*serdes_map_array = board_serdes_map;
|
||||
*count = ARRAY_SIZE(board_serdes_map);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the DDR layout / topology here in the board file. This will
|
||||
* be used by the DDR3 init code in the SPL U-Boot version to configure
|
||||
* the DDR3 controller.
|
||||
*/
|
||||
static struct mv_ddr_topology_map board_topology_map = {
|
||||
DEBUG_LEVEL_ERROR,
|
||||
0x1, /* active interfaces */
|
||||
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
|
||||
{ { { {0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0} },
|
||||
SPEED_BIN_DDR_1866M, /* speed_bin */
|
||||
MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
|
||||
MV_DDR_DIE_CAP_4GBIT, /* die capacity */
|
||||
MV_DDR_FREQ_SAR, /* frequency */
|
||||
0, 0, /* cas_l cas_wl */
|
||||
MV_DDR_TEMP_LOW, /* temperature */
|
||||
MV_DDR_TIM_2T} }, /* timing */
|
||||
BUS_MASK_32BIT_ECC, /* subphys mask */
|
||||
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
|
||||
{ {0} }, /* raw spd data */
|
||||
{0} /* timing parameters */
|
||||
};
|
||||
|
||||
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
|
||||
{
|
||||
/* Return the board topology as defined in the board code */
|
||||
return &board_topology_map;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Configure MPP */
|
||||
writel(0x00001111, MVEBU_MPP_BASE + 0x00);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x04);
|
||||
writel(0x55000000, MVEBU_MPP_BASE + 0x08);
|
||||
writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(0x55555555, MVEBU_MPP_BASE + 0x10);
|
||||
writel(0x00100565, MVEBU_MPP_BASE + 0x14);
|
||||
writel(0x40000000, MVEBU_MPP_BASE + 0x18);
|
||||
writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
/* window for NVS */
|
||||
mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
|
||||
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
|
||||
|
||||
/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
|
||||
writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
|
||||
|
||||
spl_board_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arch_preboot_os(void)
|
||||
{
|
||||
#ifdef CONFIG_WATCHDOG
|
||||
wdt_stop(gd->watchdog_dev);
|
||||
#endif
|
||||
}
|
||||
|
||||
static int led_7seg_init(unsigned int segments)
|
||||
{
|
||||
int node;
|
||||
int ret;
|
||||
int i;
|
||||
struct gpio_desc desc[8];
|
||||
|
||||
node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
|
||||
"atl,of-led-7seg");
|
||||
if (node < 0)
|
||||
return -ENODEV;
|
||||
|
||||
ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
|
||||
"segment-gpios", desc,
|
||||
ARRAY_SIZE(desc), GPIOD_IS_OUT);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(desc); i++) {
|
||||
ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
int misc_init_r(void)
|
||||
{
|
||||
static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
|
||||
led_en = {};
|
||||
|
||||
gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
|
||||
gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
|
||||
gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
|
||||
gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
|
||||
|
||||
#ifdef MTDPARTS_MTDOOPS
|
||||
env_set("mtdoops", MTDPARTS_MTDOOPS);
|
||||
#endif
|
||||
|
||||
led_7seg_init(0xff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DISPLAY_BOARDINFO
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: " CONFIG_SYS_BOARD "\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user