GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

This commit is contained in:
lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
@@ -0,0 +1,15 @@
if TARGET_AM335X_GUARDIAN
config SYS_BOARD
default "guardian"
config SYS_VENDOR
default "bosch"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "am335x_guardian"
endif
@@ -0,0 +1,8 @@
Guardian BOARD
M: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
M: Govindaraji Sivanantham <Govindaraji.Sivanantham@in.bosch.com>
M: Moses Christopher Bollavarapu <BollavarapuMoses.Christopher@in.bosch.com>
S: Maintained
F: board/bosch/guardian/
F: include/configs/am335x_guardian.h
F: configs/am335x_guardian_defconfig
@@ -0,0 +1,12 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Makefile
#
# Copyright (C) 2018 Robert Bosch Power Tools GmbH
#
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
obj-y += board.o
@@ -0,0 +1,238 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board.c
*
* Board functions for Bosch Guardian
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
#include <common.h>
#include <cpsw.h>
#include <dm.h>
#include <env_internal.h>
#include <errno.h>
#include <i2c.h>
#include <miiphy.h>
#include <panel.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
#include <spl.h>
#include <watchdog.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K128M16JT125K_RD_DQS,
.datawdsratio0 = MT41K128M16JT125K_WR_DQS,
.datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
.datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K128M16JT125K_RATIO,
.cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
.cmd1csratio = MT41K128M16JT125K_RATIO,
.cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
.cmd2csratio = MT41K128M16JT125K_RATIO,
.cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
.ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
.sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
.sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
.sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
.zq_config = MT41K128M16JT125K_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
};
#define OSC (V_OSCK / 1000000)
const struct dpll_params dpll_ddr = {
400, OSC - 1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
int mpu_vdd;
int usb_cur_lim;
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
if (i2c_probe(TPS65217_CHIP_PM))
return;
/*
* Increase USB current limit to 1300mA or 1800mA and set
* the MPU voltage controller as needed.
*/
if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
} else {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
}
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
TPS65217_POWER_PATH,
usb_cur_lim,
TPS65217_USB_INPUT_CUR_LIMIT_MASK))
puts("tps65217_reg_write failure\n");
/* Set DCDC3 (CORE) voltage to 1.125V */
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
TPS65217_DCDC_VOLT_SEL_1125MV)) {
puts("tps65217_voltage_update failure\n");
return;
}
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Set DCDC2 (MPU) voltage */
if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
puts("tps65217_voltage_update failure\n");
return;
}
/*
* Set LDO3 to 1.8V and LDO4 to 3.3V
*/
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_1_8,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS2,
TPS65217_LDO_VOLTAGE_OUT_3_3,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
return &dpll_ddr;
}
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
}
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
const struct ctrl_ioregs ioregs = {
.cm0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
.cm1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
.cm2ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
.dt0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
.dt1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
};
void sdram_init(void)
{
config_ddr(400, &ioregs,
&ddr3_data,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
#endif
int board_init(void)
{
save_omap_boot_params();
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_MTD_RAW_NAND
gpmc_init();
#endif
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
static void set_bootmode_env(void)
{
char *boot_device_name = NULL;
char *boot_mode_gpio = "gpio@44e07000_14";
int ret;
int value;
struct gpio_desc boot_mode_desc;
switch (gd->arch.omap_boot_device) {
case BOOT_DEVICE_NAND:
boot_device_name = "nand";
break;
case BOOT_DEVICE_USBETH:
boot_device_name = "usbeth";
break;
default:
break;
}
if (boot_device_name)
env_set("boot_device", boot_device_name);
ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
if (ret) {
printf("%s is not found\n", boot_mode_gpio);
goto err;
}
ret = dm_gpio_request(&boot_mode_desc, "setup_bootmode_env");
if (ret && ret != -EBUSY) {
printf("requesting gpio: %s failed\n", boot_mode_gpio);
goto err;
}
value = dm_gpio_get_value(&boot_mode_desc);
value ? env_set("swi_status", "0") : env_set("swi_status", "1");
return;
err:
env_set("swi_status", "err");
}
int board_late_init(void)
{
set_bootmode_env();
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* board.h
*
* Board header for Bosch Guardian
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
#ifndef _BOARD_H_
#define _BOARD_H_
void enable_uart0_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(void);
#endif
@@ -0,0 +1,89 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* mux.c
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
static struct module_pin_mux guardian_interfaces_pin_mux[] = {
{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
{OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)},
{OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
{OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
{OFFSET(mii1_crs), (MODE(7) | PULLDOWN_EN)},
{OFFSET(rmii1_refclk), (MODE(7) | PULLDOWN_EN)},
{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},
{OFFSET(mii1_rxdv), (MODE(7) | PULLDOWN_EN)},
{-1},
};
#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
{OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)},
#endif
{OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)},
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)},
{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
{OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)},
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)},
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
{-1},
};
#endif
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
void enable_board_pin_mux(void)
{
#ifdef CONFIG_MTD_RAW_NAND
configure_module_pin_mux(nand_pin_mux);
#endif
configure_module_pin_mux(guardian_interfaces_pin_mux);
}