GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_LSXL
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config SYS_BOARD
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default "lsxl"
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config SYS_VENDOR
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default "buffalo"
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config SYS_CONFIG_NAME
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default "lsxl"
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endif
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@@ -0,0 +1,7 @@
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LSXL BOARD
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M: Michael Walle <michael@walle.cc>
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S: Maintained
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F: board/buffalo/lsxl/
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F: include/configs/lsxl.h
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F: configs/lschlv2_defconfig
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F: configs/lsxhl_defconfig
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2012 Michael Walle
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# Michael Walle <michael@walle.cc>
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obj-y := lsxl.o
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@@ -0,0 +1,149 @@
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Intro
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-----
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The Buffalo Linkstation Pro/Live, codename LS-XHL and LS-CHLv2, is a single
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disk NAS server. The PCBs of the LS-XHL and LS-CHLv2 are almost the same.
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The LS-XHL has a faster CPU and more RAM with a wider data bus, therefore
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the LS-XHL PCB has two SDRAM chips. Both have a Kirkwood CPU (Marvell
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88F6281). The only on-board storage is a 4 Mbit SPI flash which stores the
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bootloader and its environment. The linux kernel and the initial ramdisk
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are loaded from the hard disk.
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Important! Changes since v2019.07
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---------------------------------
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In u-boot v2019.07 the driver for the SATA port was changed to a new
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one. This means that the old "ide" command and block interface is not
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supported anymore. More important, the boot commands have changed. You have
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to overwrite the boot commands in your envionment with the new ones:
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env default -f bootcmd_legacy
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env default -f bootcmd_hdd
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saveenv
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Rescue Mode
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-----------
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These linkstations don't have a populated serial port. There is no way to
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access an (unmodified) board other than using the netconsole. If you want
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to recover from a bad environment setting or an empty environment, you can
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do this only with a working network connection.
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Therefore, on entering the resuce mode, a random ethernet address is
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generated if no valid address could be loaded from the environment variable
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'ethaddr' and a DHCP request is sent. After a successful DHCP response is
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received, the network settings are configured and the ncip is unset. Thus
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all netconsole packets are broadcasted and you can use the netconsole to
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access board from any host within the network segment. To determine the IP
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address assigned to the board, you either have to sniff the traffic or
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check the logs/leases of your DHCP server.
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The resuce mode is selected by holding the push button for at least one
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second, while powering-on the device. The status LED turns solid amber if
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the resuce mode is enabled, thus providing a visual feedback.
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Pressing the same button for at least 10 seconds on power-up will erase the
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environment and reset the board. In this case the visual indication will
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be:
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- blinking blue, for about one second
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- solid amber, for about nine seconds
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- blinking amber, until you release the button
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This ensures, that you still can recover a device with a broken
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environment by first erasing the environment and then entering the rescue
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mode.
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Once the rescue mode is started, use the ncb binary from the tools/
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directory to access your board. There is a helper script named
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'restore_env' to save your changes. It unsets all the network variables
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which were set by the rescue mode, saves your changes and then resets the
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board.
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The common use case for this is setting a MAC address. Let us assume you
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have an empty environment, the board comes up with the amber LED blinking.
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Then you enter the rescue mode, connect to the board with the ncb tool and
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use the following commands to set your MAC address:
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setenv ethaddr 00:00:00:00:00:00
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run restore_env
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Of course you need to replace the 00:00:00:00:00:00 with your valid MAC
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address, which can be found on a sticker on the bottom of your box.
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Status LED
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----------
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blinking blue
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Bootloader is running normally.
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blinking amber
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No ethaddr set. Use the `Rescue Mode` to set one.
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blinking red
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Something bad happend during loading the operating system.
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The default behavior of the linux kernel is to turn on the blue LED. So if
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the blinking blue LED changes to solid blue the kernel was loaded
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successfully.
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Power-on Switch
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---------------
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The power-on switch is a software switch. If it is not in ON position when
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the bootloader starts, the bootloader will disable the HDD and USB power
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and stop the fan. Then it loops until the switch is in ON position again,
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enables the power and fan again and continue booting.
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Boot sources
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------------
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The environment defines several different boot sources:
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legacy
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This is the default boot source. It loads the kernel and ramdisk from the
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attached HDD using the original filenames. The load addresses were
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modified to support loading larger kernels. But it should behave the same
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as the original bootloader.
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hdd
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Use this for new-style booting. Loads three files /vmlinuz, /initrd.img
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and /dtb from the boot partition. This should work out of the box if you
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have debian and the flash-kernel package installed.
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usb
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Same as hdd expect, that the files are loaded from an attached USB mass
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storage device and the filename for the device tree is kirkwood-lsxhl.dtb
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(or kirkwood-lschlv2.dtb).
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net
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Same as usb expect, that the file are loaded from the network.
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rescue
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Automatically activated if the push button is pressed for at least one
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second on power-up. Does a DHCP request and enables the network console.
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See `Rescue Mode` for more information.
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You can change the boot source by setting the 'bootsource' variable to the
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corresponding value. Please note, that the restore_env script will the the
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bootsource back to 'legacy'.
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Flash map
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---------
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00000 - 5ffff u-boot
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60000 - 6ffff reserved, may be used to store dtb
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70000 - 7ffff u-boot environment
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Compiling
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---------
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make lsxhl_config (or lschlv2_config)
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make u-boot.kwb
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Update your board
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-----------------
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Just flash the resulting u-boot.kwb to the beginning of the SPI flash. If
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you already have a bootloader CLI, you can use the following commands:
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sf probe 0
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bootp ${loadaddr} u-boot.kwb
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sf erase 0 +${filelen}
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sf write 0 ${fileaddr} ${filesize}
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@@ -0,0 +1,211 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2012 Michael Walle
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# Michael Walle <michael@walle.cc>
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# Refer doc/README.kwbimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM spi
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Configure RGMII-0/1 interface pad voltage to 1.8V
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DATA 0xFFD100E0 0x1B1B1B9B
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# L2 RAM Timing 0
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DATA 0xFFD20134 0xBBBBBBBB
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# not further specified in HW manual, timing taken from original vendor port
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# L2 RAM Timing 1
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DATA 0xFFD20138 0x00BBBBBB
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# not further specified in HW manual, timing taken from original vendor port
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# DDR Configuration register
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DATA 0xFFD01400 0x43000618
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# bit13-0: 0x618, 1560 DDR2 clks refresh rate
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# bit23-14: 0 required
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# bit24: 1, enable exit self refresh mode on DDR access
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# bit25: 1 required
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# bit29-26: 0 required
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# bit31-30: 0b01 required
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# DDR Controller Control Low
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DATA 0xFFD01404 0x39543000
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# bit3-0: 0 required
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# bit4: 0, addr/cmd in same cycle
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# bit5: 0, clk is driven during self refresh, we don't care for APX
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# bit6: 0, use recommended falling edge of clk for addr/cmd
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# bit11-7: 0 required
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# bit12: 1 required
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# bit13: 1 required
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# bit14: 0, input buffer always powered up
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# bit17-15: 0 required
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# bit18: 1, cpu lock transaction enabled
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# bit19: 0 required
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# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 3 required
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# bit31: 0, no additional STARTBURST delay
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# DDR Timing (Low)
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DATA 0xFFD01408 0x3302444F
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# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
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# bit7-4: 4, 5 cycle tRCD
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# bit11-8: 4, 5 cyle tRP
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# bit15-12: 4, 5 cyle tWR
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# bit19-16: 2, 3 cyle tWTR
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# bit20: 0, 16 cycle tRAS (tRAS[4])
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# bit23-21: 0 required
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# bit27-24: 3, 4 cycle tRRD
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# bit31-28: 3, 4 cyle tRTP
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# DDR Timing (High)
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DATA 0xFFD0140C 0x00000823
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# bit6-0: 0x23, 35 cycle tRFC
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# bit8-7: 0, 1 cycle tR2R
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# bit10-9: 0, 1 cyle tR2W
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# bit12-11: 1, 2 cylce tW2W
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# bit31-13: 0 required
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# DDR Address Control
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DATA 0xFFD01410 0x00000009
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# bit1-0: 1, Cs0width=x16
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# bit3-2: 2, Cs0size=512Mbit
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# bit5-4: 0, Cs1width=nonexistent
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# bit7-6: 0, Cs1size=nonexistent
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# bit9-8: 0, Cs2width=nonexistent
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# bit11-10: 0, Cs2size=nonexistent
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# bit13-12: 0, Cs3width=nonexistent
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# bit15-14: 0, Cs3size=nonexistent
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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# bit19: 0, Cs3AddrSel
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# bit31-20: 0 required
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# DDR Open Pages Control
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DATA 0xFFD01414 0x00000000
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# bit0: 0, OPEn=OpenPage enabled
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# bit31-1: 0 required
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# DDR Operation
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DATA 0xFFD01418 0x00000000
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# bit3-0: 0, Cmd=Normal SDRAM Mode
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# bit31-4: 0 required
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# DDR Mode
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DATA 0xFFD0141C 0x00000652
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# bit2-0: 2, Burst Length (2 required)
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# bit3: 0, Burst Type (0 required)
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# bit6-4: 5, CAS Latency (CL) 5
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# bit7: 0, (Test Mode) Normal operation
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# bit8: 0, (Reset DLL) Normal operation
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# bit11-9: 3, Write recovery for auto-precharge (3 required)
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# bit12: 0, Fast Active power down exit time (0 required)
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# bit31-13: 0 required
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# DDR Extended Mode
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DATA 0xFFD01420 0x00000042
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# bit0: 0, DRAM DLL enabled
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# bit1: 1, DRAM drive strength reduced
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# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
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# bit5-3: 0 required
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# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
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# bit9-7: 0 required
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# bit10: 0, differential DQS enabled
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# bit11: 0 required
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# bit12: 0, DRAM output buffer enabled
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# bit31-13: 0 required
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# DDR Controller Control High
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DATA 0xFFD01424 0x0000F17F
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# bit2-0: 0x7 required
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# bit3: 1, MBUS Burst Chop disabled
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# bit6-4: 0x7 required
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# bit7: 0 required (???)
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# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
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# bit9: 0, no half clock cycle addition to dataout
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# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
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# bit11: 0, 1/4 clock cycle skew disabled for write mesh
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# bit15-12: 0xf required
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# bit31-16: 0 required
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# DDR2 ODT Read Timing (default values)
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DATA 0xFFD01428 0x00085520
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# bit3-0: 0 required
|
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# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
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# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
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# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
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# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
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# bit31-20: 0 required
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|
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# DDR2 ODT Write Timing (default values)
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DATA 0xFFD0147C 0x00008552
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# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
|
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# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
|
||||
# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
|
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# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
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# bit31-16: 0 required
|
||||
|
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# CS[0]n Base address
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DATA 0xFFD01500 0x00000000
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# at 0x0
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||||
|
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# CS[0]n Size
|
||||
DATA 0xFFD01504 0x03FFFFF1
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# bit0: 1, Window enabled
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# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 0x0, CS0 hit selected
|
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# bit23-4: 0xfffff required
|
||||
# bit31-24: 0x03, Size (i.e. 64MB)
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|
||||
# CS[1]n Size
|
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DATA 0xFFD0150C 0x00000000
|
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# window disabled
|
||||
|
||||
# CS[2]n Size
|
||||
DATA 0xFFD01514 0x00000000
|
||||
# window disabled
|
||||
|
||||
# CS[3]n Size
|
||||
DATA 0xFFD0151C 0x00000000
|
||||
# window disabled
|
||||
|
||||
# DDR ODT Control (Low)
|
||||
DATA 0xFFD01494 0x003C0000
|
||||
# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
|
||||
# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
|
||||
# bit15-8: 0 required
|
||||
# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
||||
# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
|
||||
# bit31-24: 0 required
|
||||
|
||||
# DDR ODT Control (High)
|
||||
DATA 0xFFD01498 0x00000000
|
||||
# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
|
||||
# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
|
||||
# bit31-4 0 required
|
||||
|
||||
# CPU ODT Control
|
||||
DATA 0xFFD0149C 0x0000E80F
|
||||
# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
|
||||
# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
|
||||
# bit9-8: 0, Internal ODT assertion is controlled by fiels
|
||||
# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
|
||||
# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
|
||||
# bit14: 1, M_STARTBURST_IN ODT enabled
|
||||
# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
|
||||
# bit20-16: 0, Pad N channel driving strength for ODT
|
||||
# bit25-21: 0, Pad P channel driving strength for ODT
|
||||
# bit31-26: 0 required
|
||||
|
||||
# DDR Initialization Control
|
||||
DATA 0xFFD01480 0x00000001
|
||||
# bit0: 1, enable DDR init upon this register write
|
||||
# bit31-1: 0, required
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,211 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (c) 2012 Michael Walle
|
||||
# Michael Walle <michael@walle.cc>
|
||||
# Refer doc/README.kwbimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0/1 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100E0 0x1B1B9B9B
|
||||
|
||||
# L2 RAM Timing 0
|
||||
DATA 0xFFD20134 0xBBBBBBBB
|
||||
# not further specified in HW manual, timing taken from original vendor port
|
||||
|
||||
# L2 RAM Timing 1
|
||||
DATA 0xFFD20138 0x00BBBBBB
|
||||
# not further specified in HW manual, timing taken from original vendor port
|
||||
|
||||
# DDR Configuration register
|
||||
DATA 0xFFD01400 0x43000618
|
||||
# bit13-0: 0x618, 1560 DDR2 clks refresh rate
|
||||
# bit23-14: 0 required
|
||||
# bit24: 1, enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: 0 required
|
||||
# bit31-30: 0b01 required
|
||||
|
||||
# DDR Controller Control Low
|
||||
DATA 0xFFD01404 0x39543010
|
||||
# bit3-0: 0 required
|
||||
# bit4: 1, T2 mode, addr/cmd are driven for two cycles
|
||||
# bit5: 0, clk is driven during self refresh, we don't care for APX
|
||||
# bit6: 0, use recommended falling edge of clk for addr/cmd
|
||||
# bit11-7: 0 required
|
||||
# bit12: 1 required
|
||||
# bit13: 1 required
|
||||
# bit14: 0, input buffer always powered up
|
||||
# bit17-15: 0 required
|
||||
# bit18: 1, cpu lock transaction enabled
|
||||
# bit19: 0 required
|
||||
# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0, no additional STARTBURST delay
|
||||
|
||||
# DDR Timing (Low)
|
||||
DATA 0xFFD01408 0x22125441
|
||||
# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
|
||||
# bit7-4: 4, 5 cycle tRCD
|
||||
# bit11-8: 4, 5 cyle tRP
|
||||
# bit15-12: 5, 6 cyle tWR
|
||||
# bit19-16: 2, 3 cyle tWTR
|
||||
# bit20: 1, 18 cycle tRAS (tRAS[4])
|
||||
# bit23-21: 0 required
|
||||
# bit27-24: 2, 3 cycle tRRD
|
||||
# bit31-28: 2, 3 cyle tRTP
|
||||
|
||||
# DDR Timing (High)
|
||||
DATA 0xFFD0140C 0x00000832
|
||||
# bit6-0: 0x32, 50 cycle tRFC
|
||||
# bit8-7: 0, 1 cycle tR2R
|
||||
# bit10-9: 0, 1 cyle tR2W
|
||||
# bit12-11: 1, 2 cylce tW2W
|
||||
# bit31-13: 0 required
|
||||
|
||||
# DDR Address Control
|
||||
DATA 0xFFD01410 0x0000000C
|
||||
# bit1-0: 0, Cs0width=x8
|
||||
# bit3-2: 3, Cs0size=1Gbit
|
||||
# bit5-4: 0, Cs1width=nonexistent
|
||||
# bit7-6: 0, Cs1size=nonexistent
|
||||
# bit9-8: 0, Cs2width=nonexistent
|
||||
# bit11-10: 0, Cs2size=nonexistent
|
||||
# bit13-12: 0, Cs3width=nonexistent
|
||||
# bit15-14: 0, Cs3size=nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
# DDR Open Pages Control
|
||||
DATA 0xFFD01414 0x00000000
|
||||
# bit0: 0, OPEn=OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
# DDR Operation
|
||||
DATA 0xFFD01418 0x00000000
|
||||
# bit3-0: 0, Cmd=Normal SDRAM Mode
|
||||
# bit31-4: 0 required
|
||||
|
||||
# DDR Mode
|
||||
DATA 0xFFD0141C 0x00000652
|
||||
# bit2-0: 2, Burst Length (2 required)
|
||||
# bit3: 0, Burst Type (0 required)
|
||||
# bit6-4: 5, CAS Latency (CL) 5
|
||||
# bit7: 0, (Test Mode) Normal operation
|
||||
# bit8: 0, (Reset DLL) Normal operation
|
||||
# bit11-9: 3, Write recovery for auto-precharge (3 required)
|
||||
# bit12: 0, Fast Active power down exit time (0 required)
|
||||
# bit31-13: 0 required
|
||||
|
||||
# DDR Extended Mode
|
||||
DATA 0xFFD01420 0x00000006
|
||||
# bit0: 0, DRAM DLL enabled
|
||||
# bit1: 1, DRAM drive strength reduced
|
||||
# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
|
||||
# bit5-3: 0 required
|
||||
# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
|
||||
# bit9-7: 0 required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0 required
|
||||
# bit12: 0, DRAM output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
# DDR Controller Control High
|
||||
DATA 0xFFD01424 0x0000F17F
|
||||
# bit2-0: 0x7 required
|
||||
# bit3: 1, MBUS Burst Chop disabled
|
||||
# bit6-4: 0x7 required
|
||||
# bit7: 0 required (???)
|
||||
# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9: 0, no half clock cycle addition to dataout
|
||||
# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11: 0, 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 0xf required
|
||||
# bit31-16: 0 required
|
||||
|
||||
# DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD01428 0x00085520
|
||||
# bit3-0: 0 required
|
||||
# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
|
||||
# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
|
||||
# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
|
||||
# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
|
||||
# bit31-20: 0 required
|
||||
|
||||
# DDR2 ODT Write Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552
|
||||
# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
|
||||
# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
|
||||
# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
|
||||
# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
|
||||
# bit31-16: 0 required
|
||||
|
||||
# CS[0]n Base address
|
||||
DATA 0xFFD01500 0x00000000
|
||||
# at 0x0
|
||||
|
||||
# CS[0]n Size
|
||||
DATA 0xFFD01504 0x0FFFFFF1
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 0x0, CS0 hit selected
|
||||
# bit23-4: 0xfffff required
|
||||
# bit31-24: 0x0f, Size (i.e. 256MB)
|
||||
|
||||
# CS[1]n Size
|
||||
DATA 0xFFD0150C 0x00000000
|
||||
# window disabled
|
||||
|
||||
# CS[2]n Size
|
||||
DATA 0xFFD01514 0x00000000
|
||||
# window disabled
|
||||
|
||||
# CS[3]n Size
|
||||
DATA 0xFFD0151C 0x00000000
|
||||
# window disabled
|
||||
|
||||
# DDR ODT Control (Low)
|
||||
DATA 0xFFD01494 0x00010000
|
||||
# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
|
||||
# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
|
||||
# bit15-8: 0 required
|
||||
# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
||||
# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
|
||||
# bit31-24: 0 required
|
||||
|
||||
# DDR ODT Control (High)
|
||||
DATA 0xFFD01498 0x00000000
|
||||
# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
|
||||
# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
|
||||
# bit31-4 0 required
|
||||
|
||||
# CPU ODT Control
|
||||
DATA 0xFFD0149C 0x0000E80F
|
||||
# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
|
||||
# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
|
||||
# bit9-8: 0, Internal ODT assertion is controlled by fiels
|
||||
# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
|
||||
# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
|
||||
# bit14: 1, M_STARTBURST_IN ODT enabled
|
||||
# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
|
||||
# bit20-16: 0, Pad N channel driving strength for ODT
|
||||
# bit25-21: 0, Pad P channel driving strength for ODT
|
||||
# bit31-26: 0 required
|
||||
|
||||
# DDR Initialization Control
|
||||
DATA 0xFFD01480 0x00000001
|
||||
# bit0: 1, enable DDR init upon this register write
|
||||
# bit31-1: 0, required
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@@ -0,0 +1,280 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2012 Michael Walle
|
||||
* Michael Walle <michael@walle.cc>
|
||||
*
|
||||
* Based on sheevaplug/sheevaplug.c by
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <env_internal.h>
|
||||
#include <net.h>
|
||||
#include <malloc.h>
|
||||
#include <netdev.h>
|
||||
#include <miiphy.h>
|
||||
#include <spi.h>
|
||||
#include <spi_flash.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
#include "lsxl.h"
|
||||
|
||||
/*
|
||||
* Rescue mode
|
||||
*
|
||||
* Selected by holding the push button for 3 seconds, while powering on
|
||||
* the device.
|
||||
*
|
||||
* These linkstations don't have a (populated) serial port. There is no
|
||||
* way to access an (unmodified) board other than using the netconsole. If
|
||||
* you want to recover from a bad environment setting or an empty environment,
|
||||
* you can do this only with a working network connection. Therefore, a random
|
||||
* ethernet address is generated if none is set and a DHCP request is sent.
|
||||
* After a successful DHCP response is received, the network settings are
|
||||
* configured and the ncip is unset. Therefore, all netconsole packets are
|
||||
* broadcasted.
|
||||
* Additionally, the bootsource is set to 'rescue'.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_ENV_OVERWRITE
|
||||
# error "You need to set CONFIG_ENV_OVERWRITE"
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* default gpio configuration
|
||||
* There are maximum 64 gpios controlled through 2 sets of registers
|
||||
* the below configuration configures mainly initial LED status
|
||||
*/
|
||||
mvebu_config_gpio(LSXL_OE_VAL_LOW,
|
||||
LSXL_OE_VAL_HIGH,
|
||||
LSXL_OE_LOW, LSXL_OE_HIGH);
|
||||
|
||||
/*
|
||||
* Multi-Purpose Pins Functionality configuration
|
||||
* These strappings are taken from the original vendor uboot port.
|
||||
*/
|
||||
static const u32 kwmpp_config[] = {
|
||||
MPP0_SPI_SCn,
|
||||
MPP1_SPI_MOSI,
|
||||
MPP2_SPI_SCK,
|
||||
MPP3_SPI_MISO,
|
||||
MPP4_UART0_RXD,
|
||||
MPP5_UART0_TXD,
|
||||
MPP6_SYSRST_OUTn,
|
||||
MPP7_GPO,
|
||||
MPP8_GPIO,
|
||||
MPP9_GPIO,
|
||||
MPP10_GPO, /* HDD power */
|
||||
MPP11_GPIO, /* USB Vbus enable */
|
||||
MPP12_SD_CLK,
|
||||
MPP13_SD_CMD,
|
||||
MPP14_SD_D0,
|
||||
MPP15_SD_D1,
|
||||
MPP16_SD_D2,
|
||||
MPP17_SD_D3,
|
||||
MPP18_GPO, /* fan speed high */
|
||||
MPP19_GPO, /* fan speed low */
|
||||
MPP20_GE1_0,
|
||||
MPP21_GE1_1,
|
||||
MPP22_GE1_2,
|
||||
MPP23_GE1_3,
|
||||
MPP24_GE1_4,
|
||||
MPP25_GE1_5,
|
||||
MPP26_GE1_6,
|
||||
MPP27_GE1_7,
|
||||
MPP28_GPIO,
|
||||
MPP29_GPIO,
|
||||
MPP30_GE1_10,
|
||||
MPP31_GE1_11,
|
||||
MPP32_GE1_12,
|
||||
MPP33_GE1_13,
|
||||
MPP34_GPIO,
|
||||
MPP35_GPIO,
|
||||
MPP36_GPIO, /* function LED */
|
||||
MPP37_GPIO, /* alarm LED */
|
||||
MPP38_GPIO, /* info LED */
|
||||
MPP39_GPIO, /* power LED */
|
||||
MPP40_GPIO, /* fan alarm */
|
||||
MPP41_GPIO, /* funtion button */
|
||||
MPP42_GPIO, /* power switch */
|
||||
MPP43_GPIO, /* power auto switch */
|
||||
MPP44_GPIO,
|
||||
MPP45_GPIO,
|
||||
MPP46_GPIO,
|
||||
MPP47_GPIO,
|
||||
MPP48_GPIO, /* function red LED */
|
||||
MPP49_GPIO,
|
||||
0
|
||||
};
|
||||
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define LED_OFF 0
|
||||
#define LED_ALARM_ON 1
|
||||
#define LED_ALARM_BLINKING 2
|
||||
#define LED_POWER_ON 3
|
||||
#define LED_POWER_BLINKING 4
|
||||
#define LED_INFO_ON 5
|
||||
#define LED_INFO_BLINKING 6
|
||||
|
||||
static void __set_led(int blink_alarm, int blink_info, int blink_power,
|
||||
int value_alarm, int value_info, int value_power)
|
||||
{
|
||||
kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm);
|
||||
kw_gpio_set_blink(GPIO_INFO_LED, blink_info);
|
||||
kw_gpio_set_blink(GPIO_POWER_LED, blink_power);
|
||||
kw_gpio_set_value(GPIO_ALARM_LED, value_alarm);
|
||||
kw_gpio_set_value(GPIO_INFO_LED, value_info);
|
||||
kw_gpio_set_value(GPIO_POWER_LED, value_power);
|
||||
}
|
||||
|
||||
static void set_led(int state)
|
||||
{
|
||||
switch (state) {
|
||||
case LED_OFF:
|
||||
__set_led(0, 0, 0, 1, 1, 1);
|
||||
break;
|
||||
case LED_ALARM_ON:
|
||||
__set_led(0, 0, 0, 0, 1, 1);
|
||||
break;
|
||||
case LED_ALARM_BLINKING:
|
||||
__set_led(1, 0, 0, 1, 1, 1);
|
||||
break;
|
||||
case LED_INFO_ON:
|
||||
__set_led(0, 0, 0, 1, 0, 1);
|
||||
break;
|
||||
case LED_INFO_BLINKING:
|
||||
__set_led(0, 1, 0, 1, 1, 1);
|
||||
break;
|
||||
case LED_POWER_ON:
|
||||
__set_led(0, 0, 0, 1, 1, 0);
|
||||
break;
|
||||
case LED_POWER_BLINKING:
|
||||
__set_led(0, 0, 1, 1, 1, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
set_led(LED_POWER_BLINKING);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
static void check_power_switch(void)
|
||||
{
|
||||
if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
|
||||
/* turn off fan, HDD and USB power */
|
||||
kw_gpio_set_value(GPIO_HDD_POWER, 0);
|
||||
kw_gpio_set_value(GPIO_USB_VBUS, 0);
|
||||
kw_gpio_set_value(GPIO_FAN_HIGH, 1);
|
||||
kw_gpio_set_value(GPIO_FAN_LOW, 1);
|
||||
set_led(LED_OFF);
|
||||
|
||||
/* loop until released */
|
||||
while (kw_gpio_get_value(GPIO_POWER_SWITCH))
|
||||
;
|
||||
|
||||
/* turn power on again */
|
||||
kw_gpio_set_value(GPIO_HDD_POWER, 1);
|
||||
kw_gpio_set_value(GPIO_USB_VBUS, 1);
|
||||
kw_gpio_set_value(GPIO_FAN_HIGH, 0);
|
||||
kw_gpio_set_value(GPIO_FAN_LOW, 0);
|
||||
set_led(LED_POWER_BLINKING);
|
||||
}
|
||||
}
|
||||
|
||||
void check_enetaddr(void)
|
||||
{
|
||||
uchar enetaddr[6];
|
||||
|
||||
if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
|
||||
/* signal unset/invalid ethaddr to user */
|
||||
set_led(LED_INFO_BLINKING);
|
||||
}
|
||||
}
|
||||
|
||||
static void erase_environment(void)
|
||||
{
|
||||
struct spi_flash *flash;
|
||||
|
||||
printf("Erasing environment..\n");
|
||||
flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
|
||||
if (!flash) {
|
||||
printf("Erasing flash failed\n");
|
||||
return;
|
||||
}
|
||||
|
||||
spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE);
|
||||
spi_flash_free(flash);
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
|
||||
static void rescue_mode(void)
|
||||
{
|
||||
printf("Entering rescue mode..\n");
|
||||
env_set("bootsource", "rescue");
|
||||
}
|
||||
|
||||
static void check_push_button(void)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) {
|
||||
udelay(100000);
|
||||
i++;
|
||||
|
||||
if (i == 10)
|
||||
set_led(LED_INFO_ON);
|
||||
|
||||
if (i >= 100) {
|
||||
set_led(LED_INFO_BLINKING);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i >= 100)
|
||||
erase_environment();
|
||||
else if (i >= 10)
|
||||
rescue_mode();
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
check_power_switch();
|
||||
check_enetaddr();
|
||||
check_push_button();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS
|
||||
void show_boot_progress(int progress)
|
||||
{
|
||||
if (progress > 0)
|
||||
return;
|
||||
|
||||
/* this is not an error, eg. bootp with autoload=no will trigger this */
|
||||
if (progress == -BOOTSTAGE_ID_NET_LOADED)
|
||||
return;
|
||||
|
||||
set_led(LED_ALARM_BLINKING);
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,58 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2012 Michael Walle
|
||||
* Michael Walle <michael@walle.cc>
|
||||
*/
|
||||
|
||||
#ifndef __LSXL_H
|
||||
#define __LSXL_H
|
||||
|
||||
#define GPIO_HDD_POWER 10
|
||||
#define GPIO_USB_VBUS 11
|
||||
#define GPIO_FAN_HIGH 18
|
||||
#define GPIO_FAN_LOW 19
|
||||
#define GPIO_FUNC_LED 36
|
||||
#define GPIO_ALARM_LED 37
|
||||
#define GPIO_INFO_LED 38
|
||||
#define GPIO_POWER_LED 39
|
||||
#define GPIO_FAN_LOCK 40
|
||||
#define GPIO_FUNC_BUTTON 41
|
||||
#define GPIO_POWER_SWITCH 42
|
||||
#define GPIO_POWER_AUTO_SWITCH 43
|
||||
#define GPIO_FUNC_RED_LED 48
|
||||
|
||||
#define _BIT(x) (1<<(x))
|
||||
|
||||
#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER) \
|
||||
| _BIT(GPIO_USB_VBUS) \
|
||||
| _BIT(GPIO_FAN_HIGH) \
|
||||
| _BIT(GPIO_FAN_LOW)))
|
||||
|
||||
#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32) \
|
||||
| _BIT(GPIO_ALARM_LED - 32) \
|
||||
| _BIT(GPIO_INFO_LED - 32) \
|
||||
| _BIT(GPIO_POWER_LED - 32) \
|
||||
| _BIT(GPIO_FUNC_RED_LED - 32)))
|
||||
|
||||
#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER) \
|
||||
| _BIT(GPIO_USB_VBUS))
|
||||
|
||||
#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \
|
||||
| _BIT(GPIO_ALARM_LED - 32) \
|
||||
| _BIT(GPIO_INFO_LED - 32) \
|
||||
| _BIT(GPIO_POWER_LED - 32) \
|
||||
| _BIT(GPIO_FUNC_RED_LED - 32))
|
||||
|
||||
#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH) \
|
||||
| _BIT(GPIO_FAN_LOW))
|
||||
|
||||
#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \
|
||||
| _BIT(GPIO_ALARM_LED - 32) \
|
||||
| _BIT(GPIO_INFO_LED - 32) \
|
||||
| _BIT(GPIO_POWER_LED - 32) \
|
||||
| _BIT(GPIO_FUNC_BUTTON - 32) \
|
||||
| _BIT(GPIO_POWER_SWITCH - 32) \
|
||||
| _BIT(GPIO_POWER_AUTO_SWITCH - 32) \
|
||||
| _BIT(GPIO_FUNC_RED_LED - 32))
|
||||
|
||||
#endif /* __LSXL_H */
|
||||
Reference in New Issue
Block a user