GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,12 @@
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if TARGET_COBRA5272
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config SYS_CPU
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default "mcf52x2"
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config SYS_BOARD
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default "cobra5272"
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config SYS_CONFIG_NAME
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default "cobra5272"
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endif
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@@ -0,0 +1,6 @@
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COBRA5272 BOARD
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#M: -
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S: Maintained
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F: board/cobra5272/
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F: include/configs/cobra5272.h
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F: configs/cobra5272_defconfig
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y = cobra5272.o flash.o
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@@ -0,0 +1,156 @@
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File: README.COBRA5272
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Author: Florian Schlote for Sentec elektronik (linux@sentec-elektronik.de)
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Contents: This is the README of u-boot (Universal bootloader) for our
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COBRA5272 board.
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Version: v01.00
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Date: Tue Mar 30 00:28:33 CEST 2004
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License: This document is published under the GNU GPL
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______________________________________________________________________
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CHANGES
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040330 v01.00 Creation
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______________________________________________________________________
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CONFIGURING
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-----------
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1. Modify include/configs/cobra5272.h acc. to your prefs
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2. If necessary, modify board/cobra5272/config.mk (see below)
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3.
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> make cobra5272_config
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> make
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Please refer to u-boot README (general info, u-boot-x-x-x/README),
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to u-boot-x-x-x/doc/README.COBRA5272 and
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to the comments in u-boot-x-x-x/include/configs/cobra5272.h
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Configuring u-boot is done by commenting/uncommenting preprocessor defines.
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Default configuration is
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FLASH version (for further info see subsection below)
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link address 0xffe00000
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16 MB RAM
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network enabled
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no default IP address for target, host set, no MACaddress set
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bootdelay for autoboot 5 sec.
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autoboot disabled
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#-----------------------------------
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# u-boot FLASH version & RAM version
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#-----------------------------------
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The u-boot bootloader for Coldfire processors can be configured
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1. as a standalone bootloader residing in flash & relocating itself to RAM on
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startup automatically => "FLASH version"
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2. as a RAM version which will not load from flash automatically as it needs a
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prestage bootloader ("chainloading") & is running only from the RAM address it
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is linked to => "RAM version"
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This version may be very helpful when installing u-boot for the first time
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since it can be used to make available s. th. like a "bootstrap
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mechanism".
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How to build the different images:
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------------------------------
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Flash version
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------------------------------
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Compile u-boot
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in dir ./u-boot-x-x-x/
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please first check:
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in ./include/configs/cobra5272.h
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CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows:
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#if 0
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#define CONFIG_MONITOR_IS_IN_RAM
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/* define if monitor is started from a pre-loader */
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#endif
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=> u-boot as single bootloader starting from flash
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in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
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CONFIG_SYS_TEXT_BASE = 0xffe00000
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=> linking address for u-boot as single bootloader stored in flash
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then:
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host> make cobra5272_config
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rm -f include/config.h include/config.mk
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Configuring for cobra5272 board...
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host> make
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[...]
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host> cp u-boot.bin /tftpboot/u-boot_flash.bin
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------------------------------
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RAM version
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------------------------------
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in dir ./u-boot-x-x-x/
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host> make distclean
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please modify the settings:
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in ./include/configs/cobra5272.h
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CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows:
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#if 1
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#define CONFIG_MONITOR_IS_IN_RAM
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/*define if monitor is started from a pre-loader */
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#endif
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=> u-boot as RAM version, chainloaded by another bootloader or using bdm cable
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in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
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CONFIG_SYS_TEXT_BASE = 0x00020000
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=> target linking address for RAM
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then:
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host> make cobra5272_config
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rm -f include/config.h include/config.mk
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Configuring for cobra5272 board...
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host> make
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[...]
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host> cp u-boot.bin /tftpboot/u-boot_ram.bin
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----
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HINT
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----
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If the m68k-elf-toolchain & the m68k-bdm-gdb is installed you can run the RAM
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version by typing (in dir ./u-boot-x-x-x/)
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"board/cobra5272/bdm/load-cobra_uboot" ,
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in ./u-boot-x-x-x/ the RAM version u-boot (elf format) has to be available.
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@@ -0,0 +1,169 @@
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#
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# GDB Init script for the Coldfire 5272 processor.
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#
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# The main purpose of this script is to configure the
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# DRAM controller so code can be loaded.
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#
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# This file was changed to suite the senTec COBRA5272 board.
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#
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define addresses
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set $mbar = 0x10000001
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set $scr = $mbar - 1 + 0x004
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set $spr = $mbar - 1 + 0x006
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set $pmr = $mbar - 1 + 0x008
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set $apmr = $mbar - 1 + 0x00e
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set $dir = $mbar - 1 + 0x010
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set $icr1 = $mbar - 1 + 0x020
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set $icr2 = $mbar - 1 + 0x024
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set $icr3 = $mbar - 1 + 0x028
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set $icr4 = $mbar - 1 + 0x02c
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set $isr = $mbar - 1 + 0x030
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set $pitr = $mbar - 1 + 0x034
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set $piwr = $mbar - 1 + 0x038
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set $pivr = $mbar - 1 + 0x03f
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set $csbr0 = $mbar - 1 + 0x040
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set $csor0 = $mbar - 1 + 0x044
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set $csbr1 = $mbar - 1 + 0x048
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set $csor1 = $mbar - 1 + 0x04c
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set $csbr2 = $mbar - 1 + 0x050
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set $csor2 = $mbar - 1 + 0x054
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set $csbr3 = $mbar - 1 + 0x058
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set $csor3 = $mbar - 1 + 0x05c
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set $csbr4 = $mbar - 1 + 0x060
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set $csor4 = $mbar - 1 + 0x064
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set $csbr5 = $mbar - 1 + 0x068
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set $csor5 = $mbar - 1 + 0x06c
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set $csbr6 = $mbar - 1 + 0x070
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set $csor6 = $mbar - 1 + 0x074
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set $csbr7 = $mbar - 1 + 0x078
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set $csor7 = $mbar - 1 + 0x07c
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set $pacnt = $mbar - 1 + 0x080
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set $paddr = $mbar - 1 + 0x084
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set $padat = $mbar - 1 + 0x086
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set $pbcnt = $mbar - 1 + 0x088
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set $pbddr = $mbar - 1 + 0x08c
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set $pbdat = $mbar - 1 + 0x08e
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set $pcddr = $mbar - 1 + 0x094
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set $pcdat = $mbar - 1 + 0x096
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set $pdcnt = $mbar - 1 + 0x098
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set $sdcr = $mbar - 1 + 0x180
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set $sdtr = $mbar - 1 + 0x184
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set $wrrr = $mbar - 1 + 0x280
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set $wirr = $mbar - 1 + 0x283
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set $wcr = $mbar - 1 + 0x288
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set $wer = $mbar - 1 + 0x28c
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end
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#
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# Setup system configuration
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#
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define setup-sys
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set *((unsigned short *) $scr) = 0x0003
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set *((unsigned short *) $spr) = 0xffff
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set *((unsigned char *) $pivr) = 0x4f
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end
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#
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# Setup Chip Selects (as per Motorola M5272C3 board)
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#
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define setup-cs
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# CS0 -- FLASH
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set *((unsigned long *) $csbr0) = 0xffe00201
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set *((unsigned long *) $csor0) = 0xffe00014
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# CS1 -- external bus test
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set *((unsigned long *) $csbr1) = 0x0
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set *((unsigned long *) $csor1) = 0x0
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# CS2 -- Optional FSRAM
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set *((unsigned long *) $csbr2) = 0x30000001
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set *((unsigned long *) $csor2) = 0xfff80000
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# CS3 -- not used
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set *((unsigned long *) $csbr3) = 0x0
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set *((unsigned long *) $csor3) = 0x0
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# CS4 -- not used
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set *((unsigned long *) $csbr4) = 0x0
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set *((unsigned long *) $csor4) = 0x0
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# CS5 -- PLI socket0
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set *((unsigned long *) $csbr5) = 0x0
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set *((unsigned long *) $csor5) = 0x0
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# CS6 -- PLI socket1
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set *((unsigned long *) $csbr6) = 0x0
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set *((unsigned long *) $csor6) = 0x0
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# CS7 -- SDRAM
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set *((unsigned long *) $csbr7) = 0x00000701
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set *((unsigned long *) $csor7) = 0xff00007c
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end
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#
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# Setup the DRAM controller.
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#
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define setup-dram
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set *((unsigned long *) $sdtr) = 0x0000f539
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set *((unsigned long *) $sdcr) = 0x00004211
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# Dummy write to start SDRAM
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set *((unsigned long *) 0) = 0
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end
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#
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# Setup for GPIO pins
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#
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define setup-ppio
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# PORT A -- the LED's
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set *((unsigned long *) $pacnt) = 0x00000000
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# lower 8 bits for output:
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set *((unsigned short *) $paddr) = 0xff
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# LED's off:
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set *((unsigned short *) $padat) = 0xff
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# PORT B
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set *((unsigned long *) $pbcnt) = 0x55554155
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set *((unsigned short *) $pbddr) = 0x0000
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set *((unsigned short *) $pbdat) = 0x17ea
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# PORT C
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#set *((unsigned short *) $pcddr) = 0x0000
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#set *((unsigned short *) $pcdat) = 0x1898
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# PORT D
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set *((unsigned long *) $pdcnt) = 0x00000000
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end
|
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|
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|
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#
|
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# Added for uClinux-coldfire target...
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#
|
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target bdm /dev/bdm
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|
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addresses
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setup-sys
|
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setup-cs
|
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setup-dram
|
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setup-ppio
|
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set print pretty
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set print asm-demangle
|
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display/i $pc
|
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|
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|
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#
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load u-boot
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set $pc=0x20000
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c
|
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@@ -0,0 +1,2 @@
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target bdm /dev/bdmcf0
|
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q
|
||||
@@ -0,0 +1,2 @@
|
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m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot
|
||||
|
||||
@@ -0,0 +1,2 @@
|
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m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset
|
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|
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@@ -0,0 +1,40 @@
|
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// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
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* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
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#include <common.h>
|
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#include <asm/immap.h>
|
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|
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DECLARE_GLOBAL_DATA_PTR;
|
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|
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int checkboard (void)
|
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{
|
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puts ("Board: ");
|
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puts ("senTec COBRA5272 Board\n");
|
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return 0;
|
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};
|
||||
|
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int dram_init(void)
|
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{
|
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volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
|
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|
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sdp->sdram_sdtr = 0xf539;
|
||||
sdp->sdram_sdcr = 0x4211;
|
||||
|
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/* Dummy write to start SDRAM */
|
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*((volatile unsigned long *) 0) = 0;
|
||||
|
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
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int testdram (void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
@@ -0,0 +1,366 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <console.h>
|
||||
#include <cpu_func.h>
|
||||
#include <irq_func.h>
|
||||
|
||||
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
|
||||
#define FLASH_BANK_SIZE 0x200000
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
|
||||
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (AMD_MANUFACT & FLASH_VENDMASK):
|
||||
printf ("AMD: ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (AMD_ID_PL160CB & FLASH_TYPEMASK):
|
||||
printf ("AM29PL160CB (16Mbit)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
goto Done;
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((i % 5) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
Done:
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
int i, j;
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
|
||||
ulong flashbase = 0;
|
||||
|
||||
flash_info[i].flash_id =
|
||||
(AMD_MANUFACT & FLASH_VENDMASK) |
|
||||
(AMD_ID_PL160CB & FLASH_TYPEMASK);
|
||||
flash_info[i].size = FLASH_BANK_SIZE;
|
||||
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
|
||||
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
|
||||
if (i == 0)
|
||||
flashbase = PHYS_FLASH_1;
|
||||
else
|
||||
panic ("configured to many flash banks!\n");
|
||||
|
||||
for (j = 0; j < flash_info[i].sector_count; j++) {
|
||||
if (j == 0) {
|
||||
/* 1st is 16 KiB */
|
||||
flash_info[i].start[j] = flashbase;
|
||||
}
|
||||
if ((j >= 1) && (j <= 2)) {
|
||||
/* 2nd and 3rd are 8 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x4000 + 0x2000 * (j - 1);
|
||||
}
|
||||
if (j == 3) {
|
||||
/* 4th is 224 KiB */
|
||||
flash_info[i].start[j] = flashbase + 0x8000;
|
||||
}
|
||||
if ((j >= 4) && (j <= 10)) {
|
||||
/* rest is 256 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x40000 + 0x40000 * (j -
|
||||
4);
|
||||
}
|
||||
}
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_FLASH_BASE,
|
||||
CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
|
||||
#define CMD_READ_ARRAY 0x00F0
|
||||
#define CMD_UNLOCK1 0x00AA
|
||||
#define CMD_UNLOCK2 0x0055
|
||||
#define CMD_ERASE_SETUP 0x0080
|
||||
#define CMD_ERASE_CONFIRM 0x0030
|
||||
#define CMD_PROGRAM 0x00A0
|
||||
#define CMD_UNLOCK_BYPASS 0x0020
|
||||
|
||||
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
|
||||
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
|
||||
|
||||
#define BIT_ERASE_DONE 0x0080
|
||||
#define BIT_RDY_MASK 0x0080
|
||||
#define BIT_PROGRAM_ERROR 0x0020
|
||||
#define BIT_TIMEOUT 0x80000000 /* our flag */
|
||||
|
||||
#define READY 1
|
||||
#define ERR 2
|
||||
#define TMO 4
|
||||
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
ulong result;
|
||||
int iflag, cflag, prot, sect;
|
||||
int rc = ERR_OK;
|
||||
int chip1;
|
||||
ulong start;
|
||||
|
||||
/* first look for protection bits */
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
return ERR_UNKNOWN_FLASH_TYPE;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
return ERR_INVAL;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) !=
|
||||
(AMD_MANUFACT & FLASH_VENDMASK)) {
|
||||
return ERR_UNKNOWN_FLASH_VENDOR;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot)
|
||||
return ERR_PROTECTED;
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status();
|
||||
icache_disable();
|
||||
iflag = disable_interrupts();
|
||||
|
||||
printf ("\n");
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
|
||||
printf ("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
volatile u16 *addr =
|
||||
(volatile u16 *) (info->start[sect]);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
*addr = CMD_ERASE_CONFIRM;
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
chip1 = TMO;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!chip1
|
||||
&& (result & 0xFFFF) & BIT_ERASE_DONE)
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR) {
|
||||
rc = ERR_PROG_ERROR;
|
||||
goto outahere;
|
||||
}
|
||||
if (chip1 == TMO) {
|
||||
rc = ERR_TIMEOUT;
|
||||
goto outahere;
|
||||
}
|
||||
|
||||
printf ("ok.\n");
|
||||
} else { /* it was protected */
|
||||
|
||||
printf ("protected!\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (ctrlc ())
|
||||
printf ("User Interrupt!\n");
|
||||
|
||||
outahere:
|
||||
/* allow flash to settle - wait 10 ms */
|
||||
udelay (10000);
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts();
|
||||
|
||||
if (cflag)
|
||||
icache_enable();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile u16 *addr = (volatile u16 *) dest;
|
||||
ulong result;
|
||||
int rc = ERR_OK;
|
||||
int cflag, iflag;
|
||||
int chip1;
|
||||
ulong start;
|
||||
|
||||
/*
|
||||
* Check if Flash is (sufficiently) erased
|
||||
*/
|
||||
result = *addr;
|
||||
if ((result & data) != data)
|
||||
return ERR_NOT_ERASED;
|
||||
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status();
|
||||
icache_disable();
|
||||
iflag = disable_interrupts();
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_PROGRAM;
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
chip1 = ERR | TMO;
|
||||
break;
|
||||
}
|
||||
if (!chip1 && ((result & 0x80) == (data & 0x80)))
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
*addr = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR || *addr != data)
|
||||
rc = ERR_PROG_ERROR;
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts();
|
||||
|
||||
if (cflag)
|
||||
icache_enable();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp, data;
|
||||
int rc;
|
||||
|
||||
if (addr & 1) {
|
||||
printf ("unaligned destination not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (cnt & 1) {
|
||||
printf ("odd transfer sizes not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
#endif
|
||||
|
||||
wp = addr;
|
||||
|
||||
if (addr & 1) {
|
||||
data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
|
||||
src);
|
||||
if ((rc = write_word (info, wp - 1, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
while (cnt >= 2) {
|
||||
data = *((volatile u16 *) src);
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 2;
|
||||
wp += 2;
|
||||
cnt -= 2;
|
||||
}
|
||||
|
||||
if (cnt == 1) {
|
||||
data = (*((volatile u8 *) src) << 8) |
|
||||
*((volatile u8 *) (wp + 1));
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
Reference in New Issue
Block a user