GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
21813 changed files with 4413081 additions and 0 deletions
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if TARGET_COBRA5272
config SYS_CPU
default "mcf52x2"
config SYS_BOARD
default "cobra5272"
config SYS_CONFIG_NAME
default "cobra5272"
endif
@@ -0,0 +1,6 @@
COBRA5272 BOARD
#M: -
S: Maintained
F: board/cobra5272/
F: include/configs/cobra5272.h
F: configs/cobra5272_defconfig
@@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y = cobra5272.o flash.o
@@ -0,0 +1,156 @@
File: README.COBRA5272
Author: Florian Schlote for Sentec elektronik (linux@sentec-elektronik.de)
Contents: This is the README of u-boot (Universal bootloader) for our
COBRA5272 board.
Version: v01.00
Date: Tue Mar 30 00:28:33 CEST 2004
License: This document is published under the GNU GPL
______________________________________________________________________
CHANGES
040330 v01.00 Creation
______________________________________________________________________
CONFIGURING
-----------
1. Modify include/configs/cobra5272.h acc. to your prefs
2. If necessary, modify board/cobra5272/config.mk (see below)
3.
> make cobra5272_config
> make
Please refer to u-boot README (general info, u-boot-x-x-x/README),
to u-boot-x-x-x/doc/README.COBRA5272 and
to the comments in u-boot-x-x-x/include/configs/cobra5272.h
Configuring u-boot is done by commenting/uncommenting preprocessor defines.
Default configuration is
FLASH version (for further info see subsection below)
link address 0xffe00000
16 MB RAM
network enabled
no default IP address for target, host set, no MACaddress set
bootdelay for autoboot 5 sec.
autoboot disabled
#-----------------------------------
# u-boot FLASH version & RAM version
#-----------------------------------
The u-boot bootloader for Coldfire processors can be configured
1. as a standalone bootloader residing in flash & relocating itself to RAM on
startup automatically => "FLASH version"
2. as a RAM version which will not load from flash automatically as it needs a
prestage bootloader ("chainloading") & is running only from the RAM address it
is linked to => "RAM version"
This version may be very helpful when installing u-boot for the first time
since it can be used to make available s. th. like a "bootstrap
mechanism".
How to build the different images:
------------------------------
Flash version
------------------------------
Compile u-boot
in dir ./u-boot-x-x-x/
please first check:
in ./include/configs/cobra5272.h
CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows:
#if 0
#define CONFIG_MONITOR_IS_IN_RAM
/* define if monitor is started from a pre-loader */
#endif
=> u-boot as single bootloader starting from flash
in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
CONFIG_SYS_TEXT_BASE = 0xffe00000
=> linking address for u-boot as single bootloader stored in flash
then:
host> make cobra5272_config
rm -f include/config.h include/config.mk
Configuring for cobra5272 board...
host> make
[...]
host> cp u-boot.bin /tftpboot/u-boot_flash.bin
------------------------------
RAM version
------------------------------
in dir ./u-boot-x-x-x/
host> make distclean
please modify the settings:
in ./include/configs/cobra5272.h
CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows:
#if 1
#define CONFIG_MONITOR_IS_IN_RAM
/*define if monitor is started from a pre-loader */
#endif
=> u-boot as RAM version, chainloaded by another bootloader or using bdm cable
in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
CONFIG_SYS_TEXT_BASE = 0x00020000
=> target linking address for RAM
then:
host> make cobra5272_config
rm -f include/config.h include/config.mk
Configuring for cobra5272 board...
host> make
[...]
host> cp u-boot.bin /tftpboot/u-boot_ram.bin
----
HINT
----
If the m68k-elf-toolchain & the m68k-bdm-gdb is installed you can run the RAM
version by typing (in dir ./u-boot-x-x-x/)
"board/cobra5272/bdm/load-cobra_uboot" ,
in ./u-boot-x-x-x/ the RAM version u-boot (elf format) has to be available.
@@ -0,0 +1,169 @@
#
# GDB Init script for the Coldfire 5272 processor.
#
# The main purpose of this script is to configure the
# DRAM controller so code can be loaded.
#
# This file was changed to suite the senTec COBRA5272 board.
#
define addresses
set $mbar = 0x10000001
set $scr = $mbar - 1 + 0x004
set $spr = $mbar - 1 + 0x006
set $pmr = $mbar - 1 + 0x008
set $apmr = $mbar - 1 + 0x00e
set $dir = $mbar - 1 + 0x010
set $icr1 = $mbar - 1 + 0x020
set $icr2 = $mbar - 1 + 0x024
set $icr3 = $mbar - 1 + 0x028
set $icr4 = $mbar - 1 + 0x02c
set $isr = $mbar - 1 + 0x030
set $pitr = $mbar - 1 + 0x034
set $piwr = $mbar - 1 + 0x038
set $pivr = $mbar - 1 + 0x03f
set $csbr0 = $mbar - 1 + 0x040
set $csor0 = $mbar - 1 + 0x044
set $csbr1 = $mbar - 1 + 0x048
set $csor1 = $mbar - 1 + 0x04c
set $csbr2 = $mbar - 1 + 0x050
set $csor2 = $mbar - 1 + 0x054
set $csbr3 = $mbar - 1 + 0x058
set $csor3 = $mbar - 1 + 0x05c
set $csbr4 = $mbar - 1 + 0x060
set $csor4 = $mbar - 1 + 0x064
set $csbr5 = $mbar - 1 + 0x068
set $csor5 = $mbar - 1 + 0x06c
set $csbr6 = $mbar - 1 + 0x070
set $csor6 = $mbar - 1 + 0x074
set $csbr7 = $mbar - 1 + 0x078
set $csor7 = $mbar - 1 + 0x07c
set $pacnt = $mbar - 1 + 0x080
set $paddr = $mbar - 1 + 0x084
set $padat = $mbar - 1 + 0x086
set $pbcnt = $mbar - 1 + 0x088
set $pbddr = $mbar - 1 + 0x08c
set $pbdat = $mbar - 1 + 0x08e
set $pcddr = $mbar - 1 + 0x094
set $pcdat = $mbar - 1 + 0x096
set $pdcnt = $mbar - 1 + 0x098
set $sdcr = $mbar - 1 + 0x180
set $sdtr = $mbar - 1 + 0x184
set $wrrr = $mbar - 1 + 0x280
set $wirr = $mbar - 1 + 0x283
set $wcr = $mbar - 1 + 0x288
set $wer = $mbar - 1 + 0x28c
end
#
# Setup system configuration
#
define setup-sys
set *((unsigned short *) $scr) = 0x0003
set *((unsigned short *) $spr) = 0xffff
set *((unsigned char *) $pivr) = 0x4f
end
#
# Setup Chip Selects (as per Motorola M5272C3 board)
#
define setup-cs
# CS0 -- FLASH
set *((unsigned long *) $csbr0) = 0xffe00201
set *((unsigned long *) $csor0) = 0xffe00014
# CS1 -- external bus test
set *((unsigned long *) $csbr1) = 0x0
set *((unsigned long *) $csor1) = 0x0
# CS2 -- Optional FSRAM
set *((unsigned long *) $csbr2) = 0x30000001
set *((unsigned long *) $csor2) = 0xfff80000
# CS3 -- not used
set *((unsigned long *) $csbr3) = 0x0
set *((unsigned long *) $csor3) = 0x0
# CS4 -- not used
set *((unsigned long *) $csbr4) = 0x0
set *((unsigned long *) $csor4) = 0x0
# CS5 -- PLI socket0
set *((unsigned long *) $csbr5) = 0x0
set *((unsigned long *) $csor5) = 0x0
# CS6 -- PLI socket1
set *((unsigned long *) $csbr6) = 0x0
set *((unsigned long *) $csor6) = 0x0
# CS7 -- SDRAM
set *((unsigned long *) $csbr7) = 0x00000701
set *((unsigned long *) $csor7) = 0xff00007c
end
#
# Setup the DRAM controller.
#
define setup-dram
set *((unsigned long *) $sdtr) = 0x0000f539
set *((unsigned long *) $sdcr) = 0x00004211
# Dummy write to start SDRAM
set *((unsigned long *) 0) = 0
end
#
# Setup for GPIO pins
#
define setup-ppio
# PORT A -- the LED's
set *((unsigned long *) $pacnt) = 0x00000000
# lower 8 bits for output:
set *((unsigned short *) $paddr) = 0xff
# LED's off:
set *((unsigned short *) $padat) = 0xff
# PORT B
set *((unsigned long *) $pbcnt) = 0x55554155
set *((unsigned short *) $pbddr) = 0x0000
set *((unsigned short *) $pbdat) = 0x17ea
# PORT C
#set *((unsigned short *) $pcddr) = 0x0000
#set *((unsigned short *) $pcdat) = 0x1898
# PORT D
set *((unsigned long *) $pdcnt) = 0x00000000
end
#
# Added for uClinux-coldfire target...
#
target bdm /dev/bdm
addresses
setup-sys
setup-cs
setup-dram
setup-ppio
set print pretty
set print asm-demangle
display/i $pc
#
load u-boot
set $pc=0x20000
c
@@ -0,0 +1,2 @@
target bdm /dev/bdmcf0
q
@@ -0,0 +1,2 @@
m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot
@@ -0,0 +1,2 @@
m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset
@@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard (void)
{
puts ("Board: ");
puts ("senTec COBRA5272 Board\n");
return 0;
};
int dram_init(void)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
sdp->sdram_sdtr = 0xf539;
sdp->sdram_sdcr = 0x4211;
/* Dummy write to start SDRAM */
*((volatile unsigned long *) 0) = 0;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("DRAM test not implemented!\n");
return (0);
}
@@ -0,0 +1,366 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <console.h>
#include <cpu_func.h>
#include <irq_func.h>
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
void flash_print_info (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (AMD_MANUFACT & FLASH_VENDMASK):
printf ("AMD: ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (AMD_ID_PL160CB & FLASH_TYPEMASK):
printf ("AM29PL160CB (16Mbit)\n");
break;
default:
printf ("Unknown Chip Type\n");
goto Done;
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
Done:
return;
}
unsigned long flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_PL160CB & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
if (i == 0)
flashbase = PHYS_FLASH_1;
else
panic ("configured to many flash banks!\n");
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j == 0) {
/* 1st is 16 KiB */
flash_info[i].start[j] = flashbase;
}
if ((j >= 1) && (j <= 2)) {
/* 2nd and 3rd are 8 KiB */
flash_info[i].start[j] =
flashbase + 0x4000 + 0x2000 * (j - 1);
}
if (j == 3) {
/* 4th is 224 KiB */
flash_info[i].start[j] = flashbase + 0x8000;
}
if ((j >= 4) && (j <= 10)) {
/* rest is 256 KiB */
flash_info[i].start[j] =
flashbase + 0x40000 + 0x40000 * (j -
4);
}
}
size += flash_info[i].size;
}
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
return size;
}
#define CMD_READ_ARRAY 0x00F0
#define CMD_UNLOCK1 0x00AA
#define CMD_UNLOCK2 0x0055
#define CMD_ERASE_SETUP 0x0080
#define CMD_ERASE_CONFIRM 0x0030
#define CMD_PROGRAM 0x00A0
#define CMD_UNLOCK_BYPASS 0x0020
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
#define BIT_ERASE_DONE 0x0080
#define BIT_RDY_MASK 0x0080
#define BIT_PROGRAM_ERROR 0x0020
#define BIT_TIMEOUT 0x80000000 /* our flag */
#define READY 1
#define ERR 2
#define TMO 4
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
ulong result;
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip1;
ulong start;
/* first look for protection bits */
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last)) {
return ERR_INVAL;
}
if ((info->flash_id & FLASH_VENDMASK) !=
(AMD_MANUFACT & FLASH_VENDMASK)) {
return ERR_UNKNOWN_FLASH_VENDOR;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status();
icache_disable();
iflag = disable_interrupts();
printf ("\n");
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
volatile u16 *addr =
(volatile u16 *) (info->start[sect]);
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
*addr = CMD_ERASE_CONFIRM;
/* wait until flash is ready */
chip1 = 0;
do {
result = *addr;
/* check timeout */
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
break;
}
if (!chip1
&& (result & 0xFFFF) & BIT_ERASE_DONE)
chip1 = READY;
} while (!chip1);
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
if (chip1 == ERR) {
rc = ERR_PROG_ERROR;
goto outahere;
}
if (chip1 == TMO) {
rc = ERR_TIMEOUT;
goto outahere;
}
printf ("ok.\n");
} else { /* it was protected */
printf ("protected!\n");
}
}
if (ctrlc ())
printf ("User Interrupt!\n");
outahere:
/* allow flash to settle - wait 10 ms */
udelay (10000);
if (iflag)
enable_interrupts();
if (cflag)
icache_enable();
return rc;
}
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile u16 *addr = (volatile u16 *) dest;
ulong result;
int rc = ERR_OK;
int cflag, iflag;
int chip1;
ulong start;
/*
* Check if Flash is (sufficiently) erased
*/
result = *addr;
if ((result & data) != data)
return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status();
icache_disable();
iflag = disable_interrupts();
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait until flash is ready */
chip1 = 0;
do {
result = *addr;
/* check timeout */
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip1 = ERR | TMO;
break;
}
if (!chip1 && ((result & 0x80) == (data & 0x80)))
chip1 = READY;
} while (!chip1);
*addr = CMD_READ_ARRAY;
if (chip1 == ERR || *addr != data)
rc = ERR_PROG_ERROR;
if (iflag)
enable_interrupts();
if (cflag)
icache_enable();
return rc;
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp, data;
int rc;
if (addr & 1) {
printf ("unaligned destination not supported\n");
return ERR_ALIGN;
}
#if 0
if (cnt & 1) {
printf ("odd transfer sizes not supported\n");
return ERR_ALIGN;
}
#endif
wp = addr;
if (addr & 1) {
data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
src);
if ((rc = write_word (info, wp - 1, data)) != 0) {
return (rc);
}
src += 1;
wp += 1;
cnt -= 1;
}
while (cnt >= 2) {
data = *((volatile u16 *) src);
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
src += 2;
wp += 2;
cnt -= 2;
}
if (cnt == 1) {
data = (*((volatile u8 *) src) << 8) |
*((volatile u8 *) (wp + 1));
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
src += 1;
wp += 1;
cnt -= 1;
}
return ERR_OK;
}